2 * linux/drivers/video/omap2/dss/venc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * VENC settings from TI's DSS driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #define DSS_SUBSYS_NAME "VENC"
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
29 #include <linux/mutex.h>
30 #include <linux/completion.h>
31 #include <linux/delay.h>
32 #include <linux/string.h>
33 #include <linux/seq_file.h>
34 #include <linux/platform_device.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
38 #include <linux/component.h>
40 #include <video/omapfb_dss.h>
43 #include "dss_features.h"
46 #define VENC_REV_ID 0x00
47 #define VENC_STATUS 0x04
48 #define VENC_F_CONTROL 0x08
49 #define VENC_VIDOUT_CTRL 0x10
50 #define VENC_SYNC_CTRL 0x14
51 #define VENC_LLEN 0x1C
52 #define VENC_FLENS 0x20
53 #define VENC_HFLTR_CTRL 0x24
54 #define VENC_CC_CARR_WSS_CARR 0x28
55 #define VENC_C_PHASE 0x2C
56 #define VENC_GAIN_U 0x30
57 #define VENC_GAIN_V 0x34
58 #define VENC_GAIN_Y 0x38
59 #define VENC_BLACK_LEVEL 0x3C
60 #define VENC_BLANK_LEVEL 0x40
61 #define VENC_X_COLOR 0x44
62 #define VENC_M_CONTROL 0x48
63 #define VENC_BSTAMP_WSS_DATA 0x4C
64 #define VENC_S_CARR 0x50
65 #define VENC_LINE21 0x54
66 #define VENC_LN_SEL 0x58
67 #define VENC_L21__WC_CTL 0x5C
68 #define VENC_HTRIGGER_VTRIGGER 0x60
69 #define VENC_SAVID__EAVID 0x64
70 #define VENC_FLEN__FAL 0x68
71 #define VENC_LAL__PHASE_RESET 0x6C
72 #define VENC_HS_INT_START_STOP_X 0x70
73 #define VENC_HS_EXT_START_STOP_X 0x74
74 #define VENC_VS_INT_START_X 0x78
75 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
76 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
77 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
78 #define VENC_VS_EXT_STOP_Y 0x88
79 #define VENC_AVID_START_STOP_X 0x90
80 #define VENC_AVID_START_STOP_Y 0x94
81 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
82 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
83 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
84 #define VENC_TVDETGP_INT_START_STOP_X 0xB0
85 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4
86 #define VENC_GEN_CTRL 0xB8
87 #define VENC_OUTPUT_CONTROL 0xC4
88 #define VENC_OUTPUT_TEST 0xC8
89 #define VENC_DAC_B__DAC_C 0xC8
112 u32 htrigger_vtrigger;
115 u32 lal__phase_reset;
116 u32 hs_int_start_stop_x;
117 u32 hs_ext_start_stop_x;
119 u32 vs_int_stop_x__vs_int_start_y;
120 u32 vs_int_stop_y__vs_ext_start_x;
121 u32 vs_ext_stop_x__vs_ext_start_y;
123 u32 avid_start_stop_x;
124 u32 avid_start_stop_y;
125 u32 fid_int_start_x__fid_int_start_y;
126 u32 fid_int_offset_y__fid_ext_start_x;
127 u32 fid_ext_start_y__fid_ext_offset_y;
128 u32 tvdetgp_int_start_stop_x;
129 u32 tvdetgp_int_start_stop_y;
134 static const struct venc_config venc_config_pal_trm = {
138 .llen = 0x35F, /* 863 */
139 .flens = 0x270, /* 624 */
141 .cc_carr_wss_carr = 0x2F7225ED,
150 .bstamp_wss_data = 0x3F,
151 .s_carr = 0x2A098ACB,
153 .ln_sel = 0x01290015,
154 .l21__wc_ctl = 0x0000F603,
155 .htrigger_vtrigger = 0,
157 .savid__eavid = 0x06A70108,
158 .flen__fal = 0x00180270,
159 .lal__phase_reset = 0x00040135,
160 .hs_int_start_stop_x = 0x00880358,
161 .hs_ext_start_stop_x = 0x000F035F,
162 .vs_int_start_x = 0x01A70000,
163 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
164 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
165 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
166 .vs_ext_stop_y = 0x00000025,
167 .avid_start_stop_x = 0x03530083,
168 .avid_start_stop_y = 0x026C002E,
169 .fid_int_start_x__fid_int_start_y = 0x0001008A,
170 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
171 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
173 .tvdetgp_int_start_stop_x = 0x00140001,
174 .tvdetgp_int_start_stop_y = 0x00010001,
175 .gen_ctrl = 0x00FF0000,
179 static const struct venc_config venc_config_ntsc_trm = {
186 .cc_carr_wss_carr = 0x043F2631,
195 .bstamp_wss_data = 0x38,
196 .s_carr = 0x21F07C1F,
198 .ln_sel = 0x01310011,
199 .l21__wc_ctl = 0x0000F003,
200 .htrigger_vtrigger = 0,
202 .savid__eavid = 0x069300F4,
203 .flen__fal = 0x0016020C,
204 .lal__phase_reset = 0x00060107,
205 .hs_int_start_stop_x = 0x008E0350,
206 .hs_ext_start_stop_x = 0x000F0359,
207 .vs_int_start_x = 0x01A00000,
208 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
209 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
210 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
211 .vs_ext_stop_y = 0x00000006,
212 .avid_start_stop_x = 0x03480078,
213 .avid_start_stop_y = 0x02060024,
214 .fid_int_start_x__fid_int_start_y = 0x0001008A,
215 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
216 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
218 .tvdetgp_int_start_stop_x = 0x00140001,
219 .tvdetgp_int_start_stop_y = 0x00010001,
220 .gen_ctrl = 0x00F90000,
223 static const struct venc_config venc_config_pal_bdghi = {
231 .htrigger_vtrigger = 0,
232 .tvdetgp_int_start_stop_x = 0x00140001,
233 .tvdetgp_int_start_stop_y = 0x00010001,
234 .gen_ctrl = 0x00FB0000,
238 .cc_carr_wss_carr = 0x2F7625ED,
245 .m_control = 0<<2 | 1<<1,
246 .bstamp_wss_data = 0x42,
247 .s_carr = 0x2a098acb,
248 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
249 .savid__eavid = 0x06A70108,
250 .flen__fal = 23<<16 | 624<<0,
251 .lal__phase_reset = 2<<17 | 310<<0,
252 .hs_int_start_stop_x = 0x00920358,
253 .hs_ext_start_stop_x = 0x000F035F,
254 .vs_int_start_x = 0x1a7<<16,
255 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
256 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
257 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
258 .vs_ext_stop_y = 0x05,
259 .avid_start_stop_x = 0x03530082,
260 .avid_start_stop_y = 0x0270002E,
261 .fid_int_start_x__fid_int_start_y = 0x0005008A,
262 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
263 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
266 const struct omap_video_timings omap_dss_pal_timings = {
269 .pixelclock = 13500000,
279 EXPORT_SYMBOL(omap_dss_pal_timings);
281 const struct omap_video_timings omap_dss_ntsc_timings = {
284 .pixelclock = 13500000,
294 EXPORT_SYMBOL(omap_dss_ntsc_timings);
297 struct platform_device *pdev;
299 struct mutex venc_lock;
301 struct regulator *vdda_dac_reg;
303 struct clk *tv_dac_clk;
305 struct omap_video_timings timings;
306 enum omap_dss_venc_type type;
307 bool invert_polarity;
309 struct omap_dss_device output;
312 static inline void venc_write_reg(int idx, u32 val)
314 __raw_writel(val, venc.base + idx);
317 static inline u32 venc_read_reg(int idx)
319 u32 l = __raw_readl(venc.base + idx);
323 static void venc_write_config(const struct venc_config *config)
325 DSSDBG("write venc conf\n");
327 venc_write_reg(VENC_LLEN, config->llen);
328 venc_write_reg(VENC_FLENS, config->flens);
329 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
330 venc_write_reg(VENC_C_PHASE, config->c_phase);
331 venc_write_reg(VENC_GAIN_U, config->gain_u);
332 venc_write_reg(VENC_GAIN_V, config->gain_v);
333 venc_write_reg(VENC_GAIN_Y, config->gain_y);
334 venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
335 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
336 venc_write_reg(VENC_M_CONTROL, config->m_control);
337 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
339 venc_write_reg(VENC_S_CARR, config->s_carr);
340 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
341 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
342 venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
343 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
344 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
345 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
346 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
347 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
348 config->vs_int_stop_x__vs_int_start_y);
349 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
350 config->vs_int_stop_y__vs_ext_start_x);
351 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
352 config->vs_ext_stop_x__vs_ext_start_y);
353 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
354 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
355 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
356 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
357 config->fid_int_start_x__fid_int_start_y);
358 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
359 config->fid_int_offset_y__fid_ext_start_x);
360 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
361 config->fid_ext_start_y__fid_ext_offset_y);
363 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
364 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
365 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
366 venc_write_reg(VENC_X_COLOR, config->x_color);
367 venc_write_reg(VENC_LINE21, config->line21);
368 venc_write_reg(VENC_LN_SEL, config->ln_sel);
369 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
370 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
371 config->tvdetgp_int_start_stop_x);
372 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
373 config->tvdetgp_int_start_stop_y);
374 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
375 venc_write_reg(VENC_F_CONTROL, config->f_control);
376 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
379 static void venc_reset(void)
383 venc_write_reg(VENC_F_CONTROL, 1<<8);
384 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
386 DSSERR("Failed to reset venc\n");
391 #ifdef CONFIG_FB_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
392 /* the magical sleep that makes things work */
393 /* XXX more info? What bug this circumvents? */
398 static int venc_runtime_get(void)
402 DSSDBG("venc_runtime_get\n");
404 r = pm_runtime_get_sync(&venc.pdev->dev);
405 if (WARN_ON(r < 0)) {
406 pm_runtime_put_sync(&venc.pdev->dev);
412 static void venc_runtime_put(void)
416 DSSDBG("venc_runtime_put\n");
418 r = pm_runtime_put_sync(&venc.pdev->dev);
419 WARN_ON(r < 0 && r != -ENOSYS);
422 static const struct venc_config *venc_timings_to_config(
423 struct omap_video_timings *timings)
425 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
426 return &venc_config_pal_trm;
428 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
429 return &venc_config_ntsc_trm;
435 static int venc_power_on(struct omap_dss_device *dssdev)
437 struct omap_overlay_manager *mgr = venc.output.manager;
441 r = venc_runtime_get();
446 venc_write_config(venc_timings_to_config(&venc.timings));
448 dss_set_venc_output(venc.type);
449 dss_set_dac_pwrdn_bgz(1);
453 if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
456 l |= (1 << 0) | (1 << 2);
458 if (venc.invert_polarity == false)
461 venc_write_reg(VENC_OUTPUT_CONTROL, l);
463 dss_mgr_set_timings(mgr, &venc.timings);
465 r = regulator_enable(venc.vdda_dac_reg);
469 r = dss_mgr_enable(mgr);
476 regulator_disable(venc.vdda_dac_reg);
478 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
479 dss_set_dac_pwrdn_bgz(0);
486 static void venc_power_off(struct omap_dss_device *dssdev)
488 struct omap_overlay_manager *mgr = venc.output.manager;
490 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
491 dss_set_dac_pwrdn_bgz(0);
493 dss_mgr_disable(mgr);
495 regulator_disable(venc.vdda_dac_reg);
500 static int venc_display_enable(struct omap_dss_device *dssdev)
502 struct omap_dss_device *out = &venc.output;
505 DSSDBG("venc_display_enable\n");
507 mutex_lock(&venc.venc_lock);
509 if (out->manager == NULL) {
510 DSSERR("Failed to enable display: no output/manager\n");
515 r = venc_power_on(dssdev);
521 mutex_unlock(&venc.venc_lock);
525 mutex_unlock(&venc.venc_lock);
529 static void venc_display_disable(struct omap_dss_device *dssdev)
531 DSSDBG("venc_display_disable\n");
533 mutex_lock(&venc.venc_lock);
535 venc_power_off(dssdev);
537 mutex_unlock(&venc.venc_lock);
540 static void venc_set_timings(struct omap_dss_device *dssdev,
541 struct omap_video_timings *timings)
543 DSSDBG("venc_set_timings\n");
545 mutex_lock(&venc.venc_lock);
547 /* Reset WSS data when the TV standard changes. */
548 if (memcmp(&venc.timings, timings, sizeof(*timings)))
551 venc.timings = *timings;
553 dispc_set_tv_pclk(13500000);
555 mutex_unlock(&venc.venc_lock);
558 static int venc_check_timings(struct omap_dss_device *dssdev,
559 struct omap_video_timings *timings)
561 DSSDBG("venc_check_timings\n");
563 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
566 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
572 static void venc_get_timings(struct omap_dss_device *dssdev,
573 struct omap_video_timings *timings)
575 mutex_lock(&venc.venc_lock);
577 *timings = venc.timings;
579 mutex_unlock(&venc.venc_lock);
582 static u32 venc_get_wss(struct omap_dss_device *dssdev)
584 /* Invert due to VENC_L21_WC_CTL:INV=1 */
585 return (venc.wss_data >> 8) ^ 0xfffff;
588 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
590 const struct venc_config *config;
593 DSSDBG("venc_set_wss\n");
595 mutex_lock(&venc.venc_lock);
597 config = venc_timings_to_config(&venc.timings);
599 /* Invert due to VENC_L21_WC_CTL:INV=1 */
600 venc.wss_data = (wss ^ 0xfffff) << 8;
602 r = venc_runtime_get();
606 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
612 mutex_unlock(&venc.venc_lock);
617 static void venc_set_type(struct omap_dss_device *dssdev,
618 enum omap_dss_venc_type type)
620 mutex_lock(&venc.venc_lock);
624 mutex_unlock(&venc.venc_lock);
627 static void venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
628 bool invert_polarity)
630 mutex_lock(&venc.venc_lock);
632 venc.invert_polarity = invert_polarity;
634 mutex_unlock(&venc.venc_lock);
637 static int venc_init_regulator(void)
639 struct regulator *vdda_dac;
641 if (venc.vdda_dac_reg != NULL)
644 if (venc.pdev->dev.of_node)
645 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda");
647 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac");
649 if (IS_ERR(vdda_dac)) {
650 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER)
651 DSSERR("can't get VDDA_DAC regulator\n");
652 return PTR_ERR(vdda_dac);
655 venc.vdda_dac_reg = vdda_dac;
660 static void venc_dump_regs(struct seq_file *s)
662 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
664 if (venc_runtime_get())
667 DUMPREG(VENC_F_CONTROL);
668 DUMPREG(VENC_VIDOUT_CTRL);
669 DUMPREG(VENC_SYNC_CTRL);
672 DUMPREG(VENC_HFLTR_CTRL);
673 DUMPREG(VENC_CC_CARR_WSS_CARR);
674 DUMPREG(VENC_C_PHASE);
675 DUMPREG(VENC_GAIN_U);
676 DUMPREG(VENC_GAIN_V);
677 DUMPREG(VENC_GAIN_Y);
678 DUMPREG(VENC_BLACK_LEVEL);
679 DUMPREG(VENC_BLANK_LEVEL);
680 DUMPREG(VENC_X_COLOR);
681 DUMPREG(VENC_M_CONTROL);
682 DUMPREG(VENC_BSTAMP_WSS_DATA);
683 DUMPREG(VENC_S_CARR);
684 DUMPREG(VENC_LINE21);
685 DUMPREG(VENC_LN_SEL);
686 DUMPREG(VENC_L21__WC_CTL);
687 DUMPREG(VENC_HTRIGGER_VTRIGGER);
688 DUMPREG(VENC_SAVID__EAVID);
689 DUMPREG(VENC_FLEN__FAL);
690 DUMPREG(VENC_LAL__PHASE_RESET);
691 DUMPREG(VENC_HS_INT_START_STOP_X);
692 DUMPREG(VENC_HS_EXT_START_STOP_X);
693 DUMPREG(VENC_VS_INT_START_X);
694 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
695 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
696 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
697 DUMPREG(VENC_VS_EXT_STOP_Y);
698 DUMPREG(VENC_AVID_START_STOP_X);
699 DUMPREG(VENC_AVID_START_STOP_Y);
700 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
701 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
702 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
703 DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
704 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
705 DUMPREG(VENC_GEN_CTRL);
706 DUMPREG(VENC_OUTPUT_CONTROL);
707 DUMPREG(VENC_OUTPUT_TEST);
714 static int venc_get_clocks(struct platform_device *pdev)
718 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
719 clk = devm_clk_get(&pdev->dev, "tv_dac_clk");
721 DSSERR("can't get tv_dac_clk\n");
728 venc.tv_dac_clk = clk;
733 static int venc_connect(struct omap_dss_device *dssdev,
734 struct omap_dss_device *dst)
736 struct omap_overlay_manager *mgr;
739 r = venc_init_regulator();
743 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
747 r = dss_mgr_connect(mgr, dssdev);
751 r = omapdss_output_set_device(dssdev, dst);
753 DSSERR("failed to connect output to new device: %s\n",
755 dss_mgr_disconnect(mgr, dssdev);
762 static void venc_disconnect(struct omap_dss_device *dssdev,
763 struct omap_dss_device *dst)
765 WARN_ON(dst != dssdev->dst);
767 if (dst != dssdev->dst)
770 omapdss_output_unset_device(dssdev);
773 dss_mgr_disconnect(dssdev->manager, dssdev);
776 static const struct omapdss_atv_ops venc_ops = {
777 .connect = venc_connect,
778 .disconnect = venc_disconnect,
780 .enable = venc_display_enable,
781 .disable = venc_display_disable,
783 .check_timings = venc_check_timings,
784 .set_timings = venc_set_timings,
785 .get_timings = venc_get_timings,
787 .set_type = venc_set_type,
788 .invert_vid_out_polarity = venc_invert_vid_out_polarity,
790 .set_wss = venc_set_wss,
791 .get_wss = venc_get_wss,
794 static void venc_init_output(struct platform_device *pdev)
796 struct omap_dss_device *out = &venc.output;
798 out->dev = &pdev->dev;
799 out->id = OMAP_DSS_OUTPUT_VENC;
800 out->output_type = OMAP_DISPLAY_TYPE_VENC;
801 out->name = "venc.0";
802 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
803 out->ops.atv = &venc_ops;
804 out->owner = THIS_MODULE;
806 omapdss_register_output(out);
809 static void venc_uninit_output(struct platform_device *pdev)
811 struct omap_dss_device *out = &venc.output;
813 omapdss_unregister_output(out);
816 static int venc_probe_of(struct platform_device *pdev)
818 struct device_node *node = pdev->dev.of_node;
819 struct device_node *ep;
823 ep = omapdss_of_get_first_endpoint(node);
827 venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
829 r = of_property_read_u32(ep, "ti,channels", &channels);
832 "failed to read property 'ti,channels': %d\n", r);
838 venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE;
841 venc.type = OMAP_DSS_VENC_TYPE_SVIDEO;
844 dev_err(&pdev->dev, "bad channel propert '%d'\n", channels);
858 /* VENC HW IP initialisation */
859 static int venc_bind(struct device *dev, struct device *master, void *data)
861 struct platform_device *pdev = to_platform_device(dev);
863 struct resource *venc_mem;
868 mutex_init(&venc.venc_lock);
872 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
874 DSSERR("can't get IORESOURCE_MEM VENC\n");
878 venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
879 resource_size(venc_mem));
881 DSSERR("can't ioremap VENC\n");
885 r = venc_get_clocks(pdev);
889 pm_runtime_enable(&pdev->dev);
891 r = venc_runtime_get();
893 goto err_runtime_get;
895 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
896 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
900 if (pdev->dev.of_node) {
901 r = venc_probe_of(pdev);
903 DSSERR("Invalid DT data\n");
908 dss_debugfs_create_file("venc", venc_dump_regs);
910 venc_init_output(pdev);
916 pm_runtime_disable(&pdev->dev);
920 static void venc_unbind(struct device *dev, struct device *master, void *data)
922 struct platform_device *pdev = to_platform_device(dev);
924 venc_uninit_output(pdev);
926 pm_runtime_disable(&pdev->dev);
929 static const struct component_ops venc_component_ops = {
931 .unbind = venc_unbind,
934 static int venc_probe(struct platform_device *pdev)
936 return component_add(&pdev->dev, &venc_component_ops);
939 static int venc_remove(struct platform_device *pdev)
941 component_del(&pdev->dev, &venc_component_ops);
945 static int venc_runtime_suspend(struct device *dev)
948 clk_disable_unprepare(venc.tv_dac_clk);
955 static int venc_runtime_resume(struct device *dev)
959 r = dispc_runtime_get();
964 clk_prepare_enable(venc.tv_dac_clk);
969 static const struct dev_pm_ops venc_pm_ops = {
970 .runtime_suspend = venc_runtime_suspend,
971 .runtime_resume = venc_runtime_resume,
974 static const struct of_device_id venc_of_match[] = {
975 { .compatible = "ti,omap2-venc", },
976 { .compatible = "ti,omap3-venc", },
977 { .compatible = "ti,omap4-venc", },
981 static struct platform_driver omap_venchw_driver = {
983 .remove = venc_remove,
985 .name = "omapdss_venc",
987 .of_match_table = venc_of_match,
988 .suppress_bind_attrs = true,
992 int __init venc_init_platform_driver(void)
994 return platform_driver_register(&omap_venchw_driver);
997 void venc_uninit_platform_driver(void)
999 platform_driver_unregister(&omap_venchw_driver);