4 * Copyright (C) 2013 Texas Instruments Incorporated
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/err.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <video/omapfb_dss.h>
21 struct hdmi_phy_features {
24 unsigned long max_phy;
27 static const struct hdmi_phy_features *phy_feat;
29 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s)
31 #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
32 hdmi_read_reg(phy->base, r))
34 DUMPPHY(HDMI_TXPHY_TX_CTRL);
35 DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
36 DUMPPHY(HDMI_TXPHY_POWER_CTRL);
37 DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
38 if (phy_feat->bist_ctrl)
39 DUMPPHY(HDMI_TXPHY_BIST_CONTROL);
42 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes)
46 for (i = 0; i < 8; i += 2) {
53 if (dx < 0 || dx >= 8)
56 if (dy < 0 || dy >= 8)
71 phy->lane_function[lane] = i / 2;
72 phy->lane_polarity[lane] = pol;
78 static void hdmi_phy_configure_lanes(struct hdmi_phy_data *phy)
80 static const u16 pad_cfg_list[] = {
109 unsigned lane_cfg_val;
112 for (i = 0; i < 4; ++i)
113 lane_cfg |= phy->lane_function[i] << ((3 - i) * 4);
115 pol_val |= phy->lane_polarity[0] << 0;
116 pol_val |= phy->lane_polarity[1] << 3;
117 pol_val |= phy->lane_polarity[2] << 2;
118 pol_val |= phy->lane_polarity[3] << 1;
120 for (i = 0; i < ARRAY_SIZE(pad_cfg_list); ++i)
121 if (pad_cfg_list[i] == lane_cfg)
124 if (WARN_ON(i == ARRAY_SIZE(pad_cfg_list)))
129 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22);
130 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27);
133 int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
134 unsigned long lfbitclk)
139 * Read address 0 in order to get the SCP reset done completed
140 * Dummy access performed to make sure reset is done
142 hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL);
145 * In OMAP5+, the HFBITCLK must be divided by 2 before issuing the
146 * HDMI_PHYPWRCMD_LDOON command.
148 if (phy_feat->bist_ctrl)
149 REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11);
152 * If the hfbitclk != lfbitclk, it means the lfbitclk was configured
153 * to be used for TMDS.
155 if (hfbitclk != lfbitclk)
157 else if (hfbitclk / 10 < phy_feat->max_phy)
163 * Write to phy address 0 to configure the clock
164 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
166 REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30);
168 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
169 hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
171 /* Setup max LDO voltage */
172 if (phy_feat->ldo_voltage)
173 REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
175 hdmi_phy_configure_lanes(phy);
180 static const struct hdmi_phy_features omap44xx_phy_feats = {
183 .max_phy = 185675000,
186 static const struct hdmi_phy_features omap54xx_phy_feats = {
188 .ldo_voltage = false,
189 .max_phy = 186000000,
192 static int hdmi_phy_init_features(struct platform_device *pdev)
194 struct hdmi_phy_features *dst;
195 const struct hdmi_phy_features *src;
197 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
199 dev_err(&pdev->dev, "Failed to allocate HDMI PHY Features\n");
203 switch (omapdss_get_version()) {
204 case OMAPDSS_VER_OMAP4430_ES1:
205 case OMAPDSS_VER_OMAP4430_ES2:
206 case OMAPDSS_VER_OMAP4:
207 src = &omap44xx_phy_feats;
210 case OMAPDSS_VER_OMAP5:
211 case OMAPDSS_VER_DRA7xx:
212 src = &omap54xx_phy_feats;
219 memcpy(dst, src, sizeof(*dst));
225 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy)
228 struct resource *res;
230 r = hdmi_phy_init_features(pdev);
234 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
236 DSSERR("can't get PHY mem resource\n");
240 phy->base = devm_ioremap_resource(&pdev->dev, res);
241 if (IS_ERR(phy->base)) {
242 DSSERR("can't ioremap TX PHY\n");
243 return PTR_ERR(phy->base);