drivers/video/fbdev/omap2/omapfb/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/io.h>
  28 #include <linux/export.h>
  29 #include <linux/err.h>
  30 #include <linux/delay.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/clk.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/gfp.h>
  36 #include <linux/sizes.h>
  37 #include <linux/mfd/syscon.h>
  38 #include <linux/regmap.h>
  39 #include <linux/of.h>
  40 #include <linux/regulator/consumer.h>
  41 #include <linux/suspend.h>
  42 #include <linux/component.h>
  43
  44 #include <video/omapfb_dss.h>
  45
  46 #include "dss.h"
  47 #include "dss_features.h"
  48
  49 #define DSS_SZ_REGS                     SZ_512
  50
  51 struct dss_reg {
  52         u16 idx;
  53 };
  54
  55 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  56
  57 #define DSS_REVISION                    DSS_REG(0x0000)
  58 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  59 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  60 #define DSS_CONTROL                     DSS_REG(0x0040)
  61 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  62 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  63 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  64
  65 #define REG_GET(idx, start, end) \
  66         FLD_GET(dss_read_reg(idx), start, end)
  67
  68 #define REG_FLD_MOD(idx, val, start, end) \
  69         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  70
  71 struct dss_features {
  72         u8 fck_div_max;
  73         u8 dss_fck_multiplier;
  74         const char *parent_clk_name;
  75         const enum omap_display_type *ports;
  76         int num_ports;
  77         int (*dpi_select_source)(int port, enum omap_channel channel);
  78 };
  79
  80 static struct {
  81         struct platform_device *pdev;
  82         void __iomem    *base;
  83         struct regmap   *syscon_pll_ctrl;
  84         u32             syscon_pll_ctrl_offset;
  85
  86         struct clk      *parent_clk;
  87         struct clk      *dss_clk;
  88         unsigned long   dss_clk_rate;
  89
  90         unsigned long   cache_req_pck;
  91         unsigned long   cache_prate;
  92         struct dispc_clock_info cache_dispc_cinfo;
  93
  94         enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
  95         enum omap_dss_clk_source dispc_clk_source;
  96         enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
  97
  98         bool            ctx_valid;
  99         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
 100
 101         const struct dss_features *feat;
 102
 103         struct dss_pll  *video1_pll;
 104         struct dss_pll  *video2_pll;
 105 } dss;
 106
 107 static const char * const dss_generic_clk_source_names[] = {
 108         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DSI_PLL_HSDIV_DISPC",
 109         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DSI_PLL_HSDIV_DSI",
 110         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCK",
 111         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DSI_PLL2_HSDIV_DISPC",
 112         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI]   = "DSI_PLL2_HSDIV_DSI",
 113 };
 114
 115 static bool dss_initialized;
 116
 117 bool omapdss_is_initialized(void)
 118 {
 119         return dss_initialized;
 120 }
 121 EXPORT_SYMBOL(omapdss_is_initialized);
 122
 123 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
 124 {
 125         __raw_writel(val, dss.base + idx.idx);
 126 }
 127
 128 static inline u32 dss_read_reg(const struct dss_reg idx)
 129 {
 130         return __raw_readl(dss.base + idx.idx);
 131 }
 132
 133 #define SR(reg) \
 134         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
 135 #define RR(reg) \
 136         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
 137
 138 static void dss_save_context(void)
 139 {
 140         DSSDBG("dss_save_context\n");
 141
 142         SR(CONTROL);
 143
 144         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 145                         OMAP_DISPLAY_TYPE_SDI) {
 146                 SR(SDI_CONTROL);
 147                 SR(PLL_CONTROL);
 148         }
 149
 150         dss.ctx_valid = true;
 151
 152         DSSDBG("context saved\n");
 153 }
 154
 155 static void dss_restore_context(void)
 156 {
 157         DSSDBG("dss_restore_context\n");
 158
 159         if (!dss.ctx_valid)
 160                 return;
 161
 162         RR(CONTROL);
 163
 164         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 165                         OMAP_DISPLAY_TYPE_SDI) {
 166                 RR(SDI_CONTROL);
 167                 RR(PLL_CONTROL);
 168         }
 169
 170         DSSDBG("context restored\n");
 171 }
 172
 173 #undef SR
 174 #undef RR
 175
 176 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable)
 177 {
 178         unsigned shift;
 179         unsigned val;
 180
 181         if (!dss.syscon_pll_ctrl)
 182                 return;
 183
 184         val = !enable;
 185
 186         switch (pll_id) {
 187         case DSS_PLL_VIDEO1:
 188                 shift = 0;
 189                 break;
 190         case DSS_PLL_VIDEO2:
 191                 shift = 1;
 192                 break;
 193         case DSS_PLL_HDMI:
 194                 shift = 2;
 195                 break;
 196         default:
 197                 DSSERR("illegal DSS PLL ID %d\n", pll_id);
 198                 return;
 199         }
 200
 201         regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
 202                 1 << shift, val << shift);
 203 }
 204
 205 void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
 206         enum omap_channel channel)
 207 {
 208         unsigned shift, val;
 209
 210         if (!dss.syscon_pll_ctrl)
 211                 return;
 212
 213         switch (channel) {
 214         case OMAP_DSS_CHANNEL_LCD:
 215                 shift = 3;
 216
 217                 switch (pll_id) {
 218                 case DSS_PLL_VIDEO1:
 219                         val = 0; break;
 220                 case DSS_PLL_HDMI:
 221                         val = 1; break;
 222                 default:
 223                         DSSERR("error in PLL mux config for LCD\n");
 224                         return;
 225                 }
 226
 227                 break;
 228         case OMAP_DSS_CHANNEL_LCD2:
 229                 shift = 5;
 230
 231                 switch (pll_id) {
 232                 case DSS_PLL_VIDEO1:
 233                         val = 0; break;
 234                 case DSS_PLL_VIDEO2:
 235                         val = 1; break;
 236                 case DSS_PLL_HDMI:
 237                         val = 2; break;
 238                 default:
 239                         DSSERR("error in PLL mux config for LCD2\n");
 240                         return;
 241                 }
 242
 243                 break;
 244         case OMAP_DSS_CHANNEL_LCD3:
 245                 shift = 7;
 246
 247                 switch (pll_id) {
 248                 case DSS_PLL_VIDEO1:
 249                         val = 1; break;
 250                 case DSS_PLL_VIDEO2:
 251                         val = 0; break;
 252                 case DSS_PLL_HDMI:
 253                         val = 2; break;
 254                 default:
 255                         DSSERR("error in PLL mux config for LCD3\n");
 256                         return;
 257                 }
 258
 259                 break;
 260         default:
 261                 DSSERR("error in PLL mux config\n");
 262                 return;
 263         }
 264
 265         regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
 266                 0x3 << shift, val << shift);
 267 }
 268
 269 void dss_sdi_init(int datapairs)
 270 {
 271         u32 l;
 272
 273         BUG_ON(datapairs > 3 || datapairs < 1);
 274
 275         l = dss_read_reg(DSS_SDI_CONTROL);
 276         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 277         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 278         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 279         dss_write_reg(DSS_SDI_CONTROL, l);
 280
 281         l = dss_read_reg(DSS_PLL_CONTROL);
 282         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 283         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 284         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 285         dss_write_reg(DSS_PLL_CONTROL, l);
 286 }
 287
 288 int dss_sdi_enable(void)
 289 {
 290         unsigned long timeout;
 291
 292         dispc_pck_free_enable(1);
 293
 294         /* Reset SDI PLL */
 295         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 296         udelay(1);      /* wait 2x PCLK */
 297
 298         /* Lock SDI PLL */
 299         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 300
 301         /* Waiting for PLL lock request to complete */
 302         timeout = jiffies + msecs_to_jiffies(500);
 303         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 304                 if (time_after_eq(jiffies, timeout)) {
 305                         DSSERR("PLL lock request timed out\n");
 306                         goto err1;
 307                 }
 308         }
 309
 310         /* Clearing PLL_GO bit */
 311         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 312
 313         /* Waiting for PLL to lock */
 314         timeout = jiffies + msecs_to_jiffies(500);
 315         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 316                 if (time_after_eq(jiffies, timeout)) {
 317                         DSSERR("PLL lock timed out\n");
 318                         goto err1;
 319                 }
 320         }
 321
 322         dispc_lcd_enable_signal(1);
 323
 324         /* Waiting for SDI reset to complete */
 325         timeout = jiffies + msecs_to_jiffies(500);
 326         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 327                 if (time_after_eq(jiffies, timeout)) {
 328                         DSSERR("SDI reset timed out\n");
 329                         goto err2;
 330                 }
 331         }
 332
 333         return 0;
 334
 335  err2:
 336         dispc_lcd_enable_signal(0);
 337  err1:
 338         /* Reset SDI PLL */
 339         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 340
 341         dispc_pck_free_enable(0);
 342
 343         return -ETIMEDOUT;
 344 }
 345
 346 void dss_sdi_disable(void)
 347 {
 348         dispc_lcd_enable_signal(0);
 349
 350         dispc_pck_free_enable(0);
 351
 352         /* Reset SDI PLL */
 353         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 354 }
 355
 356 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
 357 {
 358         return dss_generic_clk_source_names[clk_src];
 359 }
 360
 361 void dss_dump_clocks(struct seq_file *s)
 362 {
 363         const char *fclk_name, *fclk_real_name;
 364         unsigned long fclk_rate;
 365
 366         if (dss_runtime_get())
 367                 return;
 368
 369         seq_printf(s, "- DSS -\n");
 370
 371         fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 372         fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 373         fclk_rate = clk_get_rate(dss.dss_clk);
 374
 375         seq_printf(s, "%s (%s) = %lu\n",
 376                         fclk_name, fclk_real_name,
 377                         fclk_rate);
 378
 379         dss_runtime_put();
 380 }
 381
 382 static void dss_dump_regs(struct seq_file *s)
 383 {
 384 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 385
 386         if (dss_runtime_get())
 387                 return;
 388
 389         DUMPREG(DSS_REVISION);
 390         DUMPREG(DSS_SYSCONFIG);
 391         DUMPREG(DSS_SYSSTATUS);
 392         DUMPREG(DSS_CONTROL);
 393
 394         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 395                         OMAP_DISPLAY_TYPE_SDI) {
 396                 DUMPREG(DSS_SDI_CONTROL);
 397                 DUMPREG(DSS_PLL_CONTROL);
 398                 DUMPREG(DSS_SDI_STATUS);
 399         }
 400
 401         dss_runtime_put();
 402 #undef DUMPREG
 403 }
 404
 405 static void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
 406 {
 407         int b;
 408         u8 start, end;
 409
 410         switch (clk_src) {
 411         case OMAP_DSS_CLK_SRC_FCK:
 412                 b = 0;
 413                 break;
 414         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 415                 b = 1;
 416                 break;
 417         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 418                 b = 2;
 419                 break;
 420         default:
 421                 BUG();
 422                 return;
 423         }
 424
 425         dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
 426
 427         REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
 428
 429         dss.dispc_clk_source = clk_src;
 430 }
 431
 432 void dss_select_dsi_clk_source(int dsi_module,
 433                 enum omap_dss_clk_source clk_src)
 434 {
 435         int b, pos;
 436
 437         switch (clk_src) {
 438         case OMAP_DSS_CLK_SRC_FCK:
 439                 b = 0;
 440                 break;
 441         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
 442                 BUG_ON(dsi_module != 0);
 443                 b = 1;
 444                 break;
 445         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
 446                 BUG_ON(dsi_module != 1);
 447                 b = 1;
 448                 break;
 449         default:
 450                 BUG();
 451                 return;
 452         }
 453
 454         pos = dsi_module == 0 ? 1 : 10;
 455         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* DSIx_CLK_SWITCH */
 456
 457         dss.dsi_clk_source[dsi_module] = clk_src;
 458 }
 459
 460 void dss_select_lcd_clk_source(enum omap_channel channel,
 461                 enum omap_dss_clk_source clk_src)
 462 {
 463         int b, ix, pos;
 464
 465         if (!dss_has_feature(FEAT_LCD_CLK_SRC)) {
 466                 dss_select_dispc_clk_source(clk_src);
 467                 return;
 468         }
 469
 470         switch (clk_src) {
 471         case OMAP_DSS_CLK_SRC_FCK:
 472                 b = 0;
 473                 break;
 474         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 475                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
 476                 b = 1;
 477                 break;
 478         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 479                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 &&
 480                        channel != OMAP_DSS_CHANNEL_LCD3);
 481                 b = 1;
 482                 break;
 483         default:
 484                 BUG();
 485                 return;
 486         }
 487
 488         pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 489              (channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19);
 490         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
 491
 492         ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 493             (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
 494         dss.lcd_clk_source[ix] = clk_src;
 495 }
 496
 497 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
 498 {
 499         return dss.dispc_clk_source;
 500 }
 501
 502 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
 503 {
 504         return dss.dsi_clk_source[dsi_module];
 505 }
 506
 507 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
 508 {
 509         if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
 510                 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 511                         (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
 512                 return dss.lcd_clk_source[ix];
 513         } else {
 514                 /* LCD_CLK source is the same as DISPC_FCLK source for
 515                  * OMAP2 and OMAP3 */
 516                 return dss.dispc_clk_source;
 517         }
 518 }
 519
 520 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
 521                 dss_div_calc_func func, void *data)
 522 {
 523         int fckd, fckd_start, fckd_stop;
 524         unsigned long fck;
 525         unsigned long fck_hw_max;
 526         unsigned long fckd_hw_max;
 527         unsigned long prate;
 528         unsigned m;
 529
 530         fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 531
 532         if (dss.parent_clk == NULL) {
 533                 unsigned pckd;
 534
 535                 pckd = fck_hw_max / pck;
 536
 537                 fck = pck * pckd;
 538
 539                 fck = clk_round_rate(dss.dss_clk, fck);
 540
 541                 return func(fck, data);
 542         }
 543
 544         fckd_hw_max = dss.feat->fck_div_max;
 545
 546         m = dss.feat->dss_fck_multiplier;
 547         prate = clk_get_rate(dss.parent_clk);
 548
 549         fck_min = fck_min ? fck_min : 1;
 550
 551         fckd_start = min(prate * m / fck_min, fckd_hw_max);
 552         fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
 553
 554         for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
 555                 fck = DIV_ROUND_UP(prate, fckd) * m;
 556
 557                 if (func(fck, data))
 558                         return true;
 559         }
 560
 561         return false;
 562 }
 563
 564 int dss_set_fck_rate(unsigned long rate)
 565 {
 566         int r;
 567
 568         DSSDBG("set fck to %lu\n", rate);
 569
 570         r = clk_set_rate(dss.dss_clk, rate);
 571         if (r)
 572                 return r;
 573
 574         dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
 575
 576         WARN_ONCE(dss.dss_clk_rate != rate,
 577                         "clk rate mismatch: %lu != %lu", dss.dss_clk_rate,
 578                         rate);
 579
 580         return 0;
 581 }
 582
 583 unsigned long dss_get_dispc_clk_rate(void)
 584 {
 585         return dss.dss_clk_rate;
 586 }
 587
 588 static int dss_setup_default_clock(void)
 589 {
 590         unsigned long max_dss_fck, prate;
 591         unsigned long fck;
 592         unsigned fck_div;
 593         int r;
 594
 595         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 596
 597         if (dss.parent_clk == NULL) {
 598                 fck = clk_round_rate(dss.dss_clk, max_dss_fck);
 599         } else {
 600                 prate = clk_get_rate(dss.parent_clk);
 601
 602                 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
 603                                 max_dss_fck);
 604                 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier;
 605         }
 606
 607         r = dss_set_fck_rate(fck);
 608         if (r)
 609                 return r;
 610
 611         return 0;
 612 }
 613
 614 void dss_set_venc_output(enum omap_dss_venc_type type)
 615 {
 616         int l = 0;
 617
 618         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 619                 l = 0;
 620         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 621                 l = 1;
 622         else
 623                 BUG();
 624
 625         /* venc out selection. 0 = comp, 1 = svideo */
 626         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 627 }
 628
 629 void dss_set_dac_pwrdn_bgz(bool enable)
 630 {
 631         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 632 }
 633
 634 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)
 635 {
 636         enum omap_display_type dp;
 637         dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 638
 639         /* Complain about invalid selections */
 640         WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC));
 641         WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI));
 642
 643         /* Select only if we have options */
 644         if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI))
 645                 REG_FLD_MOD(DSS_CONTROL, src, 15, 15);  /* VENC_HDMI_SWITCH */
 646 }
 647
 648 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
 649 {
 650         enum omap_display_type displays;
 651
 652         displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 653         if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
 654                 return DSS_VENC_TV_CLK;
 655
 656         if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0)
 657                 return DSS_HDMI_M_PCLK;
 658
 659         return REG_GET(DSS_CONTROL, 15, 15);
 660 }
 661
 662 static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel)
 663 {
 664         if (channel != OMAP_DSS_CHANNEL_LCD)
 665                 return -EINVAL;
 666
 667         return 0;
 668 }
 669
 670 static int dss_dpi_select_source_omap4(int port, enum omap_channel channel)
 671 {
 672         int val;
 673
 674         switch (channel) {
 675         case OMAP_DSS_CHANNEL_LCD2:
 676                 val = 0;
 677                 break;
 678         case OMAP_DSS_CHANNEL_DIGIT:
 679                 val = 1;
 680                 break;
 681         default:
 682                 return -EINVAL;
 683         }
 684
 685         REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
 686
 687         return 0;
 688 }
 689
 690 static int dss_dpi_select_source_omap5(int port, enum omap_channel channel)
 691 {
 692         int val;
 693
 694         switch (channel) {
 695         case OMAP_DSS_CHANNEL_LCD:
 696                 val = 1;
 697                 break;
 698         case OMAP_DSS_CHANNEL_LCD2:
 699                 val = 2;
 700                 break;
 701         case OMAP_DSS_CHANNEL_LCD3:
 702                 val = 3;
 703                 break;
 704         case OMAP_DSS_CHANNEL_DIGIT:
 705                 val = 0;
 706                 break;
 707         default:
 708                 return -EINVAL;
 709         }
 710
 711         REG_FLD_MOD(DSS_CONTROL, val, 17, 16);
 712
 713         return 0;
 714 }
 715
 716 static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel)
 717 {
 718         switch (port) {
 719         case 0:
 720                 return dss_dpi_select_source_omap5(port, channel);
 721         case 1:
 722                 if (channel != OMAP_DSS_CHANNEL_LCD2)
 723                         return -EINVAL;
 724                 break;
 725         case 2:
 726                 if (channel != OMAP_DSS_CHANNEL_LCD3)
 727                         return -EINVAL;
 728                 break;
 729         default:
 730                 return -EINVAL;
 731         }
 732
 733         return 0;
 734 }
 735
 736 int dss_dpi_select_source(int port, enum omap_channel channel)
 737 {
 738         return dss.feat->dpi_select_source(port, channel);
 739 }
 740
 741 static int dss_get_clocks(void)
 742 {
 743         struct clk *clk;
 744
 745         clk = devm_clk_get(&dss.pdev->dev, "fck");
 746         if (IS_ERR(clk)) {
 747                 DSSERR("can't get clock fck\n");
 748                 return PTR_ERR(clk);
 749         }
 750
 751         dss.dss_clk = clk;
 752
 753         if (dss.feat->parent_clk_name) {
 754                 clk = clk_get(NULL, dss.feat->parent_clk_name);
 755                 if (IS_ERR(clk)) {
 756                         DSSERR("Failed to get %s\n", dss.feat->parent_clk_name);
 757                         return PTR_ERR(clk);
 758                 }
 759         } else {
 760                 clk = NULL;
 761         }
 762
 763         dss.parent_clk = clk;
 764
 765         return 0;
 766 }
 767
 768 static void dss_put_clocks(void)
 769 {
 770         if (dss.parent_clk)
 771                 clk_put(dss.parent_clk);
 772 }
 773
 774 int dss_runtime_get(void)
 775 {
 776         int r;
 777
 778         DSSDBG("dss_runtime_get\n");
 779
 780         r = pm_runtime_get_sync(&dss.pdev->dev);
 781         if (WARN_ON(r < 0)) {
 782                 pm_runtime_put_sync(&dss.pdev->dev);
 783                 return r;
 784         }
 785         return 0;
 786 }
 787
 788 void dss_runtime_put(void)
 789 {
 790         int r;
 791
 792         DSSDBG("dss_runtime_put\n");
 793
 794         r = pm_runtime_put_sync(&dss.pdev->dev);
 795         WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
 796 }
 797
 798 /* DEBUGFS */
 799 #if defined(CONFIG_FB_OMAP2_DSS_DEBUGFS)
 800 void dss_debug_dump_clocks(struct seq_file *s)
 801 {
 802         dss_dump_clocks(s);
 803         dispc_dump_clocks(s);
 804 #ifdef CONFIG_FB_OMAP2_DSS_DSI
 805         dsi_dump_clocks(s);
 806 #endif
 807 }
 808 #endif
 809
 810
 811 static const enum omap_display_type omap2plus_ports[] = {
 812         OMAP_DISPLAY_TYPE_DPI,
 813 };
 814
 815 static const enum omap_display_type omap34xx_ports[] = {
 816         OMAP_DISPLAY_TYPE_DPI,
 817         OMAP_DISPLAY_TYPE_SDI,
 818 };
 819
 820 static const enum omap_display_type dra7xx_ports[] = {
 821         OMAP_DISPLAY_TYPE_DPI,
 822         OMAP_DISPLAY_TYPE_DPI,
 823         OMAP_DISPLAY_TYPE_DPI,
 824 };
 825
 826 static const struct dss_features omap24xx_dss_feats = {
 827         /*
 828          * fck div max is really 16, but the divider range has gaps. The range
 829          * from 1 to 6 has no gaps, so let's use that as a max.
 830          */
 831         .fck_div_max            =       6,
 832         .dss_fck_multiplier     =       2,
 833         .parent_clk_name        =       "core_ck",
 834         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 835         .ports                  =       omap2plus_ports,
 836         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 837 };
 838
 839 static const struct dss_features omap34xx_dss_feats = {
 840         .fck_div_max            =       16,
 841         .dss_fck_multiplier     =       2,
 842         .parent_clk_name        =       "dpll4_ck",
 843         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 844         .ports                  =       omap34xx_ports,
 845         .num_ports              =       ARRAY_SIZE(omap34xx_ports),
 846 };
 847
 848 static const struct dss_features omap3630_dss_feats = {
 849         .fck_div_max            =       31,
 850         .dss_fck_multiplier     =       1,
 851         .parent_clk_name        =       "dpll4_ck",
 852         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 853         .ports                  =       omap2plus_ports,
 854         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 855 };
 856
 857 static const struct dss_features omap44xx_dss_feats = {
 858         .fck_div_max            =       32,
 859         .dss_fck_multiplier     =       1,
 860         .parent_clk_name        =       "dpll_per_x2_ck",
 861         .dpi_select_source      =       &dss_dpi_select_source_omap4,
 862         .ports                  =       omap2plus_ports,
 863         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 864 };
 865
 866 static const struct dss_features omap54xx_dss_feats = {
 867         .fck_div_max            =       64,
 868         .dss_fck_multiplier     =       1,
 869         .parent_clk_name        =       "dpll_per_x2_ck",
 870         .dpi_select_source      =       &dss_dpi_select_source_omap5,
 871         .ports                  =       omap2plus_ports,
 872         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 873 };
 874
 875 static const struct dss_features am43xx_dss_feats = {
 876         .fck_div_max            =       0,
 877         .dss_fck_multiplier     =       0,
 878         .parent_clk_name        =       NULL,
 879         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 880         .ports                  =       omap2plus_ports,
 881         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 882 };
 883
 884 static const struct dss_features dra7xx_dss_feats = {
 885         .fck_div_max            =       64,
 886         .dss_fck_multiplier     =       1,
 887         .parent_clk_name        =       "dpll_per_x2_ck",
 888         .dpi_select_source      =       &dss_dpi_select_source_dra7xx,
 889         .ports                  =       dra7xx_ports,
 890         .num_ports              =       ARRAY_SIZE(dra7xx_ports),
 891 };
 892
 893 static int dss_init_features(struct platform_device *pdev)
 894 {
 895         const struct dss_features *src;
 896         struct dss_features *dst;
 897
 898         dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
 899         if (!dst) {
 900                 dev_err(&pdev->dev, "Failed to allocate local DSS Features\n");
 901                 return -ENOMEM;
 902         }
 903
 904         switch (omapdss_get_version()) {
 905         case OMAPDSS_VER_OMAP24xx:
 906                 src = &omap24xx_dss_feats;
 907                 break;
 908
 909         case OMAPDSS_VER_OMAP34xx_ES1:
 910         case OMAPDSS_VER_OMAP34xx_ES3:
 911         case OMAPDSS_VER_AM35xx:
 912                 src = &omap34xx_dss_feats;
 913                 break;
 914
 915         case OMAPDSS_VER_OMAP3630:
 916                 src = &omap3630_dss_feats;
 917                 break;
 918
 919         case OMAPDSS_VER_OMAP4430_ES1:
 920         case OMAPDSS_VER_OMAP4430_ES2:
 921         case OMAPDSS_VER_OMAP4:
 922                 src = &omap44xx_dss_feats;
 923                 break;
 924
 925         case OMAPDSS_VER_OMAP5:
 926                 src = &omap54xx_dss_feats;
 927                 break;
 928
 929         case OMAPDSS_VER_AM43xx:
 930                 src = &am43xx_dss_feats;
 931                 break;
 932
 933         case OMAPDSS_VER_DRA7xx:
 934                 src = &dra7xx_dss_feats;
 935                 break;
 936
 937         default:
 938                 return -ENODEV;
 939         }
 940
 941         memcpy(dst, src, sizeof(*dst));
 942         dss.feat = dst;
 943
 944         return 0;
 945 }
 946
 947 static void dss_uninit_ports(struct platform_device *pdev);
 948
 949 static int dss_init_ports(struct platform_device *pdev)
 950 {
 951         struct device_node *parent = pdev->dev.of_node;
 952         struct device_node *port;
 953         int r, ret = 0;
 954
 955         if (parent == NULL)
 956                 return 0;
 957
 958         port = omapdss_of_get_next_port(parent, NULL);
 959         if (!port)
 960                 return 0;
 961
 962         if (dss.feat->num_ports == 0)
 963                 return 0;
 964
 965         do {
 966                 enum omap_display_type port_type;
 967                 u32 reg;
 968
 969                 r = of_property_read_u32(port, "reg", &reg);
 970                 if (r)
 971                         reg = 0;
 972
 973                 if (reg >= dss.feat->num_ports)
 974                         continue;
 975
 976                 port_type = dss.feat->ports[reg];
 977
 978                 switch (port_type) {
 979                 case OMAP_DISPLAY_TYPE_DPI:
 980                         ret = dpi_init_port(pdev, port);
 981                         break;
 982                 case OMAP_DISPLAY_TYPE_SDI:
 983                         ret = sdi_init_port(pdev, port);
 984                         break;
 985                 default:
 986                         break;
 987                 }
 988         } while (!ret &&
 989                  (port = omapdss_of_get_next_port(parent, port)) != NULL);
 990
 991         if (ret)
 992                 dss_uninit_ports(pdev);
 993
 994         return ret;
 995 }
 996
 997 static void dss_uninit_ports(struct platform_device *pdev)
 998 {
 999         struct device_node *parent = pdev->dev.of_node;
1000         struct device_node *port;
1001
1002         if (parent == NULL)
1003                 return;
1004
1005         port = omapdss_of_get_next_port(parent, NULL);
1006         if (!port)
1007                 return;
1008
1009         if (dss.feat->num_ports == 0)
1010                 return;
1011
1012         do {
1013                 enum omap_display_type port_type;
1014                 u32 reg;
1015                 int r;
1016
1017                 r = of_property_read_u32(port, "reg", &reg);
1018                 if (r)
1019                         reg = 0;
1020
1021                 if (reg >= dss.feat->num_ports)
1022                         continue;
1023
1024                 port_type = dss.feat->ports[reg];
1025
1026                 switch (port_type) {
1027                 case OMAP_DISPLAY_TYPE_DPI:
1028                         dpi_uninit_port(port);
1029                         break;
1030                 case OMAP_DISPLAY_TYPE_SDI:
1031                         sdi_uninit_port(port);
1032                         break;
1033                 default:
1034                         break;
1035                 }
1036         } while ((port = omapdss_of_get_next_port(parent, port)) != NULL);
1037 }
1038
1039 static int dss_video_pll_probe(struct platform_device *pdev)
1040 {
1041         struct device_node *np = pdev->dev.of_node;
1042         struct regulator *pll_regulator;
1043         int r;
1044
1045         if (!np)
1046                 return 0;
1047
1048         if (of_property_read_bool(np, "syscon-pll-ctrl")) {
1049                 dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np,
1050                         "syscon-pll-ctrl");
1051                 if (IS_ERR(dss.syscon_pll_ctrl)) {
1052                         dev_err(&pdev->dev,
1053                                 "failed to get syscon-pll-ctrl regmap\n");
1054                         return PTR_ERR(dss.syscon_pll_ctrl);
1055                 }
1056
1057                 if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1,
1058                                 &dss.syscon_pll_ctrl_offset)) {
1059                         dev_err(&pdev->dev,
1060                                 "failed to get syscon-pll-ctrl offset\n");
1061                         return -EINVAL;
1062                 }
1063         }
1064
1065         pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video");
1066         if (IS_ERR(pll_regulator)) {
1067                 r = PTR_ERR(pll_regulator);
1068
1069                 switch (r) {
1070                 case -ENOENT:
1071                         pll_regulator = NULL;
1072                         break;
1073
1074                 case -EPROBE_DEFER:
1075                         return -EPROBE_DEFER;
1076
1077                 default:
1078                         DSSERR("can't get DPLL VDDA regulator\n");
1079                         return r;
1080                 }
1081         }
1082
1083         if (of_property_match_string(np, "reg-names", "pll1") >= 0) {
1084                 dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator);
1085                 if (IS_ERR(dss.video1_pll))
1086                         return PTR_ERR(dss.video1_pll);
1087         }
1088
1089         if (of_property_match_string(np, "reg-names", "pll2") >= 0) {
1090                 dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator);
1091                 if (IS_ERR(dss.video2_pll)) {
1092                         dss_video_pll_uninit(dss.video1_pll);
1093                         return PTR_ERR(dss.video2_pll);
1094                 }
1095         }
1096
1097         return 0;
1098 }
1099
1100 /* DSS HW IP initialisation */
1101 static int dss_bind(struct device *dev)
1102 {
1103         struct platform_device *pdev = to_platform_device(dev);
1104         struct resource *dss_mem;
1105         u32 rev;
1106         int r;
1107
1108         dss.pdev = pdev;
1109
1110         r = dss_init_features(dss.pdev);
1111         if (r)
1112                 return r;
1113
1114         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
1115         if (!dss_mem) {
1116                 DSSERR("can't get IORESOURCE_MEM DSS\n");
1117                 return -EINVAL;
1118         }
1119
1120         dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
1121                                 resource_size(dss_mem));
1122         if (!dss.base) {
1123                 DSSERR("can't ioremap DSS\n");
1124                 return -ENOMEM;
1125         }
1126
1127         r = dss_get_clocks();
1128         if (r)
1129                 return r;
1130
1131         r = dss_setup_default_clock();
1132         if (r)
1133                 goto err_setup_clocks;
1134
1135         r = dss_video_pll_probe(pdev);
1136         if (r)
1137                 goto err_pll_init;
1138
1139         r = dss_init_ports(pdev);
1140         if (r)
1141                 goto err_init_ports;
1142
1143         pm_runtime_enable(&pdev->dev);
1144
1145         r = dss_runtime_get();
1146         if (r)
1147                 goto err_runtime_get;
1148
1149         dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
1150
1151         /* Select DPLL */
1152         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
1153
1154         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
1155
1156 #ifdef CONFIG_FB_OMAP2_DSS_VENC
1157         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
1158         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
1159         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
1160 #endif
1161         dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
1162         dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
1163         dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
1164         dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
1165         dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
1166
1167         rev = dss_read_reg(DSS_REVISION);
1168         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
1169                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1170
1171         dss_runtime_put();
1172
1173         r = component_bind_all(&pdev->dev, NULL);
1174         if (r)
1175                 goto err_component;
1176
1177         dss_debugfs_create_file("dss", dss_dump_regs);
1178
1179         pm_set_vt_switch(0);
1180
1181         dss_initialized = true;
1182
1183         return 0;
1184
1185 err_component:
1186 err_runtime_get:
1187         pm_runtime_disable(&pdev->dev);
1188         dss_uninit_ports(pdev);
1189 err_init_ports:
1190         if (dss.video1_pll)
1191                 dss_video_pll_uninit(dss.video1_pll);
1192
1193         if (dss.video2_pll)
1194                 dss_video_pll_uninit(dss.video2_pll);
1195 err_pll_init:
1196 err_setup_clocks:
1197         dss_put_clocks();
1198         return r;
1199 }
1200
1201 static void dss_unbind(struct device *dev)
1202 {
1203         struct platform_device *pdev = to_platform_device(dev);
1204
1205         dss_initialized = false;
1206
1207         component_unbind_all(&pdev->dev, NULL);
1208
1209         if (dss.video1_pll)
1210                 dss_video_pll_uninit(dss.video1_pll);
1211
1212         if (dss.video2_pll)
1213                 dss_video_pll_uninit(dss.video2_pll);
1214
1215         dss_uninit_ports(pdev);
1216
1217         pm_runtime_disable(&pdev->dev);
1218
1219         dss_put_clocks();
1220 }
1221
1222 static const struct component_master_ops dss_component_ops = {
1223         .bind = dss_bind,
1224         .unbind = dss_unbind,
1225 };
1226
1227 static int dss_component_compare(struct device *dev, void *data)
1228 {
1229         struct device *child = data;
1230         return dev == child;
1231 }
1232
1233 static int dss_add_child_component(struct device *dev, void *data)
1234 {
1235         struct component_match **match = data;
1236
1237         /*
1238          * HACK
1239          * We don't have a working driver for rfbi, so skip it here always.
1240          * Otherwise dss will never get probed successfully, as it will wait
1241          * for rfbi to get probed.
1242          */
1243         if (strstr(dev_name(dev), "rfbi"))
1244                 return 0;
1245
1246         component_match_add(dev->parent, match, dss_component_compare, dev);
1247
1248         return 0;
1249 }
1250
1251 static int dss_probe(struct platform_device *pdev)
1252 {
1253         struct component_match *match = NULL;
1254         int r;
1255
1256         /* add all the child devices as components */
1257         device_for_each_child(&pdev->dev, &match, dss_add_child_component);
1258
1259         r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match);
1260         if (r)
1261                 return r;
1262
1263         return 0;
1264 }
1265
1266 static int dss_remove(struct platform_device *pdev)
1267 {
1268         component_master_del(&pdev->dev, &dss_component_ops);
1269         return 0;
1270 }
1271
1272 static int dss_runtime_suspend(struct device *dev)
1273 {
1274         dss_save_context();
1275         dss_set_min_bus_tput(dev, 0);
1276
1277         pinctrl_pm_select_sleep_state(dev);
1278
1279         return 0;
1280 }
1281
1282 static int dss_runtime_resume(struct device *dev)
1283 {
1284         int r;
1285
1286         pinctrl_pm_select_default_state(dev);
1287
1288         /*
1289          * Set an arbitrarily high tput request to ensure OPP100.
1290          * What we should really do is to make a request to stay in OPP100,
1291          * without any tput requirements, but that is not currently possible
1292          * via the PM layer.
1293          */
1294
1295         r = dss_set_min_bus_tput(dev, 1000000000);
1296         if (r)
1297                 return r;
1298
1299         dss_restore_context();
1300         return 0;
1301 }
1302
1303 static const struct dev_pm_ops dss_pm_ops = {
1304         .runtime_suspend = dss_runtime_suspend,
1305         .runtime_resume = dss_runtime_resume,
1306 };
1307
1308 static const struct of_device_id dss_of_match[] = {
1309         { .compatible = "ti,omap2-dss", },
1310         { .compatible = "ti,omap3-dss", },
1311         { .compatible = "ti,omap4-dss", },
1312         { .compatible = "ti,omap5-dss", },
1313         { .compatible = "ti,dra7-dss", },
1314         {},
1315 };
1316
1317 MODULE_DEVICE_TABLE(of, dss_of_match);
1318
1319 static struct platform_driver omap_dsshw_driver = {
1320         .probe          = dss_probe,
1321         .remove         = dss_remove,
1322         .driver         = {
1323                 .name   = "omapdss_dss",
1324                 .pm     = &dss_pm_ops,
1325                 .of_match_table = dss_of_match,
1326                 .suppress_bind_attrs = true,
1327         },
1328 };
1329
1330 int __init dss_init_platform_driver(void)
1331 {
1332         return platform_driver_register(&omap_dsshw_driver);
1333 }
1334
1335 void dss_uninit_platform_driver(void)
1336 {
1337         platform_driver_unregister(&omap_dsshw_driver);
1338 }