2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/sizes.h>
39 #include <linux/mfd/syscon.h>
40 #include <linux/regmap.h>
42 #include <linux/component.h>
44 #include <video/omapfb_dss.h>
47 #include "dss_features.h"
51 #define DISPC_SZ_REGS SZ_4K
53 enum omap_burst_size {
59 #define REG_GET(idx, start, end) \
60 FLD_GET(dispc_read_reg(idx), start, end)
62 #define REG_FLD_MOD(idx, val, start, end) \
63 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
65 struct dispc_features {
76 unsigned long max_lcd_pclk;
77 unsigned long max_tv_pclk;
78 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
79 const struct omap_video_timings *mgr_timings,
80 u16 width, u16 height, u16 out_width, u16 out_height,
81 enum omap_color_mode color_mode, bool *five_taps,
82 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
83 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
84 unsigned long (*calc_core_clk) (unsigned long pclk,
85 u16 width, u16 height, u16 out_width, u16 out_height,
89 /* swap GFX & WB fifos */
90 bool gfx_fifo_workaround:1;
92 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
93 bool no_framedone_tv:1;
95 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
96 bool mstandby_workaround:1;
98 bool set_max_preload:1;
100 /* PIXEL_INC is not added to the last pixel of a line */
101 bool last_pixel_inc_missing:1;
103 /* POL_FREQ has ALIGN bit */
104 bool supports_sync_align:1;
106 bool has_writeback:1;
109 #define DISPC_MAX_NR_FIFOS 5
112 struct platform_device *pdev;
116 irq_handler_t user_handler;
119 unsigned long core_clk_rate;
120 unsigned long tv_pclk_rate;
122 u32 fifo_size[DISPC_MAX_NR_FIFOS];
123 /* maps which plane is using a fifo. fifo-id -> plane-id */
124 int fifo_assignment[DISPC_MAX_NR_FIFOS];
127 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
129 const struct dispc_features *feat;
133 struct regmap *syscon_pol;
134 u32 syscon_pol_offset;
136 /* DISPC_CONTROL & DISPC_CONFIG lock*/
137 spinlock_t control_lock;
140 enum omap_color_component {
141 /* used for all color formats for OMAP3 and earlier
142 * and for RGB and Y color component on OMAP4
144 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
145 /* used for UV component for
146 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
147 * color formats on OMAP4
149 DISPC_COLOR_COMPONENT_UV = 1 << 1,
152 enum mgr_reg_fields {
153 DISPC_MGR_FLD_ENABLE,
154 DISPC_MGR_FLD_STNTFT,
156 DISPC_MGR_FLD_TFTDATALINES,
157 DISPC_MGR_FLD_STALLMODE,
158 DISPC_MGR_FLD_TCKENABLE,
159 DISPC_MGR_FLD_TCKSELECTION,
161 DISPC_MGR_FLD_FIFOHANDCHECK,
162 /* used to maintain a count of the above fields */
166 struct dispc_reg_field {
172 static const struct {
177 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
179 [OMAP_DSS_CHANNEL_LCD] = {
181 .vsync_irq = DISPC_IRQ_VSYNC,
182 .framedone_irq = DISPC_IRQ_FRAMEDONE,
183 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
185 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
186 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
187 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
188 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
189 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
190 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
191 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
192 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
193 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
196 [OMAP_DSS_CHANNEL_DIGIT] = {
198 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
199 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
200 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
202 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
203 [DISPC_MGR_FLD_STNTFT] = { },
204 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
205 [DISPC_MGR_FLD_TFTDATALINES] = { },
206 [DISPC_MGR_FLD_STALLMODE] = { },
207 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
208 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
209 [DISPC_MGR_FLD_CPR] = { },
210 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
213 [OMAP_DSS_CHANNEL_LCD2] = {
215 .vsync_irq = DISPC_IRQ_VSYNC2,
216 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
217 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
219 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
220 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
221 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
222 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
223 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
224 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
225 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
226 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
227 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
230 [OMAP_DSS_CHANNEL_LCD3] = {
232 .vsync_irq = DISPC_IRQ_VSYNC3,
233 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
234 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
236 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
237 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
238 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
239 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
240 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
241 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
242 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
243 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
244 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
249 struct color_conv_coef {
250 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
254 static unsigned long dispc_fclk_rate(void);
255 static unsigned long dispc_core_clk_rate(void);
256 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
257 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
259 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
260 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
262 static inline void dispc_write_reg(const u16 idx, u32 val)
264 __raw_writel(val, dispc.base + idx);
267 static inline u32 dispc_read_reg(const u16 idx)
269 return __raw_readl(dispc.base + idx);
272 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
274 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
275 return REG_GET(rfld.reg, rfld.high, rfld.low);
278 static void mgr_fld_write(enum omap_channel channel,
279 enum mgr_reg_fields regfld, int val) {
280 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
281 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
285 spin_lock_irqsave(&dispc.control_lock, flags);
287 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
290 spin_unlock_irqrestore(&dispc.control_lock, flags);
294 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
296 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
298 static void dispc_save_context(void)
302 DSSDBG("dispc_save_context\n");
308 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
309 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
311 if (dss_has_feature(FEAT_MGR_LCD2)) {
315 if (dss_has_feature(FEAT_MGR_LCD3)) {
320 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
321 SR(DEFAULT_COLOR(i));
324 if (i == OMAP_DSS_CHANNEL_DIGIT)
335 if (dss_has_feature(FEAT_CPR)) {
342 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
347 SR(OVL_ATTRIBUTES(i));
348 SR(OVL_FIFO_THRESHOLD(i));
350 SR(OVL_PIXEL_INC(i));
351 if (dss_has_feature(FEAT_PRELOAD))
353 if (i == OMAP_DSS_GFX) {
354 SR(OVL_WINDOW_SKIP(i));
359 SR(OVL_PICTURE_SIZE(i));
363 for (j = 0; j < 8; j++)
364 SR(OVL_FIR_COEF_H(i, j));
366 for (j = 0; j < 8; j++)
367 SR(OVL_FIR_COEF_HV(i, j));
369 for (j = 0; j < 5; j++)
370 SR(OVL_CONV_COEF(i, j));
372 if (dss_has_feature(FEAT_FIR_COEF_V)) {
373 for (j = 0; j < 8; j++)
374 SR(OVL_FIR_COEF_V(i, j));
377 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
384 for (j = 0; j < 8; j++)
385 SR(OVL_FIR_COEF_H2(i, j));
387 for (j = 0; j < 8; j++)
388 SR(OVL_FIR_COEF_HV2(i, j));
390 for (j = 0; j < 8; j++)
391 SR(OVL_FIR_COEF_V2(i, j));
393 if (dss_has_feature(FEAT_ATTR2))
394 SR(OVL_ATTRIBUTES2(i));
397 if (dss_has_feature(FEAT_CORE_CLK_DIV))
400 dispc.ctx_valid = true;
402 DSSDBG("context saved\n");
405 static void dispc_restore_context(void)
409 DSSDBG("dispc_restore_context\n");
411 if (!dispc.ctx_valid)
418 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
419 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
421 if (dss_has_feature(FEAT_MGR_LCD2))
423 if (dss_has_feature(FEAT_MGR_LCD3))
426 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
427 RR(DEFAULT_COLOR(i));
430 if (i == OMAP_DSS_CHANNEL_DIGIT)
441 if (dss_has_feature(FEAT_CPR)) {
448 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
453 RR(OVL_ATTRIBUTES(i));
454 RR(OVL_FIFO_THRESHOLD(i));
456 RR(OVL_PIXEL_INC(i));
457 if (dss_has_feature(FEAT_PRELOAD))
459 if (i == OMAP_DSS_GFX) {
460 RR(OVL_WINDOW_SKIP(i));
465 RR(OVL_PICTURE_SIZE(i));
469 for (j = 0; j < 8; j++)
470 RR(OVL_FIR_COEF_H(i, j));
472 for (j = 0; j < 8; j++)
473 RR(OVL_FIR_COEF_HV(i, j));
475 for (j = 0; j < 5; j++)
476 RR(OVL_CONV_COEF(i, j));
478 if (dss_has_feature(FEAT_FIR_COEF_V)) {
479 for (j = 0; j < 8; j++)
480 RR(OVL_FIR_COEF_V(i, j));
483 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
490 for (j = 0; j < 8; j++)
491 RR(OVL_FIR_COEF_H2(i, j));
493 for (j = 0; j < 8; j++)
494 RR(OVL_FIR_COEF_HV2(i, j));
496 for (j = 0; j < 8; j++)
497 RR(OVL_FIR_COEF_V2(i, j));
499 if (dss_has_feature(FEAT_ATTR2))
500 RR(OVL_ATTRIBUTES2(i));
503 if (dss_has_feature(FEAT_CORE_CLK_DIV))
506 /* enable last, because LCD & DIGIT enable are here */
508 if (dss_has_feature(FEAT_MGR_LCD2))
510 if (dss_has_feature(FEAT_MGR_LCD3))
512 /* clear spurious SYNC_LOST_DIGIT interrupts */
513 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
516 * enable last so IRQs won't trigger before
517 * the context is fully restored
521 DSSDBG("context restored\n");
527 int dispc_runtime_get(void)
531 DSSDBG("dispc_runtime_get\n");
533 r = pm_runtime_get_sync(&dispc.pdev->dev);
534 if (WARN_ON(r < 0)) {
535 pm_runtime_put_sync(&dispc.pdev->dev);
540 EXPORT_SYMBOL(dispc_runtime_get);
542 void dispc_runtime_put(void)
546 DSSDBG("dispc_runtime_put\n");
548 r = pm_runtime_put_sync(&dispc.pdev->dev);
549 WARN_ON(r < 0 && r != -ENOSYS);
551 EXPORT_SYMBOL(dispc_runtime_put);
553 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
555 return mgr_desc[channel].vsync_irq;
557 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
559 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
561 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
564 return mgr_desc[channel].framedone_irq;
566 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
568 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
570 return mgr_desc[channel].sync_lost_irq;
572 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
574 u32 dispc_wb_get_framedone_irq(void)
576 return DISPC_IRQ_FRAMEDONEWB;
579 bool dispc_mgr_go_busy(enum omap_channel channel)
581 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
583 EXPORT_SYMBOL(dispc_mgr_go_busy);
585 void dispc_mgr_go(enum omap_channel channel)
587 WARN_ON(!dispc_mgr_is_enabled(channel));
588 WARN_ON(dispc_mgr_go_busy(channel));
590 DSSDBG("GO %s\n", mgr_desc[channel].name);
592 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
594 EXPORT_SYMBOL(dispc_mgr_go);
596 bool dispc_wb_go_busy(void)
598 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
601 void dispc_wb_go(void)
603 enum omap_plane plane = OMAP_DSS_WB;
606 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
611 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
613 DSSERR("GO bit not down for WB\n");
617 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
620 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
622 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
625 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
627 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
630 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
632 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
635 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
637 BUG_ON(plane == OMAP_DSS_GFX);
639 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
642 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
645 BUG_ON(plane == OMAP_DSS_GFX);
647 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
650 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
652 BUG_ON(plane == OMAP_DSS_GFX);
654 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
657 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
658 int fir_vinc, int five_taps,
659 enum omap_color_component color_comp)
661 const struct dispc_coef *h_coef, *v_coef;
664 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
665 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
667 for (i = 0; i < 8; i++) {
670 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
671 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
672 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
673 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
674 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
675 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
676 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
677 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
679 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
680 dispc_ovl_write_firh_reg(plane, i, h);
681 dispc_ovl_write_firhv_reg(plane, i, hv);
683 dispc_ovl_write_firh2_reg(plane, i, h);
684 dispc_ovl_write_firhv2_reg(plane, i, hv);
690 for (i = 0; i < 8; i++) {
692 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
693 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
694 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
695 dispc_ovl_write_firv_reg(plane, i, v);
697 dispc_ovl_write_firv2_reg(plane, i, v);
703 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
704 const struct color_conv_coef *ct)
706 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
708 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
709 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
710 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
711 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
712 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
714 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
719 static void dispc_setup_color_conv_coef(void)
722 int num_ovl = dss_feat_get_num_ovls();
723 const struct color_conv_coef ctbl_bt601_5_ovl = {
725 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
727 const struct color_conv_coef ctbl_bt601_5_wb = {
729 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
732 for (i = 1; i < num_ovl; i++)
733 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
735 if (dispc.feat->has_writeback)
736 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
739 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
741 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
744 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
746 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
749 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
751 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
754 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
756 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
759 static void dispc_ovl_set_pos(enum omap_plane plane,
760 enum omap_overlay_caps caps, int x, int y)
764 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
767 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
769 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
772 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
775 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
777 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
778 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
780 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
783 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
788 BUG_ON(plane == OMAP_DSS_GFX);
790 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
792 if (plane == OMAP_DSS_WB)
793 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
795 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
798 static void dispc_ovl_set_zorder(enum omap_plane plane,
799 enum omap_overlay_caps caps, u8 zorder)
801 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
804 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
807 static void dispc_ovl_enable_zorder_planes(void)
811 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
814 for (i = 0; i < dss_feat_get_num_ovls(); i++)
815 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
818 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
819 enum omap_overlay_caps caps, bool enable)
821 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
824 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
827 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
828 enum omap_overlay_caps caps, u8 global_alpha)
830 static const unsigned shifts[] = { 0, 8, 16, 24, };
833 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
836 shift = shifts[plane];
837 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
840 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
842 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
845 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
847 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
850 static void dispc_ovl_set_color_mode(enum omap_plane plane,
851 enum omap_color_mode color_mode)
854 if (plane != OMAP_DSS_GFX) {
855 switch (color_mode) {
856 case OMAP_DSS_COLOR_NV12:
858 case OMAP_DSS_COLOR_RGBX16:
860 case OMAP_DSS_COLOR_RGBA16:
862 case OMAP_DSS_COLOR_RGB12U:
864 case OMAP_DSS_COLOR_ARGB16:
866 case OMAP_DSS_COLOR_RGB16:
868 case OMAP_DSS_COLOR_ARGB16_1555:
870 case OMAP_DSS_COLOR_RGB24U:
872 case OMAP_DSS_COLOR_RGB24P:
874 case OMAP_DSS_COLOR_YUV2:
876 case OMAP_DSS_COLOR_UYVY:
878 case OMAP_DSS_COLOR_ARGB32:
880 case OMAP_DSS_COLOR_RGBA32:
882 case OMAP_DSS_COLOR_RGBX32:
884 case OMAP_DSS_COLOR_XRGB16_1555:
890 switch (color_mode) {
891 case OMAP_DSS_COLOR_CLUT1:
893 case OMAP_DSS_COLOR_CLUT2:
895 case OMAP_DSS_COLOR_CLUT4:
897 case OMAP_DSS_COLOR_CLUT8:
899 case OMAP_DSS_COLOR_RGB12U:
901 case OMAP_DSS_COLOR_ARGB16:
903 case OMAP_DSS_COLOR_RGB16:
905 case OMAP_DSS_COLOR_ARGB16_1555:
907 case OMAP_DSS_COLOR_RGB24U:
909 case OMAP_DSS_COLOR_RGB24P:
911 case OMAP_DSS_COLOR_RGBX16:
913 case OMAP_DSS_COLOR_RGBA16:
915 case OMAP_DSS_COLOR_ARGB32:
917 case OMAP_DSS_COLOR_RGBA32:
919 case OMAP_DSS_COLOR_RGBX32:
921 case OMAP_DSS_COLOR_XRGB16_1555:
928 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
931 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
932 enum omap_dss_rotation_type rotation_type)
934 if (dss_has_feature(FEAT_BURST_2D) == 0)
937 if (rotation_type == OMAP_DSS_ROT_TILER)
938 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
940 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
943 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
947 int chan = 0, chan2 = 0;
953 case OMAP_DSS_VIDEO1:
954 case OMAP_DSS_VIDEO2:
955 case OMAP_DSS_VIDEO3:
963 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
964 if (dss_has_feature(FEAT_MGR_LCD2)) {
966 case OMAP_DSS_CHANNEL_LCD:
970 case OMAP_DSS_CHANNEL_DIGIT:
974 case OMAP_DSS_CHANNEL_LCD2:
978 case OMAP_DSS_CHANNEL_LCD3:
979 if (dss_has_feature(FEAT_MGR_LCD3)) {
987 case OMAP_DSS_CHANNEL_WB:
996 val = FLD_MOD(val, chan, shift, shift);
997 val = FLD_MOD(val, chan2, 31, 30);
999 val = FLD_MOD(val, channel, shift, shift);
1001 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1003 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
1005 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
1014 case OMAP_DSS_VIDEO1:
1015 case OMAP_DSS_VIDEO2:
1016 case OMAP_DSS_VIDEO3:
1024 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1026 if (FLD_GET(val, shift, shift) == 1)
1027 return OMAP_DSS_CHANNEL_DIGIT;
1029 if (!dss_has_feature(FEAT_MGR_LCD2))
1030 return OMAP_DSS_CHANNEL_LCD;
1032 switch (FLD_GET(val, 31, 30)) {
1035 return OMAP_DSS_CHANNEL_LCD;
1037 return OMAP_DSS_CHANNEL_LCD2;
1039 return OMAP_DSS_CHANNEL_LCD3;
1041 return OMAP_DSS_CHANNEL_WB;
1045 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1047 enum omap_plane plane = OMAP_DSS_WB;
1049 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1052 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1053 enum omap_burst_size burst_size)
1055 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1058 shift = shifts[plane];
1059 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1062 static void dispc_configure_burst_sizes(void)
1065 const int burst_size = BURST_SIZE_X8;
1067 /* Configure burst size always to maximum size */
1068 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1069 dispc_ovl_set_burst_size(i, burst_size);
1070 if (dispc.feat->has_writeback)
1071 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1074 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1076 unsigned unit = dss_feat_get_burst_size_unit();
1077 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1081 void dispc_enable_gamma_table(bool enable)
1084 * This is partially implemented to support only disabling of
1088 DSSWARN("Gamma table enabling for TV not yet supported");
1092 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1095 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1097 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1100 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1103 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1104 const struct omap_dss_cpr_coefs *coefs)
1106 u32 coef_r, coef_g, coef_b;
1108 if (!dss_mgr_is_lcd(channel))
1111 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1112 FLD_VAL(coefs->rb, 9, 0);
1113 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1114 FLD_VAL(coefs->gb, 9, 0);
1115 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1116 FLD_VAL(coefs->bb, 9, 0);
1118 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1119 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1120 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1123 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1127 BUG_ON(plane == OMAP_DSS_GFX);
1129 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1130 val = FLD_MOD(val, enable, 9, 9);
1131 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1134 static void dispc_ovl_enable_replication(enum omap_plane plane,
1135 enum omap_overlay_caps caps, bool enable)
1137 static const unsigned shifts[] = { 5, 10, 10, 10 };
1140 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1143 shift = shifts[plane];
1144 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1147 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1152 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1153 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1155 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1158 static void dispc_init_fifos(void)
1166 unit = dss_feat_get_buffer_size_unit();
1168 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1170 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1171 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1173 dispc.fifo_size[fifo] = size;
1176 * By default fifos are mapped directly to overlays, fifo 0 to
1177 * ovl 0, fifo 1 to ovl 1, etc.
1179 dispc.fifo_assignment[fifo] = fifo;
1183 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1184 * causes problems with certain use cases, like using the tiler in 2D
1185 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1186 * giving GFX plane a larger fifo. WB but should work fine with a
1189 if (dispc.feat->gfx_fifo_workaround) {
1192 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1194 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1195 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1196 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1197 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1199 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1201 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1202 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1206 * Setup default fifo thresholds.
1208 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1210 const bool use_fifomerge = false;
1211 const bool manual_update = false;
1213 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1214 use_fifomerge, manual_update);
1216 dispc_ovl_set_fifo_threshold(i, low, high);
1219 if (dispc.feat->has_writeback) {
1221 const bool use_fifomerge = false;
1222 const bool manual_update = false;
1224 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1225 use_fifomerge, manual_update);
1227 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1231 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1236 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1237 if (dispc.fifo_assignment[fifo] == plane)
1238 size += dispc.fifo_size[fifo];
1244 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1246 u8 hi_start, hi_end, lo_start, lo_end;
1249 unit = dss_feat_get_buffer_size_unit();
1251 WARN_ON(low % unit != 0);
1252 WARN_ON(high % unit != 0);
1257 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1258 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1260 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1262 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1263 lo_start, lo_end) * unit,
1264 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1265 hi_start, hi_end) * unit,
1266 low * unit, high * unit);
1268 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1269 FLD_VAL(high, hi_start, hi_end) |
1270 FLD_VAL(low, lo_start, lo_end));
1273 * configure the preload to the pipeline's high threhold, if HT it's too
1274 * large for the preload field, set the threshold to the maximum value
1275 * that can be held by the preload register
1277 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1278 plane != OMAP_DSS_WB)
1279 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1282 void dispc_enable_fifomerge(bool enable)
1284 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1289 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1290 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1293 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1294 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1298 * All sizes are in bytes. Both the buffer and burst are made of
1299 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1302 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1303 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1306 burst_size = dispc_ovl_get_burst_size(plane);
1307 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1309 if (use_fifomerge) {
1310 total_fifo_size = 0;
1311 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1312 total_fifo_size += dispc_ovl_get_fifo_size(i);
1314 total_fifo_size = ovl_fifo_size;
1318 * We use the same low threshold for both fifomerge and non-fifomerge
1319 * cases, but for fifomerge we calculate the high threshold using the
1320 * combined fifo size
1323 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1324 *fifo_low = ovl_fifo_size - burst_size * 2;
1325 *fifo_high = total_fifo_size - burst_size;
1326 } else if (plane == OMAP_DSS_WB) {
1328 * Most optimal configuration for writeback is to push out data
1329 * to the interconnect the moment writeback pushes enough pixels
1330 * in the FIFO to form a burst
1333 *fifo_high = burst_size;
1335 *fifo_low = ovl_fifo_size - burst_size;
1336 *fifo_high = total_fifo_size - buf_unit;
1340 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1344 if (plane == OMAP_DSS_GFX)
1349 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1352 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1355 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1356 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1359 static void dispc_init_mflag(void)
1364 * HACK: NV12 color format and MFLAG seem to have problems working
1365 * together: using two displays, and having an NV12 overlay on one of
1366 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1367 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1368 * remove the errors, but there doesn't seem to be a clear logic on
1369 * which values work and which not.
1371 * As a work-around, set force MFLAG to always on.
1373 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1374 (1 << 0) | /* MFLAG_CTRL = force always on */
1375 (0 << 2)); /* MFLAG_START = disable */
1377 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1378 u32 size = dispc_ovl_get_fifo_size(i);
1379 u32 unit = dss_feat_get_buffer_size_unit();
1382 dispc_ovl_set_mflag(i, true);
1385 * Simulation team suggests below thesholds:
1386 * HT = fifosize * 5 / 8;
1387 * LT = fifosize * 4 / 8;
1390 low = size * 4 / 8 / unit;
1391 high = size * 5 / 8 / unit;
1393 dispc_ovl_set_mflag_threshold(i, low, high);
1396 if (dispc.feat->has_writeback) {
1397 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1398 u32 unit = dss_feat_get_buffer_size_unit();
1401 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1404 * Simulation team suggests below thesholds:
1405 * HT = fifosize * 5 / 8;
1406 * LT = fifosize * 4 / 8;
1409 low = size * 4 / 8 / unit;
1410 high = size * 5 / 8 / unit;
1412 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1416 static void dispc_ovl_set_fir(enum omap_plane plane,
1418 enum omap_color_component color_comp)
1422 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1423 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1425 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1426 &hinc_start, &hinc_end);
1427 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1428 &vinc_start, &vinc_end);
1429 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1430 FLD_VAL(hinc, hinc_start, hinc_end);
1432 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1434 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1435 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1439 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1442 u8 hor_start, hor_end, vert_start, vert_end;
1444 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1445 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1447 val = FLD_VAL(vaccu, vert_start, vert_end) |
1448 FLD_VAL(haccu, hor_start, hor_end);
1450 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1453 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1456 u8 hor_start, hor_end, vert_start, vert_end;
1458 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1459 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1461 val = FLD_VAL(vaccu, vert_start, vert_end) |
1462 FLD_VAL(haccu, hor_start, hor_end);
1464 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1467 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1472 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1473 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1476 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1481 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1482 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1485 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1486 u16 orig_width, u16 orig_height,
1487 u16 out_width, u16 out_height,
1488 bool five_taps, u8 rotation,
1489 enum omap_color_component color_comp)
1491 int fir_hinc, fir_vinc;
1493 fir_hinc = 1024 * orig_width / out_width;
1494 fir_vinc = 1024 * orig_height / out_height;
1496 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1498 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1501 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1502 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1503 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1505 int h_accu2_0, h_accu2_1;
1506 int v_accu2_0, v_accu2_1;
1507 int chroma_hinc, chroma_vinc;
1517 const struct accu *accu_table;
1518 const struct accu *accu_val;
1520 static const struct accu accu_nv12[4] = {
1521 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1522 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1523 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1524 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1527 static const struct accu accu_nv12_ilace[4] = {
1528 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1529 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1530 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1531 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1534 static const struct accu accu_yuv[4] = {
1535 { 0, 1, 0, 1, 0, 1, 0, 1 },
1536 { 0, 1, 0, 1, 0, 1, 0, 1 },
1537 { -1, 1, 0, 1, 0, 1, 0, 1 },
1538 { 0, 1, 0, 1, -1, 1, 0, 1 },
1542 case OMAP_DSS_ROT_0:
1545 case OMAP_DSS_ROT_90:
1548 case OMAP_DSS_ROT_180:
1551 case OMAP_DSS_ROT_270:
1559 switch (color_mode) {
1560 case OMAP_DSS_COLOR_NV12:
1562 accu_table = accu_nv12_ilace;
1564 accu_table = accu_nv12;
1566 case OMAP_DSS_COLOR_YUV2:
1567 case OMAP_DSS_COLOR_UYVY:
1568 accu_table = accu_yuv;
1575 accu_val = &accu_table[idx];
1577 chroma_hinc = 1024 * orig_width / out_width;
1578 chroma_vinc = 1024 * orig_height / out_height;
1580 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1581 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1582 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1583 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1585 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1586 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1589 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1590 u16 orig_width, u16 orig_height,
1591 u16 out_width, u16 out_height,
1592 bool ilace, bool five_taps,
1593 bool fieldmode, enum omap_color_mode color_mode,
1600 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1601 out_width, out_height, five_taps,
1602 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1603 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1605 /* RESIZEENABLE and VERTICALTAPS */
1606 l &= ~((0x3 << 5) | (0x1 << 21));
1607 l |= (orig_width != out_width) ? (1 << 5) : 0;
1608 l |= (orig_height != out_height) ? (1 << 6) : 0;
1609 l |= five_taps ? (1 << 21) : 0;
1611 /* VRESIZECONF and HRESIZECONF */
1612 if (dss_has_feature(FEAT_RESIZECONF)) {
1614 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1615 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1618 /* LINEBUFFERSPLIT */
1619 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1621 l |= five_taps ? (1 << 22) : 0;
1624 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1627 * field 0 = even field = bottom field
1628 * field 1 = odd field = top field
1630 if (ilace && !fieldmode) {
1632 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1633 if (accu0 >= 1024/2) {
1639 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1640 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1643 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1644 u16 orig_width, u16 orig_height,
1645 u16 out_width, u16 out_height,
1646 bool ilace, bool five_taps,
1647 bool fieldmode, enum omap_color_mode color_mode,
1650 int scale_x = out_width != orig_width;
1651 int scale_y = out_height != orig_height;
1652 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1654 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1656 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1657 color_mode != OMAP_DSS_COLOR_UYVY &&
1658 color_mode != OMAP_DSS_COLOR_NV12)) {
1659 /* reset chroma resampling for RGB formats */
1660 if (plane != OMAP_DSS_WB)
1661 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1665 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1666 out_height, ilace, color_mode, rotation);
1668 switch (color_mode) {
1669 case OMAP_DSS_COLOR_NV12:
1670 if (chroma_upscale) {
1671 /* UV is subsampled by 2 horizontally and vertically */
1675 /* UV is downsampled by 2 horizontally and vertically */
1681 case OMAP_DSS_COLOR_YUV2:
1682 case OMAP_DSS_COLOR_UYVY:
1683 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1684 if (rotation == OMAP_DSS_ROT_0 ||
1685 rotation == OMAP_DSS_ROT_180) {
1687 /* UV is subsampled by 2 horizontally */
1690 /* UV is downsampled by 2 horizontally */
1694 /* must use FIR for YUV422 if rotated */
1695 if (rotation != OMAP_DSS_ROT_0)
1696 scale_x = scale_y = true;
1704 if (out_width != orig_width)
1706 if (out_height != orig_height)
1709 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1710 out_width, out_height, five_taps,
1711 rotation, DISPC_COLOR_COMPONENT_UV);
1713 if (plane != OMAP_DSS_WB)
1714 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1715 (scale_x || scale_y) ? 1 : 0, 8, 8);
1718 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1720 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1723 static void dispc_ovl_set_scaling(enum omap_plane plane,
1724 u16 orig_width, u16 orig_height,
1725 u16 out_width, u16 out_height,
1726 bool ilace, bool five_taps,
1727 bool fieldmode, enum omap_color_mode color_mode,
1730 BUG_ON(plane == OMAP_DSS_GFX);
1732 dispc_ovl_set_scaling_common(plane,
1733 orig_width, orig_height,
1734 out_width, out_height,
1736 fieldmode, color_mode,
1739 dispc_ovl_set_scaling_uv(plane,
1740 orig_width, orig_height,
1741 out_width, out_height,
1743 fieldmode, color_mode,
1747 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1748 enum omap_dss_rotation_type rotation_type,
1749 bool mirroring, enum omap_color_mode color_mode)
1751 bool row_repeat = false;
1754 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1755 color_mode == OMAP_DSS_COLOR_UYVY) {
1759 case OMAP_DSS_ROT_0:
1762 case OMAP_DSS_ROT_90:
1765 case OMAP_DSS_ROT_180:
1768 case OMAP_DSS_ROT_270:
1774 case OMAP_DSS_ROT_0:
1777 case OMAP_DSS_ROT_90:
1780 case OMAP_DSS_ROT_180:
1783 case OMAP_DSS_ROT_270:
1789 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1796 * OMAP4/5 Errata i631:
1797 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1798 * rows beyond the framebuffer, which may cause OCP error.
1800 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1801 rotation_type != OMAP_DSS_ROT_TILER)
1804 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1805 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1806 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1807 row_repeat ? 1 : 0, 18, 18);
1809 if (color_mode == OMAP_DSS_COLOR_NV12) {
1810 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1811 (rotation == OMAP_DSS_ROT_0 ||
1812 rotation == OMAP_DSS_ROT_180);
1814 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1819 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1821 switch (color_mode) {
1822 case OMAP_DSS_COLOR_CLUT1:
1824 case OMAP_DSS_COLOR_CLUT2:
1826 case OMAP_DSS_COLOR_CLUT4:
1828 case OMAP_DSS_COLOR_CLUT8:
1829 case OMAP_DSS_COLOR_NV12:
1831 case OMAP_DSS_COLOR_RGB12U:
1832 case OMAP_DSS_COLOR_RGB16:
1833 case OMAP_DSS_COLOR_ARGB16:
1834 case OMAP_DSS_COLOR_YUV2:
1835 case OMAP_DSS_COLOR_UYVY:
1836 case OMAP_DSS_COLOR_RGBA16:
1837 case OMAP_DSS_COLOR_RGBX16:
1838 case OMAP_DSS_COLOR_ARGB16_1555:
1839 case OMAP_DSS_COLOR_XRGB16_1555:
1841 case OMAP_DSS_COLOR_RGB24P:
1843 case OMAP_DSS_COLOR_RGB24U:
1844 case OMAP_DSS_COLOR_ARGB32:
1845 case OMAP_DSS_COLOR_RGBA32:
1846 case OMAP_DSS_COLOR_RGBX32:
1854 static s32 pixinc(int pixels, u8 ps)
1858 else if (pixels > 1)
1859 return 1 + (pixels - 1) * ps;
1860 else if (pixels < 0)
1861 return 1 - (-pixels + 1) * ps;
1867 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1869 u16 width, u16 height,
1870 enum omap_color_mode color_mode, bool fieldmode,
1871 unsigned int field_offset,
1872 unsigned *offset0, unsigned *offset1,
1873 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1877 /* FIXME CLUT formats */
1878 switch (color_mode) {
1879 case OMAP_DSS_COLOR_CLUT1:
1880 case OMAP_DSS_COLOR_CLUT2:
1881 case OMAP_DSS_COLOR_CLUT4:
1882 case OMAP_DSS_COLOR_CLUT8:
1885 case OMAP_DSS_COLOR_YUV2:
1886 case OMAP_DSS_COLOR_UYVY:
1890 ps = color_mode_to_bpp(color_mode) / 8;
1894 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1898 * field 0 = even field = bottom field
1899 * field 1 = odd field = top field
1901 switch (rotation + mirror * 4) {
1902 case OMAP_DSS_ROT_0:
1903 case OMAP_DSS_ROT_180:
1905 * If the pixel format is YUV or UYVY divide the width
1906 * of the image by 2 for 0 and 180 degree rotation.
1908 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1909 color_mode == OMAP_DSS_COLOR_UYVY)
1911 case OMAP_DSS_ROT_90:
1912 case OMAP_DSS_ROT_270:
1915 *offset0 = field_offset * screen_width * ps;
1919 *row_inc = pixinc(1 +
1920 (y_predecim * screen_width - x_predecim * width) +
1921 (fieldmode ? screen_width : 0), ps);
1922 *pix_inc = pixinc(x_predecim, ps);
1925 case OMAP_DSS_ROT_0 + 4:
1926 case OMAP_DSS_ROT_180 + 4:
1927 /* If the pixel format is YUV or UYVY divide the width
1928 * of the image by 2 for 0 degree and 180 degree
1930 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1931 color_mode == OMAP_DSS_COLOR_UYVY)
1933 case OMAP_DSS_ROT_90 + 4:
1934 case OMAP_DSS_ROT_270 + 4:
1937 *offset0 = field_offset * screen_width * ps;
1940 *row_inc = pixinc(1 -
1941 (y_predecim * screen_width + x_predecim * width) -
1942 (fieldmode ? screen_width : 0), ps);
1943 *pix_inc = pixinc(x_predecim, ps);
1952 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1954 u16 width, u16 height,
1955 enum omap_color_mode color_mode, bool fieldmode,
1956 unsigned int field_offset,
1957 unsigned *offset0, unsigned *offset1,
1958 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1963 /* FIXME CLUT formats */
1964 switch (color_mode) {
1965 case OMAP_DSS_COLOR_CLUT1:
1966 case OMAP_DSS_COLOR_CLUT2:
1967 case OMAP_DSS_COLOR_CLUT4:
1968 case OMAP_DSS_COLOR_CLUT8:
1972 ps = color_mode_to_bpp(color_mode) / 8;
1976 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1979 /* width & height are overlay sizes, convert to fb sizes */
1981 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1990 * field 0 = even field = bottom field
1991 * field 1 = odd field = top field
1993 switch (rotation + mirror * 4) {
1994 case OMAP_DSS_ROT_0:
1997 *offset0 = *offset1 + field_offset * screen_width * ps;
1999 *offset0 = *offset1;
2000 *row_inc = pixinc(1 +
2001 (y_predecim * screen_width - fbw * x_predecim) +
2002 (fieldmode ? screen_width : 0), ps);
2003 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2004 color_mode == OMAP_DSS_COLOR_UYVY)
2005 *pix_inc = pixinc(x_predecim, 2 * ps);
2007 *pix_inc = pixinc(x_predecim, ps);
2009 case OMAP_DSS_ROT_90:
2010 *offset1 = screen_width * (fbh - 1) * ps;
2012 *offset0 = *offset1 + field_offset * ps;
2014 *offset0 = *offset1;
2015 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
2016 y_predecim + (fieldmode ? 1 : 0), ps);
2017 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2019 case OMAP_DSS_ROT_180:
2020 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2022 *offset0 = *offset1 - field_offset * screen_width * ps;
2024 *offset0 = *offset1;
2025 *row_inc = pixinc(-1 -
2026 (y_predecim * screen_width - fbw * x_predecim) -
2027 (fieldmode ? screen_width : 0), ps);
2028 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2029 color_mode == OMAP_DSS_COLOR_UYVY)
2030 *pix_inc = pixinc(-x_predecim, 2 * ps);
2032 *pix_inc = pixinc(-x_predecim, ps);
2034 case OMAP_DSS_ROT_270:
2035 *offset1 = (fbw - 1) * ps;
2037 *offset0 = *offset1 - field_offset * ps;
2039 *offset0 = *offset1;
2040 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2041 y_predecim - (fieldmode ? 1 : 0), ps);
2042 *pix_inc = pixinc(x_predecim * screen_width, ps);
2046 case OMAP_DSS_ROT_0 + 4:
2047 *offset1 = (fbw - 1) * ps;
2049 *offset0 = *offset1 + field_offset * screen_width * ps;
2051 *offset0 = *offset1;
2052 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2053 (fieldmode ? screen_width : 0),
2055 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2056 color_mode == OMAP_DSS_COLOR_UYVY)
2057 *pix_inc = pixinc(-x_predecim, 2 * ps);
2059 *pix_inc = pixinc(-x_predecim, ps);
2062 case OMAP_DSS_ROT_90 + 4:
2065 *offset0 = *offset1 + field_offset * ps;
2067 *offset0 = *offset1;
2068 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2069 y_predecim + (fieldmode ? 1 : 0),
2071 *pix_inc = pixinc(x_predecim * screen_width, ps);
2074 case OMAP_DSS_ROT_180 + 4:
2075 *offset1 = screen_width * (fbh - 1) * ps;
2077 *offset0 = *offset1 - field_offset * screen_width * ps;
2079 *offset0 = *offset1;
2080 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2081 (fieldmode ? screen_width : 0),
2083 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2084 color_mode == OMAP_DSS_COLOR_UYVY)
2085 *pix_inc = pixinc(x_predecim, 2 * ps);
2087 *pix_inc = pixinc(x_predecim, ps);
2090 case OMAP_DSS_ROT_270 + 4:
2091 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2093 *offset0 = *offset1 - field_offset * ps;
2095 *offset0 = *offset1;
2096 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2097 y_predecim - (fieldmode ? 1 : 0),
2099 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2108 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2109 enum omap_color_mode color_mode, bool fieldmode,
2110 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2111 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2115 switch (color_mode) {
2116 case OMAP_DSS_COLOR_CLUT1:
2117 case OMAP_DSS_COLOR_CLUT2:
2118 case OMAP_DSS_COLOR_CLUT4:
2119 case OMAP_DSS_COLOR_CLUT8:
2123 ps = color_mode_to_bpp(color_mode) / 8;
2127 DSSDBG("scrw %d, width %d\n", screen_width, width);
2130 * field 0 = even field = bottom field
2131 * field 1 = odd field = top field
2135 *offset0 = *offset1 + field_offset * screen_width * ps;
2137 *offset0 = *offset1;
2138 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2139 (fieldmode ? screen_width : 0), ps);
2140 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2141 color_mode == OMAP_DSS_COLOR_UYVY)
2142 *pix_inc = pixinc(x_predecim, 2 * ps);
2144 *pix_inc = pixinc(x_predecim, ps);
2148 * This function is used to avoid synclosts in OMAP3, because of some
2149 * undocumented horizontal position and timing related limitations.
2151 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2152 const struct omap_video_timings *t, u16 pos_x,
2153 u16 width, u16 height, u16 out_width, u16 out_height,
2156 const int ds = DIV_ROUND_UP(height, out_height);
2157 unsigned long nonactive;
2158 static const u8 limits[3] = { 8, 10, 20 };
2162 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2165 if (out_height < height)
2167 if (out_width < width)
2169 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2170 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2171 if (blank <= limits[i])
2174 /* FIXME add checks for 3-tap filter once the limitations are known */
2179 * Pixel data should be prepared before visible display point starts.
2180 * So, atleast DS-2 lines must have already been fetched by DISPC
2181 * during nonactive - pos_x period.
2183 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2184 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2185 val, max(0, ds - 2) * width);
2186 if (val < max(0, ds - 2) * width)
2190 * All lines need to be refilled during the nonactive period of which
2191 * only one line can be loaded during the active period. So, atleast
2192 * DS - 1 lines should be loaded during nonactive period.
2194 val = div_u64((u64)nonactive * lclk, pclk);
2195 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2196 val, max(0, ds - 1) * width);
2197 if (val < max(0, ds - 1) * width)
2203 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2204 const struct omap_video_timings *mgr_timings, u16 width,
2205 u16 height, u16 out_width, u16 out_height,
2206 enum omap_color_mode color_mode)
2211 if (height <= out_height && width <= out_width)
2212 return (unsigned long) pclk;
2214 if (height > out_height) {
2215 unsigned int ppl = mgr_timings->x_res;
2217 tmp = (u64)pclk * height * out_width;
2218 do_div(tmp, 2 * out_height * ppl);
2221 if (height > 2 * out_height) {
2222 if (ppl == out_width)
2225 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2226 do_div(tmp, 2 * out_height * (ppl - out_width));
2227 core_clk = max_t(u32, core_clk, tmp);
2231 if (width > out_width) {
2232 tmp = (u64)pclk * width;
2233 do_div(tmp, out_width);
2234 core_clk = max_t(u32, core_clk, tmp);
2236 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2243 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2244 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2246 if (height > out_height && width > out_width)
2252 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2253 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2255 unsigned int hf, vf;
2258 * FIXME how to determine the 'A' factor
2259 * for the no downscaling case ?
2262 if (width > 3 * out_width)
2264 else if (width > 2 * out_width)
2266 else if (width > out_width)
2270 if (height > out_height)
2275 return pclk * vf * hf;
2278 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2279 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2282 * If the overlay/writeback is in mem to mem mode, there are no
2283 * downscaling limitations with respect to pixel clock, return 1 as
2284 * required core clock to represent that we have sufficient enough
2285 * core clock to do maximum downscaling
2290 if (width > out_width)
2291 return DIV_ROUND_UP(pclk, out_width) * width;
2296 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2297 const struct omap_video_timings *mgr_timings,
2298 u16 width, u16 height, u16 out_width, u16 out_height,
2299 enum omap_color_mode color_mode, bool *five_taps,
2300 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2301 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2304 u16 in_width, in_height;
2305 int min_factor = min(*decim_x, *decim_y);
2306 const int maxsinglelinewidth =
2307 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2312 in_height = height / *decim_y;
2313 in_width = width / *decim_x;
2314 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2315 in_height, out_width, out_height, mem_to_mem);
2316 error = (in_width > maxsinglelinewidth || !*core_clk ||
2317 *core_clk > dispc_core_clk_rate());
2319 if (*decim_x == *decim_y) {
2320 *decim_x = min_factor;
2323 swap(*decim_x, *decim_y);
2324 if (*decim_x < *decim_y)
2328 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2331 DSSERR("failed to find scaling settings\n");
2335 if (in_width > maxsinglelinewidth) {
2336 DSSERR("Cannot scale max input width exceeded");
2342 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2343 const struct omap_video_timings *mgr_timings,
2344 u16 width, u16 height, u16 out_width, u16 out_height,
2345 enum omap_color_mode color_mode, bool *five_taps,
2346 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2347 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2350 u16 in_width, in_height;
2351 const int maxsinglelinewidth =
2352 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2355 in_height = height / *decim_y;
2356 in_width = width / *decim_x;
2357 *five_taps = in_height > out_height;
2359 if (in_width > maxsinglelinewidth)
2360 if (in_height > out_height &&
2361 in_height < out_height * 2)
2365 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2366 in_width, in_height, out_width,
2367 out_height, color_mode);
2369 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2370 in_height, out_width, out_height,
2373 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2374 pos_x, in_width, in_height, out_width,
2375 out_height, *five_taps);
2376 if (error && *five_taps) {
2381 error = (error || in_width > maxsinglelinewidth * 2 ||
2382 (in_width > maxsinglelinewidth && *five_taps) ||
2383 !*core_clk || *core_clk > dispc_core_clk_rate());
2386 /* verify that we're inside the limits of scaler */
2387 if (in_width / 4 > out_width)
2391 if (in_height / 4 > out_height)
2394 if (in_height / 2 > out_height)
2401 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2404 DSSERR("failed to find scaling settings\n");
2408 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2409 in_height, out_width, out_height, *five_taps)) {
2410 DSSERR("horizontal timing too tight\n");
2414 if (in_width > (maxsinglelinewidth * 2)) {
2415 DSSERR("Cannot setup scaling");
2416 DSSERR("width exceeds maximum width possible");
2420 if (in_width > maxsinglelinewidth && *five_taps) {
2421 DSSERR("cannot setup scaling with five taps");
2427 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2428 const struct omap_video_timings *mgr_timings,
2429 u16 width, u16 height, u16 out_width, u16 out_height,
2430 enum omap_color_mode color_mode, bool *five_taps,
2431 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2432 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2434 u16 in_width, in_width_max;
2435 int decim_x_min = *decim_x;
2436 u16 in_height = height / *decim_y;
2437 const int maxsinglelinewidth =
2438 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2439 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2442 in_width_max = out_width * maxdownscale;
2444 in_width_max = dispc_core_clk_rate() /
2445 DIV_ROUND_UP(pclk, out_width);
2448 *decim_x = DIV_ROUND_UP(width, in_width_max);
2450 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2451 if (*decim_x > *x_predecim)
2455 in_width = width / *decim_x;
2456 } while (*decim_x <= *x_predecim &&
2457 in_width > maxsinglelinewidth && ++*decim_x);
2459 if (in_width > maxsinglelinewidth) {
2460 DSSERR("Cannot scale width exceeds max line width");
2464 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2465 out_width, out_height, mem_to_mem);
2469 #define DIV_FRAC(dividend, divisor) \
2470 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2472 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2473 enum omap_overlay_caps caps,
2474 const struct omap_video_timings *mgr_timings,
2475 u16 width, u16 height, u16 out_width, u16 out_height,
2476 enum omap_color_mode color_mode, bool *five_taps,
2477 int *x_predecim, int *y_predecim, u16 pos_x,
2478 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2480 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2481 const int max_decim_limit = 16;
2482 unsigned long core_clk = 0;
2483 int decim_x, decim_y, ret;
2485 if (width == out_width && height == out_height)
2488 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
2489 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2493 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2497 *x_predecim = *y_predecim = 1;
2499 *x_predecim = max_decim_limit;
2500 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2501 dss_has_feature(FEAT_BURST_2D)) ?
2502 2 : max_decim_limit;
2505 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2506 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2507 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2508 color_mode == OMAP_DSS_COLOR_CLUT8) {
2515 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2516 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2518 if (decim_x > *x_predecim || out_width > width * 8)
2521 if (decim_y > *y_predecim || out_height > height * 8)
2524 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2525 out_width, out_height, color_mode, five_taps,
2526 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2531 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2533 out_width, out_height,
2534 out_width / width, DIV_FRAC(out_width, width),
2535 out_height / height, DIV_FRAC(out_height, height),
2538 width / decim_x, height / decim_y,
2539 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2540 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2543 core_clk, dispc_core_clk_rate());
2545 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2546 DSSERR("failed to set up scaling, "
2547 "required core clk rate = %lu Hz, "
2548 "current core clk rate = %lu Hz\n",
2549 core_clk, dispc_core_clk_rate());
2553 *x_predecim = decim_x;
2554 *y_predecim = decim_y;
2558 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2559 const struct omap_overlay_info *oi,
2560 const struct omap_video_timings *timings,
2561 int *x_predecim, int *y_predecim)
2563 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2564 bool five_taps = true;
2565 bool fieldmode = false;
2566 u16 in_height = oi->height;
2567 u16 in_width = oi->width;
2568 bool ilace = timings->interlace;
2569 u16 out_width, out_height;
2570 int pos_x = oi->pos_x;
2571 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2572 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2574 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2575 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2577 if (ilace && oi->height == out_height)
2585 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2586 in_height, out_height);
2589 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2592 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2593 in_height, out_width, out_height, oi->color_mode,
2594 &five_taps, x_predecim, y_predecim, pos_x,
2595 oi->rotation_type, false);
2597 EXPORT_SYMBOL(dispc_ovl_check);
2599 static int dispc_ovl_setup_common(enum omap_plane plane,
2600 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2601 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2602 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2603 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2604 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2605 bool replication, const struct omap_video_timings *mgr_timings,
2608 bool five_taps = true;
2609 bool fieldmode = false;
2611 unsigned offset0, offset1;
2614 u16 frame_width, frame_height;
2615 unsigned int field_offset = 0;
2616 u16 in_height = height;
2617 u16 in_width = width;
2618 int x_predecim = 1, y_predecim = 1;
2619 bool ilace = mgr_timings->interlace;
2620 unsigned long pclk = dispc_plane_pclk_rate(plane);
2621 unsigned long lclk = dispc_plane_lclk_rate(plane);
2623 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2626 switch (color_mode) {
2627 case OMAP_DSS_COLOR_YUV2:
2628 case OMAP_DSS_COLOR_UYVY:
2629 case OMAP_DSS_COLOR_NV12:
2631 DSSERR("input width %d is not even for YUV format\n",
2641 out_width = out_width == 0 ? width : out_width;
2642 out_height = out_height == 0 ? height : out_height;
2644 if (ilace && height == out_height)
2653 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2654 "out_height %d\n", in_height, pos_y,
2658 if (!dss_feat_color_mode_supported(plane, color_mode))
2661 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2662 in_height, out_width, out_height, color_mode,
2663 &five_taps, &x_predecim, &y_predecim, pos_x,
2664 rotation_type, mem_to_mem);
2668 in_width = in_width / x_predecim;
2669 in_height = in_height / y_predecim;
2671 if (x_predecim > 1 || y_predecim > 1)
2672 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2673 x_predecim, y_predecim, in_width, in_height);
2675 switch (color_mode) {
2676 case OMAP_DSS_COLOR_YUV2:
2677 case OMAP_DSS_COLOR_UYVY:
2678 case OMAP_DSS_COLOR_NV12:
2680 DSSDBG("predecimated input width is not even for YUV format\n");
2681 DSSDBG("adjusting input width %d -> %d\n",
2682 in_width, in_width & ~1);
2692 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2693 color_mode == OMAP_DSS_COLOR_UYVY ||
2694 color_mode == OMAP_DSS_COLOR_NV12)
2697 if (ilace && !fieldmode) {
2699 * when downscaling the bottom field may have to start several
2700 * source lines below the top field. Unfortunately ACCUI
2701 * registers will only hold the fractional part of the offset
2702 * so the integer part must be added to the base address of the
2705 if (!in_height || in_height == out_height)
2708 field_offset = in_height / out_height / 2;
2711 /* Fields are independent but interleaved in memory. */
2720 if (plane == OMAP_DSS_WB) {
2721 frame_width = out_width;
2722 frame_height = out_height;
2724 frame_width = in_width;
2725 frame_height = height;
2728 if (rotation_type == OMAP_DSS_ROT_TILER)
2729 calc_tiler_rotation_offset(screen_width, frame_width,
2730 color_mode, fieldmode, field_offset,
2731 &offset0, &offset1, &row_inc, &pix_inc,
2732 x_predecim, y_predecim);
2733 else if (rotation_type == OMAP_DSS_ROT_DMA)
2734 calc_dma_rotation_offset(rotation, mirror, screen_width,
2735 frame_width, frame_height,
2736 color_mode, fieldmode, field_offset,
2737 &offset0, &offset1, &row_inc, &pix_inc,
2738 x_predecim, y_predecim);
2740 calc_vrfb_rotation_offset(rotation, mirror,
2741 screen_width, frame_width, frame_height,
2742 color_mode, fieldmode, field_offset,
2743 &offset0, &offset1, &row_inc, &pix_inc,
2744 x_predecim, y_predecim);
2746 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2747 offset0, offset1, row_inc, pix_inc);
2749 dispc_ovl_set_color_mode(plane, color_mode);
2751 dispc_ovl_configure_burst_type(plane, rotation_type);
2753 dispc_ovl_set_ba0(plane, paddr + offset0);
2754 dispc_ovl_set_ba1(plane, paddr + offset1);
2756 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2757 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2758 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2761 if (dispc.feat->last_pixel_inc_missing)
2762 row_inc += pix_inc - 1;
2764 dispc_ovl_set_row_inc(plane, row_inc);
2765 dispc_ovl_set_pix_inc(plane, pix_inc);
2767 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2768 in_height, out_width, out_height);
2770 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2772 dispc_ovl_set_input_size(plane, in_width, in_height);
2774 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2775 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2776 out_height, ilace, five_taps, fieldmode,
2777 color_mode, rotation);
2778 dispc_ovl_set_output_size(plane, out_width, out_height);
2779 dispc_ovl_set_vid_color_conv(plane, cconv);
2782 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2785 dispc_ovl_set_zorder(plane, caps, zorder);
2786 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2787 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2789 dispc_ovl_enable_replication(plane, caps, replication);
2794 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2795 bool replication, const struct omap_video_timings *mgr_timings,
2799 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2800 enum omap_channel channel;
2802 channel = dispc_ovl_get_channel_out(plane);
2804 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2805 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2806 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2807 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2808 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2810 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2811 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2812 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2813 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2814 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2818 EXPORT_SYMBOL(dispc_ovl_setup);
2820 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2821 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2825 enum omap_plane plane = OMAP_DSS_WB;
2826 const int pos_x = 0, pos_y = 0;
2827 const u8 zorder = 0, global_alpha = 0;
2828 const bool replication = false;
2830 int in_width = mgr_timings->x_res;
2831 int in_height = mgr_timings->y_res;
2832 enum omap_overlay_caps caps =
2833 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2835 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2836 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2837 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2840 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2841 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2842 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2843 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2844 replication, mgr_timings, mem_to_mem);
2846 switch (wi->color_mode) {
2847 case OMAP_DSS_COLOR_RGB16:
2848 case OMAP_DSS_COLOR_RGB24P:
2849 case OMAP_DSS_COLOR_ARGB16:
2850 case OMAP_DSS_COLOR_RGBA16:
2851 case OMAP_DSS_COLOR_RGB12U:
2852 case OMAP_DSS_COLOR_ARGB16_1555:
2853 case OMAP_DSS_COLOR_XRGB16_1555:
2854 case OMAP_DSS_COLOR_RGBX16:
2862 /* setup extra DISPC_WB_ATTRIBUTES */
2863 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2864 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2865 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2867 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */
2869 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */
2870 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2874 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2878 wbdelay = min(mgr_timings->vfp + mgr_timings->vsw +
2879 mgr_timings->vbp, 255);
2882 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2888 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2890 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2892 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2896 EXPORT_SYMBOL(dispc_ovl_enable);
2898 bool dispc_ovl_enabled(enum omap_plane plane)
2900 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2902 EXPORT_SYMBOL(dispc_ovl_enabled);
2904 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2906 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2907 /* flush posted write */
2908 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2910 EXPORT_SYMBOL(dispc_mgr_enable);
2912 bool dispc_mgr_is_enabled(enum omap_channel channel)
2914 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2916 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2918 void dispc_wb_enable(bool enable)
2920 dispc_ovl_enable(OMAP_DSS_WB, enable);
2923 bool dispc_wb_is_enabled(void)
2925 return dispc_ovl_enabled(OMAP_DSS_WB);
2928 static void dispc_lcd_enable_signal_polarity(bool act_high)
2930 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2933 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2936 void dispc_lcd_enable_signal(bool enable)
2938 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2941 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2944 void dispc_pck_free_enable(bool enable)
2946 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2949 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2952 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2954 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2958 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2960 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2963 static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2965 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2969 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2971 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2974 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2975 enum omap_dss_trans_key_type type,
2978 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2980 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2983 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2985 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2988 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2991 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2994 if (ch == OMAP_DSS_CHANNEL_LCD)
2995 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2996 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2997 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
3000 void dispc_mgr_setup(enum omap_channel channel,
3001 const struct omap_overlay_manager_info *info)
3003 dispc_mgr_set_default_color(channel, info->default_color);
3004 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
3005 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
3006 dispc_mgr_enable_alpha_fixed_zorder(channel,
3007 info->partial_alpha_enabled);
3008 if (dss_has_feature(FEAT_CPR)) {
3009 dispc_mgr_enable_cpr(channel, info->cpr_enable);
3010 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
3013 EXPORT_SYMBOL(dispc_mgr_setup);
3015 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
3019 switch (data_lines) {
3037 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
3040 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
3046 case DSS_IO_PAD_MODE_RESET:
3050 case DSS_IO_PAD_MODE_RFBI:
3054 case DSS_IO_PAD_MODE_BYPASS:
3063 l = dispc_read_reg(DISPC_CONTROL);
3064 l = FLD_MOD(l, gpout0, 15, 15);
3065 l = FLD_MOD(l, gpout1, 16, 16);
3066 dispc_write_reg(DISPC_CONTROL, l);
3069 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
3071 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
3074 void dispc_mgr_set_lcd_config(enum omap_channel channel,
3075 const struct dss_lcd_mgr_config *config)
3077 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3079 dispc_mgr_enable_stallmode(channel, config->stallmode);
3080 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3082 dispc_mgr_set_clock_div(channel, &config->clock_info);
3084 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3086 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3088 dispc_mgr_set_lcd_type_tft(channel);
3090 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
3092 static bool _dispc_mgr_size_ok(u16 width, u16 height)
3094 return width <= dispc.feat->mgr_width_max &&
3095 height <= dispc.feat->mgr_height_max;
3098 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3099 int vsw, int vfp, int vbp)
3101 if (hsw < 1 || hsw > dispc.feat->sw_max ||
3102 hfp < 1 || hfp > dispc.feat->hp_max ||
3103 hbp < 1 || hbp > dispc.feat->hp_max ||
3104 vsw < 1 || vsw > dispc.feat->sw_max ||
3105 vfp < 0 || vfp > dispc.feat->vp_max ||
3106 vbp < 0 || vbp > dispc.feat->vp_max)
3111 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3114 if (dss_mgr_is_lcd(channel))
3115 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3117 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3120 bool dispc_mgr_timings_ok(enum omap_channel channel,
3121 const struct omap_video_timings *timings)
3123 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3126 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3129 if (dss_mgr_is_lcd(channel)) {
3130 /* TODO: OMAP4+ supports interlace for LCD outputs */
3131 if (timings->interlace)
3134 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
3135 timings->hbp, timings->vsw, timings->vfp,
3143 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3144 int hfp, int hbp, int vsw, int vfp, int vbp,
3145 enum omap_dss_signal_level vsync_level,
3146 enum omap_dss_signal_level hsync_level,
3147 enum omap_dss_signal_edge data_pclk_edge,
3148 enum omap_dss_signal_level de_level,
3149 enum omap_dss_signal_edge sync_pclk_edge)
3152 u32 timing_h, timing_v, l;
3153 bool onoff, rf, ipc, vs, hs, de;
3155 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3156 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3157 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3158 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3159 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3160 FLD_VAL(vbp, dispc.feat->bp_start, 20);
3162 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3163 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3165 switch (vsync_level) {
3166 case OMAPDSS_SIG_ACTIVE_LOW:
3169 case OMAPDSS_SIG_ACTIVE_HIGH:
3176 switch (hsync_level) {
3177 case OMAPDSS_SIG_ACTIVE_LOW:
3180 case OMAPDSS_SIG_ACTIVE_HIGH:
3188 case OMAPDSS_SIG_ACTIVE_LOW:
3191 case OMAPDSS_SIG_ACTIVE_HIGH:
3198 switch (data_pclk_edge) {
3199 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3202 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3209 /* always use the 'rf' setting */
3212 switch (sync_pclk_edge) {
3213 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3216 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3223 l = FLD_VAL(onoff, 17, 17) |
3224 FLD_VAL(rf, 16, 16) |
3225 FLD_VAL(de, 15, 15) |
3226 FLD_VAL(ipc, 14, 14) |
3227 FLD_VAL(hs, 13, 13) |
3228 FLD_VAL(vs, 12, 12);
3230 /* always set ALIGN bit when available */
3231 if (dispc.feat->supports_sync_align)
3234 dispc_write_reg(DISPC_POL_FREQ(channel), l);
3236 if (dispc.syscon_pol) {
3237 const int shifts[] = {
3238 [OMAP_DSS_CHANNEL_LCD] = 0,
3239 [OMAP_DSS_CHANNEL_LCD2] = 1,
3240 [OMAP_DSS_CHANNEL_LCD3] = 2,
3245 mask = (1 << 0) | (1 << 3) | (1 << 6);
3246 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3248 mask <<= 16 + shifts[channel];
3249 val <<= 16 + shifts[channel];
3251 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3256 /* change name to mode? */
3257 void dispc_mgr_set_timings(enum omap_channel channel,
3258 const struct omap_video_timings *timings)
3260 unsigned xtot, ytot;
3261 unsigned long ht, vt;
3262 struct omap_video_timings t = *timings;
3264 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3266 if (!dispc_mgr_timings_ok(channel, &t)) {
3271 if (dss_mgr_is_lcd(channel)) {
3272 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3273 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3274 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3276 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3277 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3279 ht = timings->pixelclock / xtot;
3280 vt = timings->pixelclock / xtot / ytot;
3282 DSSDBG("pck %u\n", timings->pixelclock);
3283 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3284 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3285 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3286 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3287 t.de_level, t.sync_pclk_edge);
3289 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3295 dispc_mgr_set_size(channel, t.x_res, t.y_res);
3297 EXPORT_SYMBOL(dispc_mgr_set_timings);
3299 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3302 BUG_ON(lck_div < 1);
3303 BUG_ON(pck_div < 1);
3305 dispc_write_reg(DISPC_DIVISORo(channel),
3306 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3308 if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
3309 channel == OMAP_DSS_CHANNEL_LCD)
3310 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3313 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3317 l = dispc_read_reg(DISPC_DIVISORo(channel));
3318 *lck_div = FLD_GET(l, 23, 16);
3319 *pck_div = FLD_GET(l, 7, 0);
3322 static unsigned long dispc_fclk_rate(void)
3324 struct dss_pll *pll;
3325 unsigned long r = 0;
3327 switch (dss_get_dispc_clk_source()) {
3328 case OMAP_DSS_CLK_SRC_FCK:
3329 r = dss_get_dispc_clk_rate();
3331 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3332 pll = dss_pll_find("dsi0");
3334 pll = dss_pll_find("video0");
3336 r = pll->cinfo.clkout[0];
3338 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3339 pll = dss_pll_find("dsi1");
3341 pll = dss_pll_find("video1");
3343 r = pll->cinfo.clkout[0];
3353 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3355 struct dss_pll *pll;
3360 if (dss_mgr_is_lcd(channel)) {
3361 l = dispc_read_reg(DISPC_DIVISORo(channel));
3363 lcd = FLD_GET(l, 23, 16);
3365 switch (dss_get_lcd_clk_source(channel)) {
3366 case OMAP_DSS_CLK_SRC_FCK:
3367 r = dss_get_dispc_clk_rate();
3369 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3370 pll = dss_pll_find("dsi0");
3372 pll = dss_pll_find("video0");
3374 r = pll->cinfo.clkout[0];
3376 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3377 pll = dss_pll_find("dsi1");
3379 pll = dss_pll_find("video1");
3381 r = pll->cinfo.clkout[0];
3390 return dispc_fclk_rate();
3394 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3398 if (dss_mgr_is_lcd(channel)) {
3402 l = dispc_read_reg(DISPC_DIVISORo(channel));
3404 pcd = FLD_GET(l, 7, 0);
3406 r = dispc_mgr_lclk_rate(channel);
3410 return dispc.tv_pclk_rate;
3414 void dispc_set_tv_pclk(unsigned long pclk)
3416 dispc.tv_pclk_rate = pclk;
3419 static unsigned long dispc_core_clk_rate(void)
3421 return dispc.core_clk_rate;
3424 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3426 enum omap_channel channel;
3428 if (plane == OMAP_DSS_WB)
3431 channel = dispc_ovl_get_channel_out(plane);
3433 return dispc_mgr_pclk_rate(channel);
3436 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3438 enum omap_channel channel;
3440 if (plane == OMAP_DSS_WB)
3443 channel = dispc_ovl_get_channel_out(plane);
3445 return dispc_mgr_lclk_rate(channel);
3448 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3451 enum omap_dss_clk_source lcd_clk_src;
3453 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3455 lcd_clk_src = dss_get_lcd_clk_source(channel);
3457 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3458 dss_get_generic_clk_source_name(lcd_clk_src),
3459 dss_feat_get_clk_source_name(lcd_clk_src));
3461 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3463 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3464 dispc_mgr_lclk_rate(channel), lcd);
3465 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3466 dispc_mgr_pclk_rate(channel), pcd);
3469 void dispc_dump_clocks(struct seq_file *s)
3473 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3475 if (dispc_runtime_get())
3478 seq_printf(s, "- DISPC -\n");
3480 seq_printf(s, "dispc fclk source = %s (%s)\n",
3481 dss_get_generic_clk_source_name(dispc_clk_src),
3482 dss_feat_get_clk_source_name(dispc_clk_src));
3484 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3486 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3487 seq_printf(s, "- DISPC-CORE-CLK -\n");
3488 l = dispc_read_reg(DISPC_DIVISOR);
3489 lcd = FLD_GET(l, 23, 16);
3491 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3492 (dispc_fclk_rate()/lcd), lcd);
3495 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3497 if (dss_has_feature(FEAT_MGR_LCD2))
3498 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3499 if (dss_has_feature(FEAT_MGR_LCD3))
3500 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3502 dispc_runtime_put();
3505 static void dispc_dump_regs(struct seq_file *s)
3508 const char *mgr_names[] = {
3509 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3510 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3511 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3512 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3514 const char *ovl_names[] = {
3515 [OMAP_DSS_GFX] = "GFX",
3516 [OMAP_DSS_VIDEO1] = "VID1",
3517 [OMAP_DSS_VIDEO2] = "VID2",
3518 [OMAP_DSS_VIDEO3] = "VID3",
3519 [OMAP_DSS_WB] = "WB",
3521 const char **p_names;
3523 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3525 if (dispc_runtime_get())
3528 /* DISPC common registers */
3529 DUMPREG(DISPC_REVISION);
3530 DUMPREG(DISPC_SYSCONFIG);
3531 DUMPREG(DISPC_SYSSTATUS);
3532 DUMPREG(DISPC_IRQSTATUS);
3533 DUMPREG(DISPC_IRQENABLE);
3534 DUMPREG(DISPC_CONTROL);
3535 DUMPREG(DISPC_CONFIG);
3536 DUMPREG(DISPC_CAPABLE);
3537 DUMPREG(DISPC_LINE_STATUS);
3538 DUMPREG(DISPC_LINE_NUMBER);
3539 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3540 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3541 DUMPREG(DISPC_GLOBAL_ALPHA);
3542 if (dss_has_feature(FEAT_MGR_LCD2)) {
3543 DUMPREG(DISPC_CONTROL2);
3544 DUMPREG(DISPC_CONFIG2);
3546 if (dss_has_feature(FEAT_MGR_LCD3)) {
3547 DUMPREG(DISPC_CONTROL3);
3548 DUMPREG(DISPC_CONFIG3);
3550 if (dss_has_feature(FEAT_MFLAG))
3551 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3555 #define DISPC_REG(i, name) name(i)
3556 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3557 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3558 dispc_read_reg(DISPC_REG(i, r)))
3560 p_names = mgr_names;
3562 /* DISPC channel specific registers */
3563 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3564 DUMPREG(i, DISPC_DEFAULT_COLOR);
3565 DUMPREG(i, DISPC_TRANS_COLOR);
3566 DUMPREG(i, DISPC_SIZE_MGR);
3568 if (i == OMAP_DSS_CHANNEL_DIGIT)
3571 DUMPREG(i, DISPC_TIMING_H);
3572 DUMPREG(i, DISPC_TIMING_V);
3573 DUMPREG(i, DISPC_POL_FREQ);
3574 DUMPREG(i, DISPC_DIVISORo);
3576 DUMPREG(i, DISPC_DATA_CYCLE1);
3577 DUMPREG(i, DISPC_DATA_CYCLE2);
3578 DUMPREG(i, DISPC_DATA_CYCLE3);
3580 if (dss_has_feature(FEAT_CPR)) {
3581 DUMPREG(i, DISPC_CPR_COEF_R);
3582 DUMPREG(i, DISPC_CPR_COEF_G);
3583 DUMPREG(i, DISPC_CPR_COEF_B);
3587 p_names = ovl_names;
3589 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3590 DUMPREG(i, DISPC_OVL_BA0);
3591 DUMPREG(i, DISPC_OVL_BA1);
3592 DUMPREG(i, DISPC_OVL_POSITION);
3593 DUMPREG(i, DISPC_OVL_SIZE);
3594 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3595 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3596 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3597 DUMPREG(i, DISPC_OVL_ROW_INC);
3598 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3600 if (dss_has_feature(FEAT_PRELOAD))
3601 DUMPREG(i, DISPC_OVL_PRELOAD);
3602 if (dss_has_feature(FEAT_MFLAG))
3603 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3605 if (i == OMAP_DSS_GFX) {
3606 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3607 DUMPREG(i, DISPC_OVL_TABLE_BA);
3611 DUMPREG(i, DISPC_OVL_FIR);
3612 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3613 DUMPREG(i, DISPC_OVL_ACCU0);
3614 DUMPREG(i, DISPC_OVL_ACCU1);
3615 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3616 DUMPREG(i, DISPC_OVL_BA0_UV);
3617 DUMPREG(i, DISPC_OVL_BA1_UV);
3618 DUMPREG(i, DISPC_OVL_FIR2);
3619 DUMPREG(i, DISPC_OVL_ACCU2_0);
3620 DUMPREG(i, DISPC_OVL_ACCU2_1);
3622 if (dss_has_feature(FEAT_ATTR2))
3623 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3626 if (dispc.feat->has_writeback) {
3628 DUMPREG(i, DISPC_OVL_BA0);
3629 DUMPREG(i, DISPC_OVL_BA1);
3630 DUMPREG(i, DISPC_OVL_SIZE);
3631 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3632 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3633 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3634 DUMPREG(i, DISPC_OVL_ROW_INC);
3635 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3637 if (dss_has_feature(FEAT_MFLAG))
3638 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3640 DUMPREG(i, DISPC_OVL_FIR);
3641 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3642 DUMPREG(i, DISPC_OVL_ACCU0);
3643 DUMPREG(i, DISPC_OVL_ACCU1);
3644 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3645 DUMPREG(i, DISPC_OVL_BA0_UV);
3646 DUMPREG(i, DISPC_OVL_BA1_UV);
3647 DUMPREG(i, DISPC_OVL_FIR2);
3648 DUMPREG(i, DISPC_OVL_ACCU2_0);
3649 DUMPREG(i, DISPC_OVL_ACCU2_1);
3651 if (dss_has_feature(FEAT_ATTR2))
3652 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3658 #define DISPC_REG(plane, name, i) name(plane, i)
3659 #define DUMPREG(plane, name, i) \
3660 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3661 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3662 dispc_read_reg(DISPC_REG(plane, name, i)))
3664 /* Video pipeline coefficient registers */
3666 /* start from OMAP_DSS_VIDEO1 */
3667 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3668 for (j = 0; j < 8; j++)
3669 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3671 for (j = 0; j < 8; j++)
3672 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3674 for (j = 0; j < 5; j++)
3675 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3677 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3678 for (j = 0; j < 8; j++)
3679 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3682 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3683 for (j = 0; j < 8; j++)
3684 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3686 for (j = 0; j < 8; j++)
3687 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3689 for (j = 0; j < 8; j++)
3690 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3694 dispc_runtime_put();
3700 /* calculate clock rates using dividers in cinfo */
3701 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3702 struct dispc_clock_info *cinfo)
3704 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3706 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3709 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3710 cinfo->pck = cinfo->lck / cinfo->pck_div;
3715 bool dispc_div_calc(unsigned long dispc,
3716 unsigned long pck_min, unsigned long pck_max,
3717 dispc_div_calc_func func, void *data)
3719 int lckd, lckd_start, lckd_stop;
3720 int pckd, pckd_start, pckd_stop;
3721 unsigned long pck, lck;
3722 unsigned long lck_max;
3723 unsigned long pckd_hw_min, pckd_hw_max;
3724 unsigned min_fck_per_pck;
3727 #ifdef CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK
3728 min_fck_per_pck = CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK;
3730 min_fck_per_pck = 0;
3733 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3734 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3736 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3738 pck_min = pck_min ? pck_min : 1;
3739 pck_max = pck_max ? pck_max : ULONG_MAX;
3741 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3742 lckd_stop = min(dispc / pck_min, 255ul);
3744 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3747 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3748 pckd_stop = min(lck / pck_min, pckd_hw_max);
3750 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3754 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3755 * clock, which means we're configuring DISPC fclk here
3756 * also. Thus we need to use the calculated lck. For
3757 * OMAP4+ the DISPC fclk is a separate clock.
3759 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3760 fck = dispc_core_clk_rate();
3764 if (fck < pck * min_fck_per_pck)
3767 if (func(lckd, pckd, lck, pck, data))
3775 void dispc_mgr_set_clock_div(enum omap_channel channel,
3776 const struct dispc_clock_info *cinfo)
3778 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3779 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3781 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3784 int dispc_mgr_get_clock_div(enum omap_channel channel,
3785 struct dispc_clock_info *cinfo)
3789 fck = dispc_fclk_rate();
3791 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3792 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3794 cinfo->lck = fck / cinfo->lck_div;
3795 cinfo->pck = cinfo->lck / cinfo->pck_div;
3800 u32 dispc_read_irqstatus(void)
3802 return dispc_read_reg(DISPC_IRQSTATUS);
3804 EXPORT_SYMBOL(dispc_read_irqstatus);
3806 void dispc_clear_irqstatus(u32 mask)
3808 dispc_write_reg(DISPC_IRQSTATUS, mask);
3810 EXPORT_SYMBOL(dispc_clear_irqstatus);
3812 u32 dispc_read_irqenable(void)
3814 return dispc_read_reg(DISPC_IRQENABLE);
3816 EXPORT_SYMBOL(dispc_read_irqenable);
3818 void dispc_write_irqenable(u32 mask)
3820 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3822 /* clear the irqstatus for newly enabled irqs */
3823 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3825 dispc_write_reg(DISPC_IRQENABLE, mask);
3827 EXPORT_SYMBOL(dispc_write_irqenable);
3829 void dispc_enable_sidle(void)
3831 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3834 void dispc_disable_sidle(void)
3836 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3839 static void _omap_dispc_initial_config(void)
3843 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3844 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3845 l = dispc_read_reg(DISPC_DIVISOR);
3846 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3847 l = FLD_MOD(l, 1, 0, 0);
3848 l = FLD_MOD(l, 1, 23, 16);
3849 dispc_write_reg(DISPC_DIVISOR, l);
3851 dispc.core_clk_rate = dispc_fclk_rate();
3855 if (dss_has_feature(FEAT_FUNCGATED))
3856 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3858 dispc_setup_color_conv_coef();
3860 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3864 dispc_configure_burst_sizes();
3866 dispc_ovl_enable_zorder_planes();
3868 if (dispc.feat->mstandby_workaround)
3869 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3871 if (dss_has_feature(FEAT_MFLAG))
3875 static const struct dispc_features omap24xx_dispc_feats = {
3882 .mgr_width_start = 10,
3883 .mgr_height_start = 26,
3884 .mgr_width_max = 2048,
3885 .mgr_height_max = 2048,
3886 .max_lcd_pclk = 66500000,
3887 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3888 .calc_core_clk = calc_core_clk_24xx,
3890 .no_framedone_tv = true,
3891 .set_max_preload = false,
3892 .last_pixel_inc_missing = true,
3895 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
3902 .mgr_width_start = 10,
3903 .mgr_height_start = 26,
3904 .mgr_width_max = 2048,
3905 .mgr_height_max = 2048,
3906 .max_lcd_pclk = 173000000,
3907 .max_tv_pclk = 59000000,
3908 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3909 .calc_core_clk = calc_core_clk_34xx,
3911 .no_framedone_tv = true,
3912 .set_max_preload = false,
3913 .last_pixel_inc_missing = true,
3916 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
3923 .mgr_width_start = 10,
3924 .mgr_height_start = 26,
3925 .mgr_width_max = 2048,
3926 .mgr_height_max = 2048,
3927 .max_lcd_pclk = 173000000,
3928 .max_tv_pclk = 59000000,
3929 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3930 .calc_core_clk = calc_core_clk_34xx,
3932 .no_framedone_tv = true,
3933 .set_max_preload = false,
3934 .last_pixel_inc_missing = true,
3937 static const struct dispc_features omap44xx_dispc_feats = {
3944 .mgr_width_start = 10,
3945 .mgr_height_start = 26,
3946 .mgr_width_max = 2048,
3947 .mgr_height_max = 2048,
3948 .max_lcd_pclk = 170000000,
3949 .max_tv_pclk = 185625000,
3950 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3951 .calc_core_clk = calc_core_clk_44xx,
3953 .gfx_fifo_workaround = true,
3954 .set_max_preload = true,
3955 .supports_sync_align = true,
3956 .has_writeback = true,
3959 static const struct dispc_features omap54xx_dispc_feats = {
3966 .mgr_width_start = 11,
3967 .mgr_height_start = 27,
3968 .mgr_width_max = 4096,
3969 .mgr_height_max = 4096,
3970 .max_lcd_pclk = 170000000,
3971 .max_tv_pclk = 186000000,
3972 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3973 .calc_core_clk = calc_core_clk_44xx,
3975 .gfx_fifo_workaround = true,
3976 .mstandby_workaround = true,
3977 .set_max_preload = true,
3978 .supports_sync_align = true,
3979 .has_writeback = true,
3982 static int dispc_init_features(struct platform_device *pdev)
3984 const struct dispc_features *src;
3985 struct dispc_features *dst;
3987 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3989 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3993 switch (omapdss_get_version()) {
3994 case OMAPDSS_VER_OMAP24xx:
3995 src = &omap24xx_dispc_feats;
3998 case OMAPDSS_VER_OMAP34xx_ES1:
3999 src = &omap34xx_rev1_0_dispc_feats;
4002 case OMAPDSS_VER_OMAP34xx_ES3:
4003 case OMAPDSS_VER_OMAP3630:
4004 case OMAPDSS_VER_AM35xx:
4005 case OMAPDSS_VER_AM43xx:
4006 src = &omap34xx_rev3_0_dispc_feats;
4009 case OMAPDSS_VER_OMAP4430_ES1:
4010 case OMAPDSS_VER_OMAP4430_ES2:
4011 case OMAPDSS_VER_OMAP4:
4012 src = &omap44xx_dispc_feats;
4015 case OMAPDSS_VER_OMAP5:
4016 case OMAPDSS_VER_DRA7xx:
4017 src = &omap54xx_dispc_feats;
4024 memcpy(dst, src, sizeof(*dst));
4030 static irqreturn_t dispc_irq_handler(int irq, void *arg)
4032 if (!dispc.is_enabled)
4035 return dispc.user_handler(irq, dispc.user_data);
4038 int dispc_request_irq(irq_handler_t handler, void *dev_id)
4042 if (dispc.user_handler != NULL)
4045 dispc.user_handler = handler;
4046 dispc.user_data = dev_id;
4048 /* ensure the dispc_irq_handler sees the values above */
4051 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4052 IRQF_SHARED, "OMAP DISPC", &dispc);
4054 dispc.user_handler = NULL;
4055 dispc.user_data = NULL;
4060 EXPORT_SYMBOL(dispc_request_irq);
4062 void dispc_free_irq(void *dev_id)
4064 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4066 dispc.user_handler = NULL;
4067 dispc.user_data = NULL;
4069 EXPORT_SYMBOL(dispc_free_irq);
4071 /* DISPC HW IP initialisation */
4072 static int dispc_bind(struct device *dev, struct device *master, void *data)
4074 struct platform_device *pdev = to_platform_device(dev);
4077 struct resource *dispc_mem;
4078 struct device_node *np = pdev->dev.of_node;
4082 spin_lock_init(&dispc.control_lock);
4084 r = dispc_init_features(dispc.pdev);
4088 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4090 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4094 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4095 resource_size(dispc_mem));
4097 DSSERR("can't ioremap DISPC\n");
4101 dispc.irq = platform_get_irq(dispc.pdev, 0);
4102 if (dispc.irq < 0) {
4103 DSSERR("platform_get_irq failed\n");
4107 if (np && of_property_read_bool(np, "syscon-pol")) {
4108 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4109 if (IS_ERR(dispc.syscon_pol)) {
4110 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4111 return PTR_ERR(dispc.syscon_pol);
4114 if (of_property_read_u32_index(np, "syscon-pol", 1,
4115 &dispc.syscon_pol_offset)) {
4116 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4121 pm_runtime_enable(&pdev->dev);
4123 r = dispc_runtime_get();
4125 goto err_runtime_get;
4127 _omap_dispc_initial_config();
4129 rev = dispc_read_reg(DISPC_REVISION);
4130 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4131 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4133 dispc_runtime_put();
4135 dss_init_overlay_managers();
4137 dss_debugfs_create_file("dispc", dispc_dump_regs);
4142 pm_runtime_disable(&pdev->dev);
4146 static void dispc_unbind(struct device *dev, struct device *master,
4149 pm_runtime_disable(dev);
4151 dss_uninit_overlay_managers();
4154 static const struct component_ops dispc_component_ops = {
4156 .unbind = dispc_unbind,
4159 static int dispc_probe(struct platform_device *pdev)
4161 return component_add(&pdev->dev, &dispc_component_ops);
4164 static int dispc_remove(struct platform_device *pdev)
4166 component_del(&pdev->dev, &dispc_component_ops);
4170 static int dispc_runtime_suspend(struct device *dev)
4172 dispc.is_enabled = false;
4173 /* ensure the dispc_irq_handler sees the is_enabled value */
4175 /* wait for current handler to finish before turning the DISPC off */
4176 synchronize_irq(dispc.irq);
4178 dispc_save_context();
4183 static int dispc_runtime_resume(struct device *dev)
4186 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4187 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4188 * _omap_dispc_initial_config(). We can thus use it to detect if
4189 * we have lost register context.
4191 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4192 _omap_dispc_initial_config();
4194 dispc_restore_context();
4197 dispc.is_enabled = true;
4198 /* ensure the dispc_irq_handler sees the is_enabled value */
4204 static const struct dev_pm_ops dispc_pm_ops = {
4205 .runtime_suspend = dispc_runtime_suspend,
4206 .runtime_resume = dispc_runtime_resume,
4209 static const struct of_device_id dispc_of_match[] = {
4210 { .compatible = "ti,omap2-dispc", },
4211 { .compatible = "ti,omap3-dispc", },
4212 { .compatible = "ti,omap4-dispc", },
4213 { .compatible = "ti,omap5-dispc", },
4214 { .compatible = "ti,dra7-dispc", },
4218 static struct platform_driver omap_dispchw_driver = {
4219 .probe = dispc_probe,
4220 .remove = dispc_remove,
4222 .name = "omapdss_dispc",
4223 .pm = &dispc_pm_ops,
4224 .of_match_table = dispc_of_match,
4225 .suppress_bind_attrs = true,
4229 int __init dispc_init_platform_driver(void)
4231 return platform_driver_register(&omap_dispchw_driver);
4234 void dispc_uninit_platform_driver(void)
4236 platform_driver_unregister(&omap_dispchw_driver);