drivers/video/fbdev/omap2/omapfb/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/delay.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/sizes.h>
  39 #include <linux/mfd/syscon.h>
  40 #include <linux/regmap.h>
  41 #include <linux/of.h>
  42 #include <linux/component.h>
  43
  44 #include <video/omapfb_dss.h>
  45
  46 #include "dss.h"
  47 #include "dss_features.h"
  48 #include "dispc.h"
  49
  50 /* DISPC */
  51 #define DISPC_SZ_REGS                   SZ_4K
  52
  53 enum omap_burst_size {
  54         BURST_SIZE_X2 = 0,
  55         BURST_SIZE_X4 = 1,
  56         BURST_SIZE_X8 = 2,
  57 };
  58
  59 #define REG_GET(idx, start, end) \
  60         FLD_GET(dispc_read_reg(idx), start, end)
  61
  62 #define REG_FLD_MOD(idx, val, start, end)                               \
  63         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  64
  65 struct dispc_features {
  66         u8 sw_start;
  67         u8 fp_start;
  68         u8 bp_start;
  69         u16 sw_max;
  70         u16 vp_max;
  71         u16 hp_max;
  72         u8 mgr_width_start;
  73         u8 mgr_height_start;
  74         u16 mgr_width_max;
  75         u16 mgr_height_max;
  76         unsigned long max_lcd_pclk;
  77         unsigned long max_tv_pclk;
  78         int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
  79                 const struct omap_video_timings *mgr_timings,
  80                 u16 width, u16 height, u16 out_width, u16 out_height,
  81                 enum omap_color_mode color_mode, bool *five_taps,
  82                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
  83                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
  84         unsigned long (*calc_core_clk) (unsigned long pclk,
  85                 u16 width, u16 height, u16 out_width, u16 out_height,
  86                 bool mem_to_mem);
  87         u8 num_fifos;
  88
  89         /* swap GFX & WB fifos */
  90         bool gfx_fifo_workaround:1;
  91
  92         /* no DISPC_IRQ_FRAMEDONETV on this SoC */
  93         bool no_framedone_tv:1;
  94
  95         /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
  96         bool mstandby_workaround:1;
  97
  98         bool set_max_preload:1;
  99
 100         /* PIXEL_INC is not added to the last pixel of a line */
 101         bool last_pixel_inc_missing:1;
 102
 103         /* POL_FREQ has ALIGN bit */
 104         bool supports_sync_align:1;
 105
 106         bool has_writeback:1;
 107 };
 108
 109 #define DISPC_MAX_NR_FIFOS 5
 110
 111 static struct {
 112         struct platform_device *pdev;
 113         void __iomem    *base;
 114
 115         int irq;
 116         irq_handler_t user_handler;
 117         void *user_data;
 118
 119         unsigned long core_clk_rate;
 120         unsigned long tv_pclk_rate;
 121
 122         u32 fifo_size[DISPC_MAX_NR_FIFOS];
 123         /* maps which plane is using a fifo. fifo-id -> plane-id */
 124         int fifo_assignment[DISPC_MAX_NR_FIFOS];
 125
 126         bool            ctx_valid;
 127         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 128
 129         const struct dispc_features *feat;
 130
 131         bool is_enabled;
 132
 133         struct regmap *syscon_pol;
 134         u32 syscon_pol_offset;
 135
 136         /* DISPC_CONTROL & DISPC_CONFIG lock*/
 137         spinlock_t control_lock;
 138 } dispc;
 139
 140 enum omap_color_component {
 141         /* used for all color formats for OMAP3 and earlier
 142          * and for RGB and Y color component on OMAP4
 143          */
 144         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 145         /* used for UV component for
 146          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 147          * color formats on OMAP4
 148          */
 149         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 150 };
 151
 152 enum mgr_reg_fields {
 153         DISPC_MGR_FLD_ENABLE,
 154         DISPC_MGR_FLD_STNTFT,
 155         DISPC_MGR_FLD_GO,
 156         DISPC_MGR_FLD_TFTDATALINES,
 157         DISPC_MGR_FLD_STALLMODE,
 158         DISPC_MGR_FLD_TCKENABLE,
 159         DISPC_MGR_FLD_TCKSELECTION,
 160         DISPC_MGR_FLD_CPR,
 161         DISPC_MGR_FLD_FIFOHANDCHECK,
 162         /* used to maintain a count of the above fields */
 163         DISPC_MGR_FLD_NUM,
 164 };
 165
 166 struct dispc_reg_field {
 167         u16 reg;
 168         u8 high;
 169         u8 low;
 170 };
 171
 172 static const struct {
 173         const char *name;
 174         u32 vsync_irq;
 175         u32 framedone_irq;
 176         u32 sync_lost_irq;
 177         struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
 178 } mgr_desc[] = {
 179         [OMAP_DSS_CHANNEL_LCD] = {
 180                 .name           = "LCD",
 181                 .vsync_irq      = DISPC_IRQ_VSYNC,
 182                 .framedone_irq  = DISPC_IRQ_FRAMEDONE,
 183                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST,
 184                 .reg_desc       = {
 185                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  0,  0 },
 186                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL,  3,  3 },
 187                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  5,  5 },
 188                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL,  9,  8 },
 189                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL, 11, 11 },
 190                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  10, 10 },
 191                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  11, 11 },
 192                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG,  15, 15 },
 193                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 194                 },
 195         },
 196         [OMAP_DSS_CHANNEL_DIGIT] = {
 197                 .name           = "DIGIT",
 198                 .vsync_irq      = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
 199                 .framedone_irq  = DISPC_IRQ_FRAMEDONETV,
 200                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST_DIGIT,
 201                 .reg_desc       = {
 202                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  1,  1 },
 203                         [DISPC_MGR_FLD_STNTFT]          = { },
 204                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  6,  6 },
 205                         [DISPC_MGR_FLD_TFTDATALINES]    = { },
 206                         [DISPC_MGR_FLD_STALLMODE]       = { },
 207                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  12, 12 },
 208                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  13, 13 },
 209                         [DISPC_MGR_FLD_CPR]             = { },
 210                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 211                 },
 212         },
 213         [OMAP_DSS_CHANNEL_LCD2] = {
 214                 .name           = "LCD2",
 215                 .vsync_irq      = DISPC_IRQ_VSYNC2,
 216                 .framedone_irq  = DISPC_IRQ_FRAMEDONE2,
 217                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST2,
 218                 .reg_desc       = {
 219                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL2,  0,  0 },
 220                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL2,  3,  3 },
 221                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL2,  5,  5 },
 222                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL2,  9,  8 },
 223                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL2, 11, 11 },
 224                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG2,  10, 10 },
 225                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG2,  11, 11 },
 226                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG2,  15, 15 },
 227                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG2,  16, 16 },
 228                 },
 229         },
 230         [OMAP_DSS_CHANNEL_LCD3] = {
 231                 .name           = "LCD3",
 232                 .vsync_irq      = DISPC_IRQ_VSYNC3,
 233                 .framedone_irq  = DISPC_IRQ_FRAMEDONE3,
 234                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST3,
 235                 .reg_desc       = {
 236                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL3,  0,  0 },
 237                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL3,  3,  3 },
 238                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL3,  5,  5 },
 239                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL3,  9,  8 },
 240                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL3, 11, 11 },
 241                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG3,  10, 10 },
 242                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG3,  11, 11 },
 243                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG3,  15, 15 },
 244                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG3,  16, 16 },
 245                 },
 246         },
 247 };
 248
 249 struct color_conv_coef {
 250         int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
 251         int full_range;
 252 };
 253
 254 static unsigned long dispc_fclk_rate(void);
 255 static unsigned long dispc_core_clk_rate(void);
 256 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 257 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 258
 259 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
 260 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
 261
 262 static inline void dispc_write_reg(const u16 idx, u32 val)
 263 {
 264         __raw_writel(val, dispc.base + idx);
 265 }
 266
 267 static inline u32 dispc_read_reg(const u16 idx)
 268 {
 269         return __raw_readl(dispc.base + idx);
 270 }
 271
 272 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
 273 {
 274         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 275         return REG_GET(rfld.reg, rfld.high, rfld.low);
 276 }
 277
 278 static void mgr_fld_write(enum omap_channel channel,
 279                                         enum mgr_reg_fields regfld, int val) {
 280         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 281         const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
 282         unsigned long flags;
 283
 284         if (need_lock)
 285                 spin_lock_irqsave(&dispc.control_lock, flags);
 286
 287         REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
 288
 289         if (need_lock)
 290                 spin_unlock_irqrestore(&dispc.control_lock, flags);
 291 }
 292
 293 #define SR(reg) \
 294         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 295 #define RR(reg) \
 296         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 297
 298 static void dispc_save_context(void)
 299 {
 300         int i, j;
 301
 302         DSSDBG("dispc_save_context\n");
 303
 304         SR(IRQENABLE);
 305         SR(CONTROL);
 306         SR(CONFIG);
 307         SR(LINE_NUMBER);
 308         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 309                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 310                 SR(GLOBAL_ALPHA);
 311         if (dss_has_feature(FEAT_MGR_LCD2)) {
 312                 SR(CONTROL2);
 313                 SR(CONFIG2);
 314         }
 315         if (dss_has_feature(FEAT_MGR_LCD3)) {
 316                 SR(CONTROL3);
 317                 SR(CONFIG3);
 318         }
 319
 320         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 321                 SR(DEFAULT_COLOR(i));
 322                 SR(TRANS_COLOR(i));
 323                 SR(SIZE_MGR(i));
 324                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 325                         continue;
 326                 SR(TIMING_H(i));
 327                 SR(TIMING_V(i));
 328                 SR(POL_FREQ(i));
 329                 SR(DIVISORo(i));
 330
 331                 SR(DATA_CYCLE1(i));
 332                 SR(DATA_CYCLE2(i));
 333                 SR(DATA_CYCLE3(i));
 334
 335                 if (dss_has_feature(FEAT_CPR)) {
 336                         SR(CPR_COEF_R(i));
 337                         SR(CPR_COEF_G(i));
 338                         SR(CPR_COEF_B(i));
 339                 }
 340         }
 341
 342         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 343                 SR(OVL_BA0(i));
 344                 SR(OVL_BA1(i));
 345                 SR(OVL_POSITION(i));
 346                 SR(OVL_SIZE(i));
 347                 SR(OVL_ATTRIBUTES(i));
 348                 SR(OVL_FIFO_THRESHOLD(i));
 349                 SR(OVL_ROW_INC(i));
 350                 SR(OVL_PIXEL_INC(i));
 351                 if (dss_has_feature(FEAT_PRELOAD))
 352                         SR(OVL_PRELOAD(i));
 353                 if (i == OMAP_DSS_GFX) {
 354                         SR(OVL_WINDOW_SKIP(i));
 355                         SR(OVL_TABLE_BA(i));
 356                         continue;
 357                 }
 358                 SR(OVL_FIR(i));
 359                 SR(OVL_PICTURE_SIZE(i));
 360                 SR(OVL_ACCU0(i));
 361                 SR(OVL_ACCU1(i));
 362
 363                 for (j = 0; j < 8; j++)
 364                         SR(OVL_FIR_COEF_H(i, j));
 365
 366                 for (j = 0; j < 8; j++)
 367                         SR(OVL_FIR_COEF_HV(i, j));
 368
 369                 for (j = 0; j < 5; j++)
 370                         SR(OVL_CONV_COEF(i, j));
 371
 372                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 373                         for (j = 0; j < 8; j++)
 374                                 SR(OVL_FIR_COEF_V(i, j));
 375                 }
 376
 377                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 378                         SR(OVL_BA0_UV(i));
 379                         SR(OVL_BA1_UV(i));
 380                         SR(OVL_FIR2(i));
 381                         SR(OVL_ACCU2_0(i));
 382                         SR(OVL_ACCU2_1(i));
 383
 384                         for (j = 0; j < 8; j++)
 385                                 SR(OVL_FIR_COEF_H2(i, j));
 386
 387                         for (j = 0; j < 8; j++)
 388                                 SR(OVL_FIR_COEF_HV2(i, j));
 389
 390                         for (j = 0; j < 8; j++)
 391                                 SR(OVL_FIR_COEF_V2(i, j));
 392                 }
 393                 if (dss_has_feature(FEAT_ATTR2))
 394                         SR(OVL_ATTRIBUTES2(i));
 395         }
 396
 397         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 398                 SR(DIVISOR);
 399
 400         dispc.ctx_valid = true;
 401
 402         DSSDBG("context saved\n");
 403 }
 404
 405 static void dispc_restore_context(void)
 406 {
 407         int i, j;
 408
 409         DSSDBG("dispc_restore_context\n");
 410
 411         if (!dispc.ctx_valid)
 412                 return;
 413
 414         /*RR(IRQENABLE);*/
 415         /*RR(CONTROL);*/
 416         RR(CONFIG);
 417         RR(LINE_NUMBER);
 418         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 419                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 420                 RR(GLOBAL_ALPHA);
 421         if (dss_has_feature(FEAT_MGR_LCD2))
 422                 RR(CONFIG2);
 423         if (dss_has_feature(FEAT_MGR_LCD3))
 424                 RR(CONFIG3);
 425
 426         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 427                 RR(DEFAULT_COLOR(i));
 428                 RR(TRANS_COLOR(i));
 429                 RR(SIZE_MGR(i));
 430                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 431                         continue;
 432                 RR(TIMING_H(i));
 433                 RR(TIMING_V(i));
 434                 RR(POL_FREQ(i));
 435                 RR(DIVISORo(i));
 436
 437                 RR(DATA_CYCLE1(i));
 438                 RR(DATA_CYCLE2(i));
 439                 RR(DATA_CYCLE3(i));
 440
 441                 if (dss_has_feature(FEAT_CPR)) {
 442                         RR(CPR_COEF_R(i));
 443                         RR(CPR_COEF_G(i));
 444                         RR(CPR_COEF_B(i));
 445                 }
 446         }
 447
 448         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 449                 RR(OVL_BA0(i));
 450                 RR(OVL_BA1(i));
 451                 RR(OVL_POSITION(i));
 452                 RR(OVL_SIZE(i));
 453                 RR(OVL_ATTRIBUTES(i));
 454                 RR(OVL_FIFO_THRESHOLD(i));
 455                 RR(OVL_ROW_INC(i));
 456                 RR(OVL_PIXEL_INC(i));
 457                 if (dss_has_feature(FEAT_PRELOAD))
 458                         RR(OVL_PRELOAD(i));
 459                 if (i == OMAP_DSS_GFX) {
 460                         RR(OVL_WINDOW_SKIP(i));
 461                         RR(OVL_TABLE_BA(i));
 462                         continue;
 463                 }
 464                 RR(OVL_FIR(i));
 465                 RR(OVL_PICTURE_SIZE(i));
 466                 RR(OVL_ACCU0(i));
 467                 RR(OVL_ACCU1(i));
 468
 469                 for (j = 0; j < 8; j++)
 470                         RR(OVL_FIR_COEF_H(i, j));
 471
 472                 for (j = 0; j < 8; j++)
 473                         RR(OVL_FIR_COEF_HV(i, j));
 474
 475                 for (j = 0; j < 5; j++)
 476                         RR(OVL_CONV_COEF(i, j));
 477
 478                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 479                         for (j = 0; j < 8; j++)
 480                                 RR(OVL_FIR_COEF_V(i, j));
 481                 }
 482
 483                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 484                         RR(OVL_BA0_UV(i));
 485                         RR(OVL_BA1_UV(i));
 486                         RR(OVL_FIR2(i));
 487                         RR(OVL_ACCU2_0(i));
 488                         RR(OVL_ACCU2_1(i));
 489
 490                         for (j = 0; j < 8; j++)
 491                                 RR(OVL_FIR_COEF_H2(i, j));
 492
 493                         for (j = 0; j < 8; j++)
 494                                 RR(OVL_FIR_COEF_HV2(i, j));
 495
 496                         for (j = 0; j < 8; j++)
 497                                 RR(OVL_FIR_COEF_V2(i, j));
 498                 }
 499                 if (dss_has_feature(FEAT_ATTR2))
 500                         RR(OVL_ATTRIBUTES2(i));
 501         }
 502
 503         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 504                 RR(DIVISOR);
 505
 506         /* enable last, because LCD & DIGIT enable are here */
 507         RR(CONTROL);
 508         if (dss_has_feature(FEAT_MGR_LCD2))
 509                 RR(CONTROL2);
 510         if (dss_has_feature(FEAT_MGR_LCD3))
 511                 RR(CONTROL3);
 512         /* clear spurious SYNC_LOST_DIGIT interrupts */
 513         dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
 514
 515         /*
 516          * enable last so IRQs won't trigger before
 517          * the context is fully restored
 518          */
 519         RR(IRQENABLE);
 520
 521         DSSDBG("context restored\n");
 522 }
 523
 524 #undef SR
 525 #undef RR
 526
 527 int dispc_runtime_get(void)
 528 {
 529         int r;
 530
 531         DSSDBG("dispc_runtime_get\n");
 532
 533         r = pm_runtime_get_sync(&dispc.pdev->dev);
 534         if (WARN_ON(r < 0)) {
 535                 pm_runtime_put_sync(&dispc.pdev->dev);
 536                 return r;
 537         }
 538         return 0;
 539 }
 540 EXPORT_SYMBOL(dispc_runtime_get);
 541
 542 void dispc_runtime_put(void)
 543 {
 544         int r;
 545
 546         DSSDBG("dispc_runtime_put\n");
 547
 548         r = pm_runtime_put_sync(&dispc.pdev->dev);
 549         WARN_ON(r < 0 && r != -ENOSYS);
 550 }
 551 EXPORT_SYMBOL(dispc_runtime_put);
 552
 553 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
 554 {
 555         return mgr_desc[channel].vsync_irq;
 556 }
 557 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
 558
 559 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
 560 {
 561         if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
 562                 return 0;
 563
 564         return mgr_desc[channel].framedone_irq;
 565 }
 566 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
 567
 568 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
 569 {
 570         return mgr_desc[channel].sync_lost_irq;
 571 }
 572 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
 573
 574 u32 dispc_wb_get_framedone_irq(void)
 575 {
 576         return DISPC_IRQ_FRAMEDONEWB;
 577 }
 578
 579 bool dispc_mgr_go_busy(enum omap_channel channel)
 580 {
 581         return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
 582 }
 583 EXPORT_SYMBOL(dispc_mgr_go_busy);
 584
 585 void dispc_mgr_go(enum omap_channel channel)
 586 {
 587         WARN_ON(!dispc_mgr_is_enabled(channel));
 588         WARN_ON(dispc_mgr_go_busy(channel));
 589
 590         DSSDBG("GO %s\n", mgr_desc[channel].name);
 591
 592         mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
 593 }
 594 EXPORT_SYMBOL(dispc_mgr_go);
 595
 596 bool dispc_wb_go_busy(void)
 597 {
 598         return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 599 }
 600
 601 void dispc_wb_go(void)
 602 {
 603         enum omap_plane plane = OMAP_DSS_WB;
 604         bool enable, go;
 605
 606         enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
 607
 608         if (!enable)
 609                 return;
 610
 611         go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 612         if (go) {
 613                 DSSERR("GO bit not down for WB\n");
 614                 return;
 615         }
 616
 617         REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
 618 }
 619
 620 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 621 {
 622         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 623 }
 624
 625 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 626 {
 627         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 628 }
 629
 630 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 631 {
 632         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 633 }
 634
 635 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 636 {
 637         BUG_ON(plane == OMAP_DSS_GFX);
 638
 639         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 640 }
 641
 642 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 643                 u32 value)
 644 {
 645         BUG_ON(plane == OMAP_DSS_GFX);
 646
 647         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 648 }
 649
 650 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 651 {
 652         BUG_ON(plane == OMAP_DSS_GFX);
 653
 654         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 655 }
 656
 657 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
 658                                 int fir_vinc, int five_taps,
 659                                 enum omap_color_component color_comp)
 660 {
 661         const struct dispc_coef *h_coef, *v_coef;
 662         int i;
 663
 664         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
 665         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
 666
 667         for (i = 0; i < 8; i++) {
 668                 u32 h, hv;
 669
 670                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
 671                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
 672                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
 673                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
 674                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
 675                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
 676                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
 677                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
 678
 679                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 680                         dispc_ovl_write_firh_reg(plane, i, h);
 681                         dispc_ovl_write_firhv_reg(plane, i, hv);
 682                 } else {
 683                         dispc_ovl_write_firh2_reg(plane, i, h);
 684                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 685                 }
 686
 687         }
 688
 689         if (five_taps) {
 690                 for (i = 0; i < 8; i++) {
 691                         u32 v;
 692                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
 693                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
 694                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 695                                 dispc_ovl_write_firv_reg(plane, i, v);
 696                         else
 697                                 dispc_ovl_write_firv2_reg(plane, i, v);
 698                 }
 699         }
 700 }
 701
 702
 703 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
 704                 const struct color_conv_coef *ct)
 705 {
 706 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 707
 708         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
 709         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy,  ct->rcb));
 710         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
 711         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
 712         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
 713
 714         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
 715
 716 #undef CVAL
 717 }
 718
 719 static void dispc_setup_color_conv_coef(void)
 720 {
 721         int i;
 722         int num_ovl = dss_feat_get_num_ovls();
 723         const struct color_conv_coef ctbl_bt601_5_ovl = {
 724                 /* YUV -> RGB */
 725                 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
 726         };
 727         const struct color_conv_coef ctbl_bt601_5_wb = {
 728                 /* RGB -> YUV */
 729                 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
 730         };
 731
 732         for (i = 1; i < num_ovl; i++)
 733                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
 734
 735         if (dispc.feat->has_writeback)
 736                 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
 737 }
 738
 739 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 740 {
 741         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 742 }
 743
 744 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 745 {
 746         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 747 }
 748
 749 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 750 {
 751         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 752 }
 753
 754 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 755 {
 756         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 757 }
 758
 759 static void dispc_ovl_set_pos(enum omap_plane plane,
 760                 enum omap_overlay_caps caps, int x, int y)
 761 {
 762         u32 val;
 763
 764         if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
 765                 return;
 766
 767         val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 768
 769         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 770 }
 771
 772 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
 773                 int height)
 774 {
 775         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 776
 777         if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
 778                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 779         else
 780                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 781 }
 782
 783 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
 784                 int height)
 785 {
 786         u32 val;
 787
 788         BUG_ON(plane == OMAP_DSS_GFX);
 789
 790         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 791
 792         if (plane == OMAP_DSS_WB)
 793                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 794         else
 795                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 796 }
 797
 798 static void dispc_ovl_set_zorder(enum omap_plane plane,
 799                 enum omap_overlay_caps caps, u8 zorder)
 800 {
 801         if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
 802                 return;
 803
 804         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
 805 }
 806
 807 static void dispc_ovl_enable_zorder_planes(void)
 808 {
 809         int i;
 810
 811         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 812                 return;
 813
 814         for (i = 0; i < dss_feat_get_num_ovls(); i++)
 815                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 816 }
 817
 818 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
 819                 enum omap_overlay_caps caps, bool enable)
 820 {
 821         if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 822                 return;
 823
 824         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 825 }
 826
 827 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
 828                 enum omap_overlay_caps caps, u8 global_alpha)
 829 {
 830         static const unsigned shifts[] = { 0, 8, 16, 24, };
 831         int shift;
 832
 833         if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 834                 return;
 835
 836         shift = shifts[plane];
 837         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 838 }
 839
 840 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 841 {
 842         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 843 }
 844
 845 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 846 {
 847         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 848 }
 849
 850 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 851                 enum omap_color_mode color_mode)
 852 {
 853         u32 m = 0;
 854         if (plane != OMAP_DSS_GFX) {
 855                 switch (color_mode) {
 856                 case OMAP_DSS_COLOR_NV12:
 857                         m = 0x0; break;
 858                 case OMAP_DSS_COLOR_RGBX16:
 859                         m = 0x1; break;
 860                 case OMAP_DSS_COLOR_RGBA16:
 861                         m = 0x2; break;
 862                 case OMAP_DSS_COLOR_RGB12U:
 863                         m = 0x4; break;
 864                 case OMAP_DSS_COLOR_ARGB16:
 865                         m = 0x5; break;
 866                 case OMAP_DSS_COLOR_RGB16:
 867                         m = 0x6; break;
 868                 case OMAP_DSS_COLOR_ARGB16_1555:
 869                         m = 0x7; break;
 870                 case OMAP_DSS_COLOR_RGB24U:
 871                         m = 0x8; break;
 872                 case OMAP_DSS_COLOR_RGB24P:
 873                         m = 0x9; break;
 874                 case OMAP_DSS_COLOR_YUV2:
 875                         m = 0xa; break;
 876                 case OMAP_DSS_COLOR_UYVY:
 877                         m = 0xb; break;
 878                 case OMAP_DSS_COLOR_ARGB32:
 879                         m = 0xc; break;
 880                 case OMAP_DSS_COLOR_RGBA32:
 881                         m = 0xd; break;
 882                 case OMAP_DSS_COLOR_RGBX32:
 883                         m = 0xe; break;
 884                 case OMAP_DSS_COLOR_XRGB16_1555:
 885                         m = 0xf; break;
 886                 default:
 887                         BUG(); return;
 888                 }
 889         } else {
 890                 switch (color_mode) {
 891                 case OMAP_DSS_COLOR_CLUT1:
 892                         m = 0x0; break;
 893                 case OMAP_DSS_COLOR_CLUT2:
 894                         m = 0x1; break;
 895                 case OMAP_DSS_COLOR_CLUT4:
 896                         m = 0x2; break;
 897                 case OMAP_DSS_COLOR_CLUT8:
 898                         m = 0x3; break;
 899                 case OMAP_DSS_COLOR_RGB12U:
 900                         m = 0x4; break;
 901                 case OMAP_DSS_COLOR_ARGB16:
 902                         m = 0x5; break;
 903                 case OMAP_DSS_COLOR_RGB16:
 904                         m = 0x6; break;
 905                 case OMAP_DSS_COLOR_ARGB16_1555:
 906                         m = 0x7; break;
 907                 case OMAP_DSS_COLOR_RGB24U:
 908                         m = 0x8; break;
 909                 case OMAP_DSS_COLOR_RGB24P:
 910                         m = 0x9; break;
 911                 case OMAP_DSS_COLOR_RGBX16:
 912                         m = 0xa; break;
 913                 case OMAP_DSS_COLOR_RGBA16:
 914                         m = 0xb; break;
 915                 case OMAP_DSS_COLOR_ARGB32:
 916                         m = 0xc; break;
 917                 case OMAP_DSS_COLOR_RGBA32:
 918                         m = 0xd; break;
 919                 case OMAP_DSS_COLOR_RGBX32:
 920                         m = 0xe; break;
 921                 case OMAP_DSS_COLOR_XRGB16_1555:
 922                         m = 0xf; break;
 923                 default:
 924                         BUG(); return;
 925                 }
 926         }
 927
 928         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 929 }
 930
 931 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
 932                 enum omap_dss_rotation_type rotation_type)
 933 {
 934         if (dss_has_feature(FEAT_BURST_2D) == 0)
 935                 return;
 936
 937         if (rotation_type == OMAP_DSS_ROT_TILER)
 938                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
 939         else
 940                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
 941 }
 942
 943 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
 944 {
 945         int shift;
 946         u32 val;
 947         int chan = 0, chan2 = 0;
 948
 949         switch (plane) {
 950         case OMAP_DSS_GFX:
 951                 shift = 8;
 952                 break;
 953         case OMAP_DSS_VIDEO1:
 954         case OMAP_DSS_VIDEO2:
 955         case OMAP_DSS_VIDEO3:
 956                 shift = 16;
 957                 break;
 958         default:
 959                 BUG();
 960                 return;
 961         }
 962
 963         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 964         if (dss_has_feature(FEAT_MGR_LCD2)) {
 965                 switch (channel) {
 966                 case OMAP_DSS_CHANNEL_LCD:
 967                         chan = 0;
 968                         chan2 = 0;
 969                         break;
 970                 case OMAP_DSS_CHANNEL_DIGIT:
 971                         chan = 1;
 972                         chan2 = 0;
 973                         break;
 974                 case OMAP_DSS_CHANNEL_LCD2:
 975                         chan = 0;
 976                         chan2 = 1;
 977                         break;
 978                 case OMAP_DSS_CHANNEL_LCD3:
 979                         if (dss_has_feature(FEAT_MGR_LCD3)) {
 980                                 chan = 0;
 981                                 chan2 = 2;
 982                         } else {
 983                                 BUG();
 984                                 return;
 985                         }
 986                         break;
 987                 case OMAP_DSS_CHANNEL_WB:
 988                         chan = 0;
 989                         chan2 = 3;
 990                         break;
 991                 default:
 992                         BUG();
 993                         return;
 994                 }
 995
 996                 val = FLD_MOD(val, chan, shift, shift);
 997                 val = FLD_MOD(val, chan2, 31, 30);
 998         } else {
 999                 val = FLD_MOD(val, channel, shift, shift);
1000         }
1001         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1002 }
1003 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
1004
1005 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
1006 {
1007         int shift;
1008         u32 val;
1009
1010         switch (plane) {
1011         case OMAP_DSS_GFX:
1012                 shift = 8;
1013                 break;
1014         case OMAP_DSS_VIDEO1:
1015         case OMAP_DSS_VIDEO2:
1016         case OMAP_DSS_VIDEO3:
1017                 shift = 16;
1018                 break;
1019         default:
1020                 BUG();
1021                 return 0;
1022         }
1023
1024         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1025
1026         if (FLD_GET(val, shift, shift) == 1)
1027                 return OMAP_DSS_CHANNEL_DIGIT;
1028
1029         if (!dss_has_feature(FEAT_MGR_LCD2))
1030                 return OMAP_DSS_CHANNEL_LCD;
1031
1032         switch (FLD_GET(val, 31, 30)) {
1033         case 0:
1034         default:
1035                 return OMAP_DSS_CHANNEL_LCD;
1036         case 1:
1037                 return OMAP_DSS_CHANNEL_LCD2;
1038         case 2:
1039                 return OMAP_DSS_CHANNEL_LCD3;
1040         case 3:
1041                 return OMAP_DSS_CHANNEL_WB;
1042         }
1043 }
1044
1045 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1046 {
1047         enum omap_plane plane = OMAP_DSS_WB;
1048
1049         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1050 }
1051
1052 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1053                 enum omap_burst_size burst_size)
1054 {
1055         static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1056         int shift;
1057
1058         shift = shifts[plane];
1059         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1060 }
1061
1062 static void dispc_configure_burst_sizes(void)
1063 {
1064         int i;
1065         const int burst_size = BURST_SIZE_X8;
1066
1067         /* Configure burst size always to maximum size */
1068         for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1069                 dispc_ovl_set_burst_size(i, burst_size);
1070         if (dispc.feat->has_writeback)
1071                 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1072 }
1073
1074 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1075 {
1076         unsigned unit = dss_feat_get_burst_size_unit();
1077         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1078         return unit * 8;
1079 }
1080
1081 void dispc_enable_gamma_table(bool enable)
1082 {
1083         /*
1084          * This is partially implemented to support only disabling of
1085          * the gamma table.
1086          */
1087         if (enable) {
1088                 DSSWARN("Gamma table enabling for TV not yet supported");
1089                 return;
1090         }
1091
1092         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1093 }
1094
1095 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1096 {
1097         if (channel == OMAP_DSS_CHANNEL_DIGIT)
1098                 return;
1099
1100         mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1101 }
1102
1103 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1104                 const struct omap_dss_cpr_coefs *coefs)
1105 {
1106         u32 coef_r, coef_g, coef_b;
1107
1108         if (!dss_mgr_is_lcd(channel))
1109                 return;
1110
1111         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1112                 FLD_VAL(coefs->rb, 9, 0);
1113         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1114                 FLD_VAL(coefs->gb, 9, 0);
1115         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1116                 FLD_VAL(coefs->bb, 9, 0);
1117
1118         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1119         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1120         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1121 }
1122
1123 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1124 {
1125         u32 val;
1126
1127         BUG_ON(plane == OMAP_DSS_GFX);
1128
1129         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1130         val = FLD_MOD(val, enable, 9, 9);
1131         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1132 }
1133
1134 static void dispc_ovl_enable_replication(enum omap_plane plane,
1135                 enum omap_overlay_caps caps, bool enable)
1136 {
1137         static const unsigned shifts[] = { 5, 10, 10, 10 };
1138         int shift;
1139
1140         if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1141                 return;
1142
1143         shift = shifts[plane];
1144         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1145 }
1146
1147 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1148                 u16 height)
1149 {
1150         u32 val;
1151
1152         val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1153                 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1154
1155         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1156 }
1157
1158 static void dispc_init_fifos(void)
1159 {
1160         u32 size;
1161         int fifo;
1162         u8 start, end;
1163         u32 unit;
1164         int i;
1165
1166         unit = dss_feat_get_buffer_size_unit();
1167
1168         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1169
1170         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1171                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1172                 size *= unit;
1173                 dispc.fifo_size[fifo] = size;
1174
1175                 /*
1176                  * By default fifos are mapped directly to overlays, fifo 0 to
1177                  * ovl 0, fifo 1 to ovl 1, etc.
1178                  */
1179                 dispc.fifo_assignment[fifo] = fifo;
1180         }
1181
1182         /*
1183          * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1184          * causes problems with certain use cases, like using the tiler in 2D
1185          * mode. The below hack swaps the fifos of GFX and WB planes, thus
1186          * giving GFX plane a larger fifo. WB but should work fine with a
1187          * smaller fifo.
1188          */
1189         if (dispc.feat->gfx_fifo_workaround) {
1190                 u32 v;
1191
1192                 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1193
1194                 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1195                 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1196                 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1197                 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1198
1199                 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1200
1201                 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1202                 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1203         }
1204
1205         /*
1206          * Setup default fifo thresholds.
1207          */
1208         for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1209                 u32 low, high;
1210                 const bool use_fifomerge = false;
1211                 const bool manual_update = false;
1212
1213                 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1214                         use_fifomerge, manual_update);
1215
1216                 dispc_ovl_set_fifo_threshold(i, low, high);
1217         }
1218
1219         if (dispc.feat->has_writeback) {
1220                 u32 low, high;
1221                 const bool use_fifomerge = false;
1222                 const bool manual_update = false;
1223
1224                 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1225                         use_fifomerge, manual_update);
1226
1227                 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1228         }
1229 }
1230
1231 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1232 {
1233         int fifo;
1234         u32 size = 0;
1235
1236         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1237                 if (dispc.fifo_assignment[fifo] == plane)
1238                         size += dispc.fifo_size[fifo];
1239         }
1240
1241         return size;
1242 }
1243
1244 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1245 {
1246         u8 hi_start, hi_end, lo_start, lo_end;
1247         u32 unit;
1248
1249         unit = dss_feat_get_buffer_size_unit();
1250
1251         WARN_ON(low % unit != 0);
1252         WARN_ON(high % unit != 0);
1253
1254         low /= unit;
1255         high /= unit;
1256
1257         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1258         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1259
1260         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1261                         plane,
1262                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1263                                 lo_start, lo_end) * unit,
1264                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1265                                 hi_start, hi_end) * unit,
1266                         low * unit, high * unit);
1267
1268         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1269                         FLD_VAL(high, hi_start, hi_end) |
1270                         FLD_VAL(low, lo_start, lo_end));
1271
1272         /*
1273          * configure the preload to the pipeline's high threhold, if HT it's too
1274          * large for the preload field, set the threshold to the maximum value
1275          * that can be held by the preload register
1276          */
1277         if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1278                         plane != OMAP_DSS_WB)
1279                 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1280 }
1281
1282 void dispc_enable_fifomerge(bool enable)
1283 {
1284         if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1285                 WARN_ON(enable);
1286                 return;
1287         }
1288
1289         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1290         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1291 }
1292
1293 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1294                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1295                 bool manual_update)
1296 {
1297         /*
1298          * All sizes are in bytes. Both the buffer and burst are made of
1299          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1300          */
1301
1302         unsigned buf_unit = dss_feat_get_buffer_size_unit();
1303         unsigned ovl_fifo_size, total_fifo_size, burst_size;
1304         int i;
1305
1306         burst_size = dispc_ovl_get_burst_size(plane);
1307         ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1308
1309         if (use_fifomerge) {
1310                 total_fifo_size = 0;
1311                 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1312                         total_fifo_size += dispc_ovl_get_fifo_size(i);
1313         } else {
1314                 total_fifo_size = ovl_fifo_size;
1315         }
1316
1317         /*
1318          * We use the same low threshold for both fifomerge and non-fifomerge
1319          * cases, but for fifomerge we calculate the high threshold using the
1320          * combined fifo size
1321          */
1322
1323         if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1324                 *fifo_low = ovl_fifo_size - burst_size * 2;
1325                 *fifo_high = total_fifo_size - burst_size;
1326         } else if (plane == OMAP_DSS_WB) {
1327                 /*
1328                  * Most optimal configuration for writeback is to push out data
1329                  * to the interconnect the moment writeback pushes enough pixels
1330                  * in the FIFO to form a burst
1331                  */
1332                 *fifo_low = 0;
1333                 *fifo_high = burst_size;
1334         } else {
1335                 *fifo_low = ovl_fifo_size - burst_size;
1336                 *fifo_high = total_fifo_size - buf_unit;
1337         }
1338 }
1339
1340 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1341 {
1342         int bit;
1343
1344         if (plane == OMAP_DSS_GFX)
1345                 bit = 14;
1346         else
1347                 bit = 23;
1348
1349         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1350 }
1351
1352 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1353         int low, int high)
1354 {
1355         dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1356                 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1357 }
1358
1359 static void dispc_init_mflag(void)
1360 {
1361         int i;
1362
1363         /*
1364          * HACK: NV12 color format and MFLAG seem to have problems working
1365          * together: using two displays, and having an NV12 overlay on one of
1366          * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1367          * Changing MFLAG thresholds and PRELOAD to certain values seem to
1368          * remove the errors, but there doesn't seem to be a clear logic on
1369          * which values work and which not.
1370          *
1371          * As a work-around, set force MFLAG to always on.
1372          */
1373         dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1374                 (1 << 0) |      /* MFLAG_CTRL = force always on */
1375                 (0 << 2));      /* MFLAG_START = disable */
1376
1377         for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1378                 u32 size = dispc_ovl_get_fifo_size(i);
1379                 u32 unit = dss_feat_get_buffer_size_unit();
1380                 u32 low, high;
1381
1382                 dispc_ovl_set_mflag(i, true);
1383
1384                 /*
1385                  * Simulation team suggests below thesholds:
1386                  * HT = fifosize * 5 / 8;
1387                  * LT = fifosize * 4 / 8;
1388                  */
1389
1390                 low = size * 4 / 8 / unit;
1391                 high = size * 5 / 8 / unit;
1392
1393                 dispc_ovl_set_mflag_threshold(i, low, high);
1394         }
1395
1396         if (dispc.feat->has_writeback) {
1397                 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1398                 u32 unit = dss_feat_get_buffer_size_unit();
1399                 u32 low, high;
1400
1401                 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1402
1403                 /*
1404                  * Simulation team suggests below thesholds:
1405                  * HT = fifosize * 5 / 8;
1406                  * LT = fifosize * 4 / 8;
1407                  */
1408
1409                 low = size * 4 / 8 / unit;
1410                 high = size * 5 / 8 / unit;
1411
1412                 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1413         }
1414 }
1415
1416 static void dispc_ovl_set_fir(enum omap_plane plane,
1417                                 int hinc, int vinc,
1418                                 enum omap_color_component color_comp)
1419 {
1420         u32 val;
1421
1422         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1423                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1424
1425                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1426                                         &hinc_start, &hinc_end);
1427                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1428                                         &vinc_start, &vinc_end);
1429                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1430                                 FLD_VAL(hinc, hinc_start, hinc_end);
1431
1432                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1433         } else {
1434                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1435                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1436         }
1437 }
1438
1439 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1440 {
1441         u32 val;
1442         u8 hor_start, hor_end, vert_start, vert_end;
1443
1444         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1445         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1446
1447         val = FLD_VAL(vaccu, vert_start, vert_end) |
1448                         FLD_VAL(haccu, hor_start, hor_end);
1449
1450         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1451 }
1452
1453 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1454 {
1455         u32 val;
1456         u8 hor_start, hor_end, vert_start, vert_end;
1457
1458         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1459         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1460
1461         val = FLD_VAL(vaccu, vert_start, vert_end) |
1462                         FLD_VAL(haccu, hor_start, hor_end);
1463
1464         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1465 }
1466
1467 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1468                 int vaccu)
1469 {
1470         u32 val;
1471
1472         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1473         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1474 }
1475
1476 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1477                 int vaccu)
1478 {
1479         u32 val;
1480
1481         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1482         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1483 }
1484
1485 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1486                 u16 orig_width, u16 orig_height,
1487                 u16 out_width, u16 out_height,
1488                 bool five_taps, u8 rotation,
1489                 enum omap_color_component color_comp)
1490 {
1491         int fir_hinc, fir_vinc;
1492
1493         fir_hinc = 1024 * orig_width / out_width;
1494         fir_vinc = 1024 * orig_height / out_height;
1495
1496         dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1497                                 color_comp);
1498         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1499 }
1500
1501 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1502                 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1503                 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1504 {
1505         int h_accu2_0, h_accu2_1;
1506         int v_accu2_0, v_accu2_1;
1507         int chroma_hinc, chroma_vinc;
1508         int idx;
1509
1510         struct accu {
1511                 s8 h0_m, h0_n;
1512                 s8 h1_m, h1_n;
1513                 s8 v0_m, v0_n;
1514                 s8 v1_m, v1_n;
1515         };
1516
1517         const struct accu *accu_table;
1518         const struct accu *accu_val;
1519
1520         static const struct accu accu_nv12[4] = {
1521                 {  0, 1,  0, 1 , -1, 2, 0, 1 },
1522                 {  1, 2, -3, 4 ,  0, 1, 0, 1 },
1523                 { -1, 1,  0, 1 , -1, 2, 0, 1 },
1524                 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1525         };
1526
1527         static const struct accu accu_nv12_ilace[4] = {
1528                 {  0, 1,  0, 1 , -3, 4, -1, 4 },
1529                 { -1, 4, -3, 4 ,  0, 1,  0, 1 },
1530                 { -1, 1,  0, 1 , -1, 4, -3, 4 },
1531                 { -3, 4, -3, 4 , -1, 1,  0, 1 },
1532         };
1533
1534         static const struct accu accu_yuv[4] = {
1535                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1536                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1537                 { -1, 1, 0, 1,  0, 1, 0, 1 },
1538                 {  0, 1, 0, 1, -1, 1, 0, 1 },
1539         };
1540
1541         switch (rotation) {
1542         case OMAP_DSS_ROT_0:
1543                 idx = 0;
1544                 break;
1545         case OMAP_DSS_ROT_90:
1546                 idx = 1;
1547                 break;
1548         case OMAP_DSS_ROT_180:
1549                 idx = 2;
1550                 break;
1551         case OMAP_DSS_ROT_270:
1552                 idx = 3;
1553                 break;
1554         default:
1555                 BUG();
1556                 return;
1557         }
1558
1559         switch (color_mode) {
1560         case OMAP_DSS_COLOR_NV12:
1561                 if (ilace)
1562                         accu_table = accu_nv12_ilace;
1563                 else
1564                         accu_table = accu_nv12;
1565                 break;
1566         case OMAP_DSS_COLOR_YUV2:
1567         case OMAP_DSS_COLOR_UYVY:
1568                 accu_table = accu_yuv;
1569                 break;
1570         default:
1571                 BUG();
1572                 return;
1573         }
1574
1575         accu_val = &accu_table[idx];
1576
1577         chroma_hinc = 1024 * orig_width / out_width;
1578         chroma_vinc = 1024 * orig_height / out_height;
1579
1580         h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1581         h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1582         v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1583         v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1584
1585         dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1586         dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1587 }
1588
1589 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1590                 u16 orig_width, u16 orig_height,
1591                 u16 out_width, u16 out_height,
1592                 bool ilace, bool five_taps,
1593                 bool fieldmode, enum omap_color_mode color_mode,
1594                 u8 rotation)
1595 {
1596         int accu0 = 0;
1597         int accu1 = 0;
1598         u32 l;
1599
1600         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1601                                 out_width, out_height, five_taps,
1602                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1603         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1604
1605         /* RESIZEENABLE and VERTICALTAPS */
1606         l &= ~((0x3 << 5) | (0x1 << 21));
1607         l |= (orig_width != out_width) ? (1 << 5) : 0;
1608         l |= (orig_height != out_height) ? (1 << 6) : 0;
1609         l |= five_taps ? (1 << 21) : 0;
1610
1611         /* VRESIZECONF and HRESIZECONF */
1612         if (dss_has_feature(FEAT_RESIZECONF)) {
1613                 l &= ~(0x3 << 7);
1614                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1615                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1616         }
1617
1618         /* LINEBUFFERSPLIT */
1619         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1620                 l &= ~(0x1 << 22);
1621                 l |= five_taps ? (1 << 22) : 0;
1622         }
1623
1624         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1625
1626         /*
1627          * field 0 = even field = bottom field
1628          * field 1 = odd field = top field
1629          */
1630         if (ilace && !fieldmode) {
1631                 accu1 = 0;
1632                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1633                 if (accu0 >= 1024/2) {
1634                         accu1 = 1024/2;
1635                         accu0 -= accu1;
1636                 }
1637         }
1638
1639         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1640         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1641 }
1642
1643 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1644                 u16 orig_width, u16 orig_height,
1645                 u16 out_width, u16 out_height,
1646                 bool ilace, bool five_taps,
1647                 bool fieldmode, enum omap_color_mode color_mode,
1648                 u8 rotation)
1649 {
1650         int scale_x = out_width != orig_width;
1651         int scale_y = out_height != orig_height;
1652         bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1653
1654         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1655                 return;
1656         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1657                         color_mode != OMAP_DSS_COLOR_UYVY &&
1658                         color_mode != OMAP_DSS_COLOR_NV12)) {
1659                 /* reset chroma resampling for RGB formats  */
1660                 if (plane != OMAP_DSS_WB)
1661                         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1662                 return;
1663         }
1664
1665         dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1666                         out_height, ilace, color_mode, rotation);
1667
1668         switch (color_mode) {
1669         case OMAP_DSS_COLOR_NV12:
1670                 if (chroma_upscale) {
1671                         /* UV is subsampled by 2 horizontally and vertically */
1672                         orig_height >>= 1;
1673                         orig_width >>= 1;
1674                 } else {
1675                         /* UV is downsampled by 2 horizontally and vertically */
1676                         orig_height <<= 1;
1677                         orig_width <<= 1;
1678                 }
1679
1680                 break;
1681         case OMAP_DSS_COLOR_YUV2:
1682         case OMAP_DSS_COLOR_UYVY:
1683                 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1684                 if (rotation == OMAP_DSS_ROT_0 ||
1685                                 rotation == OMAP_DSS_ROT_180) {
1686                         if (chroma_upscale)
1687                                 /* UV is subsampled by 2 horizontally */
1688                                 orig_width >>= 1;
1689                         else
1690                                 /* UV is downsampled by 2 horizontally */
1691                                 orig_width <<= 1;
1692                 }
1693
1694                 /* must use FIR for YUV422 if rotated */
1695                 if (rotation != OMAP_DSS_ROT_0)
1696                         scale_x = scale_y = true;
1697
1698                 break;
1699         default:
1700                 BUG();
1701                 return;
1702         }
1703
1704         if (out_width != orig_width)
1705                 scale_x = true;
1706         if (out_height != orig_height)
1707                 scale_y = true;
1708
1709         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1710                         out_width, out_height, five_taps,
1711                                 rotation, DISPC_COLOR_COMPONENT_UV);
1712
1713         if (plane != OMAP_DSS_WB)
1714                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1715                         (scale_x || scale_y) ? 1 : 0, 8, 8);
1716
1717         /* set H scaling */
1718         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1719         /* set V scaling */
1720         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1721 }
1722
1723 static void dispc_ovl_set_scaling(enum omap_plane plane,
1724                 u16 orig_width, u16 orig_height,
1725                 u16 out_width, u16 out_height,
1726                 bool ilace, bool five_taps,
1727                 bool fieldmode, enum omap_color_mode color_mode,
1728                 u8 rotation)
1729 {
1730         BUG_ON(plane == OMAP_DSS_GFX);
1731
1732         dispc_ovl_set_scaling_common(plane,
1733                         orig_width, orig_height,
1734                         out_width, out_height,
1735                         ilace, five_taps,
1736                         fieldmode, color_mode,
1737                         rotation);
1738
1739         dispc_ovl_set_scaling_uv(plane,
1740                 orig_width, orig_height,
1741                 out_width, out_height,
1742                 ilace, five_taps,
1743                 fieldmode, color_mode,
1744                 rotation);
1745 }
1746
1747 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1748                 enum omap_dss_rotation_type rotation_type,
1749                 bool mirroring, enum omap_color_mode color_mode)
1750 {
1751         bool row_repeat = false;
1752         int vidrot = 0;
1753
1754         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1755                         color_mode == OMAP_DSS_COLOR_UYVY) {
1756
1757                 if (mirroring) {
1758                         switch (rotation) {
1759                         case OMAP_DSS_ROT_0:
1760                                 vidrot = 2;
1761                                 break;
1762                         case OMAP_DSS_ROT_90:
1763                                 vidrot = 1;
1764                                 break;
1765                         case OMAP_DSS_ROT_180:
1766                                 vidrot = 0;
1767                                 break;
1768                         case OMAP_DSS_ROT_270:
1769                                 vidrot = 3;
1770                                 break;
1771                         }
1772                 } else {
1773                         switch (rotation) {
1774                         case OMAP_DSS_ROT_0:
1775                                 vidrot = 0;
1776                                 break;
1777                         case OMAP_DSS_ROT_90:
1778                                 vidrot = 1;
1779                                 break;
1780                         case OMAP_DSS_ROT_180:
1781                                 vidrot = 2;
1782                                 break;
1783                         case OMAP_DSS_ROT_270:
1784                                 vidrot = 3;
1785                                 break;
1786                         }
1787                 }
1788
1789                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1790                         row_repeat = true;
1791                 else
1792                         row_repeat = false;
1793         }
1794
1795         /*
1796          * OMAP4/5 Errata i631:
1797          * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1798          * rows beyond the framebuffer, which may cause OCP error.
1799          */
1800         if (color_mode == OMAP_DSS_COLOR_NV12 &&
1801                         rotation_type != OMAP_DSS_ROT_TILER)
1802                 vidrot = 1;
1803
1804         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1805         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1806                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1807                         row_repeat ? 1 : 0, 18, 18);
1808
1809         if (color_mode == OMAP_DSS_COLOR_NV12) {
1810                 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1811                                         (rotation == OMAP_DSS_ROT_0 ||
1812                                         rotation == OMAP_DSS_ROT_180);
1813                 /* DOUBLESTRIDE */
1814                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1815         }
1816
1817 }
1818
1819 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1820 {
1821         switch (color_mode) {
1822         case OMAP_DSS_COLOR_CLUT1:
1823                 return 1;
1824         case OMAP_DSS_COLOR_CLUT2:
1825                 return 2;
1826         case OMAP_DSS_COLOR_CLUT4:
1827                 return 4;
1828         case OMAP_DSS_COLOR_CLUT8:
1829         case OMAP_DSS_COLOR_NV12:
1830                 return 8;
1831         case OMAP_DSS_COLOR_RGB12U:
1832         case OMAP_DSS_COLOR_RGB16:
1833         case OMAP_DSS_COLOR_ARGB16:
1834         case OMAP_DSS_COLOR_YUV2:
1835         case OMAP_DSS_COLOR_UYVY:
1836         case OMAP_DSS_COLOR_RGBA16:
1837         case OMAP_DSS_COLOR_RGBX16:
1838         case OMAP_DSS_COLOR_ARGB16_1555:
1839         case OMAP_DSS_COLOR_XRGB16_1555:
1840                 return 16;
1841         case OMAP_DSS_COLOR_RGB24P:
1842                 return 24;
1843         case OMAP_DSS_COLOR_RGB24U:
1844         case OMAP_DSS_COLOR_ARGB32:
1845         case OMAP_DSS_COLOR_RGBA32:
1846         case OMAP_DSS_COLOR_RGBX32:
1847                 return 32;
1848         default:
1849                 BUG();
1850                 return 0;
1851         }
1852 }
1853
1854 static s32 pixinc(int pixels, u8 ps)
1855 {
1856         if (pixels == 1)
1857                 return 1;
1858         else if (pixels > 1)
1859                 return 1 + (pixels - 1) * ps;
1860         else if (pixels < 0)
1861                 return 1 - (-pixels + 1) * ps;
1862         else
1863                 BUG();
1864                 return 0;
1865 }
1866
1867 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1868                 u16 screen_width,
1869                 u16 width, u16 height,
1870                 enum omap_color_mode color_mode, bool fieldmode,
1871                 unsigned int field_offset,
1872                 unsigned *offset0, unsigned *offset1,
1873                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1874 {
1875         u8 ps;
1876
1877         /* FIXME CLUT formats */
1878         switch (color_mode) {
1879         case OMAP_DSS_COLOR_CLUT1:
1880         case OMAP_DSS_COLOR_CLUT2:
1881         case OMAP_DSS_COLOR_CLUT4:
1882         case OMAP_DSS_COLOR_CLUT8:
1883                 BUG();
1884                 return;
1885         case OMAP_DSS_COLOR_YUV2:
1886         case OMAP_DSS_COLOR_UYVY:
1887                 ps = 4;
1888                 break;
1889         default:
1890                 ps = color_mode_to_bpp(color_mode) / 8;
1891                 break;
1892         }
1893
1894         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1895                         width, height);
1896
1897         /*
1898          * field 0 = even field = bottom field
1899          * field 1 = odd field = top field
1900          */
1901         switch (rotation + mirror * 4) {
1902         case OMAP_DSS_ROT_0:
1903         case OMAP_DSS_ROT_180:
1904                 /*
1905                  * If the pixel format is YUV or UYVY divide the width
1906                  * of the image by 2 for 0 and 180 degree rotation.
1907                  */
1908                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1909                         color_mode == OMAP_DSS_COLOR_UYVY)
1910                         width = width >> 1;
1911         case OMAP_DSS_ROT_90:
1912         case OMAP_DSS_ROT_270:
1913                 *offset1 = 0;
1914                 if (field_offset)
1915                         *offset0 = field_offset * screen_width * ps;
1916                 else
1917                         *offset0 = 0;
1918
1919                 *row_inc = pixinc(1 +
1920                         (y_predecim * screen_width - x_predecim * width) +
1921                         (fieldmode ? screen_width : 0), ps);
1922                 *pix_inc = pixinc(x_predecim, ps);
1923                 break;
1924
1925         case OMAP_DSS_ROT_0 + 4:
1926         case OMAP_DSS_ROT_180 + 4:
1927                 /* If the pixel format is YUV or UYVY divide the width
1928                  * of the image by 2  for 0 degree and 180 degree
1929                  */
1930                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1931                         color_mode == OMAP_DSS_COLOR_UYVY)
1932                         width = width >> 1;
1933         case OMAP_DSS_ROT_90 + 4:
1934         case OMAP_DSS_ROT_270 + 4:
1935                 *offset1 = 0;
1936                 if (field_offset)
1937                         *offset0 = field_offset * screen_width * ps;
1938                 else
1939                         *offset0 = 0;
1940                 *row_inc = pixinc(1 -
1941                         (y_predecim * screen_width + x_predecim * width) -
1942                         (fieldmode ? screen_width : 0), ps);
1943                 *pix_inc = pixinc(x_predecim, ps);
1944                 break;
1945
1946         default:
1947                 BUG();
1948                 return;
1949         }
1950 }
1951
1952 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1953                 u16 screen_width,
1954                 u16 width, u16 height,
1955                 enum omap_color_mode color_mode, bool fieldmode,
1956                 unsigned int field_offset,
1957                 unsigned *offset0, unsigned *offset1,
1958                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1959 {
1960         u8 ps;
1961         u16 fbw, fbh;
1962
1963         /* FIXME CLUT formats */
1964         switch (color_mode) {
1965         case OMAP_DSS_COLOR_CLUT1:
1966         case OMAP_DSS_COLOR_CLUT2:
1967         case OMAP_DSS_COLOR_CLUT4:
1968         case OMAP_DSS_COLOR_CLUT8:
1969                 BUG();
1970                 return;
1971         default:
1972                 ps = color_mode_to_bpp(color_mode) / 8;
1973                 break;
1974         }
1975
1976         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1977                         width, height);
1978
1979         /* width & height are overlay sizes, convert to fb sizes */
1980
1981         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1982                 fbw = width;
1983                 fbh = height;
1984         } else {
1985                 fbw = height;
1986                 fbh = width;
1987         }
1988
1989         /*
1990          * field 0 = even field = bottom field
1991          * field 1 = odd field = top field
1992          */
1993         switch (rotation + mirror * 4) {
1994         case OMAP_DSS_ROT_0:
1995                 *offset1 = 0;
1996                 if (field_offset)
1997                         *offset0 = *offset1 + field_offset * screen_width * ps;
1998                 else
1999                         *offset0 = *offset1;
2000                 *row_inc = pixinc(1 +
2001                         (y_predecim * screen_width - fbw * x_predecim) +
2002                         (fieldmode ? screen_width : 0), ps);
2003                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2004                         color_mode == OMAP_DSS_COLOR_UYVY)
2005                         *pix_inc = pixinc(x_predecim, 2 * ps);
2006                 else
2007                         *pix_inc = pixinc(x_predecim, ps);
2008                 break;
2009         case OMAP_DSS_ROT_90:
2010                 *offset1 = screen_width * (fbh - 1) * ps;
2011                 if (field_offset)
2012                         *offset0 = *offset1 + field_offset * ps;
2013                 else
2014                         *offset0 = *offset1;
2015                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
2016                                 y_predecim + (fieldmode ? 1 : 0), ps);
2017                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2018                 break;
2019         case OMAP_DSS_ROT_180:
2020                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2021                 if (field_offset)
2022                         *offset0 = *offset1 - field_offset * screen_width * ps;
2023                 else
2024                         *offset0 = *offset1;
2025                 *row_inc = pixinc(-1 -
2026                         (y_predecim * screen_width - fbw * x_predecim) -
2027                         (fieldmode ? screen_width : 0), ps);
2028                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2029                         color_mode == OMAP_DSS_COLOR_UYVY)
2030                         *pix_inc = pixinc(-x_predecim, 2 * ps);
2031                 else
2032                         *pix_inc = pixinc(-x_predecim, ps);
2033                 break;
2034         case OMAP_DSS_ROT_270:
2035                 *offset1 = (fbw - 1) * ps;
2036                 if (field_offset)
2037                         *offset0 = *offset1 - field_offset * ps;
2038                 else
2039                         *offset0 = *offset1;
2040                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2041                                 y_predecim - (fieldmode ? 1 : 0), ps);
2042                 *pix_inc = pixinc(x_predecim * screen_width, ps);
2043                 break;
2044
2045         /* mirroring */
2046         case OMAP_DSS_ROT_0 + 4:
2047                 *offset1 = (fbw - 1) * ps;
2048                 if (field_offset)
2049                         *offset0 = *offset1 + field_offset * screen_width * ps;
2050                 else
2051                         *offset0 = *offset1;
2052                 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2053                                 (fieldmode ? screen_width : 0),
2054                                 ps);
2055                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2056                         color_mode == OMAP_DSS_COLOR_UYVY)
2057                         *pix_inc = pixinc(-x_predecim, 2 * ps);
2058                 else
2059                         *pix_inc = pixinc(-x_predecim, ps);
2060                 break;
2061
2062         case OMAP_DSS_ROT_90 + 4:
2063                 *offset1 = 0;
2064                 if (field_offset)
2065                         *offset0 = *offset1 + field_offset * ps;
2066                 else
2067                         *offset0 = *offset1;
2068                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2069                                 y_predecim + (fieldmode ? 1 : 0),
2070                                 ps);
2071                 *pix_inc = pixinc(x_predecim * screen_width, ps);
2072                 break;
2073
2074         case OMAP_DSS_ROT_180 + 4:
2075                 *offset1 = screen_width * (fbh - 1) * ps;
2076                 if (field_offset)
2077                         *offset0 = *offset1 - field_offset * screen_width * ps;
2078                 else
2079                         *offset0 = *offset1;
2080                 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2081                                 (fieldmode ? screen_width : 0),
2082                                 ps);
2083                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2084                         color_mode == OMAP_DSS_COLOR_UYVY)
2085                         *pix_inc = pixinc(x_predecim, 2 * ps);
2086                 else
2087                         *pix_inc = pixinc(x_predecim, ps);
2088                 break;
2089
2090         case OMAP_DSS_ROT_270 + 4:
2091                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2092                 if (field_offset)
2093                         *offset0 = *offset1 - field_offset * ps;
2094                 else
2095                         *offset0 = *offset1;
2096                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2097                                 y_predecim - (fieldmode ? 1 : 0),
2098                                 ps);
2099                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2100                 break;
2101
2102         default:
2103                 BUG();
2104                 return;
2105         }
2106 }
2107
2108 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2109                 enum omap_color_mode color_mode, bool fieldmode,
2110                 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2111                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2112 {
2113         u8 ps;
2114
2115         switch (color_mode) {
2116         case OMAP_DSS_COLOR_CLUT1:
2117         case OMAP_DSS_COLOR_CLUT2:
2118         case OMAP_DSS_COLOR_CLUT4:
2119         case OMAP_DSS_COLOR_CLUT8:
2120                 BUG();
2121                 return;
2122         default:
2123                 ps = color_mode_to_bpp(color_mode) / 8;
2124                 break;
2125         }
2126
2127         DSSDBG("scrw %d, width %d\n", screen_width, width);
2128
2129         /*
2130          * field 0 = even field = bottom field
2131          * field 1 = odd field = top field
2132          */
2133         *offset1 = 0;
2134         if (field_offset)
2135                 *offset0 = *offset1 + field_offset * screen_width * ps;
2136         else
2137                 *offset0 = *offset1;
2138         *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2139                         (fieldmode ? screen_width : 0), ps);
2140         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2141                 color_mode == OMAP_DSS_COLOR_UYVY)
2142                 *pix_inc = pixinc(x_predecim, 2 * ps);
2143         else
2144                 *pix_inc = pixinc(x_predecim, ps);
2145 }
2146
2147 /*
2148  * This function is used to avoid synclosts in OMAP3, because of some
2149  * undocumented horizontal position and timing related limitations.
2150  */
2151 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2152                 const struct omap_video_timings *t, u16 pos_x,
2153                 u16 width, u16 height, u16 out_width, u16 out_height,
2154                 bool five_taps)
2155 {
2156         const int ds = DIV_ROUND_UP(height, out_height);
2157         unsigned long nonactive;
2158         static const u8 limits[3] = { 8, 10, 20 };
2159         u64 val, blank;
2160         int i;
2161
2162         nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2163
2164         i = 0;
2165         if (out_height < height)
2166                 i++;
2167         if (out_width < width)
2168                 i++;
2169         blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2170         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2171         if (blank <= limits[i])
2172                 return -EINVAL;
2173
2174         /* FIXME add checks for 3-tap filter once the limitations are known */
2175         if (!five_taps)
2176                 return 0;
2177
2178         /*
2179          * Pixel data should be prepared before visible display point starts.
2180          * So, atleast DS-2 lines must have already been fetched by DISPC
2181          * during nonactive - pos_x period.
2182          */
2183         val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2184         DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2185                 val, max(0, ds - 2) * width);
2186         if (val < max(0, ds - 2) * width)
2187                 return -EINVAL;
2188
2189         /*
2190          * All lines need to be refilled during the nonactive period of which
2191          * only one line can be loaded during the active period. So, atleast
2192          * DS - 1 lines should be loaded during nonactive period.
2193          */
2194         val =  div_u64((u64)nonactive * lclk, pclk);
2195         DSSDBG("nonactive * pcd  = %llu, max(0, DS - 1) * width = %d\n",
2196                 val, max(0, ds - 1) * width);
2197         if (val < max(0, ds - 1) * width)
2198                 return -EINVAL;
2199
2200         return 0;
2201 }
2202
2203 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2204                 const struct omap_video_timings *mgr_timings, u16 width,
2205                 u16 height, u16 out_width, u16 out_height,
2206                 enum omap_color_mode color_mode)
2207 {
2208         u32 core_clk = 0;
2209         u64 tmp;
2210
2211         if (height <= out_height && width <= out_width)
2212                 return (unsigned long) pclk;
2213
2214         if (height > out_height) {
2215                 unsigned int ppl = mgr_timings->x_res;
2216
2217                 tmp = (u64)pclk * height * out_width;
2218                 do_div(tmp, 2 * out_height * ppl);
2219                 core_clk = tmp;
2220
2221                 if (height > 2 * out_height) {
2222                         if (ppl == out_width)
2223                                 return 0;
2224
2225                         tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2226                         do_div(tmp, 2 * out_height * (ppl - out_width));
2227                         core_clk = max_t(u32, core_clk, tmp);
2228                 }
2229         }
2230
2231         if (width > out_width) {
2232                 tmp = (u64)pclk * width;
2233                 do_div(tmp, out_width);
2234                 core_clk = max_t(u32, core_clk, tmp);
2235
2236                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2237                         core_clk <<= 1;
2238         }
2239
2240         return core_clk;
2241 }
2242
2243 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2244                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2245 {
2246         if (height > out_height && width > out_width)
2247                 return pclk * 4;
2248         else
2249                 return pclk * 2;
2250 }
2251
2252 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2253                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2254 {
2255         unsigned int hf, vf;
2256
2257         /*
2258          * FIXME how to determine the 'A' factor
2259          * for the no downscaling case ?
2260          */
2261
2262         if (width > 3 * out_width)
2263                 hf = 4;
2264         else if (width > 2 * out_width)
2265                 hf = 3;
2266         else if (width > out_width)
2267                 hf = 2;
2268         else
2269                 hf = 1;
2270         if (height > out_height)
2271                 vf = 2;
2272         else
2273                 vf = 1;
2274
2275         return pclk * vf * hf;
2276 }
2277
2278 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2279                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2280 {
2281         /*
2282          * If the overlay/writeback is in mem to mem mode, there are no
2283          * downscaling limitations with respect to pixel clock, return 1 as
2284          * required core clock to represent that we have sufficient enough
2285          * core clock to do maximum downscaling
2286          */
2287         if (mem_to_mem)
2288                 return 1;
2289
2290         if (width > out_width)
2291                 return DIV_ROUND_UP(pclk, out_width) * width;
2292         else
2293                 return pclk;
2294 }
2295
2296 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2297                 const struct omap_video_timings *mgr_timings,
2298                 u16 width, u16 height, u16 out_width, u16 out_height,
2299                 enum omap_color_mode color_mode, bool *five_taps,
2300                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2301                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2302 {
2303         int error;
2304         u16 in_width, in_height;
2305         int min_factor = min(*decim_x, *decim_y);
2306         const int maxsinglelinewidth =
2307                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2308
2309         *five_taps = false;
2310
2311         do {
2312                 in_height = height / *decim_y;
2313                 in_width = width / *decim_x;
2314                 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2315                                 in_height, out_width, out_height, mem_to_mem);
2316                 error = (in_width > maxsinglelinewidth || !*core_clk ||
2317                         *core_clk > dispc_core_clk_rate());
2318                 if (error) {
2319                         if (*decim_x == *decim_y) {
2320                                 *decim_x = min_factor;
2321                                 ++*decim_y;
2322                         } else {
2323                                 swap(*decim_x, *decim_y);
2324                                 if (*decim_x < *decim_y)
2325                                         ++*decim_x;
2326                         }
2327                 }
2328         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2329
2330         if (error) {
2331                 DSSERR("failed to find scaling settings\n");
2332                 return -EINVAL;
2333         }
2334
2335         if (in_width > maxsinglelinewidth) {
2336                 DSSERR("Cannot scale max input width exceeded");
2337                 return -EINVAL;
2338         }
2339         return 0;
2340 }
2341
2342 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2343                 const struct omap_video_timings *mgr_timings,
2344                 u16 width, u16 height, u16 out_width, u16 out_height,
2345                 enum omap_color_mode color_mode, bool *five_taps,
2346                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2347                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2348 {
2349         int error;
2350         u16 in_width, in_height;
2351         const int maxsinglelinewidth =
2352                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2353
2354         do {
2355                 in_height = height / *decim_y;
2356                 in_width = width / *decim_x;
2357                 *five_taps = in_height > out_height;
2358
2359                 if (in_width > maxsinglelinewidth)
2360                         if (in_height > out_height &&
2361                                                 in_height < out_height * 2)
2362                                 *five_taps = false;
2363 again:
2364                 if (*five_taps)
2365                         *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2366                                                 in_width, in_height, out_width,
2367                                                 out_height, color_mode);
2368                 else
2369                         *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2370                                         in_height, out_width, out_height,
2371                                         mem_to_mem);
2372
2373                 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2374                                 pos_x, in_width, in_height, out_width,
2375                                 out_height, *five_taps);
2376                 if (error && *five_taps) {
2377                         *five_taps = false;
2378                         goto again;
2379                 }
2380
2381                 error = (error || in_width > maxsinglelinewidth * 2 ||
2382                         (in_width > maxsinglelinewidth && *five_taps) ||
2383                         !*core_clk || *core_clk > dispc_core_clk_rate());
2384
2385                 if (!error) {
2386                         /* verify that we're inside the limits of scaler */
2387                         if (in_width / 4 > out_width)
2388                                         error = 1;
2389
2390                         if (*five_taps) {
2391                                 if (in_height / 4 > out_height)
2392                                         error = 1;
2393                         } else {
2394                                 if (in_height / 2 > out_height)
2395                                         error = 1;
2396                         }
2397                 }
2398
2399                 if (error)
2400                         ++*decim_y;
2401         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2402
2403         if (error) {
2404                 DSSERR("failed to find scaling settings\n");
2405                 return -EINVAL;
2406         }
2407
2408         if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2409                                 in_height, out_width, out_height, *five_taps)) {
2410                         DSSERR("horizontal timing too tight\n");
2411                         return -EINVAL;
2412         }
2413
2414         if (in_width > (maxsinglelinewidth * 2)) {
2415                 DSSERR("Cannot setup scaling");
2416                 DSSERR("width exceeds maximum width possible");
2417                 return -EINVAL;
2418         }
2419
2420         if (in_width > maxsinglelinewidth && *five_taps) {
2421                 DSSERR("cannot setup scaling with five taps");
2422                 return -EINVAL;
2423         }
2424         return 0;
2425 }
2426
2427 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2428                 const struct omap_video_timings *mgr_timings,
2429                 u16 width, u16 height, u16 out_width, u16 out_height,
2430                 enum omap_color_mode color_mode, bool *five_taps,
2431                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2432                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2433 {
2434         u16 in_width, in_width_max;
2435         int decim_x_min = *decim_x;
2436         u16 in_height = height / *decim_y;
2437         const int maxsinglelinewidth =
2438                                 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2439         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2440
2441         if (mem_to_mem) {
2442                 in_width_max = out_width * maxdownscale;
2443         } else {
2444                 in_width_max = dispc_core_clk_rate() /
2445                                         DIV_ROUND_UP(pclk, out_width);
2446         }
2447
2448         *decim_x = DIV_ROUND_UP(width, in_width_max);
2449
2450         *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2451         if (*decim_x > *x_predecim)
2452                 return -EINVAL;
2453
2454         do {
2455                 in_width = width / *decim_x;
2456         } while (*decim_x <= *x_predecim &&
2457                         in_width > maxsinglelinewidth && ++*decim_x);
2458
2459         if (in_width > maxsinglelinewidth) {
2460                 DSSERR("Cannot scale width exceeds max line width");
2461                 return -EINVAL;
2462         }
2463
2464         *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2465                                 out_width, out_height, mem_to_mem);
2466         return 0;
2467 }
2468
2469 #define DIV_FRAC(dividend, divisor) \
2470         ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2471
2472 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2473                 enum omap_overlay_caps caps,
2474                 const struct omap_video_timings *mgr_timings,
2475                 u16 width, u16 height, u16 out_width, u16 out_height,
2476                 enum omap_color_mode color_mode, bool *five_taps,
2477                 int *x_predecim, int *y_predecim, u16 pos_x,
2478                 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2479 {
2480         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2481         const int max_decim_limit = 16;
2482         unsigned long core_clk = 0;
2483         int decim_x, decim_y, ret;
2484
2485         if (width == out_width && height == out_height)
2486                 return 0;
2487
2488         if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
2489                 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2490                 return -EINVAL;
2491         }
2492
2493         if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2494                 return -EINVAL;
2495
2496         if (mem_to_mem) {
2497                 *x_predecim = *y_predecim = 1;
2498         } else {
2499                 *x_predecim = max_decim_limit;
2500                 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2501                                 dss_has_feature(FEAT_BURST_2D)) ?
2502                                 2 : max_decim_limit;
2503         }
2504
2505         if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2506             color_mode == OMAP_DSS_COLOR_CLUT2 ||
2507             color_mode == OMAP_DSS_COLOR_CLUT4 ||
2508             color_mode == OMAP_DSS_COLOR_CLUT8) {
2509                 *x_predecim = 1;
2510                 *y_predecim = 1;
2511                 *five_taps = false;
2512                 return 0;
2513         }
2514
2515         decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2516         decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2517
2518         if (decim_x > *x_predecim || out_width > width * 8)
2519                 return -EINVAL;
2520
2521         if (decim_y > *y_predecim || out_height > height * 8)
2522                 return -EINVAL;
2523
2524         ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2525                 out_width, out_height, color_mode, five_taps,
2526                 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2527                 mem_to_mem);
2528         if (ret)
2529                 return ret;
2530
2531         DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2532                 width, height,
2533                 out_width, out_height,
2534                 out_width / width, DIV_FRAC(out_width, width),
2535                 out_height / height, DIV_FRAC(out_height, height),
2536
2537                 decim_x, decim_y,
2538                 width / decim_x, height / decim_y,
2539                 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2540                 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2541
2542                 *five_taps ? 5 : 3,
2543                 core_clk, dispc_core_clk_rate());
2544
2545         if (!core_clk || core_clk > dispc_core_clk_rate()) {
2546                 DSSERR("failed to set up scaling, "
2547                         "required core clk rate = %lu Hz, "
2548                         "current core clk rate = %lu Hz\n",
2549                         core_clk, dispc_core_clk_rate());
2550                 return -EINVAL;
2551         }
2552
2553         *x_predecim = decim_x;
2554         *y_predecim = decim_y;
2555         return 0;
2556 }
2557
2558 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2559                 const struct omap_overlay_info *oi,
2560                 const struct omap_video_timings *timings,
2561                 int *x_predecim, int *y_predecim)
2562 {
2563         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2564         bool five_taps = true;
2565         bool fieldmode = false;
2566         u16 in_height = oi->height;
2567         u16 in_width = oi->width;
2568         bool ilace = timings->interlace;
2569         u16 out_width, out_height;
2570         int pos_x = oi->pos_x;
2571         unsigned long pclk = dispc_mgr_pclk_rate(channel);
2572         unsigned long lclk = dispc_mgr_lclk_rate(channel);
2573
2574         out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2575         out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2576
2577         if (ilace && oi->height == out_height)
2578                 fieldmode = true;
2579
2580         if (ilace) {
2581                 if (fieldmode)
2582                         in_height /= 2;
2583                 out_height /= 2;
2584
2585                 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2586                                 in_height, out_height);
2587         }
2588
2589         if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2590                 return -EINVAL;
2591
2592         return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2593                         in_height, out_width, out_height, oi->color_mode,
2594                         &five_taps, x_predecim, y_predecim, pos_x,
2595                         oi->rotation_type, false);
2596 }
2597 EXPORT_SYMBOL(dispc_ovl_check);
2598
2599 static int dispc_ovl_setup_common(enum omap_plane plane,
2600                 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2601                 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2602                 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2603                 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2604                 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2605                 bool replication, const struct omap_video_timings *mgr_timings,
2606                 bool mem_to_mem)
2607 {
2608         bool five_taps = true;
2609         bool fieldmode = false;
2610         int r, cconv = 0;
2611         unsigned offset0, offset1;
2612         s32 row_inc;
2613         s32 pix_inc;
2614         u16 frame_width, frame_height;
2615         unsigned int field_offset = 0;
2616         u16 in_height = height;
2617         u16 in_width = width;
2618         int x_predecim = 1, y_predecim = 1;
2619         bool ilace = mgr_timings->interlace;
2620         unsigned long pclk = dispc_plane_pclk_rate(plane);
2621         unsigned long lclk = dispc_plane_lclk_rate(plane);
2622
2623         if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2624                 return -EINVAL;
2625
2626         switch (color_mode) {
2627         case OMAP_DSS_COLOR_YUV2:
2628         case OMAP_DSS_COLOR_UYVY:
2629         case OMAP_DSS_COLOR_NV12:
2630                 if (in_width & 1) {
2631                         DSSERR("input width %d is not even for YUV format\n",
2632                                 in_width);
2633                         return -EINVAL;
2634                 }
2635                 break;
2636
2637         default:
2638                 break;
2639         }
2640
2641         out_width = out_width == 0 ? width : out_width;
2642         out_height = out_height == 0 ? height : out_height;
2643
2644         if (ilace && height == out_height)
2645                 fieldmode = true;
2646
2647         if (ilace) {
2648                 if (fieldmode)
2649                         in_height /= 2;
2650                 pos_y /= 2;
2651                 out_height /= 2;
2652
2653                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2654                         "out_height %d\n", in_height, pos_y,
2655                         out_height);
2656         }
2657
2658         if (!dss_feat_color_mode_supported(plane, color_mode))
2659                 return -EINVAL;
2660
2661         r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2662                         in_height, out_width, out_height, color_mode,
2663                         &five_taps, &x_predecim, &y_predecim, pos_x,
2664                         rotation_type, mem_to_mem);
2665         if (r)
2666                 return r;
2667
2668         in_width = in_width / x_predecim;
2669         in_height = in_height / y_predecim;
2670
2671         if (x_predecim > 1 || y_predecim > 1)
2672                 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2673                         x_predecim, y_predecim, in_width, in_height);
2674
2675         switch (color_mode) {
2676         case OMAP_DSS_COLOR_YUV2:
2677         case OMAP_DSS_COLOR_UYVY:
2678         case OMAP_DSS_COLOR_NV12:
2679                 if (in_width & 1) {
2680                         DSSDBG("predecimated input width is not even for YUV format\n");
2681                         DSSDBG("adjusting input width %d -> %d\n",
2682                                 in_width, in_width & ~1);
2683
2684                         in_width &= ~1;
2685                 }
2686                 break;
2687
2688         default:
2689                 break;
2690         }
2691
2692         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2693                         color_mode == OMAP_DSS_COLOR_UYVY ||
2694                         color_mode == OMAP_DSS_COLOR_NV12)
2695                 cconv = 1;
2696
2697         if (ilace && !fieldmode) {
2698                 /*
2699                  * when downscaling the bottom field may have to start several
2700                  * source lines below the top field. Unfortunately ACCUI
2701                  * registers will only hold the fractional part of the offset
2702                  * so the integer part must be added to the base address of the
2703                  * bottom field.
2704                  */
2705                 if (!in_height || in_height == out_height)
2706                         field_offset = 0;
2707                 else
2708                         field_offset = in_height / out_height / 2;
2709         }
2710
2711         /* Fields are independent but interleaved in memory. */
2712         if (fieldmode)
2713                 field_offset = 1;
2714
2715         offset0 = 0;
2716         offset1 = 0;
2717         row_inc = 0;
2718         pix_inc = 0;
2719
2720         if (plane == OMAP_DSS_WB) {
2721                 frame_width = out_width;
2722                 frame_height = out_height;
2723         } else {
2724                 frame_width = in_width;
2725                 frame_height = height;
2726         }
2727
2728         if (rotation_type == OMAP_DSS_ROT_TILER)
2729                 calc_tiler_rotation_offset(screen_width, frame_width,
2730                                 color_mode, fieldmode, field_offset,
2731                                 &offset0, &offset1, &row_inc, &pix_inc,
2732                                 x_predecim, y_predecim);
2733         else if (rotation_type == OMAP_DSS_ROT_DMA)
2734                 calc_dma_rotation_offset(rotation, mirror, screen_width,
2735                                 frame_width, frame_height,
2736                                 color_mode, fieldmode, field_offset,
2737                                 &offset0, &offset1, &row_inc, &pix_inc,
2738                                 x_predecim, y_predecim);
2739         else
2740                 calc_vrfb_rotation_offset(rotation, mirror,
2741                                 screen_width, frame_width, frame_height,
2742                                 color_mode, fieldmode, field_offset,
2743                                 &offset0, &offset1, &row_inc, &pix_inc,
2744                                 x_predecim, y_predecim);
2745
2746         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2747                         offset0, offset1, row_inc, pix_inc);
2748
2749         dispc_ovl_set_color_mode(plane, color_mode);
2750
2751         dispc_ovl_configure_burst_type(plane, rotation_type);
2752
2753         dispc_ovl_set_ba0(plane, paddr + offset0);
2754         dispc_ovl_set_ba1(plane, paddr + offset1);
2755
2756         if (OMAP_DSS_COLOR_NV12 == color_mode) {
2757                 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2758                 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2759         }
2760
2761         if (dispc.feat->last_pixel_inc_missing)
2762                 row_inc += pix_inc - 1;
2763
2764         dispc_ovl_set_row_inc(plane, row_inc);
2765         dispc_ovl_set_pix_inc(plane, pix_inc);
2766
2767         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2768                         in_height, out_width, out_height);
2769
2770         dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2771
2772         dispc_ovl_set_input_size(plane, in_width, in_height);
2773
2774         if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2775                 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2776                                    out_height, ilace, five_taps, fieldmode,
2777                                    color_mode, rotation);
2778                 dispc_ovl_set_output_size(plane, out_width, out_height);
2779                 dispc_ovl_set_vid_color_conv(plane, cconv);
2780         }
2781
2782         dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2783                         color_mode);
2784
2785         dispc_ovl_set_zorder(plane, caps, zorder);
2786         dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2787         dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2788
2789         dispc_ovl_enable_replication(plane, caps, replication);
2790
2791         return 0;
2792 }
2793
2794 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2795                 bool replication, const struct omap_video_timings *mgr_timings,
2796                 bool mem_to_mem)
2797 {
2798         int r;
2799         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2800         enum omap_channel channel;
2801
2802         channel = dispc_ovl_get_channel_out(plane);
2803
2804         DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2805                 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2806                 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2807                 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2808                 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2809
2810         r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2811                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2812                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2813                 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2814                 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2815
2816         return r;
2817 }
2818 EXPORT_SYMBOL(dispc_ovl_setup);
2819
2820 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2821                 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2822 {
2823         int r;
2824         u32 l;
2825         enum omap_plane plane = OMAP_DSS_WB;
2826         const int pos_x = 0, pos_y = 0;
2827         const u8 zorder = 0, global_alpha = 0;
2828         const bool replication = false;
2829         bool truncation;
2830         int in_width = mgr_timings->x_res;
2831         int in_height = mgr_timings->y_res;
2832         enum omap_overlay_caps caps =
2833                 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2834
2835         DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2836                 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2837                 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2838                 wi->mirror);
2839
2840         r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2841                 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2842                 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2843                 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2844                 replication, mgr_timings, mem_to_mem);
2845
2846         switch (wi->color_mode) {
2847         case OMAP_DSS_COLOR_RGB16:
2848         case OMAP_DSS_COLOR_RGB24P:
2849         case OMAP_DSS_COLOR_ARGB16:
2850         case OMAP_DSS_COLOR_RGBA16:
2851         case OMAP_DSS_COLOR_RGB12U:
2852         case OMAP_DSS_COLOR_ARGB16_1555:
2853         case OMAP_DSS_COLOR_XRGB16_1555:
2854         case OMAP_DSS_COLOR_RGBX16:
2855                 truncation = true;
2856                 break;
2857         default:
2858                 truncation = false;
2859                 break;
2860         }
2861
2862         /* setup extra DISPC_WB_ATTRIBUTES */
2863         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2864         l = FLD_MOD(l, truncation, 10, 10);     /* TRUNCATIONENABLE */
2865         l = FLD_MOD(l, mem_to_mem, 19, 19);     /* WRITEBACKMODE */
2866         if (mem_to_mem)
2867                 l = FLD_MOD(l, 1, 26, 24);      /* CAPTUREMODE */
2868         else
2869                 l = FLD_MOD(l, 0, 26, 24);      /* CAPTUREMODE */
2870         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2871
2872         if (mem_to_mem) {
2873                 /* WBDELAYCOUNT */
2874                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2875         } else {
2876                 int wbdelay;
2877
2878                 wbdelay = min(mgr_timings->vfp + mgr_timings->vsw +
2879                         mgr_timings->vbp, 255);
2880
2881                 /* WBDELAYCOUNT */
2882                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2883         }
2884
2885         return r;
2886 }
2887
2888 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2889 {
2890         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2891
2892         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2893
2894         return 0;
2895 }
2896 EXPORT_SYMBOL(dispc_ovl_enable);
2897
2898 bool dispc_ovl_enabled(enum omap_plane plane)
2899 {
2900         return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2901 }
2902 EXPORT_SYMBOL(dispc_ovl_enabled);
2903
2904 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2905 {
2906         mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2907         /* flush posted write */
2908         mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2909 }
2910 EXPORT_SYMBOL(dispc_mgr_enable);
2911
2912 bool dispc_mgr_is_enabled(enum omap_channel channel)
2913 {
2914         return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2915 }
2916 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2917
2918 void dispc_wb_enable(bool enable)
2919 {
2920         dispc_ovl_enable(OMAP_DSS_WB, enable);
2921 }
2922
2923 bool dispc_wb_is_enabled(void)
2924 {
2925         return dispc_ovl_enabled(OMAP_DSS_WB);
2926 }
2927
2928 static void dispc_lcd_enable_signal_polarity(bool act_high)
2929 {
2930         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2931                 return;
2932
2933         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2934 }
2935
2936 void dispc_lcd_enable_signal(bool enable)
2937 {
2938         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2939                 return;
2940
2941         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2942 }
2943
2944 void dispc_pck_free_enable(bool enable)
2945 {
2946         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2947                 return;
2948
2949         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2950 }
2951
2952 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2953 {
2954         mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2955 }
2956
2957
2958 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2959 {
2960         mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2961 }
2962
2963 static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2964 {
2965         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2966 }
2967
2968
2969 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2970 {
2971         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2972 }
2973
2974 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2975                 enum omap_dss_trans_key_type type,
2976                 u32 trans_key)
2977 {
2978         mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2979
2980         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2981 }
2982
2983 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2984 {
2985         mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2986 }
2987
2988 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2989                 bool enable)
2990 {
2991         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2992                 return;
2993
2994         if (ch == OMAP_DSS_CHANNEL_LCD)
2995                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2996         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2997                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2998 }
2999
3000 void dispc_mgr_setup(enum omap_channel channel,
3001                 const struct omap_overlay_manager_info *info)
3002 {
3003         dispc_mgr_set_default_color(channel, info->default_color);
3004         dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
3005         dispc_mgr_enable_trans_key(channel, info->trans_enabled);
3006         dispc_mgr_enable_alpha_fixed_zorder(channel,
3007                         info->partial_alpha_enabled);
3008         if (dss_has_feature(FEAT_CPR)) {
3009                 dispc_mgr_enable_cpr(channel, info->cpr_enable);
3010                 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
3011         }
3012 }
3013 EXPORT_SYMBOL(dispc_mgr_setup);
3014
3015 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
3016 {
3017         int code;
3018
3019         switch (data_lines) {
3020         case 12:
3021                 code = 0;
3022                 break;
3023         case 16:
3024                 code = 1;
3025                 break;
3026         case 18:
3027                 code = 2;
3028                 break;
3029         case 24:
3030                 code = 3;
3031                 break;
3032         default:
3033                 BUG();
3034                 return;
3035         }
3036
3037         mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
3038 }
3039
3040 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
3041 {
3042         u32 l;
3043         int gpout0, gpout1;
3044
3045         switch (mode) {
3046         case DSS_IO_PAD_MODE_RESET:
3047                 gpout0 = 0;
3048                 gpout1 = 0;
3049                 break;
3050         case DSS_IO_PAD_MODE_RFBI:
3051                 gpout0 = 1;
3052                 gpout1 = 0;
3053                 break;
3054         case DSS_IO_PAD_MODE_BYPASS:
3055                 gpout0 = 1;
3056                 gpout1 = 1;
3057                 break;
3058         default:
3059                 BUG();
3060                 return;
3061         }
3062
3063         l = dispc_read_reg(DISPC_CONTROL);
3064         l = FLD_MOD(l, gpout0, 15, 15);
3065         l = FLD_MOD(l, gpout1, 16, 16);
3066         dispc_write_reg(DISPC_CONTROL, l);
3067 }
3068
3069 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
3070 {
3071         mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
3072 }
3073
3074 void dispc_mgr_set_lcd_config(enum omap_channel channel,
3075                 const struct dss_lcd_mgr_config *config)
3076 {
3077         dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3078
3079         dispc_mgr_enable_stallmode(channel, config->stallmode);
3080         dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3081
3082         dispc_mgr_set_clock_div(channel, &config->clock_info);
3083
3084         dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3085
3086         dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3087
3088         dispc_mgr_set_lcd_type_tft(channel);
3089 }
3090 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
3091
3092 static bool _dispc_mgr_size_ok(u16 width, u16 height)
3093 {
3094         return width <= dispc.feat->mgr_width_max &&
3095                 height <= dispc.feat->mgr_height_max;
3096 }
3097
3098 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3099                 int vsw, int vfp, int vbp)
3100 {
3101         if (hsw < 1 || hsw > dispc.feat->sw_max ||
3102                         hfp < 1 || hfp > dispc.feat->hp_max ||
3103                         hbp < 1 || hbp > dispc.feat->hp_max ||
3104                         vsw < 1 || vsw > dispc.feat->sw_max ||
3105                         vfp < 0 || vfp > dispc.feat->vp_max ||
3106                         vbp < 0 || vbp > dispc.feat->vp_max)
3107                 return false;
3108         return true;
3109 }
3110
3111 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3112                 unsigned long pclk)
3113 {
3114         if (dss_mgr_is_lcd(channel))
3115                 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3116         else
3117                 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3118 }
3119
3120 bool dispc_mgr_timings_ok(enum omap_channel channel,
3121                 const struct omap_video_timings *timings)
3122 {
3123         if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3124                 return false;
3125
3126         if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3127                 return false;
3128
3129         if (dss_mgr_is_lcd(channel)) {
3130                 /* TODO: OMAP4+ supports interlace for LCD outputs */
3131                 if (timings->interlace)
3132                         return false;
3133
3134                 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
3135                                 timings->hbp, timings->vsw, timings->vfp,
3136                                 timings->vbp))
3137                         return false;
3138         }
3139
3140         return true;
3141 }
3142
3143 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3144                 int hfp, int hbp, int vsw, int vfp, int vbp,
3145                 enum omap_dss_signal_level vsync_level,
3146                 enum omap_dss_signal_level hsync_level,
3147                 enum omap_dss_signal_edge data_pclk_edge,
3148                 enum omap_dss_signal_level de_level,
3149                 enum omap_dss_signal_edge sync_pclk_edge)
3150
3151 {
3152         u32 timing_h, timing_v, l;
3153         bool onoff, rf, ipc, vs, hs, de;
3154
3155         timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3156                         FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3157                         FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3158         timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3159                         FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3160                         FLD_VAL(vbp, dispc.feat->bp_start, 20);
3161
3162         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3163         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3164
3165         switch (vsync_level) {
3166         case OMAPDSS_SIG_ACTIVE_LOW:
3167                 vs = true;
3168                 break;
3169         case OMAPDSS_SIG_ACTIVE_HIGH:
3170                 vs = false;
3171                 break;
3172         default:
3173                 BUG();
3174         }
3175
3176         switch (hsync_level) {
3177         case OMAPDSS_SIG_ACTIVE_LOW:
3178                 hs = true;
3179                 break;
3180         case OMAPDSS_SIG_ACTIVE_HIGH:
3181                 hs = false;
3182                 break;
3183         default:
3184                 BUG();
3185         }
3186
3187         switch (de_level) {
3188         case OMAPDSS_SIG_ACTIVE_LOW:
3189                 de = true;
3190                 break;
3191         case OMAPDSS_SIG_ACTIVE_HIGH:
3192                 de = false;
3193                 break;
3194         default:
3195                 BUG();
3196         }
3197
3198         switch (data_pclk_edge) {
3199         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3200                 ipc = false;
3201                 break;
3202         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3203                 ipc = true;
3204                 break;
3205         default:
3206                 BUG();
3207         }
3208
3209         /* always use the 'rf' setting */
3210         onoff = true;
3211
3212         switch (sync_pclk_edge) {
3213         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3214                 rf = false;
3215                 break;
3216         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3217                 rf = true;
3218                 break;
3219         default:
3220                 BUG();
3221         }
3222
3223         l = FLD_VAL(onoff, 17, 17) |
3224                 FLD_VAL(rf, 16, 16) |
3225                 FLD_VAL(de, 15, 15) |
3226                 FLD_VAL(ipc, 14, 14) |
3227                 FLD_VAL(hs, 13, 13) |
3228                 FLD_VAL(vs, 12, 12);
3229
3230         /* always set ALIGN bit when available */
3231         if (dispc.feat->supports_sync_align)
3232                 l |= (1 << 18);
3233
3234         dispc_write_reg(DISPC_POL_FREQ(channel), l);
3235
3236         if (dispc.syscon_pol) {
3237                 const int shifts[] = {
3238                         [OMAP_DSS_CHANNEL_LCD] = 0,
3239                         [OMAP_DSS_CHANNEL_LCD2] = 1,
3240                         [OMAP_DSS_CHANNEL_LCD3] = 2,
3241                 };
3242
3243                 u32 mask, val;
3244
3245                 mask = (1 << 0) | (1 << 3) | (1 << 6);
3246                 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3247
3248                 mask <<= 16 + shifts[channel];
3249                 val <<= 16 + shifts[channel];
3250
3251                 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3252                         mask, val);
3253         }
3254 }
3255
3256 /* change name to mode? */
3257 void dispc_mgr_set_timings(enum omap_channel channel,
3258                 const struct omap_video_timings *timings)
3259 {
3260         unsigned xtot, ytot;
3261         unsigned long ht, vt;
3262         struct omap_video_timings t = *timings;
3263
3264         DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3265
3266         if (!dispc_mgr_timings_ok(channel, &t)) {
3267                 BUG();
3268                 return;
3269         }
3270
3271         if (dss_mgr_is_lcd(channel)) {
3272                 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3273                                 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3274                                 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3275
3276                 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3277                 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3278
3279                 ht = timings->pixelclock / xtot;
3280                 vt = timings->pixelclock / xtot / ytot;
3281
3282                 DSSDBG("pck %u\n", timings->pixelclock);
3283                 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3284                         t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3285                 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3286                         t.vsync_level, t.hsync_level, t.data_pclk_edge,
3287                         t.de_level, t.sync_pclk_edge);
3288
3289                 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3290         } else {
3291                 if (t.interlace)
3292                         t.y_res /= 2;
3293         }
3294
3295         dispc_mgr_set_size(channel, t.x_res, t.y_res);
3296 }
3297 EXPORT_SYMBOL(dispc_mgr_set_timings);
3298
3299 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3300                 u16 pck_div)
3301 {
3302         BUG_ON(lck_div < 1);
3303         BUG_ON(pck_div < 1);
3304
3305         dispc_write_reg(DISPC_DIVISORo(channel),
3306                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3307
3308         if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
3309                         channel == OMAP_DSS_CHANNEL_LCD)
3310                 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3311 }
3312
3313 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3314                 int *pck_div)
3315 {
3316         u32 l;
3317         l = dispc_read_reg(DISPC_DIVISORo(channel));
3318         *lck_div = FLD_GET(l, 23, 16);
3319         *pck_div = FLD_GET(l, 7, 0);
3320 }
3321
3322 static unsigned long dispc_fclk_rate(void)
3323 {
3324         struct dss_pll *pll;
3325         unsigned long r = 0;
3326
3327         switch (dss_get_dispc_clk_source()) {
3328         case OMAP_DSS_CLK_SRC_FCK:
3329                 r = dss_get_dispc_clk_rate();
3330                 break;
3331         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3332                 pll = dss_pll_find("dsi0");
3333                 if (!pll)
3334                         pll = dss_pll_find("video0");
3335
3336                 r = pll->cinfo.clkout[0];
3337                 break;
3338         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3339                 pll = dss_pll_find("dsi1");
3340                 if (!pll)
3341                         pll = dss_pll_find("video1");
3342
3343                 r = pll->cinfo.clkout[0];
3344                 break;
3345         default:
3346                 BUG();
3347                 return 0;
3348         }
3349
3350         return r;
3351 }
3352
3353 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3354 {
3355         struct dss_pll *pll;
3356         int lcd;
3357         unsigned long r;
3358         u32 l;
3359
3360         if (dss_mgr_is_lcd(channel)) {
3361                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3362
3363                 lcd = FLD_GET(l, 23, 16);
3364
3365                 switch (dss_get_lcd_clk_source(channel)) {
3366                 case OMAP_DSS_CLK_SRC_FCK:
3367                         r = dss_get_dispc_clk_rate();
3368                         break;
3369                 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3370                         pll = dss_pll_find("dsi0");
3371                         if (!pll)
3372                                 pll = dss_pll_find("video0");
3373
3374                         r = pll->cinfo.clkout[0];
3375                         break;
3376                 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3377                         pll = dss_pll_find("dsi1");
3378                         if (!pll)
3379                                 pll = dss_pll_find("video1");
3380
3381                         r = pll->cinfo.clkout[0];
3382                         break;
3383                 default:
3384                         BUG();
3385                         return 0;
3386                 }
3387
3388                 return r / lcd;
3389         } else {
3390                 return dispc_fclk_rate();
3391         }
3392 }
3393
3394 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3395 {
3396         unsigned long r;
3397
3398         if (dss_mgr_is_lcd(channel)) {
3399                 int pcd;
3400                 u32 l;
3401
3402                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3403
3404                 pcd = FLD_GET(l, 7, 0);
3405
3406                 r = dispc_mgr_lclk_rate(channel);
3407
3408                 return r / pcd;
3409         } else {
3410                 return dispc.tv_pclk_rate;
3411         }
3412 }
3413
3414 void dispc_set_tv_pclk(unsigned long pclk)
3415 {
3416         dispc.tv_pclk_rate = pclk;
3417 }
3418
3419 static unsigned long dispc_core_clk_rate(void)
3420 {
3421         return dispc.core_clk_rate;
3422 }
3423
3424 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3425 {
3426         enum omap_channel channel;
3427
3428         if (plane == OMAP_DSS_WB)
3429                 return 0;
3430
3431         channel = dispc_ovl_get_channel_out(plane);
3432
3433         return dispc_mgr_pclk_rate(channel);
3434 }
3435
3436 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3437 {
3438         enum omap_channel channel;
3439
3440         if (plane == OMAP_DSS_WB)
3441                 return 0;
3442
3443         channel = dispc_ovl_get_channel_out(plane);
3444
3445         return dispc_mgr_lclk_rate(channel);
3446 }
3447
3448 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3449 {
3450         int lcd, pcd;
3451         enum omap_dss_clk_source lcd_clk_src;
3452
3453         seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3454
3455         lcd_clk_src = dss_get_lcd_clk_source(channel);
3456
3457         seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3458                 dss_get_generic_clk_source_name(lcd_clk_src),
3459                 dss_feat_get_clk_source_name(lcd_clk_src));
3460
3461         dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3462
3463         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3464                 dispc_mgr_lclk_rate(channel), lcd);
3465         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3466                 dispc_mgr_pclk_rate(channel), pcd);
3467 }
3468
3469 void dispc_dump_clocks(struct seq_file *s)
3470 {
3471         int lcd;
3472         u32 l;
3473         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3474
3475         if (dispc_runtime_get())
3476                 return;
3477
3478         seq_printf(s, "- DISPC -\n");
3479
3480         seq_printf(s, "dispc fclk source = %s (%s)\n",
3481                         dss_get_generic_clk_source_name(dispc_clk_src),
3482                         dss_feat_get_clk_source_name(dispc_clk_src));
3483
3484         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3485
3486         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3487                 seq_printf(s, "- DISPC-CORE-CLK -\n");
3488                 l = dispc_read_reg(DISPC_DIVISOR);
3489                 lcd = FLD_GET(l, 23, 16);
3490
3491                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3492                                 (dispc_fclk_rate()/lcd), lcd);
3493         }
3494
3495         dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3496
3497         if (dss_has_feature(FEAT_MGR_LCD2))
3498                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3499         if (dss_has_feature(FEAT_MGR_LCD3))
3500                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3501
3502         dispc_runtime_put();
3503 }
3504
3505 static void dispc_dump_regs(struct seq_file *s)
3506 {
3507         int i, j;
3508         const char *mgr_names[] = {
3509                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
3510                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
3511                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
3512                 [OMAP_DSS_CHANNEL_LCD3]         = "LCD3",
3513         };
3514         const char *ovl_names[] = {
3515                 [OMAP_DSS_GFX]          = "GFX",
3516                 [OMAP_DSS_VIDEO1]       = "VID1",
3517                 [OMAP_DSS_VIDEO2]       = "VID2",
3518                 [OMAP_DSS_VIDEO3]       = "VID3",
3519                 [OMAP_DSS_WB]           = "WB",
3520         };
3521         const char **p_names;
3522
3523 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3524
3525         if (dispc_runtime_get())
3526                 return;
3527
3528         /* DISPC common registers */
3529         DUMPREG(DISPC_REVISION);
3530         DUMPREG(DISPC_SYSCONFIG);
3531         DUMPREG(DISPC_SYSSTATUS);
3532         DUMPREG(DISPC_IRQSTATUS);
3533         DUMPREG(DISPC_IRQENABLE);
3534         DUMPREG(DISPC_CONTROL);
3535         DUMPREG(DISPC_CONFIG);
3536         DUMPREG(DISPC_CAPABLE);
3537         DUMPREG(DISPC_LINE_STATUS);
3538         DUMPREG(DISPC_LINE_NUMBER);
3539         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3540                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3541                 DUMPREG(DISPC_GLOBAL_ALPHA);
3542         if (dss_has_feature(FEAT_MGR_LCD2)) {
3543                 DUMPREG(DISPC_CONTROL2);
3544                 DUMPREG(DISPC_CONFIG2);
3545         }
3546         if (dss_has_feature(FEAT_MGR_LCD3)) {
3547                 DUMPREG(DISPC_CONTROL3);
3548                 DUMPREG(DISPC_CONFIG3);
3549         }
3550         if (dss_has_feature(FEAT_MFLAG))
3551                 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3552
3553 #undef DUMPREG
3554
3555 #define DISPC_REG(i, name) name(i)
3556 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3557         (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3558         dispc_read_reg(DISPC_REG(i, r)))
3559
3560         p_names = mgr_names;
3561
3562         /* DISPC channel specific registers */
3563         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3564                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3565                 DUMPREG(i, DISPC_TRANS_COLOR);
3566                 DUMPREG(i, DISPC_SIZE_MGR);
3567
3568                 if (i == OMAP_DSS_CHANNEL_DIGIT)
3569                         continue;
3570
3571                 DUMPREG(i, DISPC_TIMING_H);
3572                 DUMPREG(i, DISPC_TIMING_V);
3573                 DUMPREG(i, DISPC_POL_FREQ);
3574                 DUMPREG(i, DISPC_DIVISORo);
3575
3576                 DUMPREG(i, DISPC_DATA_CYCLE1);
3577                 DUMPREG(i, DISPC_DATA_CYCLE2);
3578                 DUMPREG(i, DISPC_DATA_CYCLE3);
3579
3580                 if (dss_has_feature(FEAT_CPR)) {
3581                         DUMPREG(i, DISPC_CPR_COEF_R);
3582                         DUMPREG(i, DISPC_CPR_COEF_G);
3583                         DUMPREG(i, DISPC_CPR_COEF_B);
3584                 }
3585         }
3586
3587         p_names = ovl_names;
3588
3589         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3590                 DUMPREG(i, DISPC_OVL_BA0);
3591                 DUMPREG(i, DISPC_OVL_BA1);
3592                 DUMPREG(i, DISPC_OVL_POSITION);
3593                 DUMPREG(i, DISPC_OVL_SIZE);
3594                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3595                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3596                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3597                 DUMPREG(i, DISPC_OVL_ROW_INC);
3598                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3599
3600                 if (dss_has_feature(FEAT_PRELOAD))
3601                         DUMPREG(i, DISPC_OVL_PRELOAD);
3602                 if (dss_has_feature(FEAT_MFLAG))
3603                         DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3604
3605                 if (i == OMAP_DSS_GFX) {
3606                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3607                         DUMPREG(i, DISPC_OVL_TABLE_BA);
3608                         continue;
3609                 }
3610
3611                 DUMPREG(i, DISPC_OVL_FIR);
3612                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3613                 DUMPREG(i, DISPC_OVL_ACCU0);
3614                 DUMPREG(i, DISPC_OVL_ACCU1);
3615                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3616                         DUMPREG(i, DISPC_OVL_BA0_UV);
3617                         DUMPREG(i, DISPC_OVL_BA1_UV);
3618                         DUMPREG(i, DISPC_OVL_FIR2);
3619                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3620                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3621                 }
3622                 if (dss_has_feature(FEAT_ATTR2))
3623                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3624         }
3625
3626         if (dispc.feat->has_writeback) {
3627                 i = OMAP_DSS_WB;
3628                 DUMPREG(i, DISPC_OVL_BA0);
3629                 DUMPREG(i, DISPC_OVL_BA1);
3630                 DUMPREG(i, DISPC_OVL_SIZE);
3631                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3632                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3633                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3634                 DUMPREG(i, DISPC_OVL_ROW_INC);
3635                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3636
3637                 if (dss_has_feature(FEAT_MFLAG))
3638                         DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3639
3640                 DUMPREG(i, DISPC_OVL_FIR);
3641                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3642                 DUMPREG(i, DISPC_OVL_ACCU0);
3643                 DUMPREG(i, DISPC_OVL_ACCU1);
3644                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3645                         DUMPREG(i, DISPC_OVL_BA0_UV);
3646                         DUMPREG(i, DISPC_OVL_BA1_UV);
3647                         DUMPREG(i, DISPC_OVL_FIR2);
3648                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3649                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3650                 }
3651                 if (dss_has_feature(FEAT_ATTR2))
3652                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3653         }
3654
3655 #undef DISPC_REG
3656 #undef DUMPREG
3657
3658 #define DISPC_REG(plane, name, i) name(plane, i)
3659 #define DUMPREG(plane, name, i) \
3660         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3661         (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3662         dispc_read_reg(DISPC_REG(plane, name, i)))
3663
3664         /* Video pipeline coefficient registers */
3665
3666         /* start from OMAP_DSS_VIDEO1 */
3667         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3668                 for (j = 0; j < 8; j++)
3669                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3670
3671                 for (j = 0; j < 8; j++)
3672                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3673
3674                 for (j = 0; j < 5; j++)
3675                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3676
3677                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3678                         for (j = 0; j < 8; j++)
3679                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3680                 }
3681
3682                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3683                         for (j = 0; j < 8; j++)
3684                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3685
3686                         for (j = 0; j < 8; j++)
3687                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3688
3689                         for (j = 0; j < 8; j++)
3690                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3691                 }
3692         }
3693
3694         dispc_runtime_put();
3695
3696 #undef DISPC_REG
3697 #undef DUMPREG
3698 }
3699
3700 /* calculate clock rates using dividers in cinfo */
3701 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3702                 struct dispc_clock_info *cinfo)
3703 {
3704         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3705                 return -EINVAL;
3706         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3707                 return -EINVAL;
3708
3709         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3710         cinfo->pck = cinfo->lck / cinfo->pck_div;
3711
3712         return 0;
3713 }
3714
3715 bool dispc_div_calc(unsigned long dispc,
3716                 unsigned long pck_min, unsigned long pck_max,
3717                 dispc_div_calc_func func, void *data)
3718 {
3719         int lckd, lckd_start, lckd_stop;
3720         int pckd, pckd_start, pckd_stop;
3721         unsigned long pck, lck;
3722         unsigned long lck_max;
3723         unsigned long pckd_hw_min, pckd_hw_max;
3724         unsigned min_fck_per_pck;
3725         unsigned long fck;
3726
3727 #ifdef CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK
3728         min_fck_per_pck = CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK;
3729 #else
3730         min_fck_per_pck = 0;
3731 #endif
3732
3733         pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3734         pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3735
3736         lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3737
3738         pck_min = pck_min ? pck_min : 1;
3739         pck_max = pck_max ? pck_max : ULONG_MAX;
3740
3741         lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3742         lckd_stop = min(dispc / pck_min, 255ul);
3743
3744         for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3745                 lck = dispc / lckd;
3746
3747                 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3748                 pckd_stop = min(lck / pck_min, pckd_hw_max);
3749
3750                 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3751                         pck = lck / pckd;
3752
3753                         /*
3754                          * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3755                          * clock, which means we're configuring DISPC fclk here
3756                          * also. Thus we need to use the calculated lck. For
3757                          * OMAP4+ the DISPC fclk is a separate clock.
3758                          */
3759                         if (dss_has_feature(FEAT_CORE_CLK_DIV))
3760                                 fck = dispc_core_clk_rate();
3761                         else
3762                                 fck = lck;
3763
3764                         if (fck < pck * min_fck_per_pck)
3765                                 continue;
3766
3767                         if (func(lckd, pckd, lck, pck, data))
3768                                 return true;
3769                 }
3770         }
3771
3772         return false;
3773 }
3774
3775 void dispc_mgr_set_clock_div(enum omap_channel channel,
3776                 const struct dispc_clock_info *cinfo)
3777 {
3778         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3779         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3780
3781         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3782 }
3783
3784 int dispc_mgr_get_clock_div(enum omap_channel channel,
3785                 struct dispc_clock_info *cinfo)
3786 {
3787         unsigned long fck;
3788
3789         fck = dispc_fclk_rate();
3790
3791         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3792         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3793
3794         cinfo->lck = fck / cinfo->lck_div;
3795         cinfo->pck = cinfo->lck / cinfo->pck_div;
3796
3797         return 0;
3798 }
3799
3800 u32 dispc_read_irqstatus(void)
3801 {
3802         return dispc_read_reg(DISPC_IRQSTATUS);
3803 }
3804 EXPORT_SYMBOL(dispc_read_irqstatus);
3805
3806 void dispc_clear_irqstatus(u32 mask)
3807 {
3808         dispc_write_reg(DISPC_IRQSTATUS, mask);
3809 }
3810 EXPORT_SYMBOL(dispc_clear_irqstatus);
3811
3812 u32 dispc_read_irqenable(void)
3813 {
3814         return dispc_read_reg(DISPC_IRQENABLE);
3815 }
3816 EXPORT_SYMBOL(dispc_read_irqenable);
3817
3818 void dispc_write_irqenable(u32 mask)
3819 {
3820         u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3821
3822         /* clear the irqstatus for newly enabled irqs */
3823         dispc_clear_irqstatus((mask ^ old_mask) & mask);
3824
3825         dispc_write_reg(DISPC_IRQENABLE, mask);
3826 }
3827 EXPORT_SYMBOL(dispc_write_irqenable);
3828
3829 void dispc_enable_sidle(void)
3830 {
3831         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3832 }
3833
3834 void dispc_disable_sidle(void)
3835 {
3836         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3837 }
3838
3839 static void _omap_dispc_initial_config(void)
3840 {
3841         u32 l;
3842
3843         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3844         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3845                 l = dispc_read_reg(DISPC_DIVISOR);
3846                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3847                 l = FLD_MOD(l, 1, 0, 0);
3848                 l = FLD_MOD(l, 1, 23, 16);
3849                 dispc_write_reg(DISPC_DIVISOR, l);
3850
3851                 dispc.core_clk_rate = dispc_fclk_rate();
3852         }
3853
3854         /* FUNCGATED */
3855         if (dss_has_feature(FEAT_FUNCGATED))
3856                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3857
3858         dispc_setup_color_conv_coef();
3859
3860         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3861
3862         dispc_init_fifos();
3863
3864         dispc_configure_burst_sizes();
3865
3866         dispc_ovl_enable_zorder_planes();
3867
3868         if (dispc.feat->mstandby_workaround)
3869                 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3870
3871         if (dss_has_feature(FEAT_MFLAG))
3872                 dispc_init_mflag();
3873 }
3874
3875 static const struct dispc_features omap24xx_dispc_feats = {
3876         .sw_start               =       5,
3877         .fp_start               =       15,
3878         .bp_start               =       27,
3879         .sw_max                 =       64,
3880         .vp_max                 =       255,
3881         .hp_max                 =       256,
3882         .mgr_width_start        =       10,
3883         .mgr_height_start       =       26,
3884         .mgr_width_max          =       2048,
3885         .mgr_height_max         =       2048,
3886         .max_lcd_pclk           =       66500000,
3887         .calc_scaling           =       dispc_ovl_calc_scaling_24xx,
3888         .calc_core_clk          =       calc_core_clk_24xx,
3889         .num_fifos              =       3,
3890         .no_framedone_tv        =       true,
3891         .set_max_preload        =       false,
3892         .last_pixel_inc_missing =       true,
3893 };
3894
3895 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
3896         .sw_start               =       5,
3897         .fp_start               =       15,
3898         .bp_start               =       27,
3899         .sw_max                 =       64,
3900         .vp_max                 =       255,
3901         .hp_max                 =       256,
3902         .mgr_width_start        =       10,
3903         .mgr_height_start       =       26,
3904         .mgr_width_max          =       2048,
3905         .mgr_height_max         =       2048,
3906         .max_lcd_pclk           =       173000000,
3907         .max_tv_pclk            =       59000000,
3908         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3909         .calc_core_clk          =       calc_core_clk_34xx,
3910         .num_fifos              =       3,
3911         .no_framedone_tv        =       true,
3912         .set_max_preload        =       false,
3913         .last_pixel_inc_missing =       true,
3914 };
3915
3916 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
3917         .sw_start               =       7,
3918         .fp_start               =       19,
3919         .bp_start               =       31,
3920         .sw_max                 =       256,
3921         .vp_max                 =       4095,
3922         .hp_max                 =       4096,
3923         .mgr_width_start        =       10,
3924         .mgr_height_start       =       26,
3925         .mgr_width_max          =       2048,
3926         .mgr_height_max         =       2048,
3927         .max_lcd_pclk           =       173000000,
3928         .max_tv_pclk            =       59000000,
3929         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3930         .calc_core_clk          =       calc_core_clk_34xx,
3931         .num_fifos              =       3,
3932         .no_framedone_tv        =       true,
3933         .set_max_preload        =       false,
3934         .last_pixel_inc_missing =       true,
3935 };
3936
3937 static const struct dispc_features omap44xx_dispc_feats = {
3938         .sw_start               =       7,
3939         .fp_start               =       19,
3940         .bp_start               =       31,
3941         .sw_max                 =       256,
3942         .vp_max                 =       4095,
3943         .hp_max                 =       4096,
3944         .mgr_width_start        =       10,
3945         .mgr_height_start       =       26,
3946         .mgr_width_max          =       2048,
3947         .mgr_height_max         =       2048,
3948         .max_lcd_pclk           =       170000000,
3949         .max_tv_pclk            =       185625000,
3950         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3951         .calc_core_clk          =       calc_core_clk_44xx,
3952         .num_fifos              =       5,
3953         .gfx_fifo_workaround    =       true,
3954         .set_max_preload        =       true,
3955         .supports_sync_align    =       true,
3956         .has_writeback          =       true,
3957 };
3958
3959 static const struct dispc_features omap54xx_dispc_feats = {
3960         .sw_start               =       7,
3961         .fp_start               =       19,
3962         .bp_start               =       31,
3963         .sw_max                 =       256,
3964         .vp_max                 =       4095,
3965         .hp_max                 =       4096,
3966         .mgr_width_start        =       11,
3967         .mgr_height_start       =       27,
3968         .mgr_width_max          =       4096,
3969         .mgr_height_max         =       4096,
3970         .max_lcd_pclk           =       170000000,
3971         .max_tv_pclk            =       186000000,
3972         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3973         .calc_core_clk          =       calc_core_clk_44xx,
3974         .num_fifos              =       5,
3975         .gfx_fifo_workaround    =       true,
3976         .mstandby_workaround    =       true,
3977         .set_max_preload        =       true,
3978         .supports_sync_align    =       true,
3979         .has_writeback          =       true,
3980 };
3981
3982 static int dispc_init_features(struct platform_device *pdev)
3983 {
3984         const struct dispc_features *src;
3985         struct dispc_features *dst;
3986
3987         dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3988         if (!dst) {
3989                 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3990                 return -ENOMEM;
3991         }
3992
3993         switch (omapdss_get_version()) {
3994         case OMAPDSS_VER_OMAP24xx:
3995                 src = &omap24xx_dispc_feats;
3996                 break;
3997
3998         case OMAPDSS_VER_OMAP34xx_ES1:
3999                 src = &omap34xx_rev1_0_dispc_feats;
4000                 break;
4001
4002         case OMAPDSS_VER_OMAP34xx_ES3:
4003         case OMAPDSS_VER_OMAP3630:
4004         case OMAPDSS_VER_AM35xx:
4005         case OMAPDSS_VER_AM43xx:
4006                 src = &omap34xx_rev3_0_dispc_feats;
4007                 break;
4008
4009         case OMAPDSS_VER_OMAP4430_ES1:
4010         case OMAPDSS_VER_OMAP4430_ES2:
4011         case OMAPDSS_VER_OMAP4:
4012                 src = &omap44xx_dispc_feats;
4013                 break;
4014
4015         case OMAPDSS_VER_OMAP5:
4016         case OMAPDSS_VER_DRA7xx:
4017                 src = &omap54xx_dispc_feats;
4018                 break;
4019
4020         default:
4021                 return -ENODEV;
4022         }
4023
4024         memcpy(dst, src, sizeof(*dst));
4025         dispc.feat = dst;
4026
4027         return 0;
4028 }
4029
4030 static irqreturn_t dispc_irq_handler(int irq, void *arg)
4031 {
4032         if (!dispc.is_enabled)
4033                 return IRQ_NONE;
4034
4035         return dispc.user_handler(irq, dispc.user_data);
4036 }
4037
4038 int dispc_request_irq(irq_handler_t handler, void *dev_id)
4039 {
4040         int r;
4041
4042         if (dispc.user_handler != NULL)
4043                 return -EBUSY;
4044
4045         dispc.user_handler = handler;
4046         dispc.user_data = dev_id;
4047
4048         /* ensure the dispc_irq_handler sees the values above */
4049         smp_wmb();
4050
4051         r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4052                              IRQF_SHARED, "OMAP DISPC", &dispc);
4053         if (r) {
4054                 dispc.user_handler = NULL;
4055                 dispc.user_data = NULL;
4056         }
4057
4058         return r;
4059 }
4060 EXPORT_SYMBOL(dispc_request_irq);
4061
4062 void dispc_free_irq(void *dev_id)
4063 {
4064         devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4065
4066         dispc.user_handler = NULL;
4067         dispc.user_data = NULL;
4068 }
4069 EXPORT_SYMBOL(dispc_free_irq);
4070
4071 /* DISPC HW IP initialisation */
4072 static int dispc_bind(struct device *dev, struct device *master, void *data)
4073 {
4074         struct platform_device *pdev = to_platform_device(dev);
4075         u32 rev;
4076         int r = 0;
4077         struct resource *dispc_mem;
4078         struct device_node *np = pdev->dev.of_node;
4079
4080         dispc.pdev = pdev;
4081
4082         spin_lock_init(&dispc.control_lock);
4083
4084         r = dispc_init_features(dispc.pdev);
4085         if (r)
4086                 return r;
4087
4088         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4089         if (!dispc_mem) {
4090                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4091                 return -EINVAL;
4092         }
4093
4094         dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4095                                   resource_size(dispc_mem));
4096         if (!dispc.base) {
4097                 DSSERR("can't ioremap DISPC\n");
4098                 return -ENOMEM;
4099         }
4100
4101         dispc.irq = platform_get_irq(dispc.pdev, 0);
4102         if (dispc.irq < 0) {
4103                 DSSERR("platform_get_irq failed\n");
4104                 return -ENODEV;
4105         }
4106
4107         if (np && of_property_read_bool(np, "syscon-pol")) {
4108                 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4109                 if (IS_ERR(dispc.syscon_pol)) {
4110                         dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4111                         return PTR_ERR(dispc.syscon_pol);
4112                 }
4113
4114                 if (of_property_read_u32_index(np, "syscon-pol", 1,
4115                                 &dispc.syscon_pol_offset)) {
4116                         dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4117                         return -EINVAL;
4118                 }
4119         }
4120
4121         pm_runtime_enable(&pdev->dev);
4122
4123         r = dispc_runtime_get();
4124         if (r)
4125                 goto err_runtime_get;
4126
4127         _omap_dispc_initial_config();
4128
4129         rev = dispc_read_reg(DISPC_REVISION);
4130         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4131                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4132
4133         dispc_runtime_put();
4134
4135         dss_init_overlay_managers();
4136
4137         dss_debugfs_create_file("dispc", dispc_dump_regs);
4138
4139         return 0;
4140
4141 err_runtime_get:
4142         pm_runtime_disable(&pdev->dev);
4143         return r;
4144 }
4145
4146 static void dispc_unbind(struct device *dev, struct device *master,
4147                                void *data)
4148 {
4149         pm_runtime_disable(dev);
4150
4151         dss_uninit_overlay_managers();
4152 }
4153
4154 static const struct component_ops dispc_component_ops = {
4155         .bind   = dispc_bind,
4156         .unbind = dispc_unbind,
4157 };
4158
4159 static int dispc_probe(struct platform_device *pdev)
4160 {
4161         return component_add(&pdev->dev, &dispc_component_ops);
4162 }
4163
4164 static int dispc_remove(struct platform_device *pdev)
4165 {
4166         component_del(&pdev->dev, &dispc_component_ops);
4167         return 0;
4168 }
4169
4170 static int dispc_runtime_suspend(struct device *dev)
4171 {
4172         dispc.is_enabled = false;
4173         /* ensure the dispc_irq_handler sees the is_enabled value */
4174         smp_wmb();
4175         /* wait for current handler to finish before turning the DISPC off */
4176         synchronize_irq(dispc.irq);
4177
4178         dispc_save_context();
4179
4180         return 0;
4181 }
4182
4183 static int dispc_runtime_resume(struct device *dev)
4184 {
4185         /*
4186          * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4187          * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4188          * _omap_dispc_initial_config(). We can thus use it to detect if
4189          * we have lost register context.
4190          */
4191         if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4192                 _omap_dispc_initial_config();
4193
4194                 dispc_restore_context();
4195         }
4196
4197         dispc.is_enabled = true;
4198         /* ensure the dispc_irq_handler sees the is_enabled value */
4199         smp_wmb();
4200
4201         return 0;
4202 }
4203
4204 static const struct dev_pm_ops dispc_pm_ops = {
4205         .runtime_suspend = dispc_runtime_suspend,
4206         .runtime_resume = dispc_runtime_resume,
4207 };
4208
4209 static const struct of_device_id dispc_of_match[] = {
4210         { .compatible = "ti,omap2-dispc", },
4211         { .compatible = "ti,omap3-dispc", },
4212         { .compatible = "ti,omap4-dispc", },
4213         { .compatible = "ti,omap5-dispc", },
4214         { .compatible = "ti,dra7-dispc", },
4215         {},
4216 };
4217
4218 static struct platform_driver omap_dispchw_driver = {
4219         .probe          = dispc_probe,
4220         .remove         = dispc_remove,
4221         .driver         = {
4222                 .name   = "omapdss_dispc",
4223                 .pm     = &dispc_pm_ops,
4224                 .of_match_table = dispc_of_match,
4225                 .suppress_bind_attrs = true,
4226         },
4227 };
4228
4229 int __init dispc_init_platform_driver(void)
4230 {
4231         return platform_driver_register(&omap_dispchw_driver);
4232 }
4233
4234 void dispc_uninit_platform_driver(void)
4235 {
4236         platform_driver_unregister(&omap_dispchw_driver);
4237 }