1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OMAP1 internal LCD controller
5 * Copyright (C) 2004 Nokia Corporation
6 * Author: Imre Deak <imre.deak@nokia.com>
8 #include <linux/module.h>
9 #include <linux/device.h>
10 #include <linux/interrupt.h>
11 #include <linux/spinlock.h>
12 #include <linux/err.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/vmalloc.h>
17 #include <linux/clk.h>
18 #include <linux/gfp.h>
20 #include <mach/lcdc.h>
21 #include <linux/omap-dma.h>
23 #include <asm/mach-types.h>
29 #define MODULE_NAME "lcdc"
31 #define MAX_PALETTE_SIZE PAGE_SIZE
34 OMAP_LCDC_LOAD_PALETTE,
36 OMAP_LCDC_LOAD_PALETTE_AND_FRAME
39 static struct omap_lcd_controller {
40 enum omapfb_update_mode update_mode;
43 unsigned long frame_offset;
48 enum omapfb_color_format color_mode;
51 dma_addr_t palette_phys;
55 unsigned int irq_mask;
56 struct completion last_frame_complete;
57 struct completion palette_load_complete;
59 struct omapfb_device *fbdev;
61 void (*dma_callback)(void *data);
62 void *dma_callback_data;
66 unsigned long vram_size;
69 static inline void enable_irqs(int mask)
71 lcdc.irq_mask |= mask;
74 static inline void disable_irqs(int mask)
76 lcdc.irq_mask &= ~mask;
79 static void set_load_mode(enum lcdc_load_mode mode)
83 l = omap_readl(OMAP_LCDC_CONTROL);
86 case OMAP_LCDC_LOAD_PALETTE:
89 case OMAP_LCDC_LOAD_FRAME:
92 case OMAP_LCDC_LOAD_PALETTE_AND_FRAME:
97 omap_writel(l, OMAP_LCDC_CONTROL);
100 static void enable_controller(void)
104 l = omap_readl(OMAP_LCDC_CONTROL);
105 l |= OMAP_LCDC_CTRL_LCD_EN;
106 l &= ~OMAP_LCDC_IRQ_MASK;
107 l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE; /* enabled IRQs */
108 omap_writel(l, OMAP_LCDC_CONTROL);
111 static void disable_controller_async(void)
116 l = omap_readl(OMAP_LCDC_CONTROL);
117 mask = OMAP_LCDC_CTRL_LCD_EN | OMAP_LCDC_IRQ_MASK;
119 * Preserve the DONE mask, since we still want to get the
120 * final DONE irq. It will be disabled in the IRQ handler.
122 mask &= ~OMAP_LCDC_IRQ_DONE;
124 omap_writel(l, OMAP_LCDC_CONTROL);
127 static void disable_controller(void)
129 init_completion(&lcdc.last_frame_complete);
130 disable_controller_async();
131 if (!wait_for_completion_timeout(&lcdc.last_frame_complete,
132 msecs_to_jiffies(500)))
133 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
136 static void reset_controller(u32 status)
138 static unsigned long reset_count;
139 static unsigned long last_jiffies;
141 disable_controller_async();
143 if (reset_count == 1 || time_after(jiffies, last_jiffies + HZ)) {
144 dev_err(lcdc.fbdev->dev,
145 "resetting (status %#010x,reset count %lu)\n",
146 status, reset_count);
147 last_jiffies = jiffies;
149 if (reset_count < 100) {
153 dev_err(lcdc.fbdev->dev,
154 "too many reset attempts, giving up.\n");
159 * Configure the LCD DMA according to the current mode specified by parameters
160 * in lcdc.fbdev and fbdev->var.
162 static void setup_lcd_dma(void)
164 static const int dma_elem_type[] = {
166 OMAP_DMA_DATA_TYPE_S8,
167 OMAP_DMA_DATA_TYPE_S16,
169 OMAP_DMA_DATA_TYPE_S32,
171 struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par;
172 struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
174 int esize, xelem, yelem;
176 src = lcdc.vram_phys + lcdc.frame_offset;
178 switch (var->rotate) {
180 if (plane->info.mirror || (src & 3) ||
181 lcdc.color_mode == OMAPFB_COLOR_YUV420 ||
186 xelem = lcdc.xres * lcdc.bpp / 8 / esize;
192 if (cpu_is_omap15xx()) {
196 xelem = lcdc.yres * lcdc.bpp / 16;
204 dev_dbg(lcdc.fbdev->dev,
205 "setup_dma: src %#010lx esize %d xelem %d yelem %d\n",
206 src, esize, xelem, yelem);
208 omap_set_lcd_dma_b1(src, xelem, yelem, dma_elem_type[esize]);
209 if (!cpu_is_omap15xx()) {
213 * YUV support is only for external mode when we have the
214 * YUV window embedded in a 16bpp frame buffer.
216 if (lcdc.color_mode == OMAPFB_COLOR_YUV420)
218 /* Set virtual xres elem size */
219 omap_set_lcd_dma_b1_vxres(
220 lcdc.screen_width * bpp / 8 / esize);
221 /* Setup transformations */
222 omap_set_lcd_dma_b1_rotation(var->rotate);
223 omap_set_lcd_dma_b1_mirror(plane->info.mirror);
225 omap_setup_lcd_dma();
228 static irqreturn_t lcdc_irq_handler(int irq, void *dev_id)
232 status = omap_readl(OMAP_LCDC_STATUS);
234 if (status & (OMAP_LCDC_STAT_FUF | OMAP_LCDC_STAT_SYNC_LOST))
235 reset_controller(status);
237 if (status & OMAP_LCDC_STAT_DONE) {
241 * Disable IRQ_DONE. The status bit will be cleared
242 * only when the controller is reenabled and we don't
243 * want to get more interrupts.
245 l = omap_readl(OMAP_LCDC_CONTROL);
246 l &= ~OMAP_LCDC_IRQ_DONE;
247 omap_writel(l, OMAP_LCDC_CONTROL);
248 complete(&lcdc.last_frame_complete);
250 if (status & OMAP_LCDC_STAT_LOADED_PALETTE) {
251 disable_controller_async();
252 complete(&lcdc.palette_load_complete);
257 * Clear these interrupt status bits.
258 * Sync_lost, FUF bits were cleared by disabling the LCD controller
259 * LOADED_PALETTE can be cleared this way only in palette only
260 * load mode. In other load modes it's cleared by disabling the
263 status &= ~(OMAP_LCDC_STAT_VSYNC |
264 OMAP_LCDC_STAT_LOADED_PALETTE |
266 OMAP_LCDC_STAT_LINE_INT);
267 omap_writel(status, OMAP_LCDC_STATUS);
272 * Change to a new video mode. We defer this to a later time to avoid any
273 * flicker and not to mess up the current LCD DMA context. For this we disable
274 * the LCD controller, which will generate a DONE irq after the last frame has
275 * been transferred. Then it'll be safe to reconfigure both the LCD controller
276 * as well as the LCD DMA.
278 static int omap_lcdc_setup_plane(int plane, int channel_out,
279 unsigned long offset, int screen_width,
280 int pos_x, int pos_y, int width, int height,
283 struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
284 struct lcd_panel *panel = lcdc.fbdev->panel;
287 if (var->rotate == 0) {
288 rot_x = panel->x_res;
289 rot_y = panel->y_res;
291 rot_x = panel->y_res;
292 rot_y = panel->x_res;
294 if (plane != 0 || channel_out != 0 || pos_x != 0 || pos_y != 0 ||
295 width > rot_x || height > rot_y) {
297 dev_dbg(lcdc.fbdev->dev,
298 "invalid plane params plane %d pos_x %d pos_y %d "
299 "w %d h %d\n", plane, pos_x, pos_y, width, height);
304 lcdc.frame_offset = offset;
307 lcdc.screen_width = screen_width;
308 lcdc.color_mode = color_mode;
310 switch (color_mode) {
311 case OMAPFB_COLOR_CLUT_8BPP:
313 lcdc.palette_code = 0x3000;
314 lcdc.palette_size = 512;
316 case OMAPFB_COLOR_RGB565:
318 lcdc.palette_code = 0x4000;
319 lcdc.palette_size = 32;
321 case OMAPFB_COLOR_RGB444:
323 lcdc.palette_code = 0x4000;
324 lcdc.palette_size = 32;
326 case OMAPFB_COLOR_YUV420:
332 case OMAPFB_COLOR_YUV422:
339 /* FIXME: other BPPs.
340 * bpp1: code 0, size 256
341 * bpp2: code 0x1000 size 256
342 * bpp4: code 0x2000 size 256
343 * bpp12: code 0x4000 size 32
345 dev_dbg(lcdc.fbdev->dev, "invalid color mode %d\n", color_mode);
355 if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
356 disable_controller();
365 static int omap_lcdc_enable_plane(int plane, int enable)
367 dev_dbg(lcdc.fbdev->dev,
368 "plane %d enable %d update_mode %d ext_mode %d\n",
369 plane, enable, lcdc.update_mode, lcdc.ext_mode);
370 if (plane != OMAPFB_PLANE_GFX)
377 * Configure the LCD DMA for a palette load operation and do the palette
378 * downloading synchronously. We don't use the frame+palette load mode of
379 * the controller, since the palette can always be downloaded separately.
381 static void load_palette(void)
385 palette = (u16 *)lcdc.palette_virt;
387 *(u16 *)palette &= 0x0fff;
388 *(u16 *)palette |= lcdc.palette_code;
390 omap_set_lcd_dma_b1(lcdc.palette_phys,
391 lcdc.palette_size / 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32);
393 omap_set_lcd_dma_single_transfer(1);
394 omap_setup_lcd_dma();
396 init_completion(&lcdc.palette_load_complete);
397 enable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
398 set_load_mode(OMAP_LCDC_LOAD_PALETTE);
400 if (!wait_for_completion_timeout(&lcdc.palette_load_complete,
401 msecs_to_jiffies(500)))
402 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
403 /* The controller gets disabled in the irq handler */
404 disable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
407 omap_set_lcd_dma_single_transfer(lcdc.ext_mode);
410 /* Used only in internal controller mode */
411 static int omap_lcdc_setcolreg(u_int regno, u16 red, u16 green, u16 blue,
412 u16 transp, int update_hw_pal)
416 if (lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255)
419 palette = (u16 *)lcdc.palette_virt;
421 palette[regno] &= ~0x0fff;
422 palette[regno] |= ((red >> 12) << 8) | ((green >> 12) << 4 ) |
426 disable_controller();
430 set_load_mode(OMAP_LCDC_LOAD_FRAME);
437 static void calc_ck_div(int is_tft, int pck, int *pck_div)
442 lck = clk_get_rate(lcdc.lcd_ck);
443 *pck_div = (lck + pck - 1) / pck;
445 *pck_div = max(2, *pck_div);
447 *pck_div = max(3, *pck_div);
448 if (*pck_div > 255) {
449 /* FIXME: try to adjust logic clock divider as well */
451 dev_warn(lcdc.fbdev->dev, "pixclock %d kHz too low.\n",
456 static inline void setup_regs(void)
459 struct lcd_panel *panel = lcdc.fbdev->panel;
460 int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
464 l = omap_readl(OMAP_LCDC_CONTROL);
465 l &= ~OMAP_LCDC_CTRL_LCD_TFT;
466 l |= is_tft ? OMAP_LCDC_CTRL_LCD_TFT : 0;
467 #ifdef CONFIG_MACH_OMAP_PALMTE
468 /* FIXME:if (machine_is_omap_palmte()) { */
469 /* PalmTE uses alternate TFT setting in 8BPP mode */
470 l |= (is_tft && panel->bpp == 8) ? 0x810000 : 0;
473 omap_writel(l, OMAP_LCDC_CONTROL);
475 l = omap_readl(OMAP_LCDC_TIMING2);
476 l &= ~(((1 << 6) - 1) << 20);
477 l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 20;
478 omap_writel(l, OMAP_LCDC_TIMING2);
480 l = panel->x_res - 1;
481 l |= (panel->hsw - 1) << 10;
482 l |= (panel->hfp - 1) << 16;
483 l |= (panel->hbp - 1) << 24;
484 omap_writel(l, OMAP_LCDC_TIMING0);
486 l = panel->y_res - 1;
487 l |= (panel->vsw - 1) << 10;
488 l |= panel->vfp << 16;
489 l |= panel->vbp << 24;
490 omap_writel(l, OMAP_LCDC_TIMING1);
492 l = omap_readl(OMAP_LCDC_TIMING2);
495 lck = clk_get_rate(lcdc.lcd_ck);
498 calc_ck_div(is_tft, panel->pixel_clock * 1000, &pcd);
500 dev_warn(lcdc.fbdev->dev,
501 "Pixel clock divider value is obsolete.\n"
502 "Try to set pixel_clock to %lu and pcd to 0 "
503 "in drivers/video/omap/lcd_%s.c and submit a patch.\n",
504 lck / panel->pcd / 1000, panel->name);
509 l |= panel->acb << 8;
510 omap_writel(l, OMAP_LCDC_TIMING2);
512 /* update panel info with the exact clock */
513 panel->pixel_clock = lck / pcd / 1000;
517 * Configure the LCD controller, download the color palette and start a looped
518 * DMA transfer of the frame image data. Called only in internal
521 static int omap_lcdc_set_update_mode(enum omapfb_update_mode mode)
525 if (mode != lcdc.update_mode) {
527 case OMAPFB_AUTO_UPDATE:
531 /* Setup and start LCD DMA */
534 set_load_mode(OMAP_LCDC_LOAD_FRAME);
535 enable_irqs(OMAP_LCDC_IRQ_DONE);
536 /* This will start the actual DMA transfer */
538 lcdc.update_mode = mode;
540 case OMAPFB_UPDATE_DISABLED:
541 disable_controller();
543 lcdc.update_mode = mode;
553 static enum omapfb_update_mode omap_lcdc_get_update_mode(void)
555 return lcdc.update_mode;
558 /* PM code called only in internal controller mode */
559 static void omap_lcdc_suspend(void)
561 omap_lcdc_set_update_mode(OMAPFB_UPDATE_DISABLED);
564 static void omap_lcdc_resume(void)
566 omap_lcdc_set_update_mode(OMAPFB_AUTO_UPDATE);
569 static void omap_lcdc_get_caps(int plane, struct omapfb_caps *caps)
574 int omap_lcdc_set_dma_callback(void (*callback)(void *data), void *data)
576 BUG_ON(callback == NULL);
578 if (lcdc.dma_callback)
581 lcdc.dma_callback = callback;
582 lcdc.dma_callback_data = data;
586 EXPORT_SYMBOL(omap_lcdc_set_dma_callback);
588 void omap_lcdc_free_dma_callback(void)
590 lcdc.dma_callback = NULL;
592 EXPORT_SYMBOL(omap_lcdc_free_dma_callback);
594 static void lcdc_dma_handler(u16 status, void *data)
596 if (lcdc.dma_callback)
597 lcdc.dma_callback(lcdc.dma_callback_data);
600 static int alloc_palette_ram(void)
602 lcdc.palette_virt = dma_alloc_wc(lcdc.fbdev->dev, MAX_PALETTE_SIZE,
603 &lcdc.palette_phys, GFP_KERNEL);
604 if (lcdc.palette_virt == NULL) {
605 dev_err(lcdc.fbdev->dev, "failed to alloc palette memory\n");
608 memset(lcdc.palette_virt, 0, MAX_PALETTE_SIZE);
613 static void free_palette_ram(void)
615 dma_free_wc(lcdc.fbdev->dev, MAX_PALETTE_SIZE, lcdc.palette_virt,
619 static int alloc_fbmem(struct omapfb_mem_region *region)
623 struct lcd_panel *panel = lcdc.fbdev->panel;
628 frame_size = PAGE_ALIGN(panel->x_res * bpp / 8 * panel->y_res);
629 if (region->size > frame_size)
630 frame_size = region->size;
631 lcdc.vram_size = frame_size;
632 lcdc.vram_virt = dma_alloc_wc(lcdc.fbdev->dev, lcdc.vram_size,
633 &lcdc.vram_phys, GFP_KERNEL);
634 if (lcdc.vram_virt == NULL) {
635 dev_err(lcdc.fbdev->dev, "unable to allocate FB DMA memory\n");
638 region->size = frame_size;
639 region->paddr = lcdc.vram_phys;
640 region->vaddr = lcdc.vram_virt;
643 memset(lcdc.vram_virt, 0, lcdc.vram_size);
648 static void free_fbmem(void)
650 dma_free_wc(lcdc.fbdev->dev, lcdc.vram_size, lcdc.vram_virt,
654 static int setup_fbmem(struct omapfb_mem_desc *req_md)
656 if (!req_md->region_cnt) {
657 dev_err(lcdc.fbdev->dev, "no memory regions defined\n");
661 if (req_md->region_cnt > 1) {
662 dev_err(lcdc.fbdev->dev, "only one plane is supported\n");
663 req_md->region_cnt = 1;
666 return alloc_fbmem(&req_md->region[0]);
669 static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode,
670 struct omapfb_mem_desc *req_vram)
680 lcdc.ext_mode = ext_mode;
683 omap_writel(l, OMAP_LCDC_CONTROL);
686 * According to errata some platforms have a clock rate limitiation
688 lcdc.lcd_ck = clk_get(fbdev->dev, "lcd_ck");
689 if (IS_ERR(lcdc.lcd_ck)) {
690 dev_err(fbdev->dev, "unable to access LCD clock\n");
691 r = PTR_ERR(lcdc.lcd_ck);
695 tc_ck = clk_get(fbdev->dev, "tc_ck");
697 dev_err(fbdev->dev, "unable to access TC clock\n");
702 rate = clk_get_rate(tc_ck);
705 if (machine_is_ams_delta())
707 if (machine_is_omap_h3())
709 r = clk_set_rate(lcdc.lcd_ck, rate);
711 dev_err(fbdev->dev, "failed to adjust LCD rate\n");
714 clk_enable(lcdc.lcd_ck);
716 r = request_irq(OMAP_LCDC_IRQ, lcdc_irq_handler, 0, MODULE_NAME, fbdev);
718 dev_err(fbdev->dev, "unable to get IRQ\n");
722 r = omap_request_lcd_dma(lcdc_dma_handler, NULL);
724 dev_err(fbdev->dev, "unable to get LCD DMA\n");
728 omap_set_lcd_dma_single_transfer(ext_mode);
729 omap_set_lcd_dma_ext_controller(ext_mode);
732 if ((r = alloc_palette_ram()) < 0)
735 if ((r = setup_fbmem(req_vram)) < 0)
738 pr_info("omapfb: LCDC initialized\n");
747 free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
749 clk_disable(lcdc.lcd_ck);
751 clk_put(lcdc.lcd_ck);
756 static void omap_lcdc_cleanup(void)
762 free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
763 clk_disable(lcdc.lcd_ck);
764 clk_put(lcdc.lcd_ck);
767 const struct lcd_ctrl omap1_int_ctrl = {
769 .init = omap_lcdc_init,
770 .cleanup = omap_lcdc_cleanup,
771 .get_caps = omap_lcdc_get_caps,
772 .set_update_mode = omap_lcdc_set_update_mode,
773 .get_update_mode = omap_lcdc_get_update_mode,
774 .update_window = NULL,
775 .suspend = omap_lcdc_suspend,
776 .resume = omap_lcdc_resume,
777 .setup_plane = omap_lcdc_setup_plane,
778 .enable_plane = omap_lcdc_enable_plane,
779 .setcolreg = omap_lcdc_setcolreg,