drivers/video/fbdev/mxsfb.c

   1 /*
   2  * Copyright (C) 2010 Juergen Beisert, Pengutronix
   3  *
   4  * This code is based on:
   5  * Author: Vitaly Wool <vital@embeddedalley.com>
   6  *
   7  * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   8  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version 2
  13  * of the License, or (at your option) any later version.
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #define DRIVER_NAME "mxsfb"
  21
  22 /**
  23  * @file
  24  * @brief LCDIF driver for i.MX23 and i.MX28
  25  *
  26  * The LCDIF support four modes of operation
  27  * - MPU interface (to drive smart displays) -> not supported yet
  28  * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet
  29  * - Dotclock interface (to drive LC displays with RGB data and sync signals)
  30  * - DVI (to drive ITU-R BT656)  -> not supported yet
  31  *
  32  * This driver depends on a correct setup of the pins used for this purpose
  33  * (platform specific).
  34  *
  35  * For the developer: Don't forget to set the data bus width to the display
  36  * in the imx_fb_videomode structure. You will else end up with ugly colours.
  37  * If you fight against jitter you can vary the clock delay. This is a feature
  38  * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give
  39  * the required value in the imx_fb_videomode structure.
  40  */
  41
  42 #include <linux/module.h>
  43 #include <linux/kernel.h>
  44 #include <linux/of_device.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/clk.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/io.h>
  49 #include <linux/fb.h>
  50 #include <linux/regulator/consumer.h>
  51 #include <video/of_display_timing.h>
  52 #include <video/of_videomode.h>
  53 #include <video/videomode.h>
  54
  55 #define REG_SET 4
  56 #define REG_CLR 8
  57
  58 #define LCDC_CTRL                       0x00
  59 #define LCDC_CTRL1                      0x10
  60 #define LCDC_V4_CTRL2                   0x20
  61 #define LCDC_V3_TRANSFER_COUNT          0x20
  62 #define LCDC_V4_TRANSFER_COUNT          0x30
  63 #define LCDC_V4_CUR_BUF                 0x40
  64 #define LCDC_V4_NEXT_BUF                0x50
  65 #define LCDC_V3_CUR_BUF                 0x30
  66 #define LCDC_V3_NEXT_BUF                0x40
  67 #define LCDC_TIMING                     0x60
  68 #define LCDC_VDCTRL0                    0x70
  69 #define LCDC_VDCTRL1                    0x80
  70 #define LCDC_VDCTRL2                    0x90
  71 #define LCDC_VDCTRL3                    0xa0
  72 #define LCDC_VDCTRL4                    0xb0
  73 #define LCDC_DVICTRL0                   0xc0
  74 #define LCDC_DVICTRL1                   0xd0
  75 #define LCDC_DVICTRL2                   0xe0
  76 #define LCDC_DVICTRL3                   0xf0
  77 #define LCDC_DVICTRL4                   0x100
  78 #define LCDC_V4_DATA                    0x180
  79 #define LCDC_V3_DATA                    0x1b0
  80 #define LCDC_V4_DEBUG0                  0x1d0
  81 #define LCDC_V3_DEBUG0                  0x1f0
  82
  83 #define CTRL_SFTRST                     (1 << 31)
  84 #define CTRL_CLKGATE                    (1 << 30)
  85 #define CTRL_BYPASS_COUNT               (1 << 19)
  86 #define CTRL_VSYNC_MODE                 (1 << 18)
  87 #define CTRL_DOTCLK_MODE                (1 << 17)
  88 #define CTRL_DATA_SELECT                (1 << 16)
  89 #define CTRL_SET_BUS_WIDTH(x)           (((x) & 0x3) << 10)
  90 #define CTRL_GET_BUS_WIDTH(x)           (((x) >> 10) & 0x3)
  91 #define CTRL_SET_WORD_LENGTH(x)         (((x) & 0x3) << 8)
  92 #define CTRL_GET_WORD_LENGTH(x)         (((x) >> 8) & 0x3)
  93 #define CTRL_MASTER                     (1 << 5)
  94 #define CTRL_DF16                       (1 << 3)
  95 #define CTRL_DF18                       (1 << 2)
  96 #define CTRL_DF24                       (1 << 1)
  97 #define CTRL_RUN                        (1 << 0)
  98
  99 #define CTRL1_FIFO_CLEAR                (1 << 21)
 100 #define CTRL1_SET_BYTE_PACKAGING(x)     (((x) & 0xf) << 16)
 101 #define CTRL1_GET_BYTE_PACKAGING(x)     (((x) >> 16) & 0xf)
 102
 103 #define TRANSFER_COUNT_SET_VCOUNT(x)    (((x) & 0xffff) << 16)
 104 #define TRANSFER_COUNT_GET_VCOUNT(x)    (((x) >> 16) & 0xffff)
 105 #define TRANSFER_COUNT_SET_HCOUNT(x)    ((x) & 0xffff)
 106 #define TRANSFER_COUNT_GET_HCOUNT(x)    ((x) & 0xffff)
 107
 108
 109 #define VDCTRL0_ENABLE_PRESENT          (1 << 28)
 110 #define VDCTRL0_VSYNC_ACT_HIGH          (1 << 27)
 111 #define VDCTRL0_HSYNC_ACT_HIGH          (1 << 26)
 112 #define VDCTRL0_DOTCLK_ACT_FALLING      (1 << 25)
 113 #define VDCTRL0_ENABLE_ACT_HIGH         (1 << 24)
 114 #define VDCTRL0_VSYNC_PERIOD_UNIT       (1 << 21)
 115 #define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT  (1 << 20)
 116 #define VDCTRL0_HALF_LINE               (1 << 19)
 117 #define VDCTRL0_HALF_LINE_MODE          (1 << 18)
 118 #define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
 119 #define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
 120
 121 #define VDCTRL2_SET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
 122 #define VDCTRL2_GET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
 123
 124 #define VDCTRL3_MUX_SYNC_SIGNALS        (1 << 29)
 125 #define VDCTRL3_VSYNC_ONLY              (1 << 28)
 126 #define SET_HOR_WAIT_CNT(x)             (((x) & 0xfff) << 16)
 127 #define GET_HOR_WAIT_CNT(x)             (((x) >> 16) & 0xfff)
 128 #define SET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
 129 #define GET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
 130
 131 #define VDCTRL4_SET_DOTCLK_DLY(x)       (((x) & 0x7) << 29) /* v4 only */
 132 #define VDCTRL4_GET_DOTCLK_DLY(x)       (((x) >> 29) & 0x7) /* v4 only */
 133 #define VDCTRL4_SYNC_SIGNALS_ON         (1 << 18)
 134 #define SET_DOTCLK_H_VALID_DATA_CNT(x)  ((x) & 0x3ffff)
 135
 136 #define DEBUG0_HSYNC                    (1 < 26)
 137 #define DEBUG0_VSYNC                    (1 < 25)
 138
 139 #define MIN_XRES                        120
 140 #define MIN_YRES                        120
 141
 142 #define RED 0
 143 #define GREEN 1
 144 #define BLUE 2
 145 #define TRANSP 3
 146
 147 #define STMLCDIF_8BIT  1 /** pixel data bus to the display is of 8 bit width */
 148 #define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
 149 #define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
 150 #define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
 151
 152 #define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
 153 #define MXSFB_SYNC_DOTCLK_FALLING_ACT   (1 << 7) /* negative edge sampling */
 154
 155 enum mxsfb_devtype {
 156         MXSFB_V3,
 157         MXSFB_V4,
 158 };
 159
 160 /* CPU dependent register offsets */
 161 struct mxsfb_devdata {
 162         unsigned transfer_count;
 163         unsigned cur_buf;
 164         unsigned next_buf;
 165         unsigned debug0;
 166         unsigned hs_wdth_mask;
 167         unsigned hs_wdth_shift;
 168         unsigned ipversion;
 169 };
 170
 171 struct mxsfb_info {
 172         struct platform_device *pdev;
 173         struct clk *clk;
 174         struct clk *clk_axi;
 175         struct clk *clk_disp_axi;
 176         void __iomem *base;     /* registers */
 177         unsigned allocated_size;
 178         int enabled;
 179         unsigned ld_intf_width;
 180         unsigned dotclk_delay;
 181         const struct mxsfb_devdata *devdata;
 182         u32 sync;
 183         struct regulator *reg_lcd;
 184 };
 185
 186 #define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
 187 #define mxsfb_is_v4(host) (host->devdata->ipversion == 4)
 188
 189 static const struct mxsfb_devdata mxsfb_devdata[] = {
 190         [MXSFB_V3] = {
 191                 .transfer_count = LCDC_V3_TRANSFER_COUNT,
 192                 .cur_buf = LCDC_V3_CUR_BUF,
 193                 .next_buf = LCDC_V3_NEXT_BUF,
 194                 .debug0 = LCDC_V3_DEBUG0,
 195                 .hs_wdth_mask = 0xff,
 196                 .hs_wdth_shift = 24,
 197                 .ipversion = 3,
 198         },
 199         [MXSFB_V4] = {
 200                 .transfer_count = LCDC_V4_TRANSFER_COUNT,
 201                 .cur_buf = LCDC_V4_CUR_BUF,
 202                 .next_buf = LCDC_V4_NEXT_BUF,
 203                 .debug0 = LCDC_V4_DEBUG0,
 204                 .hs_wdth_mask = 0x3fff,
 205                 .hs_wdth_shift = 18,
 206                 .ipversion = 4,
 207         },
 208 };
 209
 210 /* mask and shift depends on architecture */
 211 static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
 212 {
 213         return (val & host->devdata->hs_wdth_mask) <<
 214                 host->devdata->hs_wdth_shift;
 215 }
 216
 217 static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
 218 {
 219         return (val >> host->devdata->hs_wdth_shift) &
 220                 host->devdata->hs_wdth_mask;
 221 }
 222
 223 static const struct fb_bitfield def_rgb565[] = {
 224         [RED] = {
 225                 .offset = 11,
 226                 .length = 5,
 227         },
 228         [GREEN] = {
 229                 .offset = 5,
 230                 .length = 6,
 231         },
 232         [BLUE] = {
 233                 .offset = 0,
 234                 .length = 5,
 235         },
 236         [TRANSP] = {    /* no support for transparency */
 237                 .length = 0,
 238         }
 239 };
 240
 241 static const struct fb_bitfield def_rgb888[] = {
 242         [RED] = {
 243                 .offset = 16,
 244                 .length = 8,
 245         },
 246         [GREEN] = {
 247                 .offset = 8,
 248                 .length = 8,
 249         },
 250         [BLUE] = {
 251                 .offset = 0,
 252                 .length = 8,
 253         },
 254         [TRANSP] = {    /* no support for transparency */
 255                 .length = 0,
 256         }
 257 };
 258
 259 static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf)
 260 {
 261         chan &= 0xffff;
 262         chan >>= 16 - bf->length;
 263         return chan << bf->offset;
 264 }
 265
 266 static int mxsfb_check_var(struct fb_var_screeninfo *var,
 267                 struct fb_info *fb_info)
 268 {
 269         struct mxsfb_info *host = fb_info->par;
 270         const struct fb_bitfield *rgb = NULL;
 271
 272         if (var->xres < MIN_XRES)
 273                 var->xres = MIN_XRES;
 274         if (var->yres < MIN_YRES)
 275                 var->yres = MIN_YRES;
 276
 277         var->xres_virtual = var->xres;
 278
 279         var->yres_virtual = var->yres;
 280
 281         switch (var->bits_per_pixel) {
 282         case 16:
 283                 /* always expect RGB 565 */
 284                 rgb = def_rgb565;
 285                 break;
 286         case 32:
 287                 switch (host->ld_intf_width) {
 288                 case STMLCDIF_8BIT:
 289                         pr_debug("Unsupported LCD bus width mapping\n");
 290                         break;
 291                 case STMLCDIF_16BIT:
 292                 case STMLCDIF_18BIT:
 293                 case STMLCDIF_24BIT:
 294                         /* real 24 bit */
 295                         rgb = def_rgb888;
 296                         break;
 297                 }
 298                 break;
 299         default:
 300                 pr_err("Unsupported colour depth: %u\n", var->bits_per_pixel);
 301                 return -EINVAL;
 302         }
 303
 304         /*
 305          * Copy the RGB parameters for this display
 306          * from the machine specific parameters.
 307          */
 308         var->red    = rgb[RED];
 309         var->green  = rgb[GREEN];
 310         var->blue   = rgb[BLUE];
 311         var->transp = rgb[TRANSP];
 312
 313         return 0;
 314 }
 315
 316 static inline void mxsfb_enable_axi_clk(struct mxsfb_info *host)
 317 {
 318         if (host->clk_axi)
 319                 clk_prepare_enable(host->clk_axi);
 320 }
 321
 322 static inline void mxsfb_disable_axi_clk(struct mxsfb_info *host)
 323 {
 324         if (host->clk_axi)
 325                 clk_disable_unprepare(host->clk_axi);
 326 }
 327
 328 static void mxsfb_enable_controller(struct fb_info *fb_info)
 329 {
 330         struct mxsfb_info *host = fb_info->par;
 331         u32 reg;
 332         int ret;
 333
 334         dev_dbg(&host->pdev->dev, "%s\n", __func__);
 335
 336         if (host->reg_lcd) {
 337                 ret = regulator_enable(host->reg_lcd);
 338                 if (ret) {
 339                         dev_err(&host->pdev->dev,
 340                                 "lcd regulator enable failed:   %d\n", ret);
 341                         return;
 342                 }
 343         }
 344
 345         if (host->clk_disp_axi)
 346                 clk_prepare_enable(host->clk_disp_axi);
 347         clk_prepare_enable(host->clk);
 348         clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
 349
 350         mxsfb_enable_axi_clk(host);
 351
 352         /* if it was disabled, re-enable the mode again */
 353         writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
 354
 355         /* enable the SYNC signals first, then the DMA engine */
 356         reg = readl(host->base + LCDC_VDCTRL4);
 357         reg |= VDCTRL4_SYNC_SIGNALS_ON;
 358         writel(reg, host->base + LCDC_VDCTRL4);
 359
 360         writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
 361
 362         host->enabled = 1;
 363 }
 364
 365 static void mxsfb_disable_controller(struct fb_info *fb_info)
 366 {
 367         struct mxsfb_info *host = fb_info->par;
 368         unsigned loop;
 369         u32 reg;
 370         int ret;
 371
 372         dev_dbg(&host->pdev->dev, "%s\n", __func__);
 373
 374         /*
 375          * Even if we disable the controller here, it will still continue
 376          * until its FIFOs are running out of data
 377          */
 378         writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR);
 379
 380         loop = 1000;
 381         while (loop) {
 382                 reg = readl(host->base + LCDC_CTRL);
 383                 if (!(reg & CTRL_RUN))
 384                         break;
 385                 loop--;
 386         }
 387
 388         reg = readl(host->base + LCDC_VDCTRL4);
 389         writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4);
 390
 391         mxsfb_disable_axi_clk(host);
 392
 393         clk_disable_unprepare(host->clk);
 394         if (host->clk_disp_axi)
 395                 clk_disable_unprepare(host->clk_disp_axi);
 396
 397         host->enabled = 0;
 398
 399         if (host->reg_lcd) {
 400                 ret = regulator_disable(host->reg_lcd);
 401                 if (ret)
 402                         dev_err(&host->pdev->dev,
 403                                 "lcd regulator disable failed: %d\n", ret);
 404         }
 405 }
 406
 407 static int mxsfb_set_par(struct fb_info *fb_info)
 408 {
 409         struct mxsfb_info *host = fb_info->par;
 410         u32 ctrl, vdctrl0, vdctrl4;
 411         int line_size, fb_size;
 412         int reenable = 0;
 413
 414         line_size =  fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
 415         fb_size = fb_info->var.yres_virtual * line_size;
 416
 417         if (fb_size > fb_info->fix.smem_len)
 418                 return -ENOMEM;
 419
 420         fb_info->fix.line_length = line_size;
 421
 422         /*
 423          * It seems, you can't re-program the controller if it is still running.
 424          * This may lead into shifted pictures (FIFO issue?).
 425          * So, first stop the controller and drain its FIFOs
 426          */
 427         if (host->enabled) {
 428                 reenable = 1;
 429                 mxsfb_disable_controller(fb_info);
 430         }
 431
 432         mxsfb_enable_axi_clk(host);
 433
 434         /* clear the FIFOs */
 435         writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
 436
 437         ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER |
 438                 CTRL_SET_BUS_WIDTH(host->ld_intf_width);
 439
 440         switch (fb_info->var.bits_per_pixel) {
 441         case 16:
 442                 dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n");
 443                 ctrl |= CTRL_SET_WORD_LENGTH(0);
 444                 writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1);
 445                 break;
 446         case 32:
 447                 dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
 448                 ctrl |= CTRL_SET_WORD_LENGTH(3);
 449                 switch (host->ld_intf_width) {
 450                 case STMLCDIF_8BIT:
 451                         mxsfb_disable_axi_clk(host);
 452                         dev_err(&host->pdev->dev,
 453                                         "Unsupported LCD bus width mapping\n");
 454                         return -EINVAL;
 455                 case STMLCDIF_16BIT:
 456                 case STMLCDIF_18BIT:
 457                 case STMLCDIF_24BIT:
 458                         /* real 24 bit */
 459                         break;
 460                 }
 461                 /* do not use packed pixels = one pixel per word instead */
 462                 writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
 463                 break;
 464         default:
 465                 mxsfb_disable_axi_clk(host);
 466                 dev_err(&host->pdev->dev, "Unhandled color depth of %u\n",
 467                                 fb_info->var.bits_per_pixel);
 468                 return -EINVAL;
 469         }
 470
 471         writel(ctrl, host->base + LCDC_CTRL);
 472
 473         writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) |
 474                         TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres),
 475                         host->base + host->devdata->transfer_count);
 476
 477         vdctrl0 = VDCTRL0_ENABLE_PRESENT |      /* always in DOTCLOCK mode */
 478                 VDCTRL0_VSYNC_PERIOD_UNIT |
 479                 VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 480                 VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len);
 481         if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 482                 vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
 483         if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 484                 vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
 485         if (host->sync & MXSFB_SYNC_DATA_ENABLE_HIGH_ACT)
 486                 vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
 487         if (host->sync & MXSFB_SYNC_DOTCLK_FALLING_ACT)
 488                 vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING;
 489
 490         writel(vdctrl0, host->base + LCDC_VDCTRL0);
 491
 492         /* frame length in lines */
 493         writel(fb_info->var.upper_margin + fb_info->var.vsync_len +
 494                 fb_info->var.lower_margin + fb_info->var.yres,
 495                 host->base + LCDC_VDCTRL1);
 496
 497         /* line length in units of clocks or pixels */
 498         writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) |
 499                 VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin +
 500                 fb_info->var.hsync_len + fb_info->var.right_margin +
 501                 fb_info->var.xres),
 502                 host->base + LCDC_VDCTRL2);
 503
 504         writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin +
 505                 fb_info->var.hsync_len) |
 506                 SET_VERT_WAIT_CNT(fb_info->var.upper_margin +
 507                         fb_info->var.vsync_len),
 508                 host->base + LCDC_VDCTRL3);
 509
 510         vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres);
 511         if (mxsfb_is_v4(host))
 512                 vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay);
 513         writel(vdctrl4, host->base + LCDC_VDCTRL4);
 514
 515         writel(fb_info->fix.smem_start +
 516                         fb_info->fix.line_length * fb_info->var.yoffset,
 517                         host->base + host->devdata->next_buf);
 518
 519         mxsfb_disable_axi_clk(host);
 520
 521         if (reenable)
 522                 mxsfb_enable_controller(fb_info);
 523
 524         return 0;
 525 }
 526
 527 static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 528                 u_int transp, struct fb_info *fb_info)
 529 {
 530         unsigned int val;
 531         int ret = -EINVAL;
 532
 533         /*
 534          * If greyscale is true, then we convert the RGB value
 535          * to greyscale no matter what visual we are using.
 536          */
 537         if (fb_info->var.grayscale)
 538                 red = green = blue = (19595 * red + 38470 * green +
 539                                         7471 * blue) >> 16;
 540
 541         switch (fb_info->fix.visual) {
 542         case FB_VISUAL_TRUECOLOR:
 543                 /*
 544                  * 12 or 16-bit True Colour.  We encode the RGB value
 545                  * according to the RGB bitfield information.
 546                  */
 547                 if (regno < 16) {
 548                         u32 *pal = fb_info->pseudo_palette;
 549
 550                         val  = chan_to_field(red, &fb_info->var.red);
 551                         val |= chan_to_field(green, &fb_info->var.green);
 552                         val |= chan_to_field(blue, &fb_info->var.blue);
 553
 554                         pal[regno] = val;
 555                         ret = 0;
 556                 }
 557                 break;
 558
 559         case FB_VISUAL_STATIC_PSEUDOCOLOR:
 560         case FB_VISUAL_PSEUDOCOLOR:
 561                 break;
 562         }
 563
 564         return ret;
 565 }
 566
 567 static int mxsfb_blank(int blank, struct fb_info *fb_info)
 568 {
 569         struct mxsfb_info *host = fb_info->par;
 570
 571         switch (blank) {
 572         case FB_BLANK_POWERDOWN:
 573         case FB_BLANK_VSYNC_SUSPEND:
 574         case FB_BLANK_HSYNC_SUSPEND:
 575         case FB_BLANK_NORMAL:
 576                 if (host->enabled)
 577                         mxsfb_disable_controller(fb_info);
 578                 break;
 579
 580         case FB_BLANK_UNBLANK:
 581                 if (!host->enabled)
 582                         mxsfb_enable_controller(fb_info);
 583                 break;
 584         }
 585         return 0;
 586 }
 587
 588 static int mxsfb_pan_display(struct fb_var_screeninfo *var,
 589                 struct fb_info *fb_info)
 590 {
 591         struct mxsfb_info *host = fb_info->par;
 592         unsigned offset;
 593
 594         if (var->xoffset != 0)
 595                 return -EINVAL;
 596
 597         offset = fb_info->fix.line_length * var->yoffset;
 598
 599         mxsfb_enable_axi_clk(host);
 600
 601         /* update on next VSYNC */
 602         writel(fb_info->fix.smem_start + offset,
 603                         host->base + host->devdata->next_buf);
 604
 605         mxsfb_disable_axi_clk(host);
 606
 607         return 0;
 608 }
 609
 610 static struct fb_ops mxsfb_ops = {
 611         .owner = THIS_MODULE,
 612         .fb_check_var = mxsfb_check_var,
 613         .fb_set_par = mxsfb_set_par,
 614         .fb_setcolreg = mxsfb_setcolreg,
 615         .fb_blank = mxsfb_blank,
 616         .fb_pan_display = mxsfb_pan_display,
 617         .fb_fillrect = cfb_fillrect,
 618         .fb_copyarea = cfb_copyarea,
 619         .fb_imageblit = cfb_imageblit,
 620 };
 621
 622 static int mxsfb_restore_mode(struct fb_info *fb_info,
 623                         struct fb_videomode *vmode)
 624 {
 625         struct mxsfb_info *host = fb_info->par;
 626         unsigned line_count;
 627         unsigned period;
 628         unsigned long pa, fbsize;
 629         int bits_per_pixel, ofs, ret = 0;
 630         u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
 631
 632         mxsfb_enable_axi_clk(host);
 633
 634         /* Only restore the mode when the controller is running */
 635         ctrl = readl(host->base + LCDC_CTRL);
 636         if (!(ctrl & CTRL_RUN)) {
 637                 ret = -EINVAL;
 638                 goto err;
 639         }
 640
 641         vdctrl0 = readl(host->base + LCDC_VDCTRL0);
 642         vdctrl2 = readl(host->base + LCDC_VDCTRL2);
 643         vdctrl3 = readl(host->base + LCDC_VDCTRL3);
 644         vdctrl4 = readl(host->base + LCDC_VDCTRL4);
 645
 646         transfer_count = readl(host->base + host->devdata->transfer_count);
 647
 648         vmode->xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count);
 649         vmode->yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count);
 650
 651         switch (CTRL_GET_WORD_LENGTH(ctrl)) {
 652         case 0:
 653                 bits_per_pixel = 16;
 654                 break;
 655         case 3:
 656                 bits_per_pixel = 32;
 657                 break;
 658         case 1:
 659         default:
 660                 ret = -EINVAL;
 661                 goto err;
 662         }
 663
 664         fb_info->var.bits_per_pixel = bits_per_pixel;
 665
 666         vmode->pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U);
 667         vmode->hsync_len = get_hsync_pulse_width(host, vdctrl2);
 668         vmode->left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode->hsync_len;
 669         vmode->right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) -
 670                 vmode->hsync_len - vmode->left_margin - vmode->xres;
 671         vmode->vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0);
 672         period = readl(host->base + LCDC_VDCTRL1);
 673         vmode->upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode->vsync_len;
 674         vmode->lower_margin = period - vmode->vsync_len -
 675                 vmode->upper_margin - vmode->yres;
 676
 677         vmode->vmode = FB_VMODE_NONINTERLACED;
 678
 679         vmode->sync = 0;
 680         if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH)
 681                 vmode->sync |= FB_SYNC_HOR_HIGH_ACT;
 682         if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH)
 683                 vmode->sync |= FB_SYNC_VERT_HIGH_ACT;
 684
 685         pr_debug("Reconstructed video mode:\n");
 686         pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n",
 687                 vmode->xres, vmode->yres, vmode->hsync_len, vmode->left_margin,
 688                 vmode->right_margin, vmode->vsync_len, vmode->upper_margin,
 689                 vmode->lower_margin);
 690         pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode->pixclock));
 691
 692         host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl);
 693         host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4);
 694
 695         fb_info->fix.line_length = vmode->xres * (bits_per_pixel >> 3);
 696
 697         pa = readl(host->base + host->devdata->cur_buf);
 698         fbsize = fb_info->fix.line_length * vmode->yres;
 699         if (pa < fb_info->fix.smem_start) {
 700                 ret = -EINVAL;
 701                 goto err;
 702         }
 703         if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len) {
 704                 ret = -EINVAL;
 705                 goto err;
 706         }
 707         ofs = pa - fb_info->fix.smem_start;
 708         if (ofs) {
 709                 memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize);
 710                 writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf);
 711         }
 712
 713         line_count = fb_info->fix.smem_len / fb_info->fix.line_length;
 714         fb_info->fix.ypanstep = 1;
 715
 716         clk_prepare_enable(host->clk);
 717         host->enabled = 1;
 718
 719 err:
 720         if (ret)
 721                 mxsfb_disable_axi_clk(host);
 722
 723         return ret;
 724 }
 725
 726 static int mxsfb_init_fbinfo_dt(struct fb_info *fb_info,
 727                                 struct fb_videomode *vmode)
 728 {
 729         struct mxsfb_info *host = fb_info->par;
 730         struct fb_var_screeninfo *var = &fb_info->var;
 731         struct device *dev = &host->pdev->dev;
 732         struct device_node *np = host->pdev->dev.of_node;
 733         struct device_node *display_np;
 734         struct videomode vm;
 735         u32 width;
 736         int ret;
 737
 738         display_np = of_parse_phandle(np, "display", 0);
 739         if (!display_np) {
 740                 dev_err(dev, "failed to find display phandle\n");
 741                 return -ENOENT;
 742         }
 743
 744         ret = of_property_read_u32(display_np, "bus-width", &width);
 745         if (ret < 0) {
 746                 dev_err(dev, "failed to get property bus-width\n");
 747                 goto put_display_node;
 748         }
 749
 750         switch (width) {
 751         case 8:
 752                 host->ld_intf_width = STMLCDIF_8BIT;
 753                 break;
 754         case 16:
 755                 host->ld_intf_width = STMLCDIF_16BIT;
 756                 break;
 757         case 18:
 758                 host->ld_intf_width = STMLCDIF_18BIT;
 759                 break;
 760         case 24:
 761                 host->ld_intf_width = STMLCDIF_24BIT;
 762                 break;
 763         default:
 764                 dev_err(dev, "invalid bus-width value\n");
 765                 ret = -EINVAL;
 766                 goto put_display_node;
 767         }
 768
 769         ret = of_property_read_u32(display_np, "bits-per-pixel",
 770                                    &var->bits_per_pixel);
 771         if (ret < 0) {
 772                 dev_err(dev, "failed to get property bits-per-pixel\n");
 773                 goto put_display_node;
 774         }
 775
 776         ret = of_get_videomode(display_np, &vm, OF_USE_NATIVE_MODE);
 777         if (ret) {
 778                 dev_err(dev, "failed to get videomode from DT\n");
 779                 goto put_display_node;
 780         }
 781
 782         ret = fb_videomode_from_videomode(&vm, vmode);
 783         if (ret < 0)
 784                 goto put_display_node;
 785
 786         if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
 787                 host->sync |= MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
 788
 789         /*
 790          * The PIXDATA flags of the display_flags enum are controller
 791          * centric, e.g. NEGEDGE means drive data on negative edge.
 792          * However, the drivers flag is display centric: Sample the
 793          * data on negative (falling) edge. Therefore, check for the
 794          * POSEDGE flag:
 795          * drive on positive edge => sample on negative edge
 796          */
 797         if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
 798                 host->sync |= MXSFB_SYNC_DOTCLK_FALLING_ACT;
 799
 800 put_display_node:
 801         of_node_put(display_np);
 802         return ret;
 803 }
 804
 805 static int mxsfb_init_fbinfo(struct fb_info *fb_info,
 806                         struct fb_videomode *vmode)
 807 {
 808         int ret;
 809         struct mxsfb_info *host = fb_info->par;
 810         struct device *dev = &host->pdev->dev;
 811         struct fb_var_screeninfo *var = &fb_info->var;
 812         dma_addr_t fb_phys;
 813         void *fb_virt;
 814         unsigned fb_size;
 815
 816         fb_info->fbops = &mxsfb_ops;
 817         fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
 818         strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id));
 819         fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
 820         fb_info->fix.ypanstep = 1;
 821         fb_info->fix.visual = FB_VISUAL_TRUECOLOR,
 822         fb_info->fix.accel = FB_ACCEL_NONE;
 823
 824         ret = mxsfb_init_fbinfo_dt(fb_info, vmode);
 825         if (ret)
 826                 return ret;
 827
 828         var->nonstd = 0;
 829         var->activate = FB_ACTIVATE_NOW;
 830         var->accel_flags = 0;
 831         var->vmode = FB_VMODE_NONINTERLACED;
 832
 833         /* Memory allocation for framebuffer */
 834         fb_size = SZ_2M;
 835         fb_virt = dma_alloc_wc(dev, PAGE_ALIGN(fb_size), &fb_phys, GFP_KERNEL);
 836         if (!fb_virt)
 837                 return -ENOMEM;
 838
 839         fb_info->fix.smem_start = fb_phys;
 840         fb_info->screen_base = fb_virt;
 841         fb_info->screen_size = fb_info->fix.smem_len = fb_size;
 842
 843         if (mxsfb_restore_mode(fb_info, vmode))
 844                 memset(fb_virt, 0, fb_size);
 845
 846         return 0;
 847 }
 848
 849 static void mxsfb_free_videomem(struct fb_info *fb_info)
 850 {
 851         struct mxsfb_info *host = fb_info->par;
 852         struct device *dev = &host->pdev->dev;
 853
 854         dma_free_wc(dev, fb_info->screen_size, fb_info->screen_base,
 855                     fb_info->fix.smem_start);
 856 }
 857
 858 static const struct platform_device_id mxsfb_devtype[] = {
 859         {
 860                 .name = "imx23-fb",
 861                 .driver_data = MXSFB_V3,
 862         }, {
 863                 .name = "imx28-fb",
 864                 .driver_data = MXSFB_V4,
 865         }, {
 866                 /* sentinel */
 867         }
 868 };
 869 MODULE_DEVICE_TABLE(platform, mxsfb_devtype);
 870
 871 static const struct of_device_id mxsfb_dt_ids[] = {
 872         { .compatible = "fsl,imx23-lcdif", .data = &mxsfb_devtype[0], },
 873         { .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devtype[1], },
 874         { /* sentinel */ }
 875 };
 876 MODULE_DEVICE_TABLE(of, mxsfb_dt_ids);
 877
 878 static int mxsfb_probe(struct platform_device *pdev)
 879 {
 880         const struct of_device_id *of_id =
 881                         of_match_device(mxsfb_dt_ids, &pdev->dev);
 882         struct resource *res;
 883         struct mxsfb_info *host;
 884         struct fb_info *fb_info;
 885         struct fb_videomode *mode;
 886         int ret;
 887
 888         if (of_id)
 889                 pdev->id_entry = of_id->data;
 890
 891         fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev);
 892         if (!fb_info) {
 893                 dev_err(&pdev->dev, "Failed to allocate fbdev\n");
 894                 return -ENOMEM;
 895         }
 896
 897         mode = devm_kzalloc(&pdev->dev, sizeof(struct fb_videomode),
 898                         GFP_KERNEL);
 899         if (mode == NULL)
 900                 return -ENOMEM;
 901
 902         host = fb_info->par;
 903
 904         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 905         host->base = devm_ioremap_resource(&pdev->dev, res);
 906         if (IS_ERR(host->base)) {
 907                 ret = PTR_ERR(host->base);
 908                 goto fb_release;
 909         }
 910
 911         host->pdev = pdev;
 912         platform_set_drvdata(pdev, host);
 913
 914         host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
 915
 916         host->clk = devm_clk_get(&host->pdev->dev, NULL);
 917         if (IS_ERR(host->clk)) {
 918                 ret = PTR_ERR(host->clk);
 919                 goto fb_release;
 920         }
 921
 922         host->clk_axi = devm_clk_get(&host->pdev->dev, "axi");
 923         if (IS_ERR(host->clk_axi))
 924                 host->clk_axi = NULL;
 925
 926         host->clk_disp_axi = devm_clk_get(&host->pdev->dev, "disp_axi");
 927         if (IS_ERR(host->clk_disp_axi))
 928                 host->clk_disp_axi = NULL;
 929
 930         host->reg_lcd = devm_regulator_get(&pdev->dev, "lcd");
 931         if (IS_ERR(host->reg_lcd))
 932                 host->reg_lcd = NULL;
 933
 934         fb_info->pseudo_palette = devm_kcalloc(&pdev->dev, 16, sizeof(u32),
 935                                                GFP_KERNEL);
 936         if (!fb_info->pseudo_palette) {
 937                 ret = -ENOMEM;
 938                 goto fb_release;
 939         }
 940
 941         ret = mxsfb_init_fbinfo(fb_info, mode);
 942         if (ret != 0)
 943                 goto fb_release;
 944
 945         fb_videomode_to_var(&fb_info->var, mode);
 946
 947         /* init the color fields */
 948         mxsfb_check_var(&fb_info->var, fb_info);
 949
 950         platform_set_drvdata(pdev, fb_info);
 951
 952         ret = register_framebuffer(fb_info);
 953         if (ret != 0) {
 954                 dev_err(&pdev->dev,"Failed to register framebuffer\n");
 955                 goto fb_destroy;
 956         }
 957
 958         if (!host->enabled) {
 959                 mxsfb_enable_axi_clk(host);
 960                 writel(0, host->base + LCDC_CTRL);
 961                 mxsfb_disable_axi_clk(host);
 962                 mxsfb_set_par(fb_info);
 963                 mxsfb_enable_controller(fb_info);
 964         }
 965
 966         dev_info(&pdev->dev, "initialized\n");
 967
 968         return 0;
 969
 970 fb_destroy:
 971         if (host->enabled)
 972                 clk_disable_unprepare(host->clk);
 973 fb_release:
 974         framebuffer_release(fb_info);
 975
 976         return ret;
 977 }
 978
 979 static int mxsfb_remove(struct platform_device *pdev)
 980 {
 981         struct fb_info *fb_info = platform_get_drvdata(pdev);
 982         struct mxsfb_info *host = fb_info->par;
 983
 984         if (host->enabled)
 985                 mxsfb_disable_controller(fb_info);
 986
 987         unregister_framebuffer(fb_info);
 988         mxsfb_free_videomem(fb_info);
 989
 990         framebuffer_release(fb_info);
 991
 992         return 0;
 993 }
 994
 995 static void mxsfb_shutdown(struct platform_device *pdev)
 996 {
 997         struct fb_info *fb_info = platform_get_drvdata(pdev);
 998         struct mxsfb_info *host = fb_info->par;
 999
1000         mxsfb_enable_axi_clk(host);
1001
1002         /*
1003          * Force stop the LCD controller as keeping it running during reboot
1004          * might interfere with the BootROM's boot mode pads sampling.
1005          */
1006         writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR);
1007
1008         mxsfb_disable_axi_clk(host);
1009 }
1010
1011 static struct platform_driver mxsfb_driver = {
1012         .probe = mxsfb_probe,
1013         .remove = mxsfb_remove,
1014         .shutdown = mxsfb_shutdown,
1015         .id_table = mxsfb_devtype,
1016         .driver = {
1017                    .name = DRIVER_NAME,
1018                    .of_match_table = mxsfb_dt_ids,
1019         },
1020 };
1021
1022 module_platform_driver(mxsfb_driver);
1023
1024 MODULE_DESCRIPTION("Freescale mxs framebuffer driver");
1025 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1026 MODULE_LICENSE("GPL");