2 * i740fb - framebuffer driver for Intel740
3 * Copyright (c) 2011 Ondrej Zary
5 * Based on old i740fb driver (c) 2001-2002 Andrey Ulanov <drey@rt.mipt.ru>
6 * which was partially based on:
7 * VGA 16-color framebuffer driver (c) 1999 Ben Pfaff <pfaffben@debian.org>
8 * and Petr Vandrovec <VANDROVE@vc.cvut.cz>
9 * i740 driver from XFree86 (c) 1998-1999 Precision Insight, Inc., Cedar Park,
11 * i740fb by Patrick LERDA, v0.9
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #include <linux/pci_ids.h>
25 #include <linux/i2c.h>
26 #include <linux/i2c-algo-bit.h>
27 #include <linux/console.h>
28 #include <video/vga.h>
32 static char *mode_option;
36 unsigned char __iomem *regs;
40 struct i2c_adapter ddc_adapter;
41 struct i2c_algo_bit_data ddc_algo;
42 u32 pseudo_palette[16];
43 struct mutex open_lock;
44 unsigned int ref_count;
53 /* i740 specific registers */
60 u8 video_clk2_mn_msbs;
61 u8 video_clk2_div_sel;
68 u8 ext_vert_sync_start;
69 u8 ext_vert_blank_start;
74 u32 lmi_fifo_watermark;
80 #define DACSPEED16 163
81 #define DACSPEED24_SG 136
82 #define DACSPEED24_SD 128
85 static const struct fb_fix_screeninfo i740fb_fix = {
87 .type = FB_TYPE_PACKED_PIXELS,
88 .visual = FB_VISUAL_TRUECOLOR,
91 .accel = FB_ACCEL_NONE,
94 static inline void i740outb(struct i740fb_par *par, u16 port, u8 val)
96 vga_mm_w(par->regs, port, val);
98 static inline u8 i740inb(struct i740fb_par *par, u16 port)
100 return vga_mm_r(par->regs, port);
102 static inline void i740outreg(struct i740fb_par *par, u16 port, u8 reg, u8 val)
104 vga_mm_w_fast(par->regs, port, reg, val);
106 static inline u8 i740inreg(struct i740fb_par *par, u16 port, u8 reg)
108 vga_mm_w(par->regs, port, reg);
109 return vga_mm_r(par->regs, port+1);
111 static inline void i740outreg_mask(struct i740fb_par *par, u16 port, u8 reg,
114 vga_mm_w_fast(par->regs, port, reg, (val & mask)
115 | (i740inreg(par, port, reg) & ~mask));
118 #define REG_DDC_DRIVE 0x62
119 #define REG_DDC_STATE 0x63
120 #define DDC_SCL (1 << 3)
121 #define DDC_SDA (1 << 2)
123 static void i740fb_ddc_setscl(void *data, int val)
125 struct i740fb_par *par = data;
127 i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SCL, DDC_SCL);
128 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL);
131 static void i740fb_ddc_setsda(void *data, int val)
133 struct i740fb_par *par = data;
135 i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SDA, DDC_SDA);
136 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA);
139 static int i740fb_ddc_getscl(void *data)
141 struct i740fb_par *par = data;
143 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL);
145 return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SCL);
148 static int i740fb_ddc_getsda(void *data)
150 struct i740fb_par *par = data;
152 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA);
154 return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SDA);
157 static int i740fb_setup_ddc_bus(struct fb_info *info)
159 struct i740fb_par *par = info->par;
161 strlcpy(par->ddc_adapter.name, info->fix.id,
162 sizeof(par->ddc_adapter.name));
163 par->ddc_adapter.owner = THIS_MODULE;
164 par->ddc_adapter.class = I2C_CLASS_DDC;
165 par->ddc_adapter.algo_data = &par->ddc_algo;
166 par->ddc_adapter.dev.parent = info->device;
167 par->ddc_algo.setsda = i740fb_ddc_setsda;
168 par->ddc_algo.setscl = i740fb_ddc_setscl;
169 par->ddc_algo.getsda = i740fb_ddc_getsda;
170 par->ddc_algo.getscl = i740fb_ddc_getscl;
171 par->ddc_algo.udelay = 10;
172 par->ddc_algo.timeout = 20;
173 par->ddc_algo.data = par;
175 i2c_set_adapdata(&par->ddc_adapter, par);
177 return i2c_bit_add_bus(&par->ddc_adapter);
180 static int i740fb_open(struct fb_info *info, int user)
182 struct i740fb_par *par = info->par;
184 mutex_lock(&(par->open_lock));
186 mutex_unlock(&(par->open_lock));
191 static int i740fb_release(struct fb_info *info, int user)
193 struct i740fb_par *par = info->par;
195 mutex_lock(&(par->open_lock));
196 if (par->ref_count == 0) {
197 fb_err(info, "release called with zero refcount\n");
198 mutex_unlock(&(par->open_lock));
203 mutex_unlock(&(par->open_lock));
208 static u32 i740_calc_fifo(struct i740fb_par *par, u32 freq, int bpp)
211 * Would like to calculate these values automatically, but a generic
212 * algorithm does not seem possible. Note: These FIFO water mark
213 * values were tested on several cards and seem to eliminate the
214 * all of the snow and vertical banding, but fine adjustments will
215 * probably be required for other cards.
233 if (par->has_sgram) {
270 if (par->has_sgram) {
305 if (par->has_sgram) {
334 /* clock calculation from i740fb by Patrick LERDA */
336 #define I740_RFREQ 1000000
337 #define TARGET_MAX_N 30
338 #define I740_FFIX (1 << 8)
339 #define I740_RFREQ_FIX (I740_RFREQ / I740_FFIX)
340 #define I740_REF_FREQ (6667 * I740_FFIX / 100) /* 66.67 MHz */
341 #define I740_MAX_VCO_FREQ (450 * I740_FFIX) /* 450 MHz */
343 static void i740_calc_vclk(u32 freq, struct i740fb_par *par)
345 const u32 err_max = freq / (200 * I740_RFREQ / I740_FFIX);
346 const u32 err_target = freq / (1000 * I740_RFREQ / I740_FFIX);
347 u32 err_best = 512 * I740_FFIX;
349 int m_best = 0, n_best = 0, p_best = 0;
352 p_best = min(15, ilog2(I740_MAX_VCO_FREQ / (freq / I740_RFREQ_FIX)));
353 f_vco = (freq * (1 << p_best)) / I740_RFREQ_FIX;
354 freq = freq / I740_RFREQ_FIX;
359 m = ((f_vco * n) / I740_REF_FREQ + 2) / 4;
365 u32 f_out = (((m * I740_REF_FREQ * 4)
366 / n) + ((1 << p_best) / 2)) / (1 << p_best);
368 f_err = (freq - f_out);
370 if (abs(f_err) < err_max) {
376 } while ((abs(f_err) >= err_target) &&
377 ((n <= TARGET_MAX_N) || (abs(err_best) > err_max)));
379 if (abs(f_err) < err_target) {
384 par->video_clk2_m = (m_best - 2) & 0xFF;
385 par->video_clk2_n = (n_best - 2) & 0xFF;
386 par->video_clk2_mn_msbs = ((((n_best - 2) >> 4) & VCO_N_MSBS)
387 | (((m_best - 2) >> 8) & VCO_M_MSBS));
388 par->video_clk2_div_sel = ((p_best << 4) | REF_DIV_1);
391 static int i740fb_decode_var(const struct fb_var_screeninfo *var,
392 struct i740fb_par *par, struct fb_info *info)
395 * Get the video params out of 'var'.
396 * If a value doesn't fit, round it up, if it's too big, return -EINVAL.
399 u32 xres, right, hslen, left, xtotal;
400 u32 yres, lower, vslen, upper, ytotal;
401 u32 vxres, xoffset, vyres, yoffset;
402 u32 bpp, base, dacspeed24, mem, freq;
406 dev_dbg(info->device, "decode_var: xres: %i, yres: %i, xres_v: %i, xres_v: %i\n",
407 var->xres, var->yres, var->xres_virtual, var->xres_virtual);
408 dev_dbg(info->device, " xoff: %i, yoff: %i, bpp: %i, graysc: %i\n",
409 var->xoffset, var->yoffset, var->bits_per_pixel,
411 dev_dbg(info->device, " activate: %i, nonstd: %i, vmode: %i\n",
412 var->activate, var->nonstd, var->vmode);
413 dev_dbg(info->device, " pixclock: %i, hsynclen:%i, vsynclen:%i\n",
414 var->pixclock, var->hsync_len, var->vsync_len);
415 dev_dbg(info->device, " left: %i, right: %i, up:%i, lower:%i\n",
416 var->left_margin, var->right_margin, var->upper_margin,
420 bpp = var->bits_per_pixel;
424 if ((1000000 / var->pixclock) > DACSPEED8) {
425 dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 8bpp)\n",
426 1000000 / var->pixclock, DACSPEED8);
433 if ((1000000 / var->pixclock) > DACSPEED16) {
434 dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 15/16bpp)\n",
435 1000000 / var->pixclock, DACSPEED16);
441 dacspeed24 = par->has_sgram ? DACSPEED24_SG : DACSPEED24_SD;
442 if ((1000000 / var->pixclock) > dacspeed24) {
443 dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 24bpp)\n",
444 1000000 / var->pixclock, dacspeed24);
450 if ((1000000 / var->pixclock) > DACSPEED32) {
451 dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 32bpp)\n",
452 1000000 / var->pixclock, DACSPEED32);
460 xres = ALIGN(var->xres, 8);
461 vxres = ALIGN(var->xres_virtual, 16);
465 xoffset = ALIGN(var->xoffset, 8);
466 if (xres + xoffset > vxres)
467 xoffset = vxres - xres;
469 left = ALIGN(var->left_margin, 8);
470 right = ALIGN(var->right_margin, 8);
471 hslen = ALIGN(var->hsync_len, 8);
474 vyres = var->yres_virtual;
478 yoffset = var->yoffset;
479 if (yres + yoffset > vyres)
480 yoffset = vyres - yres;
482 lower = var->lower_margin;
483 vslen = var->vsync_len;
484 upper = var->upper_margin;
486 mem = vxres * vyres * ((bpp + 1) / 8);
487 if (mem > info->screen_size) {
488 dev_err(info->device, "not enough video memory (%d KB requested, %ld KB available)\n",
489 mem >> 10, info->screen_size >> 10);
493 if (yoffset + yres > vyres)
494 yoffset = vyres - yres;
496 xtotal = xres + right + hslen + left;
497 ytotal = yres + lower + vslen + upper;
499 par->crtc[VGA_CRTC_H_TOTAL] = (xtotal >> 3) - 5;
500 par->crtc[VGA_CRTC_H_DISP] = (xres >> 3) - 1;
501 par->crtc[VGA_CRTC_H_BLANK_START] = ((xres + right) >> 3) - 1;
502 par->crtc[VGA_CRTC_H_SYNC_START] = (xres + right) >> 3;
503 par->crtc[VGA_CRTC_H_SYNC_END] = (((xres + right + hslen) >> 3) & 0x1F)
504 | ((((xres + right + hslen) >> 3) & 0x20) << 2);
505 par->crtc[VGA_CRTC_H_BLANK_END] = ((xres + right + hslen) >> 3 & 0x1F)
508 par->crtc[VGA_CRTC_V_TOTAL] = ytotal - 2;
510 r7 = 0x10; /* disable linecompare */
516 par->crtc[VGA_CRTC_PRESET_ROW] = 0;
517 par->crtc[VGA_CRTC_MAX_SCAN] = 0x40; /* 1 scanline, no linecmp */
518 if (var->vmode & FB_VMODE_DOUBLE)
519 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x80;
520 par->crtc[VGA_CRTC_CURSOR_START] = 0x00;
521 par->crtc[VGA_CRTC_CURSOR_END] = 0x00;
522 par->crtc[VGA_CRTC_CURSOR_HI] = 0x00;
523 par->crtc[VGA_CRTC_CURSOR_LO] = 0x00;
524 par->crtc[VGA_CRTC_V_DISP_END] = yres-1;
525 if ((yres-1) & 0x100)
527 if ((yres-1) & 0x200)
530 par->crtc[VGA_CRTC_V_BLANK_START] = yres + lower - 1;
531 par->crtc[VGA_CRTC_V_SYNC_START] = yres + lower - 1;
532 if ((yres + lower - 1) & 0x100)
534 if ((yres + lower - 1) & 0x200) {
535 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x20;
540 par->crtc[VGA_CRTC_V_SYNC_END] =
541 ((yres + lower - 1 + vslen) & 0x0F) & ~0x10;
542 /* 0x7F for VGA, but some SVGA chips require all 8 bits to be set */
543 par->crtc[VGA_CRTC_V_BLANK_END] = (yres + lower - 1 + vslen) & 0xFF;
545 par->crtc[VGA_CRTC_UNDERLINE] = 0x00;
546 par->crtc[VGA_CRTC_MODE] = 0xC3 ;
547 par->crtc[VGA_CRTC_LINE_COMPARE] = 0xFF;
548 par->crtc[VGA_CRTC_OVERFLOW] = r7;
550 par->vss = 0x00; /* 3DA */
552 for (i = 0x00; i < 0x10; i++)
554 par->atc[VGA_ATC_MODE] = 0x81;
555 par->atc[VGA_ATC_OVERSCAN] = 0x00; /* 0 for EGA, 0xFF for VGA */
556 par->atc[VGA_ATC_PLANE_ENABLE] = 0x0F;
557 par->atc[VGA_ATC_COLOR_PAGE] = 0x00;
560 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
562 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
565 par->seq[VGA_SEQ_CLOCK_MODE] = 0x01;
566 par->seq[VGA_SEQ_PLANE_WRITE] = 0x0F;
567 par->seq[VGA_SEQ_CHARACTER_MAP] = 0x00;
568 par->seq[VGA_SEQ_MEMORY_MODE] = 0x06;
570 par->gdc[VGA_GFX_SR_VALUE] = 0x00;
571 par->gdc[VGA_GFX_SR_ENABLE] = 0x00;
572 par->gdc[VGA_GFX_COMPARE_VALUE] = 0x00;
573 par->gdc[VGA_GFX_DATA_ROTATE] = 0x00;
574 par->gdc[VGA_GFX_PLANE_READ] = 0;
575 par->gdc[VGA_GFX_MODE] = 0x02;
576 par->gdc[VGA_GFX_MISC] = 0x05;
577 par->gdc[VGA_GFX_COMPARE_MASK] = 0x0F;
578 par->gdc[VGA_GFX_BIT_MASK] = 0xFF;
580 base = (yoffset * vxres + (xoffset & ~7)) >> 2;
583 par->crtc[VGA_CRTC_OFFSET] = vxres >> 3;
584 par->ext_offset = vxres >> 11;
585 par->pixelpipe_cfg1 = DISPLAY_8BPP_MODE;
586 par->bitblt_cntl = COLEXP_8BPP;
588 case 15: /* 0rrrrrgg gggbbbbb */
589 case 16: /* rrrrrggg gggbbbbb */
590 par->pixelpipe_cfg1 = (var->green.length == 6) ?
591 DISPLAY_16BPP_MODE : DISPLAY_15BPP_MODE;
592 par->crtc[VGA_CRTC_OFFSET] = vxres >> 2;
593 par->ext_offset = vxres >> 10;
594 par->bitblt_cntl = COLEXP_16BPP;
598 par->crtc[VGA_CRTC_OFFSET] = (vxres * 3) >> 3;
599 par->ext_offset = (vxres * 3) >> 11;
600 par->pixelpipe_cfg1 = DISPLAY_24BPP_MODE;
601 par->bitblt_cntl = COLEXP_24BPP;
602 base &= 0xFFFFFFFE; /* ...ignore the last bit. */
606 par->crtc[VGA_CRTC_OFFSET] = vxres >> 1;
607 par->ext_offset = vxres >> 9;
608 par->pixelpipe_cfg1 = DISPLAY_32BPP_MODE;
609 par->bitblt_cntl = COLEXP_RESERVED; /* Unimplemented on i740 */
614 par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
615 par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8;
616 par->ext_start_addr =
617 ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE;
618 par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
620 par->pixelpipe_cfg0 = DAC_8_BIT;
622 par->pixelpipe_cfg2 = DISPLAY_GAMMA_ENABLE | OVERLAY_GAMMA_ENABLE;
623 par->io_cntl = EXTENDED_CRTC_CNTL;
624 par->address_mapping = LINEAR_MODE_ENABLE | PAGE_MAPPING_ENABLE;
625 par->display_cntl = HIRES_MODE;
627 /* Set the MCLK freq */
628 par->pll_cntl = PLL_MEMCLK_100000KHZ; /* 100 MHz -- use as default */
630 /* Calculate the extended CRTC regs */
631 par->ext_vert_total = (ytotal - 2) >> 8;
632 par->ext_vert_disp_end = (yres - 1) >> 8;
633 par->ext_vert_sync_start = (yres + lower) >> 8;
634 par->ext_vert_blank_start = (yres + lower) >> 8;
635 par->ext_horiz_total = ((xtotal >> 3) - 5) >> 8;
636 par->ext_horiz_blank = (((xres + right) >> 3) & 0x40) >> 6;
638 par->interlace_cntl = INTERLACE_DISABLE;
640 /* Set the overscan color to 0. (NOTE: This only affects >8bpp mode) */
641 par->atc[VGA_ATC_OVERSCAN] = 0;
643 /* Calculate VCLK that most closely matches the requested dot clock */
644 freq = (((u32)1e9) / var->pixclock) * (u32)(1e3);
645 if (freq < I740_RFREQ_FIX) {
646 fb_dbg(info, "invalid pixclock\n");
647 freq = I740_RFREQ_FIX;
649 i740_calc_vclk(freq, par);
651 /* Since we program the clocks ourselves, always use VCLK2. */
654 /* Calculate the FIFO Watermark and Burst Length. */
655 par->lmi_fifo_watermark =
656 i740_calc_fifo(par, 1000000 / var->pixclock, bpp);
661 static int i740fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
663 switch (var->bits_per_pixel) {
665 var->red.offset = var->green.offset = var->blue.offset = 0;
666 var->red.length = var->green.length = var->blue.length = 8;
669 switch (var->green.length) {
672 var->red.offset = 10;
673 var->green.offset = 5;
674 var->blue.offset = 0;
676 var->green.length = 5;
677 var->blue.length = 5;
680 var->red.offset = 11;
681 var->green.offset = 5;
682 var->blue.offset = 0;
683 var->red.length = var->blue.length = 5;
688 var->red.offset = 16;
689 var->green.offset = 8;
690 var->blue.offset = 0;
691 var->red.length = var->green.length = var->blue.length = 8;
694 var->transp.offset = 24;
695 var->red.offset = 16;
696 var->green.offset = 8;
697 var->blue.offset = 0;
698 var->transp.length = 8;
699 var->red.length = var->green.length = var->blue.length = 8;
705 if (var->xres > var->xres_virtual)
706 var->xres_virtual = var->xres;
708 if (var->yres > var->yres_virtual)
709 var->yres_virtual = var->yres;
711 if (info->monspecs.hfmax && info->monspecs.vfmax &&
712 info->monspecs.dclkmax && fb_validate_mode(var, info) < 0)
718 static void vga_protect(struct i740fb_par *par)
720 /* disable the display */
721 i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0x20, 0x20);
724 i740outb(par, VGA_ATT_W, 0x00); /* enable palette access */
727 static void vga_unprotect(struct i740fb_par *par)
729 /* reenable display */
730 i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0, 0x20);
733 i740outb(par, VGA_ATT_W, 0x20); /* disable palette access */
736 static int i740fb_set_par(struct fb_info *info)
738 struct i740fb_par *par = info->par;
742 i = i740fb_decode_var(&info->var, par, info);
746 memset(info->screen_base, 0, info->screen_size);
750 i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_DISABLE);
754 i740outreg(par, XRX, VCLK2_VCO_M, par->video_clk2_m);
755 i740outreg(par, XRX, VCLK2_VCO_N, par->video_clk2_n);
756 i740outreg(par, XRX, VCLK2_VCO_MN_MSBS, par->video_clk2_mn_msbs);
757 i740outreg(par, XRX, VCLK2_VCO_DIV_SEL, par->video_clk2_div_sel);
759 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0,
760 par->pixelpipe_cfg0 & DAC_8_BIT, 0x80);
763 i740outb(par, 0x3C0, 0x00);
765 /* update misc output register */
766 i740outb(par, VGA_MIS_W, par->misc | 0x01);
768 /* synchronous reset on */
769 i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x01);
770 /* write sequencer registers */
771 i740outreg(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE,
772 par->seq[VGA_SEQ_CLOCK_MODE] | 0x20);
773 for (i = 2; i < VGA_SEQ_C; i++)
774 i740outreg(par, VGA_SEQ_I, i, par->seq[i]);
776 /* synchronous reset off */
777 i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x03);
779 /* deprotect CRT registers 0-7 */
780 i740outreg(par, VGA_CRT_IC, VGA_CRTC_V_SYNC_END,
781 par->crtc[VGA_CRTC_V_SYNC_END]);
783 /* write CRT registers */
784 for (i = 0; i < VGA_CRT_C; i++)
785 i740outreg(par, VGA_CRT_IC, i, par->crtc[i]);
787 /* write graphics controller registers */
788 for (i = 0; i < VGA_GFX_C; i++)
789 i740outreg(par, VGA_GFX_I, i, par->gdc[i]);
791 /* write attribute controller registers */
792 for (i = 0; i < VGA_ATT_C; i++) {
793 i740inb(par, VGA_IS1_RC); /* reset flip-flop */
794 i740outb(par, VGA_ATT_IW, i);
795 i740outb(par, VGA_ATT_IW, par->atc[i]);
798 i740inb(par, VGA_IS1_RC);
799 i740outb(par, VGA_ATT_IW, 0x20);
801 i740outreg(par, VGA_CRT_IC, EXT_VERT_TOTAL, par->ext_vert_total);
802 i740outreg(par, VGA_CRT_IC, EXT_VERT_DISPLAY, par->ext_vert_disp_end);
803 i740outreg(par, VGA_CRT_IC, EXT_VERT_SYNC_START,
804 par->ext_vert_sync_start);
805 i740outreg(par, VGA_CRT_IC, EXT_VERT_BLANK_START,
806 par->ext_vert_blank_start);
807 i740outreg(par, VGA_CRT_IC, EXT_HORIZ_TOTAL, par->ext_horiz_total);
808 i740outreg(par, VGA_CRT_IC, EXT_HORIZ_BLANK, par->ext_horiz_blank);
809 i740outreg(par, VGA_CRT_IC, EXT_OFFSET, par->ext_offset);
810 i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI, par->ext_start_addr_hi);
811 i740outreg(par, VGA_CRT_IC, EXT_START_ADDR, par->ext_start_addr);
813 i740outreg_mask(par, VGA_CRT_IC, INTERLACE_CNTL,
814 par->interlace_cntl, INTERLACE_ENABLE);
815 i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F);
816 i740outreg_mask(par, XRX, BITBLT_CNTL, par->bitblt_cntl, COLEXP_MODE);
817 i740outreg_mask(par, XRX, DISPLAY_CNTL,
818 par->display_cntl, VGA_WRAP_MODE | GUI_MODE);
819 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B);
820 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C);
822 i740outreg(par, XRX, PLL_CNTL, par->pll_cntl);
824 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_1,
825 par->pixelpipe_cfg1, DISPLAY_COLOR_MODE);
827 itemp = readl(par->regs + FWATER_BLC);
828 itemp &= ~(LMI_BURST_LENGTH | LMI_FIFO_WATERMARK);
829 itemp |= par->lmi_fifo_watermark;
830 writel(itemp, par->regs + FWATER_BLC);
832 i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_60HZ);
834 i740outreg_mask(par, MRX, COL_KEY_CNTL_1, 0, BLANK_DISP_OVERLAY);
835 i740outreg_mask(par, XRX, IO_CTNL,
836 par->io_cntl, EXTENDED_ATTR_CNTL | EXTENDED_CRTC_CNTL);
838 if (par->pixelpipe_cfg1 != DISPLAY_8BPP_MODE) {
839 i740outb(par, VGA_PEL_MSK, 0xFF);
840 i740outb(par, VGA_PEL_IW, 0x00);
841 for (i = 0; i < 256; i++) {
842 itemp = (par->pixelpipe_cfg0 & DAC_8_BIT) ? i : i >> 2;
843 i740outb(par, VGA_PEL_D, itemp);
844 i740outb(par, VGA_PEL_D, itemp);
845 i740outb(par, VGA_PEL_D, itemp);
849 /* Wait for screen to stabilize. */
853 info->fix.line_length =
854 info->var.xres_virtual * info->var.bits_per_pixel / 8;
855 if (info->var.bits_per_pixel == 8)
856 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
858 info->fix.visual = FB_VISUAL_TRUECOLOR;
863 static int i740fb_setcolreg(unsigned regno, unsigned red, unsigned green,
864 unsigned blue, unsigned transp,
865 struct fb_info *info)
869 dev_dbg(info->device, "setcolreg: regno: %i, red=%d, green=%d, blue=%d, transp=%d, bpp=%d\n",
870 regno, red, green, blue, transp, info->var.bits_per_pixel);
872 switch (info->fix.visual) {
873 case FB_VISUAL_PSEUDOCOLOR:
876 i740outb(info->par, VGA_PEL_IW, regno);
877 i740outb(info->par, VGA_PEL_D, red >> 8);
878 i740outb(info->par, VGA_PEL_D, green >> 8);
879 i740outb(info->par, VGA_PEL_D, blue >> 8);
881 case FB_VISUAL_TRUECOLOR:
884 r = (red >> (16 - info->var.red.length))
885 << info->var.red.offset;
886 b = (blue >> (16 - info->var.blue.length))
887 << info->var.blue.offset;
888 g = (green >> (16 - info->var.green.length))
889 << info->var.green.offset;
890 ((u32 *) info->pseudo_palette)[regno] = r | g | b;
899 static int i740fb_pan_display(struct fb_var_screeninfo *var,
900 struct fb_info *info)
902 struct i740fb_par *par = info->par;
903 u32 base = (var->yoffset * info->var.xres_virtual
904 + (var->xoffset & ~7)) >> 2;
906 dev_dbg(info->device, "pan_display: xoffset: %i yoffset: %i base: %i\n",
907 var->xoffset, var->yoffset, base);
909 switch (info->var.bits_per_pixel) {
918 * The last bit does not seem to have any effect on the start
919 * address register in 24bpp mode, so...
921 base &= 0xFFFFFFFE; /* ...ignore the last bit. */
929 par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
930 par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8;
931 par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
932 par->ext_start_addr =
933 ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE;
935 i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_LO, base & 0x000000FF);
936 i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_HI,
937 (base & 0x0000FF00) >> 8);
938 i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI,
939 (base & 0x3FC00000) >> 22);
940 i740outreg(par, VGA_CRT_IC, EXT_START_ADDR,
941 ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE);
946 static int i740fb_blank(int blank_mode, struct fb_info *info)
948 struct i740fb_par *par = info->par;
953 switch (blank_mode) {
954 case FB_BLANK_UNBLANK:
955 case FB_BLANK_NORMAL:
957 DPMSSyncSelect = HSYNC_ON | VSYNC_ON;
959 case FB_BLANK_VSYNC_SUSPEND:
961 DPMSSyncSelect = HSYNC_ON | VSYNC_OFF;
963 case FB_BLANK_HSYNC_SUSPEND:
965 DPMSSyncSelect = HSYNC_OFF | VSYNC_ON;
967 case FB_BLANK_POWERDOWN:
969 DPMSSyncSelect = HSYNC_OFF | VSYNC_OFF;
974 /* Turn the screen on/off */
975 i740outb(par, SRX, 0x01);
976 SEQ01 |= i740inb(par, SRX + 1) & ~0x20;
977 i740outb(par, SRX, 0x01);
978 i740outb(par, SRX + 1, SEQ01);
980 /* Set the DPMS mode */
981 i740outreg(par, XRX, DPMS_SYNC_SELECT, DPMSSyncSelect);
983 /* Let fbcon do a soft blank for us */
984 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
987 static struct fb_ops i740fb_ops = {
988 .owner = THIS_MODULE,
989 .fb_open = i740fb_open,
990 .fb_release = i740fb_release,
991 .fb_check_var = i740fb_check_var,
992 .fb_set_par = i740fb_set_par,
993 .fb_setcolreg = i740fb_setcolreg,
994 .fb_blank = i740fb_blank,
995 .fb_pan_display = i740fb_pan_display,
996 .fb_fillrect = cfb_fillrect,
997 .fb_copyarea = cfb_copyarea,
998 .fb_imageblit = cfb_imageblit,
1001 /* ------------------------------------------------------------------------- */
1003 static int i740fb_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1005 struct fb_info *info;
1006 struct i740fb_par *par;
1011 info = framebuffer_alloc(sizeof(struct i740fb_par), &(dev->dev));
1013 dev_err(&(dev->dev), "cannot allocate framebuffer\n");
1018 mutex_init(&par->open_lock);
1020 info->var.activate = FB_ACTIVATE_NOW;
1021 info->var.bits_per_pixel = 8;
1022 info->fbops = &i740fb_ops;
1023 info->pseudo_palette = par->pseudo_palette;
1025 ret = pci_enable_device(dev);
1027 dev_err(info->device, "cannot enable PCI device\n");
1028 goto err_enable_device;
1031 ret = pci_request_regions(dev, info->fix.id);
1033 dev_err(info->device, "error requesting regions\n");
1034 goto err_request_regions;
1037 info->screen_base = pci_ioremap_wc_bar(dev, 0);
1038 if (!info->screen_base) {
1039 dev_err(info->device, "error remapping base\n");
1044 par->regs = pci_ioremap_bar(dev, 1);
1046 dev_err(info->device, "error remapping MMIO\n");
1051 /* detect memory size */
1052 if ((i740inreg(par, XRX, DRAM_ROW_TYPE) & DRAM_ROW_1)
1053 == DRAM_ROW_1_SDRAM)
1054 i740outb(par, XRX, DRAM_ROW_BNDRY_1);
1056 i740outb(par, XRX, DRAM_ROW_BNDRY_0);
1057 info->screen_size = i740inb(par, XRX + 1) * 1024 * 1024;
1058 /* detect memory type */
1059 tmp = i740inreg(par, XRX, DRAM_ROW_CNTL_LO);
1060 par->has_sgram = !((tmp & DRAM_RAS_TIMING) ||
1061 (tmp & DRAM_RAS_PRECHARGE));
1063 fb_info(info, "Intel740 on %s, %ld KB %s\n",
1064 pci_name(dev), info->screen_size >> 10,
1065 par->has_sgram ? "SGRAM" : "SDRAM");
1067 info->fix = i740fb_fix;
1068 info->fix.mmio_start = pci_resource_start(dev, 1);
1069 info->fix.mmio_len = pci_resource_len(dev, 1);
1070 info->fix.smem_start = pci_resource_start(dev, 0);
1071 info->fix.smem_len = info->screen_size;
1072 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1074 if (i740fb_setup_ddc_bus(info) == 0) {
1075 par->ddc_registered = true;
1076 edid = fb_ddc_read(&par->ddc_adapter);
1078 fb_edid_to_monspecs(edid, &info->monspecs);
1080 if (!info->monspecs.modedb)
1081 dev_err(info->device,
1082 "error getting mode database\n");
1084 const struct fb_videomode *m;
1086 fb_videomode_to_modelist(
1087 info->monspecs.modedb,
1088 info->monspecs.modedb_len,
1090 m = fb_find_best_display(&info->monspecs,
1093 fb_videomode_to_var(&info->var, m);
1094 /* fill all other info->var's fields */
1095 if (!i740fb_check_var(&info->var, info))
1102 if (!mode_option && !found)
1103 mode_option = "640x480-8@60";
1106 ret = fb_find_mode(&info->var, info, mode_option,
1107 info->monspecs.modedb,
1108 info->monspecs.modedb_len,
1109 NULL, info->var.bits_per_pixel);
1110 if (!ret || ret == 4) {
1111 dev_err(info->device, "mode %s not found\n",
1117 fb_destroy_modedb(info->monspecs.modedb);
1118 info->monspecs.modedb = NULL;
1120 /* maximize virtual vertical size for fast scrolling */
1121 info->var.yres_virtual = info->fix.smem_len * 8 /
1122 (info->var.bits_per_pixel * info->var.xres_virtual);
1127 ret = fb_alloc_cmap(&info->cmap, 256, 0);
1129 dev_err(info->device, "cannot allocate colormap\n");
1130 goto err_alloc_cmap;
1133 ret = register_framebuffer(info);
1135 dev_err(info->device, "error registering framebuffer\n");
1136 goto err_reg_framebuffer;
1139 fb_info(info, "%s frame buffer device\n", info->fix.id);
1140 pci_set_drvdata(dev, info);
1142 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
1143 info->fix.smem_len);
1146 err_reg_framebuffer:
1147 fb_dealloc_cmap(&info->cmap);
1150 if (par->ddc_registered)
1151 i2c_del_adapter(&par->ddc_adapter);
1152 pci_iounmap(dev, par->regs);
1154 pci_iounmap(dev, info->screen_base);
1156 pci_release_regions(dev);
1157 err_request_regions:
1158 /* pci_disable_device(dev); */
1160 framebuffer_release(info);
1164 static void i740fb_remove(struct pci_dev *dev)
1166 struct fb_info *info = pci_get_drvdata(dev);
1169 struct i740fb_par *par = info->par;
1170 arch_phys_wc_del(par->wc_cookie);
1171 unregister_framebuffer(info);
1172 fb_dealloc_cmap(&info->cmap);
1173 if (par->ddc_registered)
1174 i2c_del_adapter(&par->ddc_adapter);
1175 pci_iounmap(dev, par->regs);
1176 pci_iounmap(dev, info->screen_base);
1177 pci_release_regions(dev);
1178 /* pci_disable_device(dev); */
1179 framebuffer_release(info);
1184 static int i740fb_suspend(struct pci_dev *dev, pm_message_t state)
1186 struct fb_info *info = pci_get_drvdata(dev);
1187 struct i740fb_par *par = info->par;
1189 /* don't disable console during hibernation and wakeup from it */
1190 if (state.event == PM_EVENT_FREEZE || state.event == PM_EVENT_PRETHAW)
1194 mutex_lock(&(par->open_lock));
1196 /* do nothing if framebuffer is not active */
1197 if (par->ref_count == 0) {
1198 mutex_unlock(&(par->open_lock));
1203 fb_set_suspend(info, 1);
1205 pci_save_state(dev);
1206 pci_disable_device(dev);
1207 pci_set_power_state(dev, pci_choose_state(dev, state));
1209 mutex_unlock(&(par->open_lock));
1215 static int i740fb_resume(struct pci_dev *dev)
1217 struct fb_info *info = pci_get_drvdata(dev);
1218 struct i740fb_par *par = info->par;
1221 mutex_lock(&(par->open_lock));
1223 if (par->ref_count == 0)
1226 pci_set_power_state(dev, PCI_D0);
1227 pci_restore_state(dev);
1228 if (pci_enable_device(dev))
1231 i740fb_set_par(info);
1232 fb_set_suspend(info, 0);
1235 mutex_unlock(&(par->open_lock));
1240 #define i740fb_suspend NULL
1241 #define i740fb_resume NULL
1242 #endif /* CONFIG_PM */
1244 #define I740_ID_PCI 0x00d1
1245 #define I740_ID_AGP 0x7800
1247 static const struct pci_device_id i740fb_id_table[] = {
1248 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_PCI) },
1249 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_AGP) },
1252 MODULE_DEVICE_TABLE(pci, i740fb_id_table);
1254 static struct pci_driver i740fb_driver = {
1256 .id_table = i740fb_id_table,
1257 .probe = i740fb_probe,
1258 .remove = i740fb_remove,
1259 .suspend = i740fb_suspend,
1260 .resume = i740fb_resume,
1264 static int __init i740fb_setup(char *options)
1268 if (!options || !*options)
1271 while ((opt = strsep(&options, ",")) != NULL) {
1274 else if (!strncmp(opt, "mtrr:", 5))
1275 mtrr = simple_strtoul(opt + 5, NULL, 0);
1284 static int __init i740fb_init(void)
1287 char *option = NULL;
1289 if (fb_get_options("i740fb", &option))
1291 i740fb_setup(option);
1294 return pci_register_driver(&i740fb_driver);
1297 static void __exit i740fb_exit(void)
1299 pci_unregister_driver(&i740fb_driver);
1302 module_init(i740fb_init);
1303 module_exit(i740fb_exit);
1305 MODULE_AUTHOR("(c) 2011 Ondrej Zary <linux@rainbow-software.org>");
1306 MODULE_LICENSE("GPL");
1307 MODULE_DESCRIPTION("fbdev driver for Intel740");
1309 module_param(mode_option, charp, 0444);
1310 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
1312 module_param(mtrr, int, 0444);
1313 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");