2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
6 * Contributors (thanks, all!)
9 * Overhaul for Linux 2.6
12 * Major contributions; Motorola PowerStack (PPC and PCI) support,
13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
16 * Excellent code review.
19 * Amiga updates and testing.
21 * Original cirrusfb author: Frank Neumann
23 * Based on retz3fb.c and cirrusfb.c:
24 * Copyright (C) 1997 Jes Sorensen
25 * Copyright (C) 1996 Frank Neumann
27 ***************************************************************
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive
37 #include <linux/module.h>
38 #include <linux/kernel.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
42 #include <linux/delay.h>
44 #include <linux/init.h>
47 #include <linux/zorro.h>
50 #include <linux/pci.h>
53 #include <asm/amigahw.h>
56 #include <video/vga.h>
57 #include <video/cirrus.h>
59 /*****************************************************************
61 * debugging and utility macros
65 /* disable runtime assertions? */
66 /* #define CIRRUSFB_NDEBUG */
68 /* debugging assertions */
69 #ifndef CIRRUSFB_NDEBUG
70 #define assert(expr) \
72 printk("Assertion failed! %s,%s,%s,line=%d\n", \
73 #expr, __FILE__, __func__, __LINE__); \
79 #define MB_ (1024 * 1024)
81 /*****************************************************************
91 BT_PICCOLO, /* GD5426 */
92 BT_PICASSO, /* GD5426 or GD5428 */
93 BT_SPECTRUM, /* GD5426 or GD5428 */
94 BT_PICASSO4, /* GD5446 */
95 BT_ALPINE, /* GD543x/4x */
97 BT_LAGUNA, /* GD5462/64 */
98 BT_LAGUNAB, /* GD5465 */
102 * per-board-type information, used for enumerating and abstracting
103 * chip-specific information
104 * NOTE: MUST be in the same order as enum cirrus_board in order to
105 * use direct indexing on this array
106 * NOTE: '__initdata' cannot be used as some of this info
107 * is required at runtime. Maybe separate into an init-only and
110 static const struct cirrusfb_board_info_rec {
111 char *name; /* ASCII name of chipset */
112 long maxclock[5]; /* maximum video clock */
113 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
114 bool init_sr07 : 1; /* init SR07 during init_vgachip() */
115 bool init_sr1f : 1; /* write SR1F during init_vgachip() */
116 /* construct bit 19 of screen start address */
117 bool scrn_start_bit19 : 1;
119 /* initial SR07 value, then for each mode */
121 unsigned char sr07_1bpp;
122 unsigned char sr07_1bpp_mux;
123 unsigned char sr07_8bpp;
124 unsigned char sr07_8bpp_mux;
126 unsigned char sr1f; /* SR1F VGA initial register value */
127 } cirrusfb_board_info[] = {
132 /* the SD64/P4 have a higher max. videoclock */
133 135100, 135100, 85500, 85500, 0
137 .scrn_start_bit19 = true,
140 .sr07_1bpp_mux = 0xF6,
142 .sr07_8bpp_mux = 0xF7,
146 .name = "CL Piccolo",
149 90000, 90000, 90000, 90000, 90000
153 .scrn_start_bit19 = false,
160 .name = "CL Picasso",
163 90000, 90000, 90000, 90000, 90000
167 .scrn_start_bit19 = false,
174 .name = "CL Spectrum",
177 90000, 90000, 90000, 90000, 90000
181 .scrn_start_bit19 = false,
188 .name = "CL Picasso4",
190 135100, 135100, 85500, 85500, 0
194 .scrn_start_bit19 = true,
197 .sr07_1bpp_mux = 0xA6,
199 .sr07_8bpp_mux = 0xA7,
205 /* for the GD5430. GD5446 can do more... */
206 85500, 85500, 50000, 28500, 0
210 .scrn_start_bit19 = true,
213 .sr07_1bpp_mux = 0xA6,
215 .sr07_8bpp_mux = 0xA7,
221 135100, 200000, 200000, 135100, 135100
225 .scrn_start_bit19 = true,
234 /* taken from X11 code */
235 170000, 170000, 170000, 170000, 135100,
239 .scrn_start_bit19 = true,
242 .name = "CL Laguna AGP",
244 /* taken from X11 code */
245 170000, 250000, 170000, 170000, 135100,
249 .scrn_start_bit19 = true,
254 #define CHIP(id, btype) \
255 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
257 static struct pci_device_id cirrusfb_pci_table[] = {
258 CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
259 CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_SD64),
260 CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_SD64),
261 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
262 CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
263 CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
264 CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
265 CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
266 CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
267 CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
268 CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/
271 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
273 #endif /* CONFIG_PCI */
277 enum cirrus_board type; /* Board type */
278 u32 regoffset; /* Offset of registers in first Zorro device */
279 u32 ramsize; /* Size of video RAM in first Zorro device */
280 /* If zero, use autoprobe on RAM device */
281 u32 ramoffset; /* Offset of video RAM in first Zorro device */
282 zorro_id ramid; /* Zorro ID of RAM device */
283 zorro_id ramid2; /* Zorro ID of optional second RAM device */
286 static const struct zorrocl zcl_sd64 = {
288 .ramid = ZORRO_PROD_HELFRICH_SD64_RAM,
291 static const struct zorrocl zcl_piccolo = {
293 .ramid = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
296 static const struct zorrocl zcl_picasso = {
298 .ramid = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
301 static const struct zorrocl zcl_spectrum = {
303 .ramid = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
306 static const struct zorrocl zcl_picasso4_z3 = {
308 .regoffset = 0x00600000,
310 .ramoffset = 0x01000000, /* 0x02000000 for 64 MiB boards */
313 static const struct zorrocl zcl_picasso4_z2 = {
315 .regoffset = 0x10000,
316 .ramid = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM1,
317 .ramid2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM2,
321 static const struct zorro_device_id cirrusfb_zorro_table[] = {
323 .id = ZORRO_PROD_HELFRICH_SD64_REG,
324 .driver_data = (unsigned long)&zcl_sd64,
326 .id = ZORRO_PROD_HELFRICH_PICCOLO_REG,
327 .driver_data = (unsigned long)&zcl_piccolo,
329 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
330 .driver_data = (unsigned long)&zcl_picasso,
332 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
333 .driver_data = (unsigned long)&zcl_spectrum,
335 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
336 .driver_data = (unsigned long)&zcl_picasso4_z3,
338 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_REG,
339 .driver_data = (unsigned long)&zcl_picasso4_z2,
343 MODULE_DEVICE_TABLE(zorro, cirrusfb_zorro_table);
344 #endif /* CONFIG_ZORRO */
346 #ifdef CIRRUSFB_DEBUG
347 enum cirrusfb_dbg_reg_class {
351 #endif /* CIRRUSFB_DEBUG */
353 /* info about board */
354 struct cirrusfb_info {
356 u8 __iomem *laguna_mmio;
357 enum cirrus_board btype;
358 unsigned char SFR; /* Shadow of special function register */
363 u32 pseudo_palette[16];
365 void (*unmap)(struct fb_info *info);
369 static char *mode_option = "640x480@60";
371 /****************************************************************************/
372 /**** BEGIN PROTOTYPES ******************************************************/
374 /*--- Interface used by the world ------------------------------------------*/
375 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
376 struct fb_info *info);
378 /*--- Internal routines ----------------------------------------------------*/
379 static void init_vgachip(struct fb_info *info);
380 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
381 static void WGen(const struct cirrusfb_info *cinfo,
382 int regnum, unsigned char val);
383 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
384 static void AttrOn(const struct cirrusfb_info *cinfo);
385 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
386 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
387 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
388 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
389 unsigned char red, unsigned char green, unsigned char blue);
391 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
392 unsigned char *red, unsigned char *green,
393 unsigned char *blue);
395 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
396 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
397 u_short curx, u_short cury,
398 u_short destx, u_short desty,
399 u_short width, u_short height,
400 u_short line_length);
401 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
402 u_short x, u_short y,
403 u_short width, u_short height,
404 u32 fg_color, u32 bg_color,
405 u_short line_length, u_char blitmode);
407 static void bestclock(long freq, int *nom, int *den, int *div);
409 #ifdef CIRRUSFB_DEBUG
410 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
411 static void cirrusfb_dbg_print_regs(struct fb_info *info,
413 enum cirrusfb_dbg_reg_class reg_class, ...);
414 #endif /* CIRRUSFB_DEBUG */
416 /*** END PROTOTYPES ********************************************************/
417 /*****************************************************************************/
418 /*** BEGIN Interface Used by the World ***************************************/
420 static inline int is_laguna(const struct cirrusfb_info *cinfo)
422 return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
425 static int opencount;
427 /*--- Open /dev/fbx ---------------------------------------------------------*/
428 static int cirrusfb_open(struct fb_info *info, int user)
430 if (opencount++ == 0)
431 switch_monitor(info->par, 1);
435 /*--- Close /dev/fbx --------------------------------------------------------*/
436 static int cirrusfb_release(struct fb_info *info, int user)
438 if (--opencount == 0)
439 switch_monitor(info->par, 0);
443 /**** END Interface used by the World *************************************/
444 /****************************************************************************/
445 /**** BEGIN Hardware specific Routines **************************************/
447 /* Check if the MCLK is not a better clock source */
448 static int cirrusfb_check_mclk(struct fb_info *info, long freq)
450 struct cirrusfb_info *cinfo = info->par;
451 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
453 /* Read MCLK value */
454 mclk = (14318 * mclk) >> 3;
455 dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk);
457 /* Determine if we should use MCLK instead of VCLK, and if so, what we
458 * should divide it by to get VCLK
461 if (abs(freq - mclk) < 250) {
462 dev_dbg(info->device, "Using VCLK = MCLK\n");
464 } else if (abs(freq - (mclk / 2)) < 250) {
465 dev_dbg(info->device, "Using VCLK = MCLK/2\n");
472 static int cirrusfb_check_pixclock(struct fb_var_screeninfo *var,
473 struct fb_info *info)
477 struct cirrusfb_info *cinfo = info->par;
478 unsigned maxclockidx = var->bits_per_pixel >> 3;
480 /* convert from ps to kHz */
481 freq = PICOS2KHZ(var->pixclock ? : 1);
483 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
484 cinfo->multiplexing = 0;
486 /* If the frequency is greater than we can support, we might be able
487 * to use multiplexing for the video mode */
488 if (freq > maxclock) {
489 var->pixclock = KHZ2PICOS(maxclock);
491 while ((freq = PICOS2KHZ(var->pixclock)) > maxclock)
494 dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
497 * Additional constraint: 8bpp uses DAC clock doubling to allow maximum
500 if (var->bits_per_pixel == 8) {
501 switch (cinfo->btype) {
506 cinfo->multiplexing = 1;
510 cinfo->multiplexing = 1;
518 /* If we have a 1MB 5434, we need to put ourselves in a mode where
519 * the VCLK is double the pixel clock. */
520 cinfo->doubleVCLK = 0;
521 if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ &&
522 var->bits_per_pixel == 16) {
523 cinfo->doubleVCLK = 1;
529 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
530 struct fb_info *info)
533 /* memory size in pixels */
534 unsigned pixels = info->screen_size * 8 / var->bits_per_pixel;
535 struct cirrusfb_info *cinfo = info->par;
537 switch (var->bits_per_pixel) {
541 var->green = var->red;
542 var->blue = var->red;
548 var->green = var->red;
549 var->blue = var->red;
553 var->red.offset = 11;
554 var->green.offset = 5;
555 var->blue.offset = 0;
557 var->green.length = 6;
558 var->blue.length = 5;
562 var->red.offset = 16;
563 var->green.offset = 8;
564 var->blue.offset = 0;
566 var->green.length = 8;
567 var->blue.length = 8;
571 dev_dbg(info->device,
572 "Unsupported bpp size: %d\n", var->bits_per_pixel);
576 if (var->xres_virtual < var->xres)
577 var->xres_virtual = var->xres;
578 /* use highest possible virtual resolution */
579 if (var->yres_virtual == -1) {
580 var->yres_virtual = pixels / var->xres_virtual;
582 dev_info(info->device,
583 "virtual resolution set to maximum of %dx%d\n",
584 var->xres_virtual, var->yres_virtual);
586 if (var->yres_virtual < var->yres)
587 var->yres_virtual = var->yres;
589 if (var->xres_virtual * var->yres_virtual > pixels) {
590 dev_err(info->device, "mode %dx%dx%d rejected... "
591 "virtual resolution too high to fit into video memory!\n",
592 var->xres_virtual, var->yres_virtual,
593 var->bits_per_pixel);
597 /* truncate xoffset and yoffset to maximum if too high */
598 if (var->xoffset > var->xres_virtual - var->xres)
599 var->xoffset = var->xres_virtual - var->xres - 1;
600 if (var->yoffset > var->yres_virtual - var->yres)
601 var->yoffset = var->yres_virtual - var->yres - 1;
604 var->green.msb_right =
605 var->blue.msb_right =
608 var->transp.msb_right = 0;
611 if (var->vmode & FB_VMODE_DOUBLE)
613 else if (var->vmode & FB_VMODE_INTERLACED)
614 yres = (yres + 1) / 2;
617 dev_err(info->device, "ERROR: VerticalTotal >= 1280; "
618 "special treatment required! (TODO)\n");
622 if (cirrusfb_check_pixclock(var, info))
625 if (!is_laguna(cinfo))
626 var->accel_flags = FB_ACCELF_TEXT;
631 static void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div)
633 struct cirrusfb_info *cinfo = info->par;
634 unsigned char old1f, old1e;
636 assert(cinfo != NULL);
637 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
640 dev_dbg(info->device, "Set %s as pixclock source.\n",
641 (div == 2) ? "MCLK/2" : "MCLK");
643 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
647 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
649 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
652 /*************************************************************************
653 cirrusfb_set_par_foo()
655 actually writes the values for a new video mode into the hardware,
656 **************************************************************************/
657 static int cirrusfb_set_par_foo(struct fb_info *info)
659 struct cirrusfb_info *cinfo = info->par;
660 struct fb_var_screeninfo *var = &info->var;
661 u8 __iomem *regbase = cinfo->regbase;
664 const struct cirrusfb_board_info_rec *bi;
665 int hdispend, hsyncstart, hsyncend, htotal;
666 int yres, vdispend, vsyncstart, vsyncend, vtotal;
669 unsigned int control = 0, format = 0, threshold = 0;
671 dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
672 var->xres, var->yres, var->bits_per_pixel);
674 switch (var->bits_per_pixel) {
676 info->fix.line_length = var->xres_virtual / 8;
677 info->fix.visual = FB_VISUAL_MONO10;
681 info->fix.line_length = var->xres_virtual;
682 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
687 info->fix.line_length = var->xres_virtual *
688 var->bits_per_pixel >> 3;
689 info->fix.visual = FB_VISUAL_TRUECOLOR;
692 info->fix.type = FB_TYPE_PACKED_PIXELS;
696 bi = &cirrusfb_board_info[cinfo->btype];
698 hsyncstart = var->xres + var->right_margin;
699 hsyncend = hsyncstart + var->hsync_len;
700 htotal = (hsyncend + var->left_margin) / 8;
701 hdispend = var->xres / 8;
702 hsyncstart = hsyncstart / 8;
703 hsyncend = hsyncend / 8;
705 vdispend = var->yres;
706 vsyncstart = vdispend + var->lower_margin;
707 vsyncend = vsyncstart + var->vsync_len;
708 vtotal = vsyncend + var->upper_margin;
710 if (var->vmode & FB_VMODE_DOUBLE) {
715 } else if (var->vmode & FB_VMODE_INTERLACED) {
716 vdispend = (vdispend + 1) / 2;
717 vsyncstart = (vsyncstart + 1) / 2;
718 vsyncend = (vsyncend + 1) / 2;
719 vtotal = (vtotal + 1) / 2;
734 if (cinfo->multiplexing) {
746 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
747 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
749 /* if debugging is enabled, all parameters get output before writing */
750 dev_dbg(info->device, "CRT0: %d\n", htotal);
751 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);
753 dev_dbg(info->device, "CRT1: %d\n", hdispend);
754 vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);
756 dev_dbg(info->device, "CRT2: %d\n", var->xres / 8);
757 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);
759 /* + 128: Compatible read */
760 dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32);
761 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
762 128 + ((htotal + 5) % 32));
764 dev_dbg(info->device, "CRT4: %d\n", hsyncstart);
765 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);
768 if ((htotal + 5) & 32)
770 dev_dbg(info->device, "CRT5: %d\n", tmp);
771 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
773 dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff);
774 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);
776 tmp = 16; /* LineCompare bit #9 */
781 if (vsyncstart & 256)
783 if ((vdispend + 1) & 256)
789 if (vsyncstart & 512)
791 dev_dbg(info->device, "CRT7: %d\n", tmp);
792 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
794 tmp = 0x40; /* LineCompare bit #8 */
795 if ((vdispend + 1) & 512)
797 if (var->vmode & FB_VMODE_DOUBLE)
799 dev_dbg(info->device, "CRT9: %d\n", tmp);
800 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
802 dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff);
803 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);
805 dev_dbg(info->device, "CRT11: 64+32+%d\n", vsyncend % 16);
806 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);
808 dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff);
809 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);
811 dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff);
812 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);
814 dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff);
815 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);
817 dev_dbg(info->device, "CRT18: 0xff\n");
818 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
821 if (var->vmode & FB_VMODE_INTERLACED)
823 if ((htotal + 5) & 64)
825 if ((htotal + 5) & 128)
832 dev_dbg(info->device, "CRT1a: %d\n", tmp);
833 vga_wcrt(regbase, CL_CRT1A, tmp);
835 freq = PICOS2KHZ(var->pixclock);
836 if (var->bits_per_pixel == 24)
837 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64)
839 if (cinfo->multiplexing)
841 if (cinfo->doubleVCLK)
844 bestclock(freq, &nom, &den, &div);
846 dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n",
847 freq, nom, den, div);
850 /* hardware RefClock: 14.31818 MHz */
851 /* formula: VClk = (OSC * N) / (D * (1+P)) */
852 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
854 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 ||
855 cinfo->btype == BT_SD64) {
856 /* if freq is close to mclk or mclk/2 select mclk
859 int divMCLK = cirrusfb_check_mclk(info, freq);
862 cirrusfb_set_mclk_as_source(info, divMCLK);
864 if (is_laguna(cinfo)) {
865 long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
866 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
867 unsigned short tile_control;
869 if (cinfo->btype == BT_LAGUNAB) {
870 tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
871 tile_control &= ~0x80;
872 fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4);
875 fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
876 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
877 control = fb_readw(cinfo->laguna_mmio + 0x402);
878 threshold = fb_readw(cinfo->laguna_mmio + 0xea);
881 threshold &= 0xffc0 & 0x3fbf;
887 /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
888 if ((cinfo->btype == BT_SD64) ||
889 (cinfo->btype == BT_ALPINE) ||
890 (cinfo->btype == BT_GD5480))
893 /* Laguna chipset has reversed clock registers */
894 if (is_laguna(cinfo)) {
895 vga_wseq(regbase, CL_SEQRE, tmp);
896 vga_wseq(regbase, CL_SEQR1E, nom);
898 vga_wseq(regbase, CL_SEQRE, nom);
899 vga_wseq(regbase, CL_SEQR1E, tmp);
905 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
907 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
908 * address wrap, no compat. */
909 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
911 /* don't know if it would hurt to also program this if no interlaced */
912 /* mode is used, but I feel better this way.. :-) */
913 if (var->vmode & FB_VMODE_INTERLACED)
914 vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);
916 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
918 /* adjust horizontal/vertical sync type (low/high), use VCLK3 */
919 /* enable display memory & CRTC I/O address for color mode */
921 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
923 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
925 WGen(cinfo, VGA_MIS_W, tmp);
927 /* text cursor on and start line */
928 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
929 /* text cursor end line */
930 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
932 /******************************************************
938 /* programming for different color depths */
939 if (var->bits_per_pixel == 1) {
940 dev_dbg(info->device, "preparing for 1 bit deep display\n");
941 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
944 switch (cinfo->btype) {
952 vga_wseq(regbase, CL_SEQR7,
953 cinfo->multiplexing ?
954 bi->sr07_1bpp_mux : bi->sr07_1bpp);
959 vga_wseq(regbase, CL_SEQR7,
960 vga_rseq(regbase, CL_SEQR7) & ~0x01);
964 dev_warn(info->device, "unknown Board\n");
968 /* Extended Sequencer Mode */
969 switch (cinfo->btype) {
973 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
974 vga_wseq(regbase, CL_SEQRF, 0xb0);
978 /* ## vorher d0 avoid FIFO underruns..? */
979 vga_wseq(regbase, CL_SEQRF, 0xd0);
992 dev_warn(info->device, "unknown Board\n");
996 /* pixel mask: pass-through for first plane */
997 WGen(cinfo, VGA_PEL_MSK, 0x01);
998 if (cinfo->multiplexing)
999 /* hidden dac reg: 1280x1024 */
1002 /* hidden dac: nothing */
1004 /* memory mode: odd/even, ext. memory */
1005 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
1006 /* plane mask: only write to first plane */
1007 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
1010 /******************************************************
1016 else if (var->bits_per_pixel == 8) {
1017 dev_dbg(info->device, "preparing for 8 bit deep display\n");
1018 switch (cinfo->btype) {
1026 vga_wseq(regbase, CL_SEQR7,
1027 cinfo->multiplexing ?
1028 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1033 vga_wseq(regbase, CL_SEQR7,
1034 vga_rseq(regbase, CL_SEQR7) | 0x01);
1039 dev_warn(info->device, "unknown Board\n");
1043 switch (cinfo->btype) {
1047 /* Fast Page-Mode writes */
1048 vga_wseq(regbase, CL_SEQRF, 0xb0);
1053 /* ### INCOMPLETE!! */
1054 vga_wseq(regbase, CL_SEQRF, 0xb8);
1065 dev_warn(info->device, "unknown board\n");
1069 /* mode register: 256 color mode */
1070 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1071 if (cinfo->multiplexing)
1072 /* hidden dac reg: 1280x1024 */
1075 /* hidden dac: nothing */
1079 /******************************************************
1085 else if (var->bits_per_pixel == 16) {
1086 dev_dbg(info->device, "preparing for 16 bit deep display\n");
1087 switch (cinfo->btype) {
1090 vga_wseq(regbase, CL_SEQR7, 0x87);
1091 /* Fast Page-Mode writes */
1092 vga_wseq(regbase, CL_SEQRF, 0xb0);
1096 vga_wseq(regbase, CL_SEQR7, 0x27);
1097 /* Fast Page-Mode writes */
1098 vga_wseq(regbase, CL_SEQRF, 0xb0);
1104 /* Extended Sequencer Mode: 256c col. mode */
1105 vga_wseq(regbase, CL_SEQR7,
1106 cinfo->doubleVCLK ? 0xa3 : 0xa7);
1110 vga_wseq(regbase, CL_SEQR7, 0x17);
1111 /* We already set SRF and SR1F */
1116 vga_wseq(regbase, CL_SEQR7,
1117 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1124 dev_warn(info->device, "unknown Board\n");
1128 /* mode register: 256 color mode */
1129 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1131 WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1);
1132 #elif defined(CONFIG_ZORRO)
1133 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1134 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1138 /******************************************************
1144 else if (var->bits_per_pixel == 24) {
1145 dev_dbg(info->device, "preparing for 24 bit deep display\n");
1146 switch (cinfo->btype) {
1149 vga_wseq(regbase, CL_SEQR7, 0x85);
1150 /* Fast Page-Mode writes */
1151 vga_wseq(regbase, CL_SEQRF, 0xb0);
1155 vga_wseq(regbase, CL_SEQR7, 0x25);
1156 /* Fast Page-Mode writes */
1157 vga_wseq(regbase, CL_SEQRF, 0xb0);
1163 /* Extended Sequencer Mode: 256c col. mode */
1164 vga_wseq(regbase, CL_SEQR7, 0xa5);
1168 vga_wseq(regbase, CL_SEQR7, 0x15);
1169 /* We already set SRF and SR1F */
1174 vga_wseq(regbase, CL_SEQR7,
1175 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1182 dev_warn(info->device, "unknown Board\n");
1186 /* mode register: 256 color mode */
1187 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1188 /* hidden dac reg: 8-8-8 mode (24 or 32) */
1192 /******************************************************
1194 * unknown/unsupported bpp
1199 dev_err(info->device,
1200 "What's this? requested color depth == %d.\n",
1201 var->bits_per_pixel);
1203 pitch = info->fix.line_length >> 3;
1204 vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff);
1207 tmp |= 0x10; /* offset overflow bit */
1209 /* screen start addr #16-18, fastpagemode cycles */
1210 vga_wcrt(regbase, CL_CRT1B, tmp);
1212 /* screen start address bit 19 */
1213 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
1214 vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
1216 if (is_laguna(cinfo)) {
1218 if ((htotal + 5) & 256)
1222 if (hsyncstart & 256)
1226 if (vdispend & 1024)
1228 if (vsyncstart & 1024)
1231 vga_wcrt(regbase, CL_CRT1E, tmp);
1232 dev_dbg(info->device, "CRT1e: %d\n", tmp);
1236 vga_wattr(regbase, CL_AR33, 0);
1238 /* [ EGS: SetOffset(); ] */
1239 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1242 if (is_laguna(cinfo)) {
1244 fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
1245 fb_writew(format, cinfo->laguna_mmio + 0xc0);
1246 fb_writew(threshold, cinfo->laguna_mmio + 0xea);
1248 /* finally, turn on everything - turn off "FullBandwidth" bit */
1249 /* also, set "DotClock%2" bit where requested */
1252 /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
1253 if (var->vmode & FB_VMODE_CLOCK_HALVE)
1257 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
1258 dev_dbg(info->device, "CL_SEQR1: %d\n", tmp);
1260 #ifdef CIRRUSFB_DEBUG
1261 cirrusfb_dbg_reg_dump(info, NULL);
1267 /* for some reason incomprehensible to me, cirrusfb requires that you write
1268 * the registers twice for the settings to take..grr. -dte */
1269 static int cirrusfb_set_par(struct fb_info *info)
1271 cirrusfb_set_par_foo(info);
1272 return cirrusfb_set_par_foo(info);
1275 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1276 unsigned blue, unsigned transp,
1277 struct fb_info *info)
1279 struct cirrusfb_info *cinfo = info->par;
1284 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
1286 red >>= (16 - info->var.red.length);
1287 green >>= (16 - info->var.green.length);
1288 blue >>= (16 - info->var.blue.length);
1292 v = (red << info->var.red.offset) |
1293 (green << info->var.green.offset) |
1294 (blue << info->var.blue.offset);
1296 cinfo->pseudo_palette[regno] = v;
1300 if (info->var.bits_per_pixel == 8)
1301 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1307 /*************************************************************************
1308 cirrusfb_pan_display()
1310 performs display panning - provided hardware permits this
1311 **************************************************************************/
1312 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
1313 struct fb_info *info)
1317 unsigned char tmp, xpix;
1318 struct cirrusfb_info *cinfo = info->par;
1320 /* no range checks for xoffset and yoffset, */
1321 /* as fb_pan_display has already done this */
1322 if (var->vmode & FB_VMODE_YWRAP)
1325 xoffset = var->xoffset * info->var.bits_per_pixel / 8;
1327 base = var->yoffset * info->fix.line_length + xoffset;
1329 if (info->var.bits_per_pixel == 1) {
1330 /* base is already correct */
1331 xpix = (unsigned char) (var->xoffset % 8);
1334 xpix = (unsigned char) ((xoffset % 4) * 2);
1337 if (!is_laguna(cinfo))
1338 cirrusfb_WaitBLT(cinfo->regbase);
1340 /* lower 8 + 8 bits of screen start address */
1341 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
1342 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);
1344 /* 0xf2 is %11110010, exclude tmp bits */
1345 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
1346 /* construct bits 16, 17 and 18 of screen start address */
1354 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
1356 /* construct bit 19 of screen start address */
1357 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
1358 tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
1359 if (is_laguna(cinfo))
1360 tmp = (tmp & ~0x18) | ((base >> 16) & 0x18);
1362 tmp = (tmp & ~0x80) | ((base >> 12) & 0x80);
1363 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
1366 /* write pixel panning value to AR33; this does not quite work in 8bpp
1368 * ### Piccolo..? Will this work?
1370 if (info->var.bits_per_pixel == 1)
1371 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1376 static int cirrusfb_blank(int blank_mode, struct fb_info *info)
1379 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1380 * then the caller blanks by setting the CLUT (Color Look Up Table)
1381 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
1382 * failed due to e.g. a video mode which doesn't support it.
1383 * Implements VESA suspend and powerdown modes on hardware that
1384 * supports disabling hsync/vsync:
1385 * blank_mode == 2: suspend vsync
1386 * blank_mode == 3: suspend hsync
1387 * blank_mode == 4: powerdown
1390 struct cirrusfb_info *cinfo = info->par;
1391 int current_mode = cinfo->blank_mode;
1393 dev_dbg(info->device, "ENTER, blank mode = %d\n", blank_mode);
1395 if (info->state != FBINFO_STATE_RUNNING ||
1396 current_mode == blank_mode) {
1397 dev_dbg(info->device, "EXIT, returning 0\n");
1402 if (current_mode == FB_BLANK_NORMAL ||
1403 current_mode == FB_BLANK_UNBLANK)
1404 /* clear "FullBandwidth" bit */
1407 /* set "FullBandwidth" bit */
1410 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
1411 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
1413 switch (blank_mode) {
1414 case FB_BLANK_UNBLANK:
1415 case FB_BLANK_NORMAL:
1418 case FB_BLANK_VSYNC_SUSPEND:
1421 case FB_BLANK_HSYNC_SUSPEND:
1424 case FB_BLANK_POWERDOWN:
1428 dev_dbg(info->device, "EXIT, returning 1\n");
1432 vga_wgfx(cinfo->regbase, CL_GRE, val);
1434 cinfo->blank_mode = blank_mode;
1435 dev_dbg(info->device, "EXIT, returning 0\n");
1437 /* Let fbcon do a soft blank for us */
1438 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1441 /**** END Hardware specific Routines **************************************/
1442 /****************************************************************************/
1443 /**** BEGIN Internal Routines ***********************************************/
1445 static void init_vgachip(struct fb_info *info)
1447 struct cirrusfb_info *cinfo = info->par;
1448 const struct cirrusfb_board_info_rec *bi;
1450 assert(cinfo != NULL);
1452 bi = &cirrusfb_board_info[cinfo->btype];
1454 /* reset board globally */
1455 switch (cinfo->btype) {
1474 /* disable flickerfixer */
1475 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1478 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1481 /* from Klaus' NetBSD driver: */
1482 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1485 /* put blitter into 542x compat */
1486 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1491 /* Nothing to do to reset the board. */
1495 dev_err(info->device, "Warning: Unknown board type\n");
1499 /* make sure RAM size set by this point */
1500 assert(info->screen_size > 0);
1502 /* the P4 is not fully initialized here; I rely on it having been */
1503 /* inited under AmigaOS already, which seems to work just fine */
1504 /* (Klaus advised to do it this way) */
1506 if (cinfo->btype != BT_PICASSO4) {
1507 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1508 WGen(cinfo, CL_POS102, 0x01);
1509 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1511 if (cinfo->btype != BT_SD64)
1512 WGen(cinfo, CL_VSSM2, 0x01);
1514 /* reset sequencer logic */
1515 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
1517 /* FullBandwidth (video off) and 8/9 dot clock */
1518 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1520 /* "magic cookie" - doesn't make any sense to me.. */
1521 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1522 /* unlock all extension registers */
1523 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1525 switch (cinfo->btype) {
1527 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1535 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1539 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1540 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1544 /* plane mask: nothing */
1545 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1546 /* character map select: doesn't even matter in gx mode */
1547 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1548 /* memory mode: chain4, ext. memory */
1549 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1551 /* controller-internal base address of video memory */
1553 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1555 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1556 /* EEPROM control: shouldn't be necessary to write to this at all.. */
1558 /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1559 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1560 /* graphics cursor Y position (..."... ) */
1561 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1562 /* graphics cursor attributes */
1563 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1564 /* graphics cursor pattern address */
1565 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1567 /* writing these on a P4 might give problems.. */
1568 if (cinfo->btype != BT_PICASSO4) {
1569 /* configuration readback and ext. color */
1570 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1571 /* signature generator */
1572 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1575 /* Screen A preset row scan: none */
1576 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1577 /* Text cursor start: disable text cursor */
1578 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1579 /* Text cursor end: - */
1580 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1581 /* text cursor location high: 0 */
1582 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
1583 /* text cursor location low: 0 */
1584 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
1586 /* Underline Row scanline: - */
1587 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
1588 /* ### add 0x40 for text modes with > 30 MHz pixclock */
1589 /* ext. display controls: ext.adr. wrap */
1590 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
1592 /* Set/Reset registers: - */
1593 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
1594 /* Set/Reset enable: - */
1595 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
1596 /* Color Compare: - */
1597 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
1598 /* Data Rotate: - */
1599 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
1600 /* Read Map Select: - */
1601 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
1602 /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
1603 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
1604 /* Miscellaneous: memory map base address, graphics mode */
1605 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
1606 /* Color Don't care: involve all planes */
1607 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
1608 /* Bit Mask: no mask at all */
1609 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1611 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 ||
1613 /* (5434 can't have bit 3 set for bitblt) */
1614 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1616 /* Graphics controller mode extensions: finer granularity,
1617 * 8byte data latches
1619 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
1621 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1622 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1623 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1624 /* Background color byte 1: - */
1625 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
1626 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1628 /* Attribute Controller palette registers: "identity mapping" */
1629 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
1630 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1631 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1632 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1633 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1634 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1635 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1636 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1637 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1638 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1639 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1640 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1641 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1642 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1643 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1644 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1646 /* Attribute Controller mode: graphics mode */
1647 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
1648 /* Overscan color reg.: reg. 0 */
1649 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
1650 /* Color Plane enable: Enable all 4 planes */
1651 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
1652 /* Color Select: - */
1653 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
1655 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1657 /* BLT Start/status: Blitter reset */
1658 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1659 /* - " - : "end-of-reset" */
1660 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1663 WHDR(cinfo, 0); /* Hidden DAC register: - */
1667 static void switch_monitor(struct cirrusfb_info *cinfo, int on)
1669 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
1670 static int IsOn = 0; /* XXX not ok for multiple boards */
1672 if (cinfo->btype == BT_PICASSO4)
1673 return; /* nothing to switch */
1674 if (cinfo->btype == BT_ALPINE)
1675 return; /* nothing to switch */
1676 if (cinfo->btype == BT_GD5480)
1677 return; /* nothing to switch */
1678 if (cinfo->btype == BT_PICASSO) {
1679 if ((on && !IsOn) || (!on && IsOn))
1684 switch (cinfo->btype) {
1686 WSFR(cinfo, cinfo->SFR | 0x21);
1689 WSFR(cinfo, cinfo->SFR | 0x28);
1694 default: /* do nothing */ break;
1697 switch (cinfo->btype) {
1699 WSFR(cinfo, cinfo->SFR & 0xde);
1702 WSFR(cinfo, cinfo->SFR & 0xd7);
1707 default: /* do nothing */
1711 #endif /* CONFIG_ZORRO */
1714 /******************************************/
1715 /* Linux 2.6-style accelerated functions */
1716 /******************************************/
1718 static int cirrusfb_sync(struct fb_info *info)
1720 struct cirrusfb_info *cinfo = info->par;
1722 if (!is_laguna(cinfo)) {
1723 while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03)
1729 static void cirrusfb_fillrect(struct fb_info *info,
1730 const struct fb_fillrect *region)
1732 struct fb_fillrect modded;
1734 struct cirrusfb_info *cinfo = info->par;
1735 int m = info->var.bits_per_pixel;
1736 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1737 cinfo->pseudo_palette[region->color] : region->color;
1739 if (info->state != FBINFO_STATE_RUNNING)
1741 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1742 cfb_fillrect(info, region);
1746 vxres = info->var.xres_virtual;
1747 vyres = info->var.yres_virtual;
1749 memcpy(&modded, region, sizeof(struct fb_fillrect));
1751 if (!modded.width || !modded.height ||
1752 modded.dx >= vxres || modded.dy >= vyres)
1755 if (modded.dx + modded.width > vxres)
1756 modded.width = vxres - modded.dx;
1757 if (modded.dy + modded.height > vyres)
1758 modded.height = vyres - modded.dy;
1760 cirrusfb_RectFill(cinfo->regbase,
1761 info->var.bits_per_pixel,
1762 (region->dx * m) / 8, region->dy,
1763 (region->width * m) / 8, region->height,
1765 info->fix.line_length, 0x40);
1768 static void cirrusfb_copyarea(struct fb_info *info,
1769 const struct fb_copyarea *area)
1771 struct fb_copyarea modded;
1773 struct cirrusfb_info *cinfo = info->par;
1774 int m = info->var.bits_per_pixel;
1776 if (info->state != FBINFO_STATE_RUNNING)
1778 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1779 cfb_copyarea(info, area);
1783 vxres = info->var.xres_virtual;
1784 vyres = info->var.yres_virtual;
1785 memcpy(&modded, area, sizeof(struct fb_copyarea));
1787 if (!modded.width || !modded.height ||
1788 modded.sx >= vxres || modded.sy >= vyres ||
1789 modded.dx >= vxres || modded.dy >= vyres)
1792 if (modded.sx + modded.width > vxres)
1793 modded.width = vxres - modded.sx;
1794 if (modded.dx + modded.width > vxres)
1795 modded.width = vxres - modded.dx;
1796 if (modded.sy + modded.height > vyres)
1797 modded.height = vyres - modded.sy;
1798 if (modded.dy + modded.height > vyres)
1799 modded.height = vyres - modded.dy;
1801 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
1802 (area->sx * m) / 8, area->sy,
1803 (area->dx * m) / 8, area->dy,
1804 (area->width * m) / 8, area->height,
1805 info->fix.line_length);
1809 static void cirrusfb_imageblit(struct fb_info *info,
1810 const struct fb_image *image)
1812 struct cirrusfb_info *cinfo = info->par;
1813 unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4;
1815 if (info->state != FBINFO_STATE_RUNNING)
1817 /* Alpine/SD64 does not work at 24bpp ??? */
1818 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1)
1819 cfb_imageblit(info, image);
1820 else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) &&
1822 cfb_imageblit(info, image);
1824 unsigned size = ((image->width + 7) >> 3) * image->height;
1825 int m = info->var.bits_per_pixel;
1828 if (info->var.bits_per_pixel == 8) {
1829 fg = image->fg_color;
1830 bg = image->bg_color;
1832 fg = ((u32 *)(info->pseudo_palette))[image->fg_color];
1833 bg = ((u32 *)(info->pseudo_palette))[image->bg_color];
1835 if (info->var.bits_per_pixel == 24) {
1836 /* clear background first */
1837 cirrusfb_RectFill(cinfo->regbase,
1838 info->var.bits_per_pixel,
1839 (image->dx * m) / 8, image->dy,
1840 (image->width * m) / 8,
1843 info->fix.line_length, 0x40);
1845 cirrusfb_RectFill(cinfo->regbase,
1846 info->var.bits_per_pixel,
1847 (image->dx * m) / 8, image->dy,
1848 (image->width * m) / 8, image->height,
1850 info->fix.line_length, op);
1851 memcpy(info->screen_base, image->data, size);
1856 static int release_io_ports;
1858 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
1859 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
1860 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
1862 static unsigned int cirrusfb_get_memsize(struct fb_info *info,
1863 u8 __iomem *regbase)
1866 struct cirrusfb_info *cinfo = info->par;
1868 if (is_laguna(cinfo)) {
1869 unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);
1871 mem = ((SR14 & 7) + 1) << 20;
1873 unsigned char SRF = vga_rseq(regbase, CL_SEQRF);
1874 switch ((SRF & 0x18)) {
1881 /* 64-bit DRAM data bus width; assume 2MB.
1882 * Also indicates 2MB memory on the 5430.
1888 dev_warn(info->device, "Unknown memory size!\n");
1891 /* If DRAM bank switching is enabled, there must be
1892 * twice as much memory installed. (4MB on the 5434)
1894 if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0)
1898 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
1902 static void get_pci_addrs(const struct pci_dev *pdev,
1903 unsigned long *display, unsigned long *registers)
1905 assert(pdev != NULL);
1906 assert(display != NULL);
1907 assert(registers != NULL);
1912 /* This is a best-guess for now */
1914 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
1915 *display = pci_resource_start(pdev, 1);
1916 *registers = pci_resource_start(pdev, 0);
1918 *display = pci_resource_start(pdev, 0);
1919 *registers = pci_resource_start(pdev, 1);
1922 assert(*display != 0);
1925 static void cirrusfb_pci_unmap(struct fb_info *info)
1927 struct pci_dev *pdev = to_pci_dev(info->device);
1928 struct cirrusfb_info *cinfo = info->par;
1930 if (cinfo->laguna_mmio == NULL)
1931 iounmap(cinfo->laguna_mmio);
1932 iounmap(info->screen_base);
1933 #if 0 /* if system didn't claim this region, we would... */
1934 release_mem_region(0xA0000, 65535);
1936 if (release_io_ports)
1937 release_region(0x3C0, 32);
1938 pci_release_regions(pdev);
1940 #endif /* CONFIG_PCI */
1943 static void cirrusfb_zorro_unmap(struct fb_info *info)
1945 struct cirrusfb_info *cinfo = info->par;
1946 struct zorro_dev *zdev = to_zorro_dev(info->device);
1948 if (info->fix.smem_start > 16 * MB_)
1949 iounmap(info->screen_base);
1950 if (info->fix.mmio_start > 16 * MB_)
1951 iounmap(cinfo->regbase);
1953 zorro_release_device(zdev);
1955 #endif /* CONFIG_ZORRO */
1957 /* function table of the above functions */
1958 static const struct fb_ops cirrusfb_ops = {
1959 .owner = THIS_MODULE,
1960 .fb_open = cirrusfb_open,
1961 .fb_release = cirrusfb_release,
1962 .fb_setcolreg = cirrusfb_setcolreg,
1963 .fb_check_var = cirrusfb_check_var,
1964 .fb_set_par = cirrusfb_set_par,
1965 .fb_pan_display = cirrusfb_pan_display,
1966 .fb_blank = cirrusfb_blank,
1967 .fb_fillrect = cirrusfb_fillrect,
1968 .fb_copyarea = cirrusfb_copyarea,
1969 .fb_sync = cirrusfb_sync,
1970 .fb_imageblit = cirrusfb_imageblit,
1973 static int cirrusfb_set_fbinfo(struct fb_info *info)
1975 struct cirrusfb_info *cinfo = info->par;
1976 struct fb_var_screeninfo *var = &info->var;
1978 info->pseudo_palette = cinfo->pseudo_palette;
1979 info->flags = FBINFO_DEFAULT
1980 | FBINFO_HWACCEL_XPAN
1981 | FBINFO_HWACCEL_YPAN
1982 | FBINFO_HWACCEL_FILLRECT
1983 | FBINFO_HWACCEL_IMAGEBLIT
1984 | FBINFO_HWACCEL_COPYAREA;
1985 if (noaccel || is_laguna(cinfo)) {
1986 info->flags |= FBINFO_HWACCEL_DISABLED;
1987 info->fix.accel = FB_ACCEL_NONE;
1989 info->fix.accel = FB_ACCEL_CIRRUS_ALPINE;
1991 info->fbops = &cirrusfb_ops;
1993 if (cinfo->btype == BT_GD5480) {
1994 if (var->bits_per_pixel == 16)
1995 info->screen_base += 1 * MB_;
1996 if (var->bits_per_pixel == 32)
1997 info->screen_base += 2 * MB_;
2000 /* Fill fix common fields */
2001 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2002 sizeof(info->fix.id));
2004 /* monochrome: only 1 memory plane */
2005 /* 8 bit and above: Use whole memory area */
2006 info->fix.smem_len = info->screen_size;
2007 if (var->bits_per_pixel == 1)
2008 info->fix.smem_len /= 4;
2009 info->fix.type_aux = 0;
2010 info->fix.xpanstep = 1;
2011 info->fix.ypanstep = 1;
2012 info->fix.ywrapstep = 0;
2014 /* FIXME: map region at 0xB8000 if available, fill in here */
2015 info->fix.mmio_len = 0;
2017 fb_alloc_cmap(&info->cmap, 256, 0);
2022 static int cirrusfb_register(struct fb_info *info)
2024 struct cirrusfb_info *cinfo = info->par;
2028 assert(cinfo->btype != BT_NONE);
2030 /* set all the vital stuff */
2031 cirrusfb_set_fbinfo(info);
2033 dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base);
2035 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
2037 dev_dbg(info->device, "wrong initial video mode\n");
2039 goto err_dealloc_cmap;
2042 info->var.activate = FB_ACTIVATE_NOW;
2044 err = cirrusfb_check_var(&info->var, info);
2046 /* should never happen */
2047 dev_dbg(info->device,
2048 "choking on default var... umm, no good.\n");
2049 goto err_dealloc_cmap;
2052 err = register_framebuffer(info);
2054 dev_err(info->device,
2055 "could not register fb device; err = %d!\n", err);
2056 goto err_dealloc_cmap;
2062 fb_dealloc_cmap(&info->cmap);
2066 static void cirrusfb_cleanup(struct fb_info *info)
2068 struct cirrusfb_info *cinfo = info->par;
2070 switch_monitor(cinfo, 0);
2071 unregister_framebuffer(info);
2072 fb_dealloc_cmap(&info->cmap);
2073 dev_dbg(info->device, "Framebuffer unregistered\n");
2075 framebuffer_release(info);
2079 static int cirrusfb_pci_register(struct pci_dev *pdev,
2080 const struct pci_device_id *ent)
2082 struct cirrusfb_info *cinfo;
2083 struct fb_info *info;
2084 unsigned long board_addr, board_size;
2087 ret = pci_enable_device(pdev);
2089 printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
2093 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
2100 cinfo->btype = (enum cirrus_board) ent->driver_data;
2102 dev_dbg(info->device,
2103 " Found PCI device, base address 0 is 0x%Lx, btype set to %d\n",
2104 (unsigned long long)pdev->resource[0].start, cinfo->btype);
2105 dev_dbg(info->device, " base address 1 is 0x%Lx\n",
2106 (unsigned long long)pdev->resource[1].start);
2108 dev_dbg(info->device,
2109 "Attempt to get PCI info for Cirrus Graphics Card\n");
2110 get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start);
2111 /* FIXME: this forces VGA. alternatives? */
2112 cinfo->regbase = NULL;
2113 cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000);
2115 dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n",
2116 board_addr, info->fix.mmio_start);
2118 board_size = (cinfo->btype == BT_GD5480) ?
2119 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
2121 ret = pci_request_regions(pdev, "cirrusfb");
2123 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2125 goto err_release_fb;
2127 #if 0 /* if the system didn't claim this region, we would... */
2128 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
2129 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2132 goto err_release_regions;
2135 if (request_region(0x3C0, 32, "cirrusfb"))
2136 release_io_ports = 1;
2138 info->screen_base = ioremap(board_addr, board_size);
2139 if (!info->screen_base) {
2141 goto err_release_legacy;
2144 info->fix.smem_start = board_addr;
2145 info->screen_size = board_size;
2146 cinfo->unmap = cirrusfb_pci_unmap;
2148 dev_info(info->device,
2149 "Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx\n",
2150 info->screen_size >> 10, board_addr);
2151 pci_set_drvdata(pdev, info);
2153 ret = cirrusfb_register(info);
2157 iounmap(info->screen_base);
2159 if (release_io_ports)
2160 release_region(0x3C0, 32);
2162 release_mem_region(0xA0000, 65535);
2163 err_release_regions:
2165 pci_release_regions(pdev);
2167 if (cinfo->laguna_mmio != NULL)
2168 iounmap(cinfo->laguna_mmio);
2169 framebuffer_release(info);
2174 static void cirrusfb_pci_unregister(struct pci_dev *pdev)
2176 struct fb_info *info = pci_get_drvdata(pdev);
2178 cirrusfb_cleanup(info);
2181 static struct pci_driver cirrusfb_pci_driver = {
2183 .id_table = cirrusfb_pci_table,
2184 .probe = cirrusfb_pci_register,
2185 .remove = cirrusfb_pci_unregister,
2188 .suspend = cirrusfb_pci_suspend,
2189 .resume = cirrusfb_pci_resume,
2193 #endif /* CONFIG_PCI */
2196 static int cirrusfb_zorro_register(struct zorro_dev *z,
2197 const struct zorro_device_id *ent)
2199 struct fb_info *info;
2201 const struct zorrocl *zcl;
2202 enum cirrus_board btype;
2203 unsigned long regbase, ramsize, rambase;
2204 struct cirrusfb_info *cinfo;
2206 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2210 zcl = (const struct zorrocl *)ent->driver_data;
2212 regbase = zorro_resource_start(z) + zcl->regoffset;
2213 ramsize = zcl->ramsize;
2215 rambase = zorro_resource_start(z) + zcl->ramoffset;
2216 if (zorro_resource_len(z) == 64 * MB_) {
2217 /* Quirk for 64 MiB Picasso IV */
2218 rambase += zcl->ramoffset;
2221 struct zorro_dev *ram = zorro_find_device(zcl->ramid, NULL);
2222 if (!ram || !zorro_resource_len(ram)) {
2223 dev_err(info->device, "No video RAM found\n");
2225 goto err_release_fb;
2227 rambase = zorro_resource_start(ram);
2228 ramsize = zorro_resource_len(ram);
2230 (ram = zorro_find_device(zcl->ramid2, NULL))) {
2231 if (zorro_resource_start(ram) != rambase + ramsize) {
2232 dev_warn(info->device,
2233 "Skipping non-contiguous RAM at %pR\n",
2236 ramsize += zorro_resource_len(ram);
2241 dev_info(info->device,
2242 "%s board detected, REG at 0x%lx, %lu MiB RAM at 0x%lx\n",
2243 cirrusfb_board_info[btype].name, regbase, ramsize / MB_,
2246 if (!zorro_request_device(z, "cirrusfb")) {
2247 dev_err(info->device, "Cannot reserve %pR\n", &z->resource);
2249 goto err_release_fb;
2253 cinfo->btype = btype;
2255 info->fix.mmio_start = regbase;
2256 cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024)
2257 : ZTWO_VADDR(regbase);
2258 if (!cinfo->regbase) {
2259 dev_err(info->device, "Cannot map registers\n");
2261 goto err_release_dev;
2264 info->fix.smem_start = rambase;
2265 info->screen_size = ramsize;
2266 info->screen_base = rambase > 16 * MB_ ? ioremap(rambase, ramsize)
2267 : ZTWO_VADDR(rambase);
2268 if (!info->screen_base) {
2269 dev_err(info->device, "Cannot map video RAM\n");
2274 cinfo->unmap = cirrusfb_zorro_unmap;
2276 dev_info(info->device,
2277 "Cirrus Logic chipset on Zorro bus, RAM (%lu MiB) at 0x%lx\n",
2278 ramsize / MB_, rambase);
2280 /* MCLK select etc. */
2281 if (cirrusfb_board_info[btype].init_sr1f)
2282 vga_wseq(cinfo->regbase, CL_SEQR1F,
2283 cirrusfb_board_info[btype].sr1f);
2285 error = cirrusfb_register(info);
2287 dev_err(info->device, "Failed to register device, error %d\n",
2292 zorro_set_drvdata(z, info);
2296 if (rambase > 16 * MB_)
2297 iounmap(info->screen_base);
2300 if (regbase > 16 * MB_)
2301 iounmap(cinfo->regbase);
2303 zorro_release_device(z);
2305 framebuffer_release(info);
2309 void cirrusfb_zorro_unregister(struct zorro_dev *z)
2311 struct fb_info *info = zorro_get_drvdata(z);
2313 cirrusfb_cleanup(info);
2314 zorro_set_drvdata(z, NULL);
2317 static struct zorro_driver cirrusfb_zorro_driver = {
2319 .id_table = cirrusfb_zorro_table,
2320 .probe = cirrusfb_zorro_register,
2321 .remove = cirrusfb_zorro_unregister,
2323 #endif /* CONFIG_ZORRO */
2326 static int __init cirrusfb_setup(char *options)
2330 if (!options || !*options)
2333 while ((this_opt = strsep(&options, ",")) != NULL) {
2337 if (!strcmp(this_opt, "noaccel"))
2339 else if (!strncmp(this_opt, "mode:", 5))
2340 mode_option = this_opt + 5;
2342 mode_option = this_opt;
2352 MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2353 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2354 MODULE_LICENSE("GPL");
2356 static int __init cirrusfb_init(void)
2361 char *option = NULL;
2363 if (fb_get_options("cirrusfb", &option))
2365 cirrusfb_setup(option);
2369 error |= zorro_register_driver(&cirrusfb_zorro_driver);
2372 error |= pci_register_driver(&cirrusfb_pci_driver);
2377 static void __exit cirrusfb_exit(void)
2380 pci_unregister_driver(&cirrusfb_pci_driver);
2383 zorro_unregister_driver(&cirrusfb_zorro_driver);
2387 module_init(cirrusfb_init);
2389 module_param(mode_option, charp, 0);
2390 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
2391 module_param(noaccel, bool, 0);
2392 MODULE_PARM_DESC(noaccel, "Disable acceleration");
2395 module_exit(cirrusfb_exit);
2398 /**********************************************************************/
2399 /* about the following functions - I have used the same names for the */
2400 /* functions as Markus Wild did in his Retina driver for NetBSD as */
2401 /* they just made sense for this purpose. Apart from that, I wrote */
2402 /* these functions myself. */
2403 /**********************************************************************/
2405 /*** WGen() - write into one of the external/general registers ***/
2406 static void WGen(const struct cirrusfb_info *cinfo,
2407 int regnum, unsigned char val)
2409 unsigned long regofs = 0;
2411 if (cinfo->btype == BT_PICASSO) {
2412 /* Picasso II specific hack */
2413 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2414 regnum == CL_VSSM2) */
2415 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2419 vga_w(cinfo->regbase, regofs + regnum, val);
2422 /*** RGen() - read out one of the external/general registers ***/
2423 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2425 unsigned long regofs = 0;
2427 if (cinfo->btype == BT_PICASSO) {
2428 /* Picasso II specific hack */
2429 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2430 regnum == CL_VSSM2) */
2431 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2435 return vga_r(cinfo->regbase, regofs + regnum);
2438 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2439 static void AttrOn(const struct cirrusfb_info *cinfo)
2441 assert(cinfo != NULL);
2443 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2444 /* if we're just in "write value" mode, write back the */
2445 /* same value as before to not modify anything */
2446 vga_w(cinfo->regbase, VGA_ATT_IW,
2447 vga_r(cinfo->regbase, VGA_ATT_R));
2449 /* turn on video bit */
2450 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2451 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2453 /* dummy write on Reg0 to be on "write index" mode next time */
2454 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2457 /*** WHDR() - write into the Hidden DAC register ***/
2458 /* as the HDR is the only extension register that requires special treatment
2459 * (the other extension registers are accessible just like the "ordinary"
2460 * registers of their functional group) here is a specialized routine for
2463 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2465 unsigned char dummy;
2467 if (is_laguna(cinfo))
2469 if (cinfo->btype == BT_PICASSO) {
2470 /* Klaus' hint for correct access to HDR on some boards */
2471 /* first write 0 to pixel mask (3c6) */
2472 WGen(cinfo, VGA_PEL_MSK, 0x00);
2474 /* next read dummy from pixel address (3c8) */
2475 dummy = RGen(cinfo, VGA_PEL_IW);
2478 /* now do the usual stuff to access the HDR */
2480 dummy = RGen(cinfo, VGA_PEL_MSK);
2482 dummy = RGen(cinfo, VGA_PEL_MSK);
2484 dummy = RGen(cinfo, VGA_PEL_MSK);
2486 dummy = RGen(cinfo, VGA_PEL_MSK);
2489 WGen(cinfo, VGA_PEL_MSK, val);
2492 if (cinfo->btype == BT_PICASSO) {
2493 /* now first reset HDR access counter */
2494 dummy = RGen(cinfo, VGA_PEL_IW);
2497 /* and at the end, restore the mask value */
2498 /* ## is this mask always 0xff? */
2499 WGen(cinfo, VGA_PEL_MSK, 0xff);
2504 /*** WSFR() - write to the "special function register" (SFR) ***/
2505 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2508 assert(cinfo->regbase != NULL);
2510 z_writeb(val, cinfo->regbase + 0x8000);
2514 /* The Picasso has a second register for switching the monitor bit */
2515 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2518 /* writing an arbitrary value to this one causes the monitor switcher */
2519 /* to flip to Amiga display */
2520 assert(cinfo->regbase != NULL);
2522 z_writeb(val, cinfo->regbase + 0x9000);
2526 /*** WClut - set CLUT entry (range: 0..63) ***/
2527 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2528 unsigned char green, unsigned char blue)
2530 unsigned int data = VGA_PEL_D;
2532 /* address write mode register is not translated.. */
2533 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2535 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2536 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
2537 cinfo->btype == BT_SD64 || is_laguna(cinfo)) {
2538 /* but DAC data register IS, at least for Picasso II */
2539 if (cinfo->btype == BT_PICASSO)
2541 vga_w(cinfo->regbase, data, red);
2542 vga_w(cinfo->regbase, data, green);
2543 vga_w(cinfo->regbase, data, blue);
2545 vga_w(cinfo->regbase, data, blue);
2546 vga_w(cinfo->regbase, data, green);
2547 vga_w(cinfo->regbase, data, red);
2552 /*** RClut - read CLUT entry (range 0..63) ***/
2553 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2554 unsigned char *green, unsigned char *blue)
2556 unsigned int data = VGA_PEL_D;
2558 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2560 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2561 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2562 if (cinfo->btype == BT_PICASSO)
2564 *red = vga_r(cinfo->regbase, data);
2565 *green = vga_r(cinfo->regbase, data);
2566 *blue = vga_r(cinfo->regbase, data);
2568 *blue = vga_r(cinfo->regbase, data);
2569 *green = vga_r(cinfo->regbase, data);
2570 *red = vga_r(cinfo->regbase, data);
2575 /*******************************************************************
2578 Wait for the BitBLT engine to complete a possible earlier job
2579 *********************************************************************/
2581 /* FIXME: use interrupts instead */
2582 static void cirrusfb_WaitBLT(u8 __iomem *regbase)
2584 while (vga_rgfx(regbase, CL_GR31) & 0x08)
2588 /*******************************************************************
2591 perform accelerated "scrolling"
2592 ********************************************************************/
2594 static void cirrusfb_set_blitter(u8 __iomem *regbase,
2595 u_short nwidth, u_short nheight,
2596 u_long nsrc, u_long ndest,
2597 u_short bltmode, u_short line_length)
2600 /* pitch: set to line_length */
2601 /* dest pitch low */
2602 vga_wgfx(regbase, CL_GR24, line_length & 0xff);
2604 vga_wgfx(regbase, CL_GR25, line_length >> 8);
2605 /* source pitch low */
2606 vga_wgfx(regbase, CL_GR26, line_length & 0xff);
2607 /* source pitch hi */
2608 vga_wgfx(regbase, CL_GR27, line_length >> 8);
2610 /* BLT width: actual number of pixels - 1 */
2612 vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
2614 vga_wgfx(regbase, CL_GR21, nwidth >> 8);
2616 /* BLT height: actual number of lines -1 */
2617 /* BLT height low */
2618 vga_wgfx(regbase, CL_GR22, nheight & 0xff);
2620 vga_wgfx(regbase, CL_GR23, nheight >> 8);
2622 /* BLT destination */
2624 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2626 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
2628 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2632 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
2634 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
2636 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
2639 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
2641 /* BLT ROP: SrcCopy */
2642 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2644 /* and finally: GO! */
2645 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
2648 /*******************************************************************
2651 perform accelerated "scrolling"
2652 ********************************************************************/
2654 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
2655 u_short curx, u_short cury,
2656 u_short destx, u_short desty,
2657 u_short width, u_short height,
2658 u_short line_length)
2660 u_short nwidth = width - 1;
2661 u_short nheight = height - 1;
2666 /* if source adr < dest addr, do the Blt backwards */
2667 if (cury <= desty) {
2668 if (cury == desty) {
2669 /* if src and dest are on the same line, check x */
2675 /* standard case: forward blitting */
2676 nsrc = (cury * line_length) + curx;
2677 ndest = (desty * line_length) + destx;
2679 /* this means start addresses are at the end,
2680 * counting backwards
2682 nsrc += nheight * line_length + nwidth;
2683 ndest += nheight * line_length + nwidth;
2686 cirrusfb_WaitBLT(regbase);
2688 cirrusfb_set_blitter(regbase, nwidth, nheight,
2689 nsrc, ndest, bltmode, line_length);
2692 /*******************************************************************
2695 perform accelerated rectangle fill
2696 ********************************************************************/
2698 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
2699 u_short x, u_short y, u_short width, u_short height,
2700 u32 fg_color, u32 bg_color, u_short line_length,
2703 u_long ndest = (y * line_length) + x;
2706 cirrusfb_WaitBLT(regbase);
2708 /* This is a ColorExpand Blt, using the */
2709 /* same color for foreground and background */
2710 vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color);
2711 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color);
2714 if (bits_per_pixel >= 16) {
2715 vga_wgfx(regbase, CL_GR10, bg_color >> 8);
2716 vga_wgfx(regbase, CL_GR11, fg_color >> 8);
2719 if (bits_per_pixel >= 24) {
2720 vga_wgfx(regbase, CL_GR12, bg_color >> 16);
2721 vga_wgfx(regbase, CL_GR13, fg_color >> 16);
2724 if (bits_per_pixel == 32) {
2725 vga_wgfx(regbase, CL_GR14, bg_color >> 24);
2726 vga_wgfx(regbase, CL_GR15, fg_color >> 24);
2729 cirrusfb_set_blitter(regbase, width - 1, height - 1,
2730 0, ndest, op | blitmode, line_length);
2733 /**************************************************************************
2734 * bestclock() - determine closest possible clock lower(?) than the
2735 * desired pixel clock
2736 **************************************************************************/
2737 static void bestclock(long freq, int *nom, int *den, int *div)
2742 assert(nom != NULL);
2743 assert(den != NULL);
2744 assert(div != NULL);
2755 for (n = 32; n < 128; n++) {
2758 d = (14318 * n) / freq;
2759 if ((d >= 7) && (d <= 63)) {
2766 h = ((14318 * n) / temp) >> s;
2767 h = h > freq ? h - freq : freq - h;
2776 if ((d >= 7) && (d <= 63)) {
2781 h = ((14318 * n) / d) >> s;
2782 h = h > freq ? h - freq : freq - h;
2793 /* -------------------------------------------------------------------------
2795 * debugging functions
2797 * -------------------------------------------------------------------------
2800 #ifdef CIRRUSFB_DEBUG
2803 * cirrusfb_dbg_print_regs
2804 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2805 * @reg_class: type of registers to read: %CRT, or %SEQ
2808 * Dumps the given list of VGA CRTC registers. If @base is %NULL,
2809 * old-style I/O ports are queried for information, otherwise MMIO is
2810 * used at the given @base address to query the information.
2813 static void cirrusfb_dbg_print_regs(struct fb_info *info,
2815 enum cirrusfb_dbg_reg_class reg_class, ...)
2818 unsigned char val = 0;
2822 va_start(list, reg_class);
2824 name = va_arg(list, char *);
2825 while (name != NULL) {
2826 reg = va_arg(list, int);
2828 switch (reg_class) {
2830 val = vga_rcrt(regbase, (unsigned char) reg);
2833 val = vga_rseq(regbase, (unsigned char) reg);
2836 /* should never occur */
2841 dev_dbg(info->device, "%8s = 0x%02X\n", name, val);
2843 name = va_arg(list, char *);
2850 * cirrusfb_dbg_reg_dump
2851 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2854 * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
2855 * old-style I/O ports are queried for information, otherwise MMIO is
2856 * used at the given @base address to query the information.
2859 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase)
2861 dev_dbg(info->device, "VGA CRTC register dump:\n");
2863 cirrusfb_dbg_print_regs(info, regbase, CRT,
2913 dev_dbg(info->device, "\n");
2915 dev_dbg(info->device, "VGA SEQ register dump:\n");
2917 cirrusfb_dbg_print_regs(info, regbase, SEQ,
2946 dev_dbg(info->device, "\n");
2949 #endif /* CIRRUSFB_DEBUG */