1 // SPDX-License-Identifier: GPL-2.0-only
2 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
3 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
5 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
6 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
8 * Ani Joshi / Jeff Garzik
11 * Michel Danzer <michdaen@iiic.ethz.ch>
15 * Benjamin Herrenschmidt
16 * - pmac-specific PM stuff
17 * - various fixes & cleanups
19 * Andreas Hundt <andi@convergence.de>
22 * Paul Mackerras <paulus@samba.org>
23 * - Convert to new framebuffer API,
24 * fix colormap setting at 16 bits/pixel (565)
29 * Jon Smirl <jonsmirl@yahoo.com>
31 * - replace ROM BIOS search
33 * Based off of Geert's atyfb.c and vfb.c.
36 * - monitor sensing (DDC)
38 * - other platform support (only ppc/x86 supported)
39 * - hardware cursor support
41 * Please cc: your patches to brad@neruo.com.
45 * A special note of gratitude to ATI's devrel for providing documentation,
46 * example code and hardware. Thanks Nitya. -atong and brad
50 #include <linux/module.h>
51 #include <linux/moduleparam.h>
52 #include <linux/kernel.h>
53 #include <linux/errno.h>
54 #include <linux/string.h>
56 #include <linux/vmalloc.h>
57 #include <linux/delay.h>
58 #include <linux/interrupt.h>
59 #include <linux/uaccess.h>
61 #include <linux/init.h>
62 #include <linux/pci.h>
63 #include <linux/ioport.h>
64 #include <linux/console.h>
65 #include <linux/backlight.h>
68 #ifdef CONFIG_PPC_PMAC
69 #include <asm/machdep.h>
70 #include <asm/pmac_feature.h>
71 #include "../macmodes.h"
74 #ifdef CONFIG_PMAC_BACKLIGHT
75 #include <asm/backlight.h>
78 #ifdef CONFIG_BOOTX_TEXT
79 #include <asm/btext.h>
80 #endif /* CONFIG_BOOTX_TEXT */
82 #include <video/aty128.h>
88 #define DBG(fmt, args...) \
89 printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args);
91 #define DBG(fmt, args...)
94 #ifndef CONFIG_PPC_PMAC
96 static const struct fb_var_screeninfo default_var = {
97 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
98 640, 480, 640, 480, 0, 0, 8, 0,
99 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
100 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
101 0, FB_VMODE_NONINTERLACED
104 #else /* CONFIG_PPC_PMAC */
105 /* default to 1024x768 at 75Hz on PPC - this will work
106 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
107 static const struct fb_var_screeninfo default_var = {
108 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
109 1024, 768, 1024, 768, 0, 0, 8, 0,
110 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
111 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
112 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
113 FB_VMODE_NONINTERLACED
115 #endif /* CONFIG_PPC_PMAC */
117 /* default modedb mode */
118 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
119 static const struct fb_videomode defaultmode = {
131 .vmode = FB_VMODE_NONINTERLACED
134 /* Chip generations */
146 /* Must match above enum */
147 static char * const r128_family[] = {
159 * PCI driver prototypes
161 static int aty128_probe(struct pci_dev *pdev,
162 const struct pci_device_id *ent);
163 static void aty128_remove(struct pci_dev *pdev);
164 static int aty128_pci_suspend_late(struct device *dev, pm_message_t state);
165 static int __maybe_unused aty128_pci_suspend(struct device *dev);
166 static int __maybe_unused aty128_pci_hibernate(struct device *dev);
167 static int __maybe_unused aty128_pci_freeze(struct device *dev);
168 static int __maybe_unused aty128_pci_resume(struct device *dev);
169 static int aty128_do_resume(struct pci_dev *pdev);
171 static const struct dev_pm_ops aty128_pci_pm_ops = {
172 .suspend = aty128_pci_suspend,
173 .resume = aty128_pci_resume,
174 .freeze = aty128_pci_freeze,
175 .thaw = aty128_pci_resume,
176 .poweroff = aty128_pci_hibernate,
177 .restore = aty128_pci_resume,
180 /* supported Rage128 chipsets */
181 static const struct pci_device_id aty128_pci_tbl[] = {
182 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
184 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
186 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
188 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
190 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
192 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
194 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
196 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
198 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
200 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
202 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
204 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
206 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
208 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
210 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
212 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
214 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
216 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
218 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
220 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
222 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
224 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
226 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
228 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
230 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
232 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
234 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
236 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
238 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
240 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
242 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
244 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
246 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
247 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
248 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
250 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
252 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
253 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
254 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
256 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
258 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
260 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
262 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
264 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
265 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
266 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
268 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
270 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
271 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
272 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
273 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
274 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
275 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
279 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
281 static struct pci_driver aty128fb_driver = {
283 .id_table = aty128_pci_tbl,
284 .probe = aty128_probe,
285 .remove = aty128_remove,
286 .driver.pm = &aty128_pci_pm_ops,
289 /* packed BIOS settings */
294 u8 accelerator_entry;
296 u16 VGA_table_offset;
297 u16 POST_table_offset;
303 u16 PCLK_ref_divider;
307 u16 MCLK_ref_divider;
311 u16 XCLK_ref_divider;
314 } __attribute__ ((packed)) PLL_BLOCK;
315 #endif /* !CONFIG_PPC */
317 /* onboard memory information */
318 struct aty128_meminfo {
332 /* various memory configurations */
333 static const struct aty128_meminfo sdr_128 = {
344 .name = "128-bit SDR SGRAM (1:1)",
347 static const struct aty128_meminfo sdr_sgram = {
358 .name = "64-bit SDR SGRAM (2:1)",
361 static const struct aty128_meminfo ddr_sgram = {
372 .name = "64-bit DDR SGRAM",
375 static const struct fb_fix_screeninfo aty128fb_fix = {
377 .type = FB_TYPE_PACKED_PIXELS,
378 .visual = FB_VISUAL_PSEUDOCOLOR,
382 .accel = FB_ACCEL_ATI_RAGE128,
385 static char *mode_option = NULL;
387 #ifdef CONFIG_PPC_PMAC
388 static int default_vmode = VMODE_1024_768_60;
389 static int default_cmode = CMODE_8;
392 static int default_crt_on = 0;
393 static int default_lcd_on = 1;
394 static bool mtrr = true;
396 #ifdef CONFIG_FB_ATY128_BACKLIGHT
397 static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
401 struct aty128_constants {
413 u32 h_total, h_sync_strt_wid;
414 u32 v_total, v_sync_strt_wid;
416 u32 offset, offset_cntl;
417 u32 xoffset, yoffset;
424 u32 feedback_divider;
428 struct aty128_ddafifo {
433 /* register values for a specific mode */
434 struct aty128fb_par {
435 struct aty128_crtc crtc;
436 struct aty128_pll pll;
437 struct aty128_ddafifo fifo_reg;
439 struct aty128_constants constants; /* PLL and others */
440 void __iomem *regbase; /* remapped mmio */
441 u32 vram_size; /* onboard video ram */
443 const struct aty128_meminfo *mem; /* onboard mem info */
445 int blitter_may_be_busy;
446 int fifo_slots; /* free slots in FIFO (64 max) */
449 struct pci_dev *pdev;
450 struct fb_info *next;
454 u8 red[32]; /* see aty128fb_setcolreg */
457 u32 pseudo_palette[16]; /* used for TRUECOLOR */
461 #define round_div(n, d) ((n+(d/2))/d)
463 static int aty128fb_check_var(struct fb_var_screeninfo *var,
464 struct fb_info *info);
465 static int aty128fb_set_par(struct fb_info *info);
466 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
467 u_int transp, struct fb_info *info);
468 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
470 static int aty128fb_blank(int blank, struct fb_info *fb);
471 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg);
472 static int aty128fb_sync(struct fb_info *info);
478 static int aty128_encode_var(struct fb_var_screeninfo *var,
479 const struct aty128fb_par *par);
480 static int aty128_decode_var(struct fb_var_screeninfo *var,
481 struct aty128fb_par *par);
482 static void aty128_timings(struct aty128fb_par *par);
483 static void aty128_init_engine(struct aty128fb_par *par);
484 static void aty128_reset_engine(const struct aty128fb_par *par);
485 static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
486 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
487 static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
488 static void wait_for_idle(struct aty128fb_par *par);
489 static u32 depth_to_dst(u32 depth);
491 #ifdef CONFIG_FB_ATY128_BACKLIGHT
492 static void aty128_bl_set_power(struct fb_info *info, int power);
495 #define BIOS_IN8(v) (readb(bios + (v)))
496 #define BIOS_IN16(v) (readb(bios + (v)) | \
497 (readb(bios + (v) + 1) << 8))
498 #define BIOS_IN32(v) (readb(bios + (v)) | \
499 (readb(bios + (v) + 1) << 8) | \
500 (readb(bios + (v) + 2) << 16) | \
501 (readb(bios + (v) + 3) << 24))
504 static const struct fb_ops aty128fb_ops = {
505 .owner = THIS_MODULE,
506 .fb_check_var = aty128fb_check_var,
507 .fb_set_par = aty128fb_set_par,
508 .fb_setcolreg = aty128fb_setcolreg,
509 .fb_pan_display = aty128fb_pan_display,
510 .fb_blank = aty128fb_blank,
511 .fb_ioctl = aty128fb_ioctl,
512 .fb_sync = aty128fb_sync,
513 .fb_fillrect = cfb_fillrect,
514 .fb_copyarea = cfb_copyarea,
515 .fb_imageblit = cfb_imageblit,
519 * Functions to read from/write to the mmio registers
520 * - endian conversions may possibly be avoided by
521 * using the other register aperture. TODO.
523 static inline u32 _aty_ld_le32(volatile unsigned int regindex,
524 const struct aty128fb_par *par)
526 return readl (par->regbase + regindex);
529 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val,
530 const struct aty128fb_par *par)
532 writel (val, par->regbase + regindex);
535 static inline u8 _aty_ld_8(unsigned int regindex,
536 const struct aty128fb_par *par)
538 return readb (par->regbase + regindex);
541 static inline void _aty_st_8(unsigned int regindex, u8 val,
542 const struct aty128fb_par *par)
544 writeb (val, par->regbase + regindex);
547 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
548 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
549 #define aty_ld_8(regindex) _aty_ld_8(regindex, par)
550 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
553 * Functions to read from/write to the pll registers
556 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
557 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
560 static u32 _aty_ld_pll(unsigned int pll_index,
561 const struct aty128fb_par *par)
563 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
564 return aty_ld_le32(CLOCK_CNTL_DATA);
568 static void _aty_st_pll(unsigned int pll_index, u32 val,
569 const struct aty128fb_par *par)
571 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
572 aty_st_le32(CLOCK_CNTL_DATA, val);
576 /* return true when the PLL has completed an atomic update */
577 static int aty_pll_readupdate(const struct aty128fb_par *par)
579 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
583 static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
585 unsigned long timeout = jiffies + HZ/100; // should be more than enough
588 while (time_before(jiffies, timeout))
589 if (aty_pll_readupdate(par)) {
594 if (reset) /* reset engine?? */
595 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
599 /* tell PLL to update */
600 static void aty_pll_writeupdate(const struct aty128fb_par *par)
602 aty_pll_wait_readupdate(par);
604 aty_st_pll(PPLL_REF_DIV,
605 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
609 /* write to the scratch register to test r/w functionality */
610 static int register_test(const struct aty128fb_par *par)
615 val = aty_ld_le32(BIOS_0_SCRATCH);
617 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
618 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
619 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
621 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
625 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
631 * Accelerator engine functions
633 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
638 for (i = 0; i < 2000000; i++) {
639 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
640 if (par->fifo_slots >= entries)
643 aty128_reset_engine(par);
648 static void wait_for_idle(struct aty128fb_par *par)
652 do_wait_for_fifo(64, par);
655 for (i = 0; i < 2000000; i++) {
656 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
657 aty128_flush_pixel_cache(par);
658 par->blitter_may_be_busy = 0;
662 aty128_reset_engine(par);
667 static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
669 if (par->fifo_slots < entries)
670 do_wait_for_fifo(64, par);
671 par->fifo_slots -= entries;
675 static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
680 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
683 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
685 for (i = 0; i < 2000000; i++)
686 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
691 static void aty128_reset_engine(const struct aty128fb_par *par)
693 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
695 aty128_flush_pixel_cache(par);
697 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
698 mclk_cntl = aty_ld_pll(MCLK_CNTL);
700 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
702 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
703 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
704 aty_ld_le32(GEN_RESET_CNTL);
705 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
706 aty_ld_le32(GEN_RESET_CNTL);
708 aty_st_pll(MCLK_CNTL, mclk_cntl);
709 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
710 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
712 /* use old pio mode */
713 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
719 static void aty128_init_engine(struct aty128fb_par *par)
725 /* 3D scaler not spoken here */
726 wait_for_fifo(1, par);
727 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
729 aty128_reset_engine(par);
731 pitch_value = par->crtc.pitch;
732 if (par->crtc.bpp == 24) {
733 pitch_value = pitch_value * 3;
736 wait_for_fifo(4, par);
737 /* setup engine offset registers */
738 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
740 /* setup engine pitch registers */
741 aty_st_le32(DEFAULT_PITCH, pitch_value);
743 /* set the default scissor register to max dimensions */
744 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
746 /* set the drawing controls registers */
747 aty_st_le32(DP_GUI_MASTER_CNTL,
748 GMC_SRC_PITCH_OFFSET_DEFAULT |
749 GMC_DST_PITCH_OFFSET_DEFAULT |
750 GMC_SRC_CLIP_DEFAULT |
751 GMC_DST_CLIP_DEFAULT |
752 GMC_BRUSH_SOLIDCOLOR |
753 (depth_to_dst(par->crtc.depth) << 8) |
755 GMC_BYTE_ORDER_MSB_TO_LSB |
756 GMC_DP_CONVERSION_TEMP_6500 |
760 GMC_DST_CLR_CMP_FCN_CLEAR |
764 wait_for_fifo(8, par);
765 /* clear the line drawing registers */
766 aty_st_le32(DST_BRES_ERR, 0);
767 aty_st_le32(DST_BRES_INC, 0);
768 aty_st_le32(DST_BRES_DEC, 0);
770 /* set brush color registers */
771 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
772 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
774 /* set source color registers */
775 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
776 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
778 /* default write mask */
779 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
781 /* Wait for all the writes to be completed before returning */
786 /* convert depth values to their register representation */
787 static u32 depth_to_dst(u32 depth)
791 else if (depth <= 15)
793 else if (depth == 16)
795 else if (depth <= 24)
797 else if (depth <= 32)
804 * PLL informations retreival
809 static void __iomem *aty128_map_ROM(const struct aty128fb_par *par,
817 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
819 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
822 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
823 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
825 bios = pci_map_rom(dev, &rom_size);
828 printk(KERN_ERR "aty128fb: ROM failed to map\n");
832 /* Very simple test to make sure it appeared */
833 if (BIOS_IN16(0) != 0xaa55) {
834 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should "
835 " be 0xaa55\n", BIOS_IN16(0));
839 /* Look for the PCI data to check the ROM type */
840 dptr = BIOS_IN16(0x18);
842 /* Check the PCI data signature. If it's wrong, we still assume a normal
843 * x86 ROM for now, until I've verified this works everywhere.
844 * The goal here is more to phase out Open Firmware images.
846 * Currently, we only look at the first PCI data, we could iteratre and
847 * deal with them all, and we should use fb_bios_start relative to start
848 * of image and not relative start of ROM, but so far, I never found a
849 * dual-image ATI card.
852 * u32 signature; + 0x00
855 * u16 reserved_1; + 0x08
857 * u8 drevision; + 0x0c
858 * u8 class_hi; + 0x0d
859 * u16 class_lo; + 0x0e
861 * u16 irevision; + 0x12
863 * u8 indicator; + 0x15
864 * u16 reserved_2; + 0x16
867 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
868 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
872 rom_type = BIOS_IN8(dptr + 0x14);
875 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
878 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
881 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
884 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n",
892 pci_unmap_rom(dev, bios);
896 static void aty128_get_pllinfo(struct aty128fb_par *par,
897 unsigned char __iomem *bios)
899 unsigned int bios_hdr;
900 unsigned int bios_pll;
902 bios_hdr = BIOS_IN16(0x48);
903 bios_pll = BIOS_IN16(bios_hdr + 0x30);
905 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
906 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
907 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
908 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
909 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
911 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
912 par->constants.ppll_max, par->constants.ppll_min,
913 par->constants.xclk, par->constants.ref_divider,
914 par->constants.ref_clk);
919 static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par)
921 /* I simplified this code as we used to miss the signatures in
922 * a lot of case. It's now closer to XFree, we just don't check
923 * for signatures at all... Something better will have to be done
924 * if we end up having conflicts
927 unsigned char __iomem *rom_base = NULL;
929 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
930 rom_base = ioremap(segstart, 0x10000);
931 if (rom_base == NULL)
933 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
941 #endif /* ndef(__sparc__) */
943 /* fill in known card constants if pll_block is not available */
944 static void aty128_timings(struct aty128fb_par *par)
947 /* instead of a table lookup, assume OF has properly
948 * setup the PLL registers and use their values
949 * to set the XCLK values and reference divider values */
951 u32 x_mpll_ref_fb_div;
954 static const unsigned int PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
957 if (!par->constants.ref_clk)
958 par->constants.ref_clk = 2950;
961 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
962 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
963 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
964 M = x_mpll_ref_fb_div & 0x0000ff;
966 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
967 (M * PostDivSet[xclk_cntl]));
969 par->constants.ref_divider =
970 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
973 if (!par->constants.ref_divider) {
974 par->constants.ref_divider = 0x3b;
976 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
977 aty_pll_writeupdate(par);
979 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
980 aty_pll_writeupdate(par);
982 /* from documentation */
983 if (!par->constants.ppll_min)
984 par->constants.ppll_min = 12500;
985 if (!par->constants.ppll_max)
986 par->constants.ppll_max = 25000; /* 23000 on some cards? */
987 if (!par->constants.xclk)
988 par->constants.xclk = 0x1d4d; /* same as mclk */
990 par->constants.fifo_width = 128;
991 par->constants.fifo_depth = 32;
993 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
998 par->mem = &sdr_sgram;
1001 par->mem = &ddr_sgram;
1004 par->mem = &sdr_sgram;
1014 /* Program the CRTC registers */
1015 static void aty128_set_crtc(const struct aty128_crtc *crtc,
1016 const struct aty128fb_par *par)
1018 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
1019 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
1020 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
1021 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
1022 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
1023 aty_st_le32(CRTC_PITCH, crtc->pitch);
1024 aty_st_le32(CRTC_OFFSET, crtc->offset);
1025 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
1026 /* Disable ATOMIC updating. Is this the right place? */
1027 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
1031 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1032 struct aty128_crtc *crtc,
1033 const struct aty128fb_par *par)
1035 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1036 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1037 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1038 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1040 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1045 vxres = var->xres_virtual;
1046 vyres = var->yres_virtual;
1047 xoffset = var->xoffset;
1048 yoffset = var->yoffset;
1049 bpp = var->bits_per_pixel;
1050 left = var->left_margin;
1051 right = var->right_margin;
1052 upper = var->upper_margin;
1053 lower = var->lower_margin;
1054 hslen = var->hsync_len;
1055 vslen = var->vsync_len;
1062 depth = (var->green.length == 6) ? 16 : 15;
1064 /* check for mode eligibility
1065 * accept only non interlaced modes */
1066 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1069 /* convert (and round up) and validate */
1070 xres = (xres + 7) & ~7;
1071 xoffset = (xoffset + 7) & ~7;
1073 if (vxres < xres + xoffset)
1074 vxres = xres + xoffset;
1076 if (vyres < yres + yoffset)
1077 vyres = yres + yoffset;
1079 /* convert depth into ATI register depth */
1080 dst = depth_to_dst(depth);
1082 if (dst == -EINVAL) {
1083 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1087 /* convert register depth to bytes per pixel */
1088 bytpp = mode_bytpp[dst];
1090 /* make sure there is enough video ram for the mode */
1091 if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1092 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1096 h_disp = (xres >> 3) - 1;
1097 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1100 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1102 /* check to make sure h_total and v_total are in range */
1103 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1104 printk(KERN_ERR "aty128fb: invalid width ranges\n");
1108 h_sync_wid = (hslen + 7) >> 3;
1109 if (h_sync_wid == 0)
1111 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
1114 h_sync_strt = (h_disp << 3) + right;
1117 if (v_sync_wid == 0)
1119 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
1122 v_sync_strt = v_disp + lower;
1124 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1125 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1127 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1129 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1131 crtc->h_total = h_total | (h_disp << 16);
1132 crtc->v_total = v_total | (v_disp << 16);
1134 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1136 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1139 crtc->pitch = vxres >> 3;
1143 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1144 crtc->offset_cntl = 0x00010000;
1146 crtc->offset_cntl = 0;
1148 crtc->vxres = vxres;
1149 crtc->vyres = vyres;
1150 crtc->xoffset = xoffset;
1151 crtc->yoffset = yoffset;
1152 crtc->depth = depth;
1159 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1162 /* fill in pixel info */
1163 var->red.msb_right = 0;
1164 var->green.msb_right = 0;
1165 var->blue.offset = 0;
1166 var->blue.msb_right = 0;
1167 var->transp.offset = 0;
1168 var->transp.length = 0;
1169 var->transp.msb_right = 0;
1170 switch (pix_width) {
1171 case CRTC_PIX_WIDTH_8BPP:
1172 var->bits_per_pixel = 8;
1173 var->red.offset = 0;
1174 var->red.length = 8;
1175 var->green.offset = 0;
1176 var->green.length = 8;
1177 var->blue.length = 8;
1179 case CRTC_PIX_WIDTH_15BPP:
1180 var->bits_per_pixel = 16;
1181 var->red.offset = 10;
1182 var->red.length = 5;
1183 var->green.offset = 5;
1184 var->green.length = 5;
1185 var->blue.length = 5;
1187 case CRTC_PIX_WIDTH_16BPP:
1188 var->bits_per_pixel = 16;
1189 var->red.offset = 11;
1190 var->red.length = 5;
1191 var->green.offset = 5;
1192 var->green.length = 6;
1193 var->blue.length = 5;
1195 case CRTC_PIX_WIDTH_24BPP:
1196 var->bits_per_pixel = 24;
1197 var->red.offset = 16;
1198 var->red.length = 8;
1199 var->green.offset = 8;
1200 var->green.length = 8;
1201 var->blue.length = 8;
1203 case CRTC_PIX_WIDTH_32BPP:
1204 var->bits_per_pixel = 32;
1205 var->red.offset = 16;
1206 var->red.length = 8;
1207 var->green.offset = 8;
1208 var->green.length = 8;
1209 var->blue.length = 8;
1210 var->transp.offset = 24;
1211 var->transp.length = 8;
1214 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1222 static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1223 struct fb_var_screeninfo *var)
1225 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1226 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1227 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1230 /* fun with masking */
1231 h_total = crtc->h_total & 0x1ff;
1232 h_disp = (crtc->h_total >> 16) & 0xff;
1233 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1234 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1235 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1236 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1237 v_total = crtc->v_total & 0x7ff;
1238 v_disp = (crtc->v_total >> 16) & 0x7ff;
1239 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1240 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1241 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1242 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1243 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1245 /* do conversions */
1246 xres = (h_disp + 1) << 3;
1248 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1249 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1250 hslen = h_sync_wid << 3;
1251 upper = v_total - v_sync_strt - v_sync_wid;
1252 lower = v_sync_strt - v_disp;
1254 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1255 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1256 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1258 aty128_pix_width_to_var(pix_width, var);
1262 var->xres_virtual = crtc->vxres;
1263 var->yres_virtual = crtc->vyres;
1264 var->xoffset = crtc->xoffset;
1265 var->yoffset = crtc->yoffset;
1266 var->left_margin = left;
1267 var->right_margin = right;
1268 var->upper_margin = upper;
1269 var->lower_margin = lower;
1270 var->hsync_len = hslen;
1271 var->vsync_len = vslen;
1273 var->vmode = FB_VMODE_NONINTERLACED;
1278 static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1281 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) |
1283 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) |
1284 DAC_PALETTE2_SNOOP_EN));
1286 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) &
1290 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1293 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1294 struct fb_info *info = pci_get_drvdata(par->pdev);
1298 reg = aty_ld_le32(LVDS_GEN_CNTL);
1299 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1300 reg &= ~LVDS_DISPLAY_DIS;
1301 aty_st_le32(LVDS_GEN_CNTL, reg);
1302 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1303 aty128_bl_set_power(info, FB_BLANK_UNBLANK);
1306 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1307 aty128_bl_set_power(info, FB_BLANK_POWERDOWN);
1309 reg = aty_ld_le32(LVDS_GEN_CNTL);
1310 reg |= LVDS_DISPLAY_DIS;
1311 aty_st_le32(LVDS_GEN_CNTL, reg);
1313 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1314 aty_st_le32(LVDS_GEN_CNTL, reg);
1318 static void aty128_set_pll(struct aty128_pll *pll,
1319 const struct aty128fb_par *par)
1323 /* register values for post dividers */
1324 static const unsigned char post_conv[] = {
1325 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7
1328 /* select PPLL_DIV_3 */
1329 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1332 aty_st_pll(PPLL_CNTL,
1333 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1335 /* write the reference divider */
1336 aty_pll_wait_readupdate(par);
1337 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1338 aty_pll_writeupdate(par);
1340 div3 = aty_ld_pll(PPLL_DIV_3);
1341 div3 &= ~PPLL_FB3_DIV_MASK;
1342 div3 |= pll->feedback_divider;
1343 div3 &= ~PPLL_POST3_DIV_MASK;
1344 div3 |= post_conv[pll->post_divider] << 16;
1346 /* write feedback and post dividers */
1347 aty_pll_wait_readupdate(par);
1348 aty_st_pll(PPLL_DIV_3, div3);
1349 aty_pll_writeupdate(par);
1351 aty_pll_wait_readupdate(par);
1352 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1353 aty_pll_writeupdate(par);
1355 /* clear the reset, just in case */
1356 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1360 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1361 const struct aty128fb_par *par)
1363 const struct aty128_constants c = par->constants;
1364 static const unsigned char post_dividers[] = { 1, 2, 4, 8, 3, 6, 12 };
1366 u32 vclk; /* in .01 MHz */
1370 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1372 /* adjust pixel clock if necessary */
1373 if (vclk > c.ppll_max)
1375 if (vclk * 12 < c.ppll_min)
1376 vclk = c.ppll_min/12;
1378 /* now, find an acceptable divider */
1379 for (i = 0; i < ARRAY_SIZE(post_dividers); i++) {
1380 output_freq = post_dividers[i] * vclk;
1381 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) {
1382 pll->post_divider = post_dividers[i];
1387 if (i == ARRAY_SIZE(post_dividers))
1390 /* calculate feedback divider */
1391 n = c.ref_divider * output_freq;
1394 pll->feedback_divider = round_div(n, d);
1397 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1398 "vclk_per: %d\n", pll->post_divider,
1399 pll->feedback_divider, vclk, output_freq,
1400 c.ref_divider, period_in_ps);
1406 static int aty128_pll_to_var(const struct aty128_pll *pll,
1407 struct fb_var_screeninfo *var)
1409 var->pixclock = 100000000 / pll->vclk;
1415 static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1416 const struct aty128fb_par *par)
1418 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1419 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1423 static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1424 const struct aty128_pll *pll,
1426 const struct aty128fb_par *par)
1428 const struct aty128_meminfo *m = par->mem;
1429 u32 xclk = par->constants.xclk;
1430 u32 fifo_width = par->constants.fifo_width;
1431 u32 fifo_depth = par->constants.fifo_depth;
1432 s32 x, b, p, ron, roff;
1435 /* round up to multiple of 8 */
1436 bpp = (depth+7) & ~7;
1438 n = xclk * fifo_width;
1439 d = pll->vclk * bpp;
1440 x = round_div(n, d);
1443 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1462 x = round_div(n, d);
1463 roff = x * (fifo_depth - 4);
1465 if ((ron + m->Rloop) >= roff) {
1466 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1470 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1471 p, m->Rloop, x, ron, roff);
1473 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1474 dsp->dda_on_off = ron << 16 | roff;
1481 * This actually sets the video mode.
1483 static int aty128fb_set_par(struct fb_info *info)
1485 struct aty128fb_par *par = info->par;
1489 if ((err = aty128_decode_var(&info->var, par)) != 0)
1492 if (par->blitter_may_be_busy)
1495 /* clear all registers that may interfere with mode setting */
1496 aty_st_le32(OVR_CLR, 0);
1497 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1498 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1499 aty_st_le32(OV0_SCALE_CNTL, 0);
1500 aty_st_le32(MPP_TB_CONFIG, 0);
1501 aty_st_le32(MPP_GP_CONFIG, 0);
1502 aty_st_le32(SUBPIC_CNTL, 0);
1503 aty_st_le32(VIPH_CONTROL, 0);
1504 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1505 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1506 aty_st_le32(CAP0_TRIG_CNTL, 0);
1507 aty_st_le32(CAP1_TRIG_CNTL, 0);
1509 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1511 aty128_set_crtc(&par->crtc, par);
1512 aty128_set_pll(&par->pll, par);
1513 aty128_set_fifo(&par->fifo_reg, par);
1515 config = aty_ld_le32(CNFG_CNTL) & ~3;
1517 #if defined(__BIG_ENDIAN)
1518 if (par->crtc.bpp == 32)
1519 config |= 2; /* make aperture do 32 bit swapping */
1520 else if (par->crtc.bpp == 16)
1521 config |= 1; /* make aperture do 16 bit swapping */
1524 aty_st_le32(CNFG_CNTL, config);
1525 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1527 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1528 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1529 : FB_VISUAL_DIRECTCOLOR;
1531 if (par->chip_gen == rage_M3) {
1532 aty128_set_crt_enable(par, par->crt_on);
1533 aty128_set_lcd_enable(par, par->lcd_on);
1535 if (par->accel_flags & FB_ACCELF_TEXT)
1536 aty128_init_engine(par);
1538 #ifdef CONFIG_BOOTX_TEXT
1539 btext_update_display(info->fix.smem_start,
1540 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1541 ((par->crtc.v_total>>16) & 0x7ff)+1,
1543 par->crtc.vxres*par->crtc.bpp/8);
1544 #endif /* CONFIG_BOOTX_TEXT */
1550 * encode/decode the User Defined Part of the Display
1553 static int aty128_decode_var(struct fb_var_screeninfo *var,
1554 struct aty128fb_par *par)
1557 struct aty128_crtc crtc;
1558 struct aty128_pll pll;
1559 struct aty128_ddafifo fifo_reg;
1561 if ((err = aty128_var_to_crtc(var, &crtc, par)))
1564 if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1567 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1572 par->fifo_reg = fifo_reg;
1573 par->accel_flags = var->accel_flags;
1579 static int aty128_encode_var(struct fb_var_screeninfo *var,
1580 const struct aty128fb_par *par)
1584 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1587 if ((err = aty128_pll_to_var(&par->pll, var)))
1595 var->accel_flags = par->accel_flags;
1601 static int aty128fb_check_var(struct fb_var_screeninfo *var,
1602 struct fb_info *info)
1604 struct aty128fb_par par;
1607 par = *(struct aty128fb_par *)info->par;
1608 if ((err = aty128_decode_var(var, &par)) != 0)
1610 aty128_encode_var(var, &par);
1616 * Pan or Wrap the Display
1618 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
1621 struct aty128fb_par *par = fb->par;
1622 u32 xoffset, yoffset;
1626 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1627 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1629 xoffset = (var->xoffset +7) & ~7;
1630 yoffset = var->yoffset;
1632 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1635 par->crtc.xoffset = xoffset;
1636 par->crtc.yoffset = yoffset;
1638 offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3))
1641 if (par->crtc.bpp == 24)
1642 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1644 aty_st_le32(CRTC_OFFSET, offset);
1651 * Helper function to store a single palette register
1653 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1654 struct aty128fb_par *par)
1656 if (par->chip_gen == rage_M3) {
1657 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) &
1658 ~DAC_PALETTE_ACCESS_CNTL);
1661 aty_st_8(PALETTE_INDEX, regno);
1662 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1665 static int aty128fb_sync(struct fb_info *info)
1667 struct aty128fb_par *par = info->par;
1669 if (par->blitter_may_be_busy)
1675 static int aty128fb_setup(char *options)
1679 if (!options || !*options)
1682 while ((this_opt = strsep(&options, ",")) != NULL) {
1683 if (!strncmp(this_opt, "lcd:", 4)) {
1684 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1686 } else if (!strncmp(this_opt, "crt:", 4)) {
1687 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1689 } else if (!strncmp(this_opt, "backlight:", 10)) {
1690 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1691 backlight = simple_strtoul(this_opt+10, NULL, 0);
1695 if(!strncmp(this_opt, "nomtrr", 6)) {
1699 #ifdef CONFIG_PPC_PMAC
1700 /* vmode and cmode deprecated */
1701 if (!strncmp(this_opt, "vmode:", 6)) {
1702 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1703 if (vmode > 0 && vmode <= VMODE_MAX)
1704 default_vmode = vmode;
1706 } else if (!strncmp(this_opt, "cmode:", 6)) {
1707 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1711 default_cmode = CMODE_8;
1715 default_cmode = CMODE_16;
1719 default_cmode = CMODE_32;
1724 #endif /* CONFIG_PPC_PMAC */
1725 mode_option = this_opt;
1732 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1733 #define MAX_LEVEL 0xFF
1735 static int aty128_bl_get_level_brightness(struct aty128fb_par *par,
1738 struct fb_info *info = pci_get_drvdata(par->pdev);
1741 /* Get and convert the value */
1742 /* No locking of bl_curve since we read a single value */
1743 atylevel = MAX_LEVEL -
1744 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL);
1748 else if (atylevel > MAX_LEVEL)
1749 atylevel = MAX_LEVEL;
1754 /* We turn off the LCD completely instead of just dimming the backlight.
1755 * This provides greater power saving and the display is useless without
1758 #define BACKLIGHT_LVDS_OFF
1759 /* That one prevents proper CRT output with LCD off */
1760 #undef BACKLIGHT_DAC_OFF
1762 static int aty128_bl_update_status(struct backlight_device *bd)
1764 struct aty128fb_par *par = bl_get_data(bd);
1765 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1768 if (bd->props.power != FB_BLANK_UNBLANK ||
1769 bd->props.fb_blank != FB_BLANK_UNBLANK ||
1773 level = bd->props.brightness;
1775 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
1778 if (!(reg & LVDS_ON)) {
1780 aty_st_le32(LVDS_GEN_CNTL, reg);
1781 aty_ld_le32(LVDS_GEN_CNTL);
1784 aty_st_le32(LVDS_GEN_CNTL, reg);
1786 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1787 reg |= (aty128_bl_get_level_brightness(par, level) <<
1788 LVDS_BL_MOD_LEVEL_SHIFT);
1789 #ifdef BACKLIGHT_LVDS_OFF
1790 reg |= LVDS_ON | LVDS_EN;
1791 reg &= ~LVDS_DISPLAY_DIS;
1793 aty_st_le32(LVDS_GEN_CNTL, reg);
1794 #ifdef BACKLIGHT_DAC_OFF
1795 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1798 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1799 reg |= (aty128_bl_get_level_brightness(par, 0) <<
1800 LVDS_BL_MOD_LEVEL_SHIFT);
1801 #ifdef BACKLIGHT_LVDS_OFF
1802 reg |= LVDS_DISPLAY_DIS;
1803 aty_st_le32(LVDS_GEN_CNTL, reg);
1804 aty_ld_le32(LVDS_GEN_CNTL);
1806 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
1808 aty_st_le32(LVDS_GEN_CNTL, reg);
1809 #ifdef BACKLIGHT_DAC_OFF
1810 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1817 static const struct backlight_ops aty128_bl_data = {
1818 .update_status = aty128_bl_update_status,
1821 static void aty128_bl_set_power(struct fb_info *info, int power)
1824 info->bl_dev->props.power = power;
1825 backlight_update_status(info->bl_dev);
1829 static void aty128_bl_init(struct aty128fb_par *par)
1831 struct backlight_properties props;
1832 struct fb_info *info = pci_get_drvdata(par->pdev);
1833 struct backlight_device *bd;
1836 /* Could be extended to Rage128Pro LVDS output too */
1837 if (par->chip_gen != rage_M3)
1840 #ifdef CONFIG_PMAC_BACKLIGHT
1841 if (!pmac_has_backlight_type("ati"))
1845 snprintf(name, sizeof(name), "aty128bl%d", info->node);
1847 memset(&props, 0, sizeof(struct backlight_properties));
1848 props.type = BACKLIGHT_RAW;
1849 props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
1850 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data,
1853 info->bl_dev = NULL;
1854 printk(KERN_WARNING "aty128: Backlight registration failed\n");
1859 fb_bl_default_curve(info, 0,
1860 63 * FB_BACKLIGHT_MAX / MAX_LEVEL,
1861 219 * FB_BACKLIGHT_MAX / MAX_LEVEL);
1863 bd->props.brightness = bd->props.max_brightness;
1864 bd->props.power = FB_BLANK_UNBLANK;
1865 backlight_update_status(bd);
1867 printk("aty128: Backlight initialized (%s)\n", name);
1875 static void aty128_bl_exit(struct backlight_device *bd)
1877 backlight_device_unregister(bd);
1878 printk("aty128: Backlight unloaded\n");
1880 #endif /* CONFIG_FB_ATY128_BACKLIGHT */
1886 #ifdef CONFIG_PPC_PMAC__disabled
1887 static void aty128_early_resume(void *data)
1889 struct aty128fb_par *par = data;
1891 if (!console_trylock())
1893 pci_restore_state(par->pdev);
1894 aty128_do_resume(par->pdev);
1897 #endif /* CONFIG_PPC_PMAC */
1899 static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1901 struct fb_info *info = pci_get_drvdata(pdev);
1902 struct aty128fb_par *par = info->par;
1903 struct fb_var_screeninfo var;
1904 char video_card[50];
1908 /* Get the chip revision */
1909 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
1911 strcpy(video_card, "Rage128 XX ");
1912 video_card[8] = ent->device >> 8;
1913 video_card[9] = ent->device & 0xFF;
1915 /* range check to make sure */
1916 if (ent->driver_data < ARRAY_SIZE(r128_family))
1917 strlcat(video_card, r128_family[ent->driver_data],
1918 sizeof(video_card));
1920 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1922 if (par->vram_size % (1024 * 1024) == 0)
1923 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1925 printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1927 par->chip_gen = ent->driver_data;
1930 info->fbops = &aty128fb_ops;
1931 info->flags = FBINFO_FLAG_DEFAULT;
1933 par->lcd_on = default_lcd_on;
1934 par->crt_on = default_crt_on;
1937 #ifdef CONFIG_PPC_PMAC
1938 if (machine_is(powermac)) {
1939 /* Indicate sleep capability */
1940 if (par->chip_gen == rage_M3) {
1941 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
1942 #if 0 /* Disable the early video resume hack for now as it's causing problems,
1943 * among others we now rely on the PCI core restoring the config space
1944 * for us, which isn't the case with that hack, and that code path causes
1945 * various things to be called with interrupts off while they shouldn't.
1946 * I'm leaving the code in as it can be useful for debugging purposes
1948 pmac_set_early_video_resume(aty128_early_resume, par);
1952 /* Find default mode */
1954 if (!mac_find_mode(&var, info, mode_option, 8))
1957 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1958 default_vmode = VMODE_1024_768_60;
1960 /* iMacs need that resolution
1961 * PowerMac2,1 first r128 iMacs
1962 * PowerMac2,2 summer 2000 iMacs
1963 * PowerMac4,1 january 2001 iMacs "flower power"
1965 if (of_machine_is_compatible("PowerMac2,1") ||
1966 of_machine_is_compatible("PowerMac2,2") ||
1967 of_machine_is_compatible("PowerMac4,1"))
1968 default_vmode = VMODE_1024_768_75;
1971 if (of_machine_is_compatible("PowerBook2,2"))
1972 default_vmode = VMODE_800_600_60;
1974 /* PowerBook Firewire (Pismo), iBook Dual USB */
1975 if (of_machine_is_compatible("PowerBook3,1") ||
1976 of_machine_is_compatible("PowerBook4,1"))
1977 default_vmode = VMODE_1024_768_60;
1979 /* PowerBook Titanium */
1980 if (of_machine_is_compatible("PowerBook3,2"))
1981 default_vmode = VMODE_1152_768_60;
1983 if (default_cmode > 16)
1984 default_cmode = CMODE_32;
1985 else if (default_cmode > 8)
1986 default_cmode = CMODE_16;
1988 default_cmode = CMODE_8;
1990 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1994 #endif /* CONFIG_PPC_PMAC */
1997 if (fb_find_mode(&var, info, mode_option, NULL,
1998 0, &defaultmode, 8) == 0)
2002 var.accel_flags &= ~FB_ACCELF_TEXT;
2003 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
2005 if (aty128fb_check_var(&var, info)) {
2006 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
2010 /* setup the DAC the way we like it */
2011 dac = aty_ld_le32(DAC_CNTL);
2012 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
2014 if (par->chip_gen == rage_M3)
2015 dac |= DAC_PALETTE2_SNOOP_EN;
2016 aty_st_le32(DAC_CNTL, dac);
2018 /* turn off bus mastering, just in case */
2019 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
2022 fb_alloc_cmap(&info->cmap, 256, 0);
2024 var.activate = FB_ACTIVATE_NOW;
2026 aty128_init_engine(par);
2030 par->lock_blank = 0;
2032 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2034 aty128_bl_init(par);
2037 if (register_framebuffer(info) < 0)
2040 fb_info(info, "%s frame buffer device on %s\n",
2041 info->fix.id, video_card);
2043 return 1; /* success! */
2047 /* register a card ++ajoshi */
2048 static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2050 unsigned long fb_addr, reg_addr;
2051 struct aty128fb_par *par;
2052 struct fb_info *info;
2055 void __iomem *bios = NULL;
2058 /* Enable device in PCI config */
2059 if ((err = pci_enable_device(pdev))) {
2060 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
2065 fb_addr = pci_resource_start(pdev, 0);
2066 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
2068 printk(KERN_ERR "aty128fb: cannot reserve frame "
2073 reg_addr = pci_resource_start(pdev, 2);
2074 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
2076 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
2080 /* We have the resources. Now virtualize them */
2081 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
2087 info->pseudo_palette = par->pseudo_palette;
2089 /* Virtualize mmio region */
2090 info->fix.mmio_start = reg_addr;
2091 par->regbase = pci_ioremap_bar(pdev, 2);
2095 /* Grab memory size from the card */
2096 // How does this relate to the resource length from the PCI hardware?
2097 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
2099 /* Virtualize the framebuffer */
2100 info->screen_base = ioremap_wc(fb_addr, par->vram_size);
2101 if (!info->screen_base)
2104 /* Set up info->fix */
2105 info->fix = aty128fb_fix;
2106 info->fix.smem_start = fb_addr;
2107 info->fix.smem_len = par->vram_size;
2108 info->fix.mmio_start = reg_addr;
2110 /* If we can't test scratch registers, something is seriously wrong */
2111 if (!register_test(par)) {
2112 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
2117 bios = aty128_map_ROM(par, pdev);
2120 bios = aty128_find_mem_vbios(par);
2123 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
2125 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
2126 aty128_get_pllinfo(par, bios);
2127 pci_unmap_rom(pdev, bios);
2129 #endif /* __sparc__ */
2131 aty128_timings(par);
2132 pci_set_drvdata(pdev, info);
2134 if (!aty128_init(pdev, ent))
2138 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
2143 iounmap(info->screen_base);
2145 iounmap(par->regbase);
2147 framebuffer_release(info);
2149 release_mem_region(pci_resource_start(pdev, 2),
2150 pci_resource_len(pdev, 2));
2152 release_mem_region(pci_resource_start(pdev, 0),
2153 pci_resource_len(pdev, 0));
2157 static void aty128_remove(struct pci_dev *pdev)
2159 struct fb_info *info = pci_get_drvdata(pdev);
2160 struct aty128fb_par *par;
2167 unregister_framebuffer(info);
2169 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2170 aty128_bl_exit(info->bl_dev);
2173 arch_phys_wc_del(par->wc_cookie);
2174 iounmap(par->regbase);
2175 iounmap(info->screen_base);
2177 release_mem_region(pci_resource_start(pdev, 0),
2178 pci_resource_len(pdev, 0));
2179 release_mem_region(pci_resource_start(pdev, 2),
2180 pci_resource_len(pdev, 2));
2181 framebuffer_release(info);
2183 #endif /* CONFIG_PCI */
2188 * Blank the display.
2190 static int aty128fb_blank(int blank, struct fb_info *fb)
2192 struct aty128fb_par *par = fb->par;
2195 if (par->lock_blank || par->asleep)
2199 case FB_BLANK_NORMAL:
2202 case FB_BLANK_VSYNC_SUSPEND:
2205 case FB_BLANK_HSYNC_SUSPEND:
2208 case FB_BLANK_POWERDOWN:
2211 case FB_BLANK_UNBLANK:
2216 aty_st_8(CRTC_EXT_CNTL+1, state);
2218 if (par->chip_gen == rage_M3) {
2219 aty128_set_crt_enable(par, par->crt_on && !blank);
2220 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2227 * Set a single color register. The values supplied are already
2228 * rounded down to the hardware's capabilities (according to the
2229 * entries in the var structure). Return != 0 for invalid regno.
2231 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2232 u_int transp, struct fb_info *info)
2234 struct aty128fb_par *par = info->par;
2237 || (par->crtc.depth == 16 && regno > 63)
2238 || (par->crtc.depth == 15 && regno > 31))
2247 u32 *pal = info->pseudo_palette;
2249 switch (par->crtc.depth) {
2251 pal[regno] = (regno << 10) | (regno << 5) | regno;
2254 pal[regno] = (regno << 11) | (regno << 6) | regno;
2257 pal[regno] = (regno << 16) | (regno << 8) | regno;
2260 i = (regno << 8) | regno;
2261 pal[regno] = (i << 16) | i;
2266 if (par->crtc.depth == 16 && regno > 0) {
2268 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2269 * have 32 slots for R and B values but 64 slots for G values.
2270 * Thus the R and B values go in one slot but the G value
2271 * goes in a different slot, and we have to avoid disturbing
2272 * the other fields in the slots we touch.
2274 par->green[regno] = green;
2276 par->red[regno] = red;
2277 par->blue[regno] = blue;
2278 aty128_st_pal(regno * 8, red, par->green[regno*2],
2281 red = par->red[regno/2];
2282 blue = par->blue[regno/2];
2284 } else if (par->crtc.bpp == 16)
2286 aty128_st_pal(regno, red, green, blue, par);
2291 #define ATY_MIRROR_LCD_ON 0x00000001
2292 #define ATY_MIRROR_CRT_ON 0x00000002
2294 /* out param: u32* backlight value: 0 to 15 */
2295 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
2296 /* in param: u32* backlight value: 0 to 15 */
2297 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
2299 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
2301 struct aty128fb_par *par = info->par;
2306 case FBIO_ATY128_SET_MIRROR:
2307 if (par->chip_gen != rage_M3)
2309 rc = get_user(value, (__u32 __user *)arg);
2312 par->lcd_on = (value & 0x01) != 0;
2313 par->crt_on = (value & 0x02) != 0;
2314 if (!par->crt_on && !par->lcd_on)
2316 aty128_set_crt_enable(par, par->crt_on);
2317 aty128_set_lcd_enable(par, par->lcd_on);
2319 case FBIO_ATY128_GET_MIRROR:
2320 if (par->chip_gen != rage_M3)
2322 value = (par->crt_on << 1) | par->lcd_on;
2323 return put_user(value, (__u32 __user *)arg);
2328 static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2332 if (!par->pdev->pm_cap)
2335 /* Set the chip into the appropriate suspend mode (we use D2,
2336 * D3 would require a complete re-initialisation of the chip,
2337 * including PCI config registers, clocks, AGP configuration, ...)
2339 * For resume, the core will have already brought us back to D0
2342 /* Make sure CRTC2 is reset. Remove that the day we decide to
2343 * actually use CRTC2 and replace it with real code for disabling
2344 * the CRTC2 output during sleep
2346 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2349 /* Set the power management mode to be PCI based */
2350 /* Use this magic value for now */
2352 aty_st_pll(POWER_MANAGEMENT, pmgt);
2353 (void)aty_ld_pll(POWER_MANAGEMENT);
2354 aty_st_le32(BUS_CNTL1, 0x00000010);
2355 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2360 static int aty128_pci_suspend_late(struct device *dev, pm_message_t state)
2362 struct pci_dev *pdev = to_pci_dev(dev);
2363 struct fb_info *info = pci_get_drvdata(pdev);
2364 struct aty128fb_par *par = info->par;
2366 /* We don't do anything but D2, for now we return 0, but
2367 * we may want to change that. How do we know if the BIOS
2368 * can properly take care of D3 ? Also, with swsusp, we
2369 * know we'll be rebooted, ...
2371 #ifndef CONFIG_PPC_PMAC
2372 /* HACK ALERT ! Once I find a proper way to say to each driver
2373 * individually what will happen with it's PCI slot, I'll change
2374 * that. On laptops, the AGP slot is just unclocked, so D2 is
2375 * expected, while on desktops, the card is powered off
2378 #endif /* CONFIG_PPC_PMAC */
2380 if (state.event == pdev->dev.power.power_state.event)
2383 printk(KERN_DEBUG "aty128fb: suspending...\n");
2387 fb_set_suspend(info, 1);
2389 /* Make sure engine is reset */
2391 aty128_reset_engine(par);
2394 /* Blank display and LCD */
2395 aty128fb_blank(FB_BLANK_POWERDOWN, info);
2399 par->lock_blank = 1;
2401 #ifdef CONFIG_PPC_PMAC
2402 /* On powermac, we have hooks to properly suspend/resume AGP now,
2403 * use them here. We'll ultimately need some generic support here,
2404 * but the generic code isn't quite ready for that yet
2406 pmac_suspend_agp_for_card(pdev);
2407 #endif /* CONFIG_PPC_PMAC */
2409 /* We need a way to make sure the fbdev layer will _not_ touch the
2410 * framebuffer before we put the chip to suspend state. On 2.4, I
2411 * used dummy fb ops, 2.5 need proper support for this at the
2414 if (state.event != PM_EVENT_ON)
2415 aty128_set_suspend(par, 1);
2419 pdev->dev.power.power_state = state;
2424 static int __maybe_unused aty128_pci_suspend(struct device *dev)
2426 return aty128_pci_suspend_late(dev, PMSG_SUSPEND);
2429 static int __maybe_unused aty128_pci_hibernate(struct device *dev)
2431 return aty128_pci_suspend_late(dev, PMSG_HIBERNATE);
2434 static int __maybe_unused aty128_pci_freeze(struct device *dev)
2436 return aty128_pci_suspend_late(dev, PMSG_FREEZE);
2439 static int aty128_do_resume(struct pci_dev *pdev)
2441 struct fb_info *info = pci_get_drvdata(pdev);
2442 struct aty128fb_par *par = info->par;
2444 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2447 /* PCI state will have been restored by the core, so
2448 * we should be in D0 now with our config space fully
2453 aty128_set_suspend(par, 0);
2456 /* Restore display & engine */
2457 aty128_reset_engine(par);
2459 aty128fb_set_par(info);
2460 fb_pan_display(info, &info->var);
2461 fb_set_cmap(&info->cmap, info);
2464 fb_set_suspend(info, 0);
2467 par->lock_blank = 0;
2468 aty128fb_blank(0, info);
2470 #ifdef CONFIG_PPC_PMAC
2471 /* On powermac, we have hooks to properly suspend/resume AGP now,
2472 * use them here. We'll ultimately need some generic support here,
2473 * but the generic code isn't quite ready for that yet
2475 pmac_resume_agp_for_card(pdev);
2476 #endif /* CONFIG_PPC_PMAC */
2478 pdev->dev.power.power_state = PMSG_ON;
2480 printk(KERN_DEBUG "aty128fb: resumed !\n");
2485 static int __maybe_unused aty128_pci_resume(struct device *dev)
2490 rc = aty128_do_resume(to_pci_dev(dev));
2497 static int aty128fb_init(void)
2500 char *option = NULL;
2502 if (fb_get_options("aty128fb", &option))
2504 aty128fb_setup(option);
2507 return pci_register_driver(&aty128fb_driver);
2510 static void __exit aty128fb_exit(void)
2512 pci_unregister_driver(&aty128fb_driver);
2515 module_init(aty128fb_init);
2517 module_exit(aty128fb_exit);
2519 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2520 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2521 MODULE_LICENSE("GPL");
2522 module_param(mode_option, charp, 0);
2523 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2524 module_param_named(nomtrr, mtrr, invbool, 0);
2525 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");