2 * linux/drivers/video/amba-clcd.c
4 * Copyright (C) 2001 ARM Limited, by David A Rusling
5 * Updated to 2.5, Deep Blue Solutions Ltd.
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
11 * ARM PrimeCell PL110 Color LCD Controller
13 #include <linux/amba/bus.h>
14 #include <linux/amba/clcd.h>
15 #include <linux/backlight.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
20 #include <linux/init.h>
21 #include <linux/ioport.h>
22 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/of_address.h>
26 #include <linux/of_graph.h>
27 #include <linux/slab.h>
28 #include <linux/string.h>
29 #include <video/display_timing.h>
30 #include <video/of_display_timing.h>
31 #include <video/videomode.h>
33 #include "amba-clcd-nomadik.h"
34 #include "amba-clcd-versatile.h"
36 #define to_clcd(info) container_of(info, struct clcd_fb, fb)
38 /* This is limited to 16 characters when displayed by X startup */
39 static const char *clcd_name = "CLCD FB";
42 * Unfortunately, the enable/disable functions may be called either from
43 * process or IRQ context, and we _need_ to delay. This is _not_ good.
45 static inline void clcdfb_sleep(unsigned int ms)
54 static inline void clcdfb_set_start(struct clcd_fb *fb)
56 unsigned long ustart = fb->fb.fix.smem_start;
59 ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
60 lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
62 writel(ustart, fb->regs + CLCD_UBAS);
63 writel(lstart, fb->regs + CLCD_LBAS);
66 static void clcdfb_disable(struct clcd_fb *fb)
70 if (fb->board->disable)
71 fb->board->disable(fb);
73 if (fb->panel->backlight) {
74 fb->panel->backlight->props.power = FB_BLANK_POWERDOWN;
75 backlight_update_status(fb->panel->backlight);
78 val = readl(fb->regs + fb->off_cntl);
79 if (val & CNTL_LCDPWR) {
81 writel(val, fb->regs + fb->off_cntl);
85 if (val & CNTL_LCDEN) {
87 writel(val, fb->regs + fb->off_cntl);
91 * Disable CLCD clock source.
93 if (fb->clk_enabled) {
94 fb->clk_enabled = false;
99 static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
102 * Enable the CLCD clock source.
104 if (!fb->clk_enabled) {
105 fb->clk_enabled = true;
110 * Bring up by first enabling..
113 writel(cntl, fb->regs + fb->off_cntl);
118 * and now apply power.
121 writel(cntl, fb->regs + fb->off_cntl);
126 if (fb->panel->backlight) {
127 fb->panel->backlight->props.power = FB_BLANK_UNBLANK;
128 backlight_update_status(fb->panel->backlight);
132 * finally, enable the interface.
134 if (fb->board->enable)
135 fb->board->enable(fb);
139 clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
144 if (fb->panel->caps && fb->board->caps)
145 caps = fb->panel->caps & fb->board->caps;
147 /* Old way of specifying what can be used */
148 caps = fb->panel->cntl & CNTL_BGR ?
149 CLCD_CAP_BGR : CLCD_CAP_RGB;
150 /* But mask out 444 modes as they weren't supported */
151 caps &= ~CLCD_CAP_444;
154 /* Only TFT panels can do RGB888/BGR888 */
155 if (!(fb->panel->cntl & CNTL_LCDTFT))
156 caps &= ~CLCD_CAP_888;
158 memset(&var->transp, 0, sizeof(var->transp));
160 var->red.msb_right = 0;
161 var->green.msb_right = 0;
162 var->blue.msb_right = 0;
164 switch (var->bits_per_pixel) {
169 /* If we can't do 5551, reject */
170 caps &= CLCD_CAP_5551;
176 var->red.length = var->bits_per_pixel;
178 var->green.length = var->bits_per_pixel;
179 var->green.offset = 0;
180 var->blue.length = var->bits_per_pixel;
181 var->blue.offset = 0;
185 /* If we can't do 444, 5551 or 565, reject */
186 if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) {
192 * Green length can be 4, 5 or 6 depending whether
193 * we're operating in 444, 5551 or 565 mode.
195 if (var->green.length == 4 && caps & CLCD_CAP_444)
196 caps &= CLCD_CAP_444;
197 if (var->green.length == 5 && caps & CLCD_CAP_5551)
198 caps &= CLCD_CAP_5551;
199 else if (var->green.length == 6 && caps & CLCD_CAP_565)
200 caps &= CLCD_CAP_565;
203 * PL110 officially only supports RGB555,
204 * but may be wired up to allow RGB565.
206 if (caps & CLCD_CAP_565) {
207 var->green.length = 6;
208 caps &= CLCD_CAP_565;
209 } else if (caps & CLCD_CAP_5551) {
210 var->green.length = 5;
211 caps &= CLCD_CAP_5551;
213 var->green.length = 4;
214 caps &= CLCD_CAP_444;
218 if (var->green.length >= 5) {
220 var->blue.length = 5;
223 var->blue.length = 4;
227 if (fb->vendor->packed_24_bit_pixels) {
229 var->green.length = 8;
230 var->blue.length = 8;
236 /* If we can't do 888, reject */
237 caps &= CLCD_CAP_888;
244 var->green.length = 8;
245 var->blue.length = 8;
253 * >= 16bpp displays have separate colour component bitfields
254 * encoded in the pixel data. Calculate their position from
255 * the bitfield length defined above.
257 if (ret == 0 && var->bits_per_pixel >= 16) {
260 bgr = caps & CLCD_CAP_BGR && var->blue.offset == 0;
261 rgb = caps & CLCD_CAP_RGB && var->red.offset == 0;
265 * The requested format was not possible, try just
266 * our capabilities. One of BGR or RGB must be
269 bgr = caps & CLCD_CAP_BGR;
272 var->blue.offset = 0;
273 var->green.offset = var->blue.offset + var->blue.length;
274 var->red.offset = var->green.offset + var->green.length;
277 var->green.offset = var->red.offset + var->red.length;
278 var->blue.offset = var->green.offset + var->green.length;
285 static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
287 struct clcd_fb *fb = to_clcd(info);
290 if (fb->board->check)
291 ret = fb->board->check(fb, var);
294 var->xres_virtual * var->bits_per_pixel / 8 *
295 var->yres_virtual > fb->fb.fix.smem_len)
299 ret = clcdfb_set_bitfields(fb, var);
304 static int clcdfb_set_par(struct fb_info *info)
306 struct clcd_fb *fb = to_clcd(info);
307 struct clcd_regs regs;
309 fb->fb.fix.line_length = fb->fb.var.xres_virtual *
310 fb->fb.var.bits_per_pixel / 8;
312 if (fb->fb.var.bits_per_pixel <= 8)
313 fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
315 fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
317 fb->board->decode(fb, ®s);
321 /* Some variants must be clocked here */
322 if (fb->vendor->clock_timregs && !fb->clk_enabled) {
323 fb->clk_enabled = true;
327 writel(regs.tim0, fb->regs + CLCD_TIM0);
328 writel(regs.tim1, fb->regs + CLCD_TIM1);
329 writel(regs.tim2, fb->regs + CLCD_TIM2);
330 writel(regs.tim3, fb->regs + CLCD_TIM3);
332 clcdfb_set_start(fb);
334 clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
336 fb->clcd_cntl = regs.cntl;
338 clcdfb_enable(fb, regs.cntl);
342 "CLCD: Registers set to\n"
343 " %08x %08x %08x %08x\n"
344 " %08x %08x %08x %08x\n",
345 readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
346 readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
347 readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
348 readl(fb->regs + fb->off_ienb), readl(fb->regs + fb->off_cntl));
354 static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
356 unsigned int mask = (1 << bf->length) - 1;
358 return (val >> (16 - bf->length) & mask) << bf->offset;
362 * Set a single color register. The values supplied have a 16 bit
363 * magnitude. Return != 0 for invalid regno.
366 clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
367 unsigned int blue, unsigned int transp, struct fb_info *info)
369 struct clcd_fb *fb = to_clcd(info);
372 fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
373 convert_bitfield(blue, &fb->fb.var.blue) |
374 convert_bitfield(green, &fb->fb.var.green) |
375 convert_bitfield(red, &fb->fb.var.red);
377 if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
378 int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
379 u32 val, mask, newval;
381 newval = (red >> 11) & 0x001f;
382 newval |= (green >> 6) & 0x03e0;
383 newval |= (blue >> 1) & 0x7c00;
386 * 3.2.11: if we're configured for big endian
387 * byte order, the palette entries are swapped.
389 if (fb->clcd_cntl & CNTL_BEBO)
399 val = readl(fb->regs + hw_reg) & mask;
400 writel(val | newval, fb->regs + hw_reg);
407 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
408 * then the caller blanks by setting the CLUT (Color Look Up Table) to all
409 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
410 * to e.g. a video mode which doesn't support it. Implements VESA suspend
411 * and powerdown modes on hardware that supports disabling hsync/vsync:
412 * blank_mode == 2: suspend vsync
413 * blank_mode == 3: suspend hsync
414 * blank_mode == 4: powerdown
416 static int clcdfb_blank(int blank_mode, struct fb_info *info)
418 struct clcd_fb *fb = to_clcd(info);
420 if (blank_mode != 0) {
423 clcdfb_enable(fb, fb->clcd_cntl);
428 static int clcdfb_mmap(struct fb_info *info,
429 struct vm_area_struct *vma)
431 struct clcd_fb *fb = to_clcd(info);
432 unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT;
435 len = info->fix.smem_len;
437 if (off <= len && vma->vm_end - vma->vm_start <= len - off &&
439 ret = fb->board->mmap(fb, vma);
444 static struct fb_ops clcdfb_ops = {
445 .owner = THIS_MODULE,
446 .fb_check_var = clcdfb_check_var,
447 .fb_set_par = clcdfb_set_par,
448 .fb_setcolreg = clcdfb_setcolreg,
449 .fb_blank = clcdfb_blank,
450 .fb_fillrect = cfb_fillrect,
451 .fb_copyarea = cfb_copyarea,
452 .fb_imageblit = cfb_imageblit,
453 .fb_mmap = clcdfb_mmap,
456 static int clcdfb_register(struct clcd_fb *fb)
461 * ARM PL111 always has IENB at 0x1c; it's only PL110
462 * which is reversed on some platforms.
464 if (amba_manf(fb->dev) == 0x41 && amba_part(fb->dev) == 0x111) {
465 fb->off_ienb = CLCD_PL111_IENB;
466 fb->off_cntl = CLCD_PL111_CNTL;
468 if (of_machine_is_compatible("arm,versatile-ab") ||
469 of_machine_is_compatible("arm,versatile-pb")) {
470 fb->off_ienb = CLCD_PL111_IENB;
471 fb->off_cntl = CLCD_PL111_CNTL;
473 fb->off_ienb = CLCD_PL110_IENB;
474 fb->off_cntl = CLCD_PL110_CNTL;
478 fb->clk = clk_get(&fb->dev->dev, NULL);
479 if (IS_ERR(fb->clk)) {
480 ret = PTR_ERR(fb->clk);
484 ret = clk_prepare(fb->clk);
488 fb->fb.device = &fb->dev->dev;
490 fb->fb.fix.mmio_start = fb->dev->res.start;
491 fb->fb.fix.mmio_len = resource_size(&fb->dev->res);
493 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
495 printk(KERN_ERR "CLCD: unable to remap registers\n");
500 fb->fb.fbops = &clcdfb_ops;
501 fb->fb.flags = FBINFO_FLAG_DEFAULT;
502 fb->fb.pseudo_palette = fb->cmap;
504 strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
505 fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
506 fb->fb.fix.type_aux = 0;
507 fb->fb.fix.xpanstep = 0;
508 fb->fb.fix.ypanstep = 0;
509 fb->fb.fix.ywrapstep = 0;
510 fb->fb.fix.accel = FB_ACCEL_NONE;
512 fb->fb.var.xres = fb->panel->mode.xres;
513 fb->fb.var.yres = fb->panel->mode.yres;
514 fb->fb.var.xres_virtual = fb->panel->mode.xres;
515 fb->fb.var.yres_virtual = fb->panel->mode.yres;
516 fb->fb.var.bits_per_pixel = fb->panel->bpp;
517 fb->fb.var.grayscale = fb->panel->grayscale;
518 fb->fb.var.pixclock = fb->panel->mode.pixclock;
519 fb->fb.var.left_margin = fb->panel->mode.left_margin;
520 fb->fb.var.right_margin = fb->panel->mode.right_margin;
521 fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
522 fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
523 fb->fb.var.hsync_len = fb->panel->mode.hsync_len;
524 fb->fb.var.vsync_len = fb->panel->mode.vsync_len;
525 fb->fb.var.sync = fb->panel->mode.sync;
526 fb->fb.var.vmode = fb->panel->mode.vmode;
527 fb->fb.var.activate = FB_ACTIVATE_NOW;
528 fb->fb.var.nonstd = 0;
529 fb->fb.var.height = fb->panel->height;
530 fb->fb.var.width = fb->panel->width;
531 fb->fb.var.accel_flags = 0;
533 fb->fb.monspecs.hfmin = 0;
534 fb->fb.monspecs.hfmax = 100000;
535 fb->fb.monspecs.vfmin = 0;
536 fb->fb.monspecs.vfmax = 400;
537 fb->fb.monspecs.dclkmin = 1000000;
538 fb->fb.monspecs.dclkmax = 100000000;
541 * Make sure that the bitfields are set appropriately.
543 clcdfb_set_bitfields(fb, &fb->fb.var);
546 * Allocate colourmap.
548 ret = fb_alloc_cmap(&fb->fb.cmap, 256, 0);
553 * Ensure interrupts are disabled.
555 writel(0, fb->regs + fb->off_ienb);
557 fb_set_var(&fb->fb, &fb->fb.var);
559 dev_info(&fb->dev->dev, "%s hardware, %s display\n",
560 fb->board->name, fb->panel->mode.name);
562 ret = register_framebuffer(&fb->fb);
566 printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
568 fb_dealloc_cmap(&fb->fb.cmap);
572 clk_unprepare(fb->clk);
580 static int clcdfb_of_get_dpi_panel_mode(struct device_node *node,
581 struct clcd_panel *clcd_panel)
584 struct display_timing timing;
585 struct videomode video;
587 err = of_get_display_timing(node, "panel-timing", &timing);
591 videomode_from_timing(&timing, &video);
593 err = fb_videomode_from_videomode(&video, &clcd_panel->mode);
597 /* Set up some inversion flags */
598 if (timing.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
599 clcd_panel->tim2 |= TIM2_IPC;
600 else if (!(timing.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE))
602 * To preserve backwards compatibility, the IPC (inverted
603 * pixel clock) flag needs to be set on any display that
604 * doesn't explicitly specify that the pixel clock is
605 * active on the negative or positive edge.
607 clcd_panel->tim2 |= TIM2_IPC;
609 if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW)
610 clcd_panel->tim2 |= TIM2_IHS;
612 if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW)
613 clcd_panel->tim2 |= TIM2_IVS;
615 if (timing.flags & DISPLAY_FLAGS_DE_LOW)
616 clcd_panel->tim2 |= TIM2_IOE;
621 static int clcdfb_snprintf_mode(char *buf, int size, struct fb_videomode *mode)
623 return snprintf(buf, size, "%ux%u@%u", mode->xres, mode->yres,
627 static int clcdfb_of_get_backlight(struct device_node *panel,
628 struct clcd_panel *clcd_panel)
630 struct device_node *backlight;
632 /* Look up the optional backlight phandle */
633 backlight = of_parse_phandle(panel, "backlight", 0);
635 clcd_panel->backlight = of_find_backlight_by_node(backlight);
636 of_node_put(backlight);
638 if (!clcd_panel->backlight)
639 return -EPROBE_DEFER;
644 static int clcdfb_of_get_mode(struct device *dev, struct device_node *panel,
645 struct clcd_panel *clcd_panel)
648 struct fb_videomode *mode;
652 /* Only directly connected DPI panels supported for now */
653 if (of_device_is_compatible(panel, "panel-dpi"))
654 err = clcdfb_of_get_dpi_panel_mode(panel, clcd_panel);
659 mode = &clcd_panel->mode;
661 len = clcdfb_snprintf_mode(NULL, 0, mode);
662 name = devm_kzalloc(dev, len + 1, GFP_KERNEL);
666 clcdfb_snprintf_mode(name, len + 1, mode);
672 static int clcdfb_of_init_tft_panel(struct clcd_fb *fb, u32 r0, u32 g0, u32 b0)
679 { 0x110, 1, 7, 13, CLCD_CAP_5551 },
680 { 0x110, 0, 8, 16, CLCD_CAP_888 },
681 { 0x110, 16, 8, 0, CLCD_CAP_888 },
682 { 0x111, 4, 14, 20, CLCD_CAP_444 },
683 { 0x111, 3, 11, 19, CLCD_CAP_444 | CLCD_CAP_5551 },
684 { 0x111, 3, 10, 19, CLCD_CAP_444 | CLCD_CAP_5551 |
686 { 0x111, 0, 8, 16, CLCD_CAP_444 | CLCD_CAP_5551 |
687 CLCD_CAP_565 | CLCD_CAP_888 },
691 /* Bypass pixel clock divider */
692 fb->panel->tim2 |= TIM2_BCD;
694 /* TFT display, vert. comp. interrupt at the start of the back porch */
695 fb->panel->cntl |= CNTL_LCDTFT | CNTL_LCDVCOMP(1);
699 /* Match the setup with known variants */
700 for (i = 0; i < ARRAY_SIZE(panels) && !fb->panel->caps; i++) {
701 if (amba_part(fb->dev) != panels[i].part)
703 if (g0 != panels[i].g0)
705 if (r0 == panels[i].r0 && b0 == panels[i].b0)
706 fb->panel->caps = panels[i].caps;
710 * If we actually physically connected the R lines to B and
713 if (r0 != 0 && b0 == 0)
714 fb->panel->bgr_connection = true;
716 if (fb->panel->caps && fb->vendor->st_bitmux_control) {
718 * Set up the special bits for the Nomadik control register
719 * (other platforms tend to do this through an external
723 /* Offset of the highest used color */
724 int maxoff = max3(r0, g0, b0);
725 /* Most significant bit out, highest used bit */
728 if (fb->panel->caps & CLCD_CAP_888) {
729 msb = maxoff + 8 - 1;
730 } else if (fb->panel->caps & CLCD_CAP_565) {
731 msb = maxoff + 5 - 1;
732 fb->panel->cntl |= CNTL_ST_1XBPP_565;
733 } else if (fb->panel->caps & CLCD_CAP_5551) {
734 msb = maxoff + 5 - 1;
735 fb->panel->cntl |= CNTL_ST_1XBPP_5551;
736 } else if (fb->panel->caps & CLCD_CAP_444) {
737 msb = maxoff + 4 - 1;
738 fb->panel->cntl |= CNTL_ST_1XBPP_444;
741 /* Send out as many bits as we need */
743 fb->panel->cntl |= CNTL_ST_CDWID_24;
745 fb->panel->cntl |= CNTL_ST_CDWID_18;
747 fb->panel->cntl |= CNTL_ST_CDWID_16;
749 fb->panel->cntl |= CNTL_ST_CDWID_12;
752 return fb->panel->caps ? 0 : -EINVAL;
755 static int clcdfb_of_init_display(struct clcd_fb *fb)
757 struct device_node *endpoint, *panel;
763 fb->panel = devm_kzalloc(&fb->dev->dev, sizeof(*fb->panel), GFP_KERNEL);
768 * Fetch the panel endpoint.
770 endpoint = of_graph_get_next_endpoint(fb->dev->dev.of_node, NULL);
774 panel = of_graph_get_remote_port_parent(endpoint);
777 goto out_endpoint_put;
780 if (fb->vendor->init_panel) {
781 err = fb->vendor->init_panel(fb, panel);
786 err = clcdfb_of_get_backlight(panel, fb->panel);
790 err = clcdfb_of_get_mode(&fb->dev->dev, panel, fb->panel);
794 err = of_property_read_u32(fb->dev->dev.of_node, "max-memory-bandwidth",
798 * max_bandwidth is in bytes per second and pixclock in
799 * pico-seconds, so the maximum allowed bits per pixel is
800 * 8 * max_bandwidth / (PICOS2KHZ(pixclock) * 1000)
801 * Rearrange this calculation to avoid overflow and then ensure
802 * result is a valid format.
804 bpp = max_bandwidth / (1000 / 8)
805 / PICOS2KHZ(fb->panel->mode.pixclock);
806 bpp = rounddown_pow_of_two(bpp);
811 fb->panel->bpp = bpp;
813 #ifdef CONFIG_CPU_BIG_ENDIAN
814 fb->panel->cntl |= CNTL_BEBO;
816 fb->panel->width = -1;
817 fb->panel->height = -1;
819 if (of_property_read_u32_array(endpoint,
820 "arm,pl11x,tft-r0g0b0-pads",
821 tft_r0b0g0, ARRAY_SIZE(tft_r0b0g0)) != 0) {
827 of_node_put(endpoint);
829 return clcdfb_of_init_tft_panel(fb, tft_r0b0g0[0],
830 tft_r0b0g0[1], tft_r0b0g0[2]);
834 of_node_put(endpoint);
838 static int clcdfb_of_vram_setup(struct clcd_fb *fb)
841 struct device_node *memory;
844 err = clcdfb_of_init_display(fb);
848 memory = of_parse_phandle(fb->dev->dev.of_node, "memory-region", 0);
852 fb->fb.screen_base = of_iomap(memory, 0);
853 if (!fb->fb.screen_base) {
858 fb->fb.fix.smem_start = of_translate_address(memory,
859 of_get_address(memory, 0, &size, NULL));
860 fb->fb.fix.smem_len = size;
866 static int clcdfb_of_vram_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
868 unsigned long off, user_size, kernel_size;
871 off = vma->vm_pgoff << PAGE_SHIFT;
872 user_size = vma->vm_end - vma->vm_start;
873 kernel_size = fb->fb.fix.smem_len;
875 if (off >= kernel_size || user_size > (kernel_size - off))
878 return remap_pfn_range(vma, vma->vm_start,
879 __phys_to_pfn(fb->fb.fix.smem_start) + vma->vm_pgoff,
881 pgprot_writecombine(vma->vm_page_prot));
884 static void clcdfb_of_vram_remove(struct clcd_fb *fb)
886 iounmap(fb->fb.screen_base);
889 static int clcdfb_of_dma_setup(struct clcd_fb *fb)
891 unsigned long framesize;
895 err = clcdfb_of_init_display(fb);
899 framesize = PAGE_ALIGN(fb->panel->mode.xres * fb->panel->mode.yres *
901 fb->fb.screen_base = dma_alloc_coherent(&fb->dev->dev, framesize,
903 if (!fb->fb.screen_base)
906 fb->fb.fix.smem_start = dma;
907 fb->fb.fix.smem_len = framesize;
912 static int clcdfb_of_dma_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
914 return dma_mmap_wc(&fb->dev->dev, vma, fb->fb.screen_base,
915 fb->fb.fix.smem_start, fb->fb.fix.smem_len);
918 static void clcdfb_of_dma_remove(struct clcd_fb *fb)
920 dma_free_coherent(&fb->dev->dev, fb->fb.fix.smem_len,
921 fb->fb.screen_base, fb->fb.fix.smem_start);
924 static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev)
926 struct clcd_board *board = devm_kzalloc(&dev->dev, sizeof(*board),
928 struct device_node *node = dev->dev.of_node;
933 board->name = of_node_full_name(node);
934 board->caps = CLCD_CAP_ALL;
935 board->check = clcdfb_check;
936 board->decode = clcdfb_decode;
937 if (of_find_property(node, "memory-region", NULL)) {
938 board->setup = clcdfb_of_vram_setup;
939 board->mmap = clcdfb_of_vram_mmap;
940 board->remove = clcdfb_of_vram_remove;
942 board->setup = clcdfb_of_dma_setup;
943 board->mmap = clcdfb_of_dma_mmap;
944 board->remove = clcdfb_of_dma_remove;
950 static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev)
956 static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id)
958 struct clcd_board *board = dev_get_platdata(&dev->dev);
959 struct clcd_vendor_data *vendor = id->data;
964 board = clcdfb_of_get_board(dev);
969 if (vendor->init_board) {
970 ret = vendor->init_board(dev, board);
975 ret = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
979 ret = amba_request_regions(dev, NULL);
981 printk(KERN_ERR "CLCD: unable to reserve regs region\n");
985 fb = kzalloc(sizeof(struct clcd_fb), GFP_KERNEL);
987 printk(KERN_INFO "CLCD: could not allocate new clcd_fb struct\n");
996 dev_info(&fb->dev->dev, "PL%03x designer %02x rev%u at 0x%08llx\n",
997 amba_part(dev), amba_manf(dev), amba_rev(dev),
998 (unsigned long long)dev->res.start);
1000 ret = fb->board->setup(fb);
1004 ret = clcdfb_register(fb);
1006 amba_set_drvdata(dev, fb);
1010 fb->board->remove(fb);
1014 amba_release_regions(dev);
1019 static int clcdfb_remove(struct amba_device *dev)
1021 struct clcd_fb *fb = amba_get_drvdata(dev);
1024 unregister_framebuffer(&fb->fb);
1025 if (fb->fb.cmap.len)
1026 fb_dealloc_cmap(&fb->fb.cmap);
1028 clk_unprepare(fb->clk);
1031 fb->board->remove(fb);
1035 amba_release_regions(dev);
1040 static struct clcd_vendor_data vendor_arm = {
1041 /* Sets up the versatile board displays */
1042 .init_panel = versatile_clcd_init_panel,
1045 static struct clcd_vendor_data vendor_nomadik = {
1046 .clock_timregs = true,
1047 .packed_24_bit_pixels = true,
1048 .st_bitmux_control = true,
1049 .init_board = nomadik_clcd_init_board,
1050 .init_panel = nomadik_clcd_init_panel,
1053 static const struct amba_id clcdfb_id_table[] = {
1057 .data = &vendor_arm,
1059 /* ST Electronics Nomadik variant */
1063 .data = &vendor_nomadik,
1068 MODULE_DEVICE_TABLE(amba, clcdfb_id_table);
1070 static struct amba_driver clcd_driver = {
1072 .name = "clcd-pl11x",
1074 .probe = clcdfb_probe,
1075 .remove = clcdfb_remove,
1076 .id_table = clcdfb_id_table,
1079 static int __init amba_clcdfb_init(void)
1081 if (fb_get_options("ambafb", NULL))
1084 return amba_driver_register(&clcd_driver);
1087 module_init(amba_clcdfb_init);
1089 static void __exit amba_clcdfb_exit(void)
1091 amba_driver_unregister(&clcd_driver);
1094 module_exit(amba_clcdfb_exit);
1096 MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
1097 MODULE_LICENSE("GPL");