2 * VFIO PCI config space virtualization
4 * Copyright (C) 2012 Red Hat, Inc. All rights reserved.
5 * Author: Alex Williamson <alex.williamson@redhat.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Derived from original vfio:
12 * Copyright 2010 Cisco Systems, Inc. All rights reserved.
13 * Author: Tom Lyon, pugs@cisco.com
17 * This code handles reading and writing of PCI configuration registers.
18 * This is hairy because we want to allow a lot of flexibility to the
19 * user driver, but cannot trust it with all of the config fields.
20 * Tables determine which fields can be read and written, as well as
21 * which fields are 'virtualized' - special actions and translations to
22 * make it appear to the user that he has control, when in fact things
23 * must be negotiated with the underlying OS.
27 #include <linux/pci.h>
28 #include <linux/uaccess.h>
29 #include <linux/vfio.h>
30 #include <linux/slab.h>
32 #include "vfio_pci_private.h"
34 #define PCI_CFG_SPACE_SIZE 256
36 /* Fake capability ID for standard config space */
37 #define PCI_CAP_ID_BASIC 0
39 #define is_bar(offset) \
40 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
41 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
44 * Lengths of PCI Config Capabilities
45 * 0: Removed from the user visible capability list
48 static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = {
49 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */
50 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF,
51 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF,
52 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF,
53 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */
54 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */
55 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */
56 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */
57 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */
58 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */
59 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */
60 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */
61 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */
62 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */
63 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */
64 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */
65 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */
66 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF,
67 [PCI_CAP_ID_SATA] = 0xFF,
68 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF,
72 * Lengths of PCIe/PCI-X Extended Config Capabilities
73 * 0: Removed or masked from the user visible capability list
76 static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = {
77 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND,
78 [PCI_EXT_CAP_ID_VC] = 0xFF,
79 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF,
80 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF,
81 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */
82 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */
83 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */
84 [PCI_EXT_CAP_ID_MFVC] = 0xFF,
85 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */
86 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */
87 [PCI_EXT_CAP_ID_VNDR] = 0xFF,
88 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */
89 [PCI_EXT_CAP_ID_ACS] = 0xFF,
90 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF,
91 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF,
92 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF,
93 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */
94 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF,
95 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF,
96 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */
97 [PCI_EXT_CAP_ID_REBAR] = 0xFF,
98 [PCI_EXT_CAP_ID_DPA] = 0xFF,
99 [PCI_EXT_CAP_ID_TPH] = 0xFF,
100 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF,
101 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */
102 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */
103 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */
107 * Read/Write Permission Bits - one bit for each bit in capability
108 * Any field can be read if it exists, but what is read depends on
109 * whether the field is 'virtualized', or just pass thru to the
110 * hardware. Any virtualized field is also virtualized for writes.
111 * Writes are only permitted if they have a 1 bit here.
114 u8 *virt; /* read/write virtual data, not hw */
115 u8 *write; /* writeable bits */
116 int (*readfn)(struct vfio_pci_device *vdev, int pos, int count,
117 struct perm_bits *perm, int offset, __le32 *val);
118 int (*writefn)(struct vfio_pci_device *vdev, int pos, int count,
119 struct perm_bits *perm, int offset, __le32 val);
123 #define ALL_VIRT 0xFFFFFFFFU
125 #define ALL_WRITE 0xFFFFFFFFU
127 static int vfio_user_config_read(struct pci_dev *pdev, int offset,
128 __le32 *val, int count)
137 ret = pci_user_read_config_byte(pdev, offset, &tmp);
144 ret = pci_user_read_config_word(pdev, offset, &tmp);
149 ret = pci_user_read_config_dword(pdev, offset, &tmp_val);
153 *val = cpu_to_le32(tmp_val);
155 return pcibios_err_to_errno(ret);
158 static int vfio_user_config_write(struct pci_dev *pdev, int offset,
159 __le32 val, int count)
162 u32 tmp_val = le32_to_cpu(val);
166 ret = pci_user_write_config_byte(pdev, offset, tmp_val);
169 ret = pci_user_write_config_word(pdev, offset, tmp_val);
172 ret = pci_user_write_config_dword(pdev, offset, tmp_val);
176 return pcibios_err_to_errno(ret);
179 static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos,
180 int count, struct perm_bits *perm,
181 int offset, __le32 *val)
185 memcpy(val, vdev->vconfig + pos, count);
187 memcpy(&virt, perm->virt + offset, count);
189 /* Any non-virtualized bits? */
190 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) {
191 struct pci_dev *pdev = vdev->pdev;
195 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
199 *val = (phys_val & ~virt) | (*val & virt);
205 static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos,
206 int count, struct perm_bits *perm,
207 int offset, __le32 val)
209 __le32 virt = 0, write = 0;
211 memcpy(&write, perm->write + offset, count);
214 return count; /* drop, no writable bits */
216 memcpy(&virt, perm->virt + offset, count);
218 /* Virtualized and writable bits go to vconfig */
222 memcpy(&virt_val, vdev->vconfig + pos, count);
224 virt_val &= ~(write & virt);
225 virt_val |= (val & (write & virt));
227 memcpy(vdev->vconfig + pos, &virt_val, count);
230 /* Non-virtualzed and writable bits go to hardware */
232 struct pci_dev *pdev = vdev->pdev;
236 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
240 phys_val &= ~(write & ~virt);
241 phys_val |= (val & (write & ~virt));
243 ret = vfio_user_config_write(pdev, pos, phys_val, count);
251 /* Allow direct read from hardware, except for capability next pointer */
252 static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos,
253 int count, struct perm_bits *perm,
254 int offset, __le32 *val)
258 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
260 return pcibios_err_to_errno(ret);
262 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */
264 memcpy(val, vdev->vconfig + pos, count);
265 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */
266 if (offset == PCI_CAP_LIST_ID && count > 1)
267 memcpy(val, vdev->vconfig + pos,
268 min(PCI_CAP_FLAGS, count));
269 else if (offset == PCI_CAP_LIST_NEXT)
270 memcpy(val, vdev->vconfig + pos, 1);
276 /* Raw access skips any kind of virtualization */
277 static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos,
278 int count, struct perm_bits *perm,
279 int offset, __le32 val)
283 ret = vfio_user_config_write(vdev->pdev, pos, val, count);
290 static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos,
291 int count, struct perm_bits *perm,
292 int offset, __le32 *val)
296 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
298 return pcibios_err_to_errno(ret);
303 /* Virt access uses only virtualization */
304 static int vfio_virt_config_write(struct vfio_pci_device *vdev, int pos,
305 int count, struct perm_bits *perm,
306 int offset, __le32 val)
308 memcpy(vdev->vconfig + pos, &val, count);
312 static int vfio_virt_config_read(struct vfio_pci_device *vdev, int pos,
313 int count, struct perm_bits *perm,
314 int offset, __le32 *val)
316 memcpy(val, vdev->vconfig + pos, count);
320 /* Default capability regions to read-only, no-virtualization */
321 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = {
322 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
324 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = {
325 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
328 * Default unassigned regions to raw read-write access. Some devices
329 * require this to function as they hide registers between the gaps in
330 * config space (be2net). Like MMIO and I/O port registers, we have
331 * to trust the hardware isolation.
333 static struct perm_bits unassigned_perms = {
334 .readfn = vfio_raw_config_read,
335 .writefn = vfio_raw_config_write
338 static struct perm_bits virt_perms = {
339 .readfn = vfio_virt_config_read,
340 .writefn = vfio_virt_config_write
343 static void free_perm_bits(struct perm_bits *perm)
351 static int alloc_perm_bits(struct perm_bits *perm, int size)
354 * Round up all permission bits to the next dword, this lets us
355 * ignore whether a read/write exceeds the defined capability
356 * structure. We can do this because:
357 * - Standard config space is already dword aligned
358 * - Capabilities are all dword aligned (bits 0:1 of next reserved)
359 * - Express capabilities defined as dword aligned
361 size = round_up(size, 4);
365 * - All Readable, None Writeable, None Virtualized
367 perm->virt = kzalloc(size, GFP_KERNEL);
368 perm->write = kzalloc(size, GFP_KERNEL);
369 if (!perm->virt || !perm->write) {
370 free_perm_bits(perm);
374 perm->readfn = vfio_default_config_read;
375 perm->writefn = vfio_default_config_write;
381 * Helper functions for filling in permission tables
383 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write)
386 p->write[off] = write;
389 /* Handle endian-ness - pci and tables are little-endian */
390 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write)
392 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt);
393 *(__le16 *)(&p->write[off]) = cpu_to_le16(write);
396 /* Handle endian-ness - pci and tables are little-endian */
397 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write)
399 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt);
400 *(__le32 *)(&p->write[off]) = cpu_to_le32(write);
403 /* Caller should hold memory_lock semaphore */
404 bool __vfio_pci_memory_enabled(struct vfio_pci_device *vdev)
406 struct pci_dev *pdev = vdev->pdev;
407 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
410 * SR-IOV VF memory enable is handled by the MSE bit in the
411 * PF SR-IOV capability, there's therefore no need to trigger
412 * faults based on the virtual value.
414 return pdev->is_virtfn || (cmd & PCI_COMMAND_MEMORY);
418 * Restore the *real* BARs after we detect a FLR or backdoor reset.
419 * (backdoor = some device specific technique that we didn't catch)
421 static void vfio_bar_restore(struct vfio_pci_device *vdev)
423 struct pci_dev *pdev = vdev->pdev;
424 u32 *rbar = vdev->rbar;
431 pr_info("%s: %s reset recovery - restoring bars\n",
432 __func__, dev_name(&pdev->dev));
434 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)
435 pci_user_write_config_dword(pdev, i, *rbar);
437 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
440 pci_user_read_config_word(pdev, PCI_COMMAND, &cmd);
441 cmd |= PCI_COMMAND_INTX_DISABLE;
442 pci_user_write_config_word(pdev, PCI_COMMAND, cmd);
446 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)
448 unsigned long flags = pci_resource_flags(pdev, bar);
451 if (flags & IORESOURCE_IO)
452 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO);
454 val = PCI_BASE_ADDRESS_SPACE_MEMORY;
456 if (flags & IORESOURCE_PREFETCH)
457 val |= PCI_BASE_ADDRESS_MEM_PREFETCH;
459 if (flags & IORESOURCE_MEM_64)
460 val |= PCI_BASE_ADDRESS_MEM_TYPE_64;
462 return cpu_to_le32(val);
466 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs
467 * to reflect the hardware capabilities. This implements BAR sizing.
469 static void vfio_bar_fixup(struct vfio_pci_device *vdev)
471 struct pci_dev *pdev = vdev->pdev;
476 bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
478 for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) {
479 if (!pci_resource_start(pdev, i)) {
480 *bar = 0; /* Unmapped by host = unimplemented to user */
484 mask = ~(pci_resource_len(pdev, i) - 1);
486 *bar &= cpu_to_le32((u32)mask);
487 *bar |= vfio_generate_bar_flags(pdev, i);
489 if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) {
491 *bar &= cpu_to_le32((u32)(mask >> 32));
496 bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];
499 * NB. REGION_INFO will have reported zero size if we weren't able
500 * to read the ROM, but we still return the actual BAR size here if
501 * it exists (or the shadow ROM space).
503 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) {
504 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1);
505 mask |= PCI_ROM_ADDRESS_ENABLE;
506 *bar &= cpu_to_le32((u32)mask);
507 } else if (pdev->resource[PCI_ROM_RESOURCE].flags &
508 IORESOURCE_ROM_SHADOW) {
509 mask = ~(0x20000 - 1);
510 mask |= PCI_ROM_ADDRESS_ENABLE;
511 *bar &= cpu_to_le32((u32)mask);
515 vdev->bardirty = false;
518 static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos,
519 int count, struct perm_bits *perm,
520 int offset, __le32 *val)
522 if (is_bar(offset)) /* pos == offset for basic config */
523 vfio_bar_fixup(vdev);
525 count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
527 /* Mask in virtual memory enable for SR-IOV devices */
528 if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) {
529 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
530 u32 tmp_val = le32_to_cpu(*val);
532 tmp_val |= cmd & PCI_COMMAND_MEMORY;
533 *val = cpu_to_le32(tmp_val);
539 /* Test whether BARs match the value we think they should contain */
540 static bool vfio_need_bar_restore(struct vfio_pci_device *vdev)
542 int i = 0, pos = PCI_BASE_ADDRESS_0, ret;
545 for (; pos <= PCI_BASE_ADDRESS_5; i++, pos += 4) {
547 ret = pci_user_read_config_dword(vdev->pdev, pos, &bar);
548 if (ret || vdev->rbar[i] != bar)
556 static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos,
557 int count, struct perm_bits *perm,
558 int offset, __le32 val)
560 struct pci_dev *pdev = vdev->pdev;
565 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND];
567 if (offset == PCI_COMMAND) {
568 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io;
571 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd);
575 new_cmd = le32_to_cpu(val);
577 phys_io = !!(phys_cmd & PCI_COMMAND_IO);
578 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO);
579 new_io = !!(new_cmd & PCI_COMMAND_IO);
581 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY);
582 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY);
583 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY);
586 vfio_pci_zap_and_down_write_memory_lock(vdev);
588 down_write(&vdev->memory_lock);
591 * If the user is writing mem/io enable (new_mem/io) and we
592 * think it's already enabled (virt_mem/io), but the hardware
593 * shows it disabled (phys_mem/io, then the device has
594 * undergone some kind of backdoor reset and needs to be
595 * restored before we allow it to enable the bars.
596 * SR-IOV devices will trigger this, but we catch them later
598 if ((new_mem && virt_mem && !phys_mem) ||
599 (new_io && virt_io && !phys_io) ||
600 vfio_need_bar_restore(vdev))
601 vfio_bar_restore(vdev);
604 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
606 if (offset == PCI_COMMAND)
607 up_write(&vdev->memory_lock);
612 * Save current memory/io enable bits in vconfig to allow for
613 * the test above next time.
615 if (offset == PCI_COMMAND) {
616 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
618 *virt_cmd &= cpu_to_le16(~mask);
619 *virt_cmd |= cpu_to_le16(new_cmd & mask);
621 up_write(&vdev->memory_lock);
624 /* Emulate INTx disable */
625 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) {
626 bool virt_intx_disable;
628 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) &
629 PCI_COMMAND_INTX_DISABLE);
631 if (virt_intx_disable && !vdev->virq_disabled) {
632 vdev->virq_disabled = true;
633 vfio_pci_intx_mask(vdev);
634 } else if (!virt_intx_disable && vdev->virq_disabled) {
635 vdev->virq_disabled = false;
636 vfio_pci_intx_unmask(vdev);
641 vdev->bardirty = true;
646 /* Permissions for the Basic PCI Header */
647 static int __init init_pci_cap_basic_perm(struct perm_bits *perm)
649 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))
652 perm->readfn = vfio_basic_config_read;
653 perm->writefn = vfio_basic_config_write;
655 /* Virtualized for SR-IOV functions, which just have FFFF */
656 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);
657 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);
660 * Virtualize INTx disable, we use it internally for interrupt
661 * control and can emulate it for non-PCI 2.3 devices.
663 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);
665 /* Virtualize capability list, we might want to skip/disable */
666 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);
668 /* No harm to write */
669 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
670 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
671 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);
673 /* Virtualize all bars, can't touch the real ones */
674 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
675 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);
676 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
677 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);
678 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);
679 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);
680 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
682 /* Allow us to adjust capability chain */
683 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);
685 /* Sometimes used by sw, just virtualize */
686 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
688 /* Virtualize interrupt pin to allow hiding INTx */
689 p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE);
694 static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos,
695 int count, struct perm_bits *perm,
696 int offset, __le32 val)
698 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
702 if (offset == PCI_PM_CTRL) {
705 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) {
720 pci_set_power_state(vdev->pdev, state);
726 /* Permissions for the Power Management capability */
727 static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
729 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))
732 perm->writefn = vfio_pm_config_write;
735 * We always virtualize the next field so we can remove
736 * capabilities from the chain if we want to.
738 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
741 * Power management is defined *per function*, so we can let
742 * the user change power state, but we trap and initiate the
743 * change ourselves, so the state bits are read-only.
745 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK);
749 static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos,
750 int count, struct perm_bits *perm,
751 int offset, __le32 val)
753 struct pci_dev *pdev = vdev->pdev;
754 __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR);
755 __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA);
760 * Write through to emulation. If the write includes the upper byte
761 * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we
764 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
765 if (count < 0 || offset > PCI_VPD_ADDR + 1 ||
766 offset + count <= PCI_VPD_ADDR + 1)
769 addr = le16_to_cpu(*paddr);
771 if (addr & PCI_VPD_ADDR_F) {
772 data = le32_to_cpu(*pdata);
773 if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4)
777 if (pci_read_vpd(pdev, addr, 4, &data) < 0)
779 *pdata = cpu_to_le32(data);
783 * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to
784 * signal completion. If an error occurs above, we assume that not
785 * toggling this bit will induce a driver timeout.
787 addr ^= PCI_VPD_ADDR_F;
788 *paddr = cpu_to_le16(addr);
793 /* Permissions for Vital Product Data capability */
794 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
796 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
799 perm->writefn = vfio_vpd_config_write;
802 * We always virtualize the next field so we can remove
803 * capabilities from the chain if we want to.
805 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
808 * Both the address and data registers are virtualized to
809 * enable access through the pci_vpd_read/write functions
811 p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
812 p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
817 /* Permissions for PCI-X capability */
818 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
820 /* Alloc 24, but only 8 are used in v0 */
821 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))
824 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
826 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);
827 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);
831 static int vfio_exp_config_write(struct vfio_pci_device *vdev, int pos,
832 int count, struct perm_bits *perm,
833 int offset, __le32 val)
835 __le16 *ctrl = (__le16 *)(vdev->vconfig + pos -
836 offset + PCI_EXP_DEVCTL);
837 int readrq = le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ;
839 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
844 * The FLR bit is virtualized, if set and the device supports PCIe
845 * FLR, issue a reset_function. Regardless, clear the bit, the spec
846 * requires it to be always read as zero. NB, reset_function might
847 * not use a PCIe FLR, we don't have that level of granularity.
849 if (*ctrl & cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR)) {
853 *ctrl &= ~cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR);
855 ret = pci_user_read_config_dword(vdev->pdev,
856 pos - offset + PCI_EXP_DEVCAP,
859 if (!ret && (cap & PCI_EXP_DEVCAP_FLR)) {
860 vfio_pci_zap_and_down_write_memory_lock(vdev);
861 pci_try_reset_function(vdev->pdev);
862 up_write(&vdev->memory_lock);
867 * MPS is virtualized to the user, writes do not change the physical
868 * register since determining a proper MPS value requires a system wide
869 * device view. The MRRS is largely independent of MPS, but since the
870 * user does not have that system-wide view, they might set a safe, but
871 * inefficiently low value. Here we allow writes through to hardware,
872 * but we set the floor to the physical device MPS setting, so that
873 * we can at least use full TLPs, as defined by the MPS value.
875 * NB, if any devices actually depend on an artificially low MRRS
876 * setting, this will need to be revisited, perhaps with a quirk
877 * though pcie_set_readrq().
879 if (readrq != (le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ)) {
881 ((le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ) >> 12);
882 readrq = max(readrq, pcie_get_mps(vdev->pdev));
884 pcie_set_readrq(vdev->pdev, readrq);
890 /* Permissions for PCI Express capability */
891 static int __init init_pci_cap_exp_perm(struct perm_bits *perm)
893 /* Alloc larger of two possible sizes */
894 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))
897 perm->writefn = vfio_exp_config_write;
899 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
902 * Allow writes to device control fields, except devctl_phantom,
903 * which could confuse IOMMU, MPS, which can break communication
904 * with other physical devices, and the ARI bit in devctl2, which
905 * is set at probe time. FLR and MRRS get virtualized via our
908 p_setw(perm, PCI_EXP_DEVCTL,
909 PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_PAYLOAD |
910 PCI_EXP_DEVCTL_READRQ, ~PCI_EXP_DEVCTL_PHANTOM);
911 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
915 static int vfio_af_config_write(struct vfio_pci_device *vdev, int pos,
916 int count, struct perm_bits *perm,
917 int offset, __le32 val)
919 u8 *ctrl = vdev->vconfig + pos - offset + PCI_AF_CTRL;
921 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
926 * The FLR bit is virtualized, if set and the device supports AF
927 * FLR, issue a reset_function. Regardless, clear the bit, the spec
928 * requires it to be always read as zero. NB, reset_function might
929 * not use an AF FLR, we don't have that level of granularity.
931 if (*ctrl & PCI_AF_CTRL_FLR) {
935 *ctrl &= ~PCI_AF_CTRL_FLR;
937 ret = pci_user_read_config_byte(vdev->pdev,
938 pos - offset + PCI_AF_CAP,
941 if (!ret && (cap & PCI_AF_CAP_FLR) && (cap & PCI_AF_CAP_TP)) {
942 vfio_pci_zap_and_down_write_memory_lock(vdev);
943 pci_try_reset_function(vdev->pdev);
944 up_write(&vdev->memory_lock);
951 /* Permissions for Advanced Function capability */
952 static int __init init_pci_cap_af_perm(struct perm_bits *perm)
954 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))
957 perm->writefn = vfio_af_config_write;
959 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
960 p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR);
964 /* Permissions for Advanced Error Reporting extended capability */
965 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
969 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))
973 * Virtualize the first dword of all express capabilities
974 * because it includes the next pointer. This lets us later
975 * remove capabilities from the chain if we need to.
977 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
979 /* Writable bits mask */
980 mask = PCI_ERR_UNC_UND | /* Undefined */
981 PCI_ERR_UNC_DLP | /* Data Link Protocol */
982 PCI_ERR_UNC_SURPDN | /* Surprise Down */
983 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */
984 PCI_ERR_UNC_FCP | /* Flow Control Protocol */
985 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */
986 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */
987 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */
988 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */
989 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */
990 PCI_ERR_UNC_ECRC | /* ECRC Error Status */
991 PCI_ERR_UNC_UNSUP | /* Unsupported Request */
992 PCI_ERR_UNC_ACSV | /* ACS Violation */
993 PCI_ERR_UNC_INTN | /* internal error */
994 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */
995 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */
996 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */
997 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);
998 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);
999 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);
1001 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */
1002 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */
1003 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */
1004 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */
1005 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */
1006 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */
1007 PCI_ERR_COR_INTERNAL | /* Corrected Internal */
1008 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */
1009 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);
1010 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);
1012 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */
1013 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */
1014 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);
1018 /* Permissions for Power Budgeting extended capability */
1019 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)
1021 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))
1024 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
1026 /* Writing the data selector is OK, the info is still read-only */
1027 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);
1032 * Initialize the shared permission tables
1034 void vfio_pci_uninit_perm_bits(void)
1036 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]);
1038 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]);
1039 free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]);
1040 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]);
1041 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]);
1042 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]);
1044 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
1045 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
1048 int __init vfio_pci_init_perm_bits(void)
1052 /* Basic config space */
1053 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]);
1056 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]);
1057 ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]);
1058 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]);
1059 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write;
1060 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]);
1061 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]);
1063 /* Extended capabilities */
1064 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
1065 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
1066 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write;
1069 vfio_pci_uninit_perm_bits();
1074 static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos)
1077 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE :
1078 PCI_STD_HEADER_SIZEOF;
1079 cap = vdev->pci_config_map[pos];
1081 if (cap == PCI_CAP_ID_BASIC)
1084 /* XXX Can we have to abutting capabilities of the same type? */
1085 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap)
1091 static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos,
1092 int count, struct perm_bits *perm,
1093 int offset, __le32 *val)
1095 /* Update max available queue size from msi_qmax */
1096 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1100 start = vfio_find_cap_start(vdev, pos);
1102 flags = (__le16 *)&vdev->vconfig[start];
1104 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK);
1105 *flags |= cpu_to_le16(vdev->msi_qmax << 1);
1108 return vfio_default_config_read(vdev, pos, count, perm, offset, val);
1111 static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos,
1112 int count, struct perm_bits *perm,
1113 int offset, __le32 val)
1115 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
1119 /* Fixup and write configured queue size and enable to hardware */
1120 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1125 start = vfio_find_cap_start(vdev, pos);
1127 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS];
1129 flags = le16_to_cpu(*pflags);
1131 /* MSI is enabled via ioctl */
1133 flags &= ~PCI_MSI_FLAGS_ENABLE;
1135 /* Check queue size */
1136 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) {
1137 flags &= ~PCI_MSI_FLAGS_QSIZE;
1138 flags |= vdev->msi_qmax << 4;
1141 /* Write back to virt and to hardware */
1142 *pflags = cpu_to_le16(flags);
1143 ret = pci_user_write_config_word(vdev->pdev,
1144 start + PCI_MSI_FLAGS,
1147 return pcibios_err_to_errno(ret);
1154 * MSI determination is per-device, so this routine gets used beyond
1155 * initialization time. Don't add __init
1157 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)
1159 if (alloc_perm_bits(perm, len))
1162 perm->readfn = vfio_msi_config_read;
1163 perm->writefn = vfio_msi_config_write;
1165 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
1168 * The upper byte of the control register is reserved,
1169 * just setup the lower byte.
1171 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);
1172 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);
1173 if (flags & PCI_MSI_FLAGS_64BIT) {
1174 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);
1175 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);
1176 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1177 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);
1178 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);
1181 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);
1182 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1183 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);
1184 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);
1190 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
1191 static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos)
1193 struct pci_dev *pdev = vdev->pdev;
1197 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags);
1199 return pcibios_err_to_errno(ret);
1201 len = 10; /* Minimum size */
1202 if (flags & PCI_MSI_FLAGS_64BIT)
1204 if (flags & PCI_MSI_FLAGS_MASKBIT)
1210 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL);
1211 if (!vdev->msi_perm)
1214 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);
1216 kfree(vdev->msi_perm);
1223 /* Determine extended capability length for VC (2 & 9) and MFVC */
1224 static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos)
1226 struct pci_dev *pdev = vdev->pdev;
1228 int ret, evcc, phases, vc_arb;
1229 int len = PCI_CAP_VC_BASE_SIZEOF;
1231 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp);
1233 return pcibios_err_to_errno(ret);
1235 evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */
1236 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp);
1238 return pcibios_err_to_errno(ret);
1240 if (tmp & PCI_VC_CAP2_128_PHASE)
1242 else if (tmp & PCI_VC_CAP2_64_PHASE)
1244 else if (tmp & PCI_VC_CAP2_32_PHASE)
1249 vc_arb = phases * 4;
1252 * Port arbitration tables are root & switch only;
1253 * function arbitration tables are function 0 only.
1254 * In either case, we'll never let user write them so
1255 * we don't care how big they are
1257 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF;
1259 len = round_up(len, 16);
1265 static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos)
1267 struct pci_dev *pdev = vdev->pdev;
1274 case PCI_CAP_ID_MSI:
1275 return vfio_msi_cap_len(vdev, pos);
1276 case PCI_CAP_ID_PCIX:
1277 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word);
1279 return pcibios_err_to_errno(ret);
1281 if (PCI_X_CMD_VERSION(word)) {
1282 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
1283 /* Test for extended capabilities */
1284 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE,
1286 vdev->extended_caps = (dword != 0);
1288 return PCI_CAP_PCIX_SIZEOF_V2;
1290 return PCI_CAP_PCIX_SIZEOF_V0;
1291 case PCI_CAP_ID_VNDR:
1292 /* length follows next field */
1293 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte);
1295 return pcibios_err_to_errno(ret);
1298 case PCI_CAP_ID_EXP:
1299 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
1300 /* Test for extended capabilities */
1301 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
1302 vdev->extended_caps = (dword != 0);
1305 /* length based on version */
1306 if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1)
1307 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1;
1309 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2;
1311 ret = pci_read_config_byte(pdev, pos + 3, &byte);
1313 return pcibios_err_to_errno(ret);
1315 return (byte & HT_3BIT_CAP_MASK) ?
1316 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG;
1317 case PCI_CAP_ID_SATA:
1318 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte);
1320 return pcibios_err_to_errno(ret);
1322 byte &= PCI_SATA_REGS_MASK;
1323 if (byte == PCI_SATA_REGS_INLINE)
1324 return PCI_SATA_SIZEOF_LONG;
1326 return PCI_SATA_SIZEOF_SHORT;
1328 pr_warn("%s: %s unknown length for pci cap 0x%x@0x%x\n",
1329 dev_name(&pdev->dev), __func__, cap, pos);
1335 static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos)
1337 struct pci_dev *pdev = vdev->pdev;
1343 case PCI_EXT_CAP_ID_VNDR:
1344 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword);
1346 return pcibios_err_to_errno(ret);
1348 return dword >> PCI_VSEC_HDR_LEN_SHIFT;
1349 case PCI_EXT_CAP_ID_VC:
1350 case PCI_EXT_CAP_ID_VC9:
1351 case PCI_EXT_CAP_ID_MFVC:
1352 return vfio_vc_cap_len(vdev, epos);
1353 case PCI_EXT_CAP_ID_ACS:
1354 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte);
1356 return pcibios_err_to_errno(ret);
1358 if (byte & PCI_ACS_EC) {
1361 ret = pci_read_config_byte(pdev,
1362 epos + PCI_ACS_EGRESS_BITS,
1365 return pcibios_err_to_errno(ret);
1367 bits = byte ? round_up(byte, 32) : 256;
1368 return 8 + (bits / 8);
1372 case PCI_EXT_CAP_ID_REBAR:
1373 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte);
1375 return pcibios_err_to_errno(ret);
1377 byte &= PCI_REBAR_CTRL_NBAR_MASK;
1378 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT;
1380 return 4 + (byte * 8);
1381 case PCI_EXT_CAP_ID_DPA:
1382 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte);
1384 return pcibios_err_to_errno(ret);
1386 byte &= PCI_DPA_CAP_SUBSTATE_MASK;
1387 return PCI_DPA_BASE_SIZEOF + byte + 1;
1388 case PCI_EXT_CAP_ID_TPH:
1389 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword);
1391 return pcibios_err_to_errno(ret);
1393 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) {
1396 sts = dword & PCI_TPH_CAP_ST_MASK;
1397 sts >>= PCI_TPH_CAP_ST_SHIFT;
1398 return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2;
1400 return PCI_TPH_BASE_SIZEOF;
1402 pr_warn("%s: %s unknown length for pci ecap 0x%x@0x%x\n",
1403 dev_name(&pdev->dev), __func__, ecap, epos);
1409 static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev,
1410 int offset, int size)
1412 struct pci_dev *pdev = vdev->pdev;
1416 * We try to read physical config space in the largest chunks
1417 * we can, assuming that all of the fields support dword access.
1418 * pci_save_state() makes this same assumption and seems to do ok.
1423 if (size >= 4 && !(offset % 4)) {
1424 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset];
1427 ret = pci_read_config_dword(pdev, offset, &dword);
1430 *dwordp = cpu_to_le32(dword);
1432 } else if (size >= 2 && !(offset % 2)) {
1433 __le16 *wordp = (__le16 *)&vdev->vconfig[offset];
1436 ret = pci_read_config_word(pdev, offset, &word);
1439 *wordp = cpu_to_le16(word);
1442 u8 *byte = &vdev->vconfig[offset];
1443 ret = pci_read_config_byte(pdev, offset, byte);
1456 static int vfio_cap_init(struct vfio_pci_device *vdev)
1458 struct pci_dev *pdev = vdev->pdev;
1459 u8 *map = vdev->pci_config_map;
1462 int loops, ret, caps = 0;
1464 /* Any capabilities? */
1465 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
1469 if (!(status & PCI_STATUS_CAP_LIST))
1470 return 0; /* Done */
1472 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
1476 /* Mark the previous position in case we want to skip a capability */
1477 prev = &vdev->vconfig[PCI_CAPABILITY_LIST];
1479 /* We can bound our loop, capabilities are dword aligned */
1480 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;
1481 while (pos && loops--) {
1485 ret = pci_read_config_byte(pdev, pos, &cap);
1489 ret = pci_read_config_byte(pdev,
1490 pos + PCI_CAP_LIST_NEXT, &next);
1495 * ID 0 is a NULL capability, conflicting with our fake
1496 * PCI_CAP_ID_BASIC. As it has no content, consider it
1499 if (cap && cap <= PCI_CAP_ID_MAX) {
1500 len = pci_cap_length[cap];
1501 if (len == 0xFF) { /* Variable length */
1502 len = vfio_cap_len(vdev, cap, pos);
1509 pr_info("%s: %s hiding cap 0x%x\n",
1510 __func__, dev_name(&pdev->dev), cap);
1516 /* Sanity check, do we overlap other capabilities? */
1517 for (i = 0; i < len; i++) {
1518 if (likely(map[pos + i] == PCI_CAP_ID_INVALID))
1521 pr_warn("%s: %s pci config conflict @0x%x, was cap 0x%x now cap 0x%x\n",
1522 __func__, dev_name(&pdev->dev),
1523 pos + i, map[pos + i], cap);
1526 BUILD_BUG_ON(PCI_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1528 memset(map + pos, cap, len);
1529 ret = vfio_fill_vconfig_bytes(vdev, pos, len);
1533 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT];
1538 /* If we didn't fill any capabilities, clear the status flag */
1540 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS];
1541 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST);
1547 static int vfio_ecap_init(struct vfio_pci_device *vdev)
1549 struct pci_dev *pdev = vdev->pdev;
1550 u8 *map = vdev->pci_config_map;
1552 __le32 *prev = NULL;
1553 int loops, ret, ecaps = 0;
1555 if (!vdev->extended_caps)
1558 epos = PCI_CFG_SPACE_SIZE;
1560 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF;
1562 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) {
1566 bool hidden = false;
1568 ret = pci_read_config_dword(pdev, epos, &header);
1572 ecap = PCI_EXT_CAP_ID(header);
1574 if (ecap <= PCI_EXT_CAP_ID_MAX) {
1575 len = pci_ext_cap_length[ecap];
1577 len = vfio_ext_cap_len(vdev, ecap, epos);
1584 pr_info("%s: %s hiding ecap 0x%x@0x%x\n",
1585 __func__, dev_name(&pdev->dev), ecap, epos);
1587 /* If not the first in the chain, we can skip over it */
1589 u32 val = epos = PCI_EXT_CAP_NEXT(header);
1590 *prev &= cpu_to_le32(~(0xffcU << 20));
1591 *prev |= cpu_to_le32(val << 20);
1596 * Otherwise, fill in a placeholder, the direct
1597 * readfn will virtualize this automatically
1599 len = PCI_CAP_SIZEOF;
1603 for (i = 0; i < len; i++) {
1604 if (likely(map[epos + i] == PCI_CAP_ID_INVALID))
1607 pr_warn("%s: %s pci config conflict @0x%x, was ecap 0x%x now ecap 0x%x\n",
1608 __func__, dev_name(&pdev->dev),
1609 epos + i, map[epos + i], ecap);
1613 * Even though ecap is 2 bytes, we're currently a long way
1614 * from exceeding 1 byte capabilities. If we ever make it
1615 * up to 0xFE we'll need to up this to a two-byte, byte map.
1617 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1619 memset(map + epos, ecap, len);
1620 ret = vfio_fill_vconfig_bytes(vdev, epos, len);
1625 * If we're just using this capability to anchor the list,
1626 * hide the real ID. Only count real ecaps. XXX PCI spec
1627 * indicates to use cap id = 0, version = 0, next = 0 if
1628 * ecaps are absent, hope users check all the way to next.
1631 *(__le32 *)&vdev->vconfig[epos] &=
1632 cpu_to_le32((0xffcU << 20));
1636 prev = (__le32 *)&vdev->vconfig[epos];
1637 epos = PCI_EXT_CAP_NEXT(header);
1641 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;
1647 * Nag about hardware bugs, hopefully to have vendors fix them, but at least
1648 * to collect a list of dependencies for the VF INTx pin quirk below.
1650 static const struct pci_device_id known_bogus_vf_intx_pin[] = {
1651 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x270c) },
1656 * For each device we allocate a pci_config_map that indicates the
1657 * capability occupying each dword and thus the struct perm_bits we
1658 * use for read and write. We also allocate a virtualized config
1659 * space which tracks reads and writes to bits that we emulate for
1660 * the user. Initial values filled from device.
1662 * Using shared struct perm_bits between all vfio-pci devices saves
1663 * us from allocating cfg_size buffers for virt and write for every
1664 * device. We could remove vconfig and allocate individual buffers
1665 * for each area requiring emulated bits, but the array of pointers
1666 * would be comparable in size (at least for standard config space).
1668 int vfio_config_init(struct vfio_pci_device *vdev)
1670 struct pci_dev *pdev = vdev->pdev;
1675 * Config space, caps and ecaps are all dword aligned, so we could
1676 * use one byte per dword to record the type. However, there are
1677 * no requiremenst on the length of a capability, so the gap between
1678 * capabilities needs byte granularity.
1680 map = kmalloc(pdev->cfg_size, GFP_KERNEL);
1684 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL);
1690 vdev->pci_config_map = map;
1691 vdev->vconfig = vconfig;
1693 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF);
1694 memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID,
1695 pdev->cfg_size - PCI_STD_HEADER_SIZEOF);
1697 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF);
1701 vdev->bardirty = true;
1704 * XXX can we just pci_load_saved_state/pci_restore_state?
1705 * may need to rebuild vconfig after that
1708 /* For restore after reset */
1709 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
1710 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]);
1711 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);
1712 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]);
1713 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]);
1714 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]);
1715 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);
1717 if (pdev->is_virtfn) {
1718 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);
1719 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
1722 * Per SR-IOV spec rev 1.1, 3.4.1.18 the interrupt pin register
1723 * does not apply to VFs and VFs must implement this register
1724 * as read-only with value zero. Userspace is not readily able
1725 * to identify whether a device is a VF and thus that the pin
1726 * definition on the device is bogus should it violate this
1727 * requirement. We already virtualize the pin register for
1728 * other purposes, so we simply need to replace the bogus value
1729 * and consider VFs when we determine INTx IRQ count.
1731 if (vconfig[PCI_INTERRUPT_PIN] &&
1732 !pci_match_id(known_bogus_vf_intx_pin, pdev))
1734 "Hardware bug: VF reports bogus INTx pin %d\n",
1735 vconfig[PCI_INTERRUPT_PIN]);
1737 vconfig[PCI_INTERRUPT_PIN] = 0; /* Gratuitous for good VFs */
1740 * VFs do no implement the memory enable bit of the COMMAND
1741 * register therefore we'll not have it set in our initial
1742 * copy of config space after pci_enable_device(). For
1743 * consistency with PFs, set the virtual enable bit here.
1745 *(__le16 *)&vconfig[PCI_COMMAND] |=
1746 cpu_to_le16(PCI_COMMAND_MEMORY);
1749 if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx)
1750 vconfig[PCI_INTERRUPT_PIN] = 0;
1752 ret = vfio_cap_init(vdev);
1756 ret = vfio_ecap_init(vdev);
1764 vdev->pci_config_map = NULL;
1766 vdev->vconfig = NULL;
1767 return pcibios_err_to_errno(ret);
1770 void vfio_config_free(struct vfio_pci_device *vdev)
1772 kfree(vdev->vconfig);
1773 vdev->vconfig = NULL;
1774 kfree(vdev->pci_config_map);
1775 vdev->pci_config_map = NULL;
1776 if (vdev->msi_perm) {
1777 free_perm_bits(vdev->msi_perm);
1778 kfree(vdev->msi_perm);
1779 vdev->msi_perm = NULL;
1784 * Find the remaining number of bytes in a dword that match the given
1785 * position. Stop at either the end of the capability or the dword boundary.
1787 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev,
1790 u8 cap = vdev->pci_config_map[pos];
1793 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++)
1799 static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf,
1800 size_t count, loff_t *ppos, bool iswrite)
1802 struct pci_dev *pdev = vdev->pdev;
1803 struct perm_bits *perm;
1805 int cap_start = 0, offset;
1809 if (*ppos < 0 || *ppos >= pdev->cfg_size ||
1810 *ppos + count > pdev->cfg_size)
1814 * Chop accesses into aligned chunks containing no more than a
1815 * single capability. Caller increments to the next chunk.
1817 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos));
1818 if (count >= 4 && !(*ppos % 4))
1820 else if (count >= 2 && !(*ppos % 2))
1827 cap_id = vdev->pci_config_map[*ppos];
1829 if (cap_id == PCI_CAP_ID_INVALID) {
1830 perm = &unassigned_perms;
1832 } else if (cap_id == PCI_CAP_ID_INVALID_VIRT) {
1836 if (*ppos >= PCI_CFG_SPACE_SIZE) {
1837 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX);
1839 perm = &ecap_perms[cap_id];
1840 cap_start = vfio_find_cap_start(vdev, *ppos);
1842 WARN_ON(cap_id > PCI_CAP_ID_MAX);
1844 perm = &cap_perms[cap_id];
1846 if (cap_id == PCI_CAP_ID_MSI)
1847 perm = vdev->msi_perm;
1849 if (cap_id > PCI_CAP_ID_BASIC)
1850 cap_start = vfio_find_cap_start(vdev, *ppos);
1854 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC);
1855 WARN_ON(cap_start > *ppos);
1857 offset = *ppos - cap_start;
1863 if (copy_from_user(&val, buf, count))
1866 ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
1869 ret = perm->readfn(vdev, *ppos, count,
1870 perm, offset, &val);
1875 if (copy_to_user(buf, &val, count))
1882 ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf,
1883 size_t count, loff_t *ppos, bool iswrite)
1889 pos &= VFIO_PCI_OFFSET_MASK;
1892 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite);