2 * VFIO PCI config space virtualization
4 * Copyright (C) 2012 Red Hat, Inc. All rights reserved.
5 * Author: Alex Williamson <alex.williamson@redhat.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Derived from original vfio:
12 * Copyright 2010 Cisco Systems, Inc. All rights reserved.
13 * Author: Tom Lyon, pugs@cisco.com
17 * This code handles reading and writing of PCI configuration registers.
18 * This is hairy because we want to allow a lot of flexibility to the
19 * user driver, but cannot trust it with all of the config fields.
20 * Tables determine which fields can be read and written, as well as
21 * which fields are 'virtualized' - special actions and translations to
22 * make it appear to the user that he has control, when in fact things
23 * must be negotiated with the underlying OS.
27 #include <linux/pci.h>
28 #include <linux/uaccess.h>
29 #include <linux/vfio.h>
30 #include <linux/slab.h>
32 #include "vfio_pci_private.h"
34 #define PCI_CFG_SPACE_SIZE 256
36 /* Useful "pseudo" capabilities */
37 #define PCI_CAP_ID_BASIC 0
38 #define PCI_CAP_ID_INVALID 0xFF
40 #define is_bar(offset) \
41 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
42 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
45 * Lengths of PCI Config Capabilities
46 * 0: Removed from the user visible capability list
49 static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = {
50 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */
51 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF,
52 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF,
53 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF,
54 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */
55 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */
56 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */
57 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */
58 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */
59 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */
60 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */
61 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */
62 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */
63 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */
64 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */
65 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */
66 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */
67 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF,
68 [PCI_CAP_ID_SATA] = 0xFF,
69 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF,
73 * Lengths of PCIe/PCI-X Extended Config Capabilities
74 * 0: Removed or masked from the user visible capabilty list
77 static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = {
78 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND,
79 [PCI_EXT_CAP_ID_VC] = 0xFF,
80 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF,
81 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF,
82 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */
83 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */
84 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */
85 [PCI_EXT_CAP_ID_MFVC] = 0xFF,
86 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */
87 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */
88 [PCI_EXT_CAP_ID_VNDR] = 0xFF,
89 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */
90 [PCI_EXT_CAP_ID_ACS] = 0xFF,
91 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF,
92 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF,
93 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF,
94 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */
95 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF,
96 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF,
97 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */
98 [PCI_EXT_CAP_ID_REBAR] = 0xFF,
99 [PCI_EXT_CAP_ID_DPA] = 0xFF,
100 [PCI_EXT_CAP_ID_TPH] = 0xFF,
101 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF,
102 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */
103 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */
104 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */
108 * Read/Write Permission Bits - one bit for each bit in capability
109 * Any field can be read if it exists, but what is read depends on
110 * whether the field is 'virtualized', or just pass thru to the
111 * hardware. Any virtualized field is also virtualized for writes.
112 * Writes are only permitted if they have a 1 bit here.
115 u8 *virt; /* read/write virtual data, not hw */
116 u8 *write; /* writeable bits */
117 int (*readfn)(struct vfio_pci_device *vdev, int pos, int count,
118 struct perm_bits *perm, int offset, __le32 *val);
119 int (*writefn)(struct vfio_pci_device *vdev, int pos, int count,
120 struct perm_bits *perm, int offset, __le32 val);
124 #define ALL_VIRT 0xFFFFFFFFU
126 #define ALL_WRITE 0xFFFFFFFFU
128 static int vfio_user_config_read(struct pci_dev *pdev, int offset,
129 __le32 *val, int count)
138 ret = pci_user_read_config_byte(pdev, offset, &tmp);
145 ret = pci_user_read_config_word(pdev, offset, &tmp);
150 ret = pci_user_read_config_dword(pdev, offset, &tmp_val);
154 *val = cpu_to_le32(tmp_val);
156 return pcibios_err_to_errno(ret);
159 static int vfio_user_config_write(struct pci_dev *pdev, int offset,
160 __le32 val, int count)
163 u32 tmp_val = le32_to_cpu(val);
167 ret = pci_user_write_config_byte(pdev, offset, tmp_val);
170 ret = pci_user_write_config_word(pdev, offset, tmp_val);
173 ret = pci_user_write_config_dword(pdev, offset, tmp_val);
177 return pcibios_err_to_errno(ret);
180 static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos,
181 int count, struct perm_bits *perm,
182 int offset, __le32 *val)
186 memcpy(val, vdev->vconfig + pos, count);
188 memcpy(&virt, perm->virt + offset, count);
190 /* Any non-virtualized bits? */
191 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) {
192 struct pci_dev *pdev = vdev->pdev;
196 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
200 *val = (phys_val & ~virt) | (*val & virt);
206 static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos,
207 int count, struct perm_bits *perm,
208 int offset, __le32 val)
210 __le32 virt = 0, write = 0;
212 memcpy(&write, perm->write + offset, count);
215 return count; /* drop, no writable bits */
217 memcpy(&virt, perm->virt + offset, count);
219 /* Virtualized and writable bits go to vconfig */
223 memcpy(&virt_val, vdev->vconfig + pos, count);
225 virt_val &= ~(write & virt);
226 virt_val |= (val & (write & virt));
228 memcpy(vdev->vconfig + pos, &virt_val, count);
231 /* Non-virtualzed and writable bits go to hardware */
233 struct pci_dev *pdev = vdev->pdev;
237 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
241 phys_val &= ~(write & ~virt);
242 phys_val |= (val & (write & ~virt));
244 ret = vfio_user_config_write(pdev, pos, phys_val, count);
252 /* Allow direct read from hardware, except for capability next pointer */
253 static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos,
254 int count, struct perm_bits *perm,
255 int offset, __le32 *val)
259 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
261 return pcibios_err_to_errno(ret);
263 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */
265 memcpy(val, vdev->vconfig + pos, count);
266 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */
267 if (offset == PCI_CAP_LIST_ID && count > 1)
268 memcpy(val, vdev->vconfig + pos,
269 min(PCI_CAP_FLAGS, count));
270 else if (offset == PCI_CAP_LIST_NEXT)
271 memcpy(val, vdev->vconfig + pos, 1);
277 /* Raw access skips any kind of virtualization */
278 static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos,
279 int count, struct perm_bits *perm,
280 int offset, __le32 val)
284 ret = vfio_user_config_write(vdev->pdev, pos, val, count);
291 static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos,
292 int count, struct perm_bits *perm,
293 int offset, __le32 *val)
297 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
299 return pcibios_err_to_errno(ret);
304 /* Default capability regions to read-only, no-virtualization */
305 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = {
306 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
308 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = {
309 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
312 * Default unassigned regions to raw read-write access. Some devices
313 * require this to function as they hide registers between the gaps in
314 * config space (be2net). Like MMIO and I/O port registers, we have
315 * to trust the hardware isolation.
317 static struct perm_bits unassigned_perms = {
318 .readfn = vfio_raw_config_read,
319 .writefn = vfio_raw_config_write
322 static void free_perm_bits(struct perm_bits *perm)
330 static int alloc_perm_bits(struct perm_bits *perm, int size)
333 * Round up all permission bits to the next dword, this lets us
334 * ignore whether a read/write exceeds the defined capability
335 * structure. We can do this because:
336 * - Standard config space is already dword aligned
337 * - Capabilities are all dword alinged (bits 0:1 of next reserved)
338 * - Express capabilities defined as dword aligned
340 size = round_up(size, 4);
344 * - All Readable, None Writeable, None Virtualized
346 perm->virt = kzalloc(size, GFP_KERNEL);
347 perm->write = kzalloc(size, GFP_KERNEL);
348 if (!perm->virt || !perm->write) {
349 free_perm_bits(perm);
353 perm->readfn = vfio_default_config_read;
354 perm->writefn = vfio_default_config_write;
360 * Helper functions for filling in permission tables
362 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write)
365 p->write[off] = write;
368 /* Handle endian-ness - pci and tables are little-endian */
369 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write)
371 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt);
372 *(__le16 *)(&p->write[off]) = cpu_to_le16(write);
375 /* Handle endian-ness - pci and tables are little-endian */
376 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write)
378 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt);
379 *(__le32 *)(&p->write[off]) = cpu_to_le32(write);
383 * Restore the *real* BARs after we detect a FLR or backdoor reset.
384 * (backdoor = some device specific technique that we didn't catch)
386 static void vfio_bar_restore(struct vfio_pci_device *vdev)
388 struct pci_dev *pdev = vdev->pdev;
389 u32 *rbar = vdev->rbar;
395 pr_info("%s: %s reset recovery - restoring bars\n",
396 __func__, dev_name(&pdev->dev));
398 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)
399 pci_user_write_config_dword(pdev, i, *rbar);
401 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
404 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)
406 unsigned long flags = pci_resource_flags(pdev, bar);
409 if (flags & IORESOURCE_IO)
410 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO);
412 val = PCI_BASE_ADDRESS_SPACE_MEMORY;
414 if (flags & IORESOURCE_PREFETCH)
415 val |= PCI_BASE_ADDRESS_MEM_PREFETCH;
417 if (flags & IORESOURCE_MEM_64)
418 val |= PCI_BASE_ADDRESS_MEM_TYPE_64;
420 return cpu_to_le32(val);
424 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs
425 * to reflect the hardware capabilities. This implements BAR sizing.
427 static void vfio_bar_fixup(struct vfio_pci_device *vdev)
429 struct pci_dev *pdev = vdev->pdev;
434 bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
436 for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) {
437 if (!pci_resource_start(pdev, i)) {
438 *bar = 0; /* Unmapped by host = unimplemented to user */
442 mask = ~(pci_resource_len(pdev, i) - 1);
444 *bar &= cpu_to_le32((u32)mask);
445 *bar |= vfio_generate_bar_flags(pdev, i);
447 if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) {
449 *bar &= cpu_to_le32((u32)(mask >> 32));
454 bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];
457 * NB. we expose the actual BAR size here, regardless of whether
458 * we can read it. When we report the REGION_INFO for the ROM
459 * we report what PCI tells us is the actual ROM size.
461 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) {
462 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1);
463 mask |= PCI_ROM_ADDRESS_ENABLE;
464 *bar &= cpu_to_le32((u32)mask);
468 vdev->bardirty = false;
471 static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos,
472 int count, struct perm_bits *perm,
473 int offset, __le32 *val)
475 if (is_bar(offset)) /* pos == offset for basic config */
476 vfio_bar_fixup(vdev);
478 count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
480 /* Mask in virtual memory enable for SR-IOV devices */
481 if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) {
482 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
483 u32 tmp_val = le32_to_cpu(*val);
485 tmp_val |= cmd & PCI_COMMAND_MEMORY;
486 *val = cpu_to_le32(tmp_val);
492 static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos,
493 int count, struct perm_bits *perm,
494 int offset, __le32 val)
496 struct pci_dev *pdev = vdev->pdev;
501 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND];
503 if (offset == PCI_COMMAND) {
504 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io;
507 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd);
511 new_cmd = le32_to_cpu(val);
513 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY);
514 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY);
515 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY);
517 phys_io = !!(phys_cmd & PCI_COMMAND_IO);
518 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO);
519 new_io = !!(new_cmd & PCI_COMMAND_IO);
522 * If the user is writing mem/io enable (new_mem/io) and we
523 * think it's already enabled (virt_mem/io), but the hardware
524 * shows it disabled (phys_mem/io, then the device has
525 * undergone some kind of backdoor reset and needs to be
526 * restored before we allow it to enable the bars.
527 * SR-IOV devices will trigger this, but we catch them later
529 if ((new_mem && virt_mem && !phys_mem) ||
530 (new_io && virt_io && !phys_io))
531 vfio_bar_restore(vdev);
534 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
539 * Save current memory/io enable bits in vconfig to allow for
540 * the test above next time.
542 if (offset == PCI_COMMAND) {
543 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
545 *virt_cmd &= cpu_to_le16(~mask);
546 *virt_cmd |= cpu_to_le16(new_cmd & mask);
549 /* Emulate INTx disable */
550 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) {
551 bool virt_intx_disable;
553 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) &
554 PCI_COMMAND_INTX_DISABLE);
556 if (virt_intx_disable && !vdev->virq_disabled) {
557 vdev->virq_disabled = true;
558 vfio_pci_intx_mask(vdev);
559 } else if (!virt_intx_disable && vdev->virq_disabled) {
560 vdev->virq_disabled = false;
561 vfio_pci_intx_unmask(vdev);
566 vdev->bardirty = true;
571 /* Permissions for the Basic PCI Header */
572 static int __init init_pci_cap_basic_perm(struct perm_bits *perm)
574 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))
577 perm->readfn = vfio_basic_config_read;
578 perm->writefn = vfio_basic_config_write;
580 /* Virtualized for SR-IOV functions, which just have FFFF */
581 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);
582 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);
585 * Virtualize INTx disable, we use it internally for interrupt
586 * control and can emulate it for non-PCI 2.3 devices.
588 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);
590 /* Virtualize capability list, we might want to skip/disable */
591 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);
593 /* No harm to write */
594 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
595 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
596 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);
598 /* Virtualize all bars, can't touch the real ones */
599 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
600 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);
601 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
602 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);
603 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);
604 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);
605 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
607 /* Allow us to adjust capability chain */
608 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);
610 /* Sometimes used by sw, just virtualize */
611 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
613 /* Virtualize interrupt pin to allow hiding INTx */
614 p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE);
619 static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos,
620 int count, struct perm_bits *perm,
621 int offset, __le32 val)
623 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
627 if (offset == PCI_PM_CTRL) {
630 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) {
645 pci_set_power_state(vdev->pdev, state);
651 /* Permissions for the Power Management capability */
652 static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
654 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))
657 perm->writefn = vfio_pm_config_write;
660 * We always virtualize the next field so we can remove
661 * capabilities from the chain if we want to.
663 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
666 * Power management is defined *per function*, so we can let
667 * the user change power state, but we trap and initiate the
668 * change ourselves, so the state bits are read-only.
670 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK);
674 static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos,
675 int count, struct perm_bits *perm,
676 int offset, __le32 val)
678 struct pci_dev *pdev = vdev->pdev;
679 __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR);
680 __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA);
685 * Write through to emulation. If the write includes the upper byte
686 * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we
689 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
690 if (count < 0 || offset > PCI_VPD_ADDR + 1 ||
691 offset + count <= PCI_VPD_ADDR + 1)
694 addr = le16_to_cpu(*paddr);
696 if (addr & PCI_VPD_ADDR_F) {
697 data = le32_to_cpu(*pdata);
698 if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4)
702 if (pci_read_vpd(pdev, addr, 4, &data) < 0)
704 *pdata = cpu_to_le32(data);
708 * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to
709 * signal completion. If an error occurs above, we assume that not
710 * toggling this bit will induce a driver timeout.
712 addr ^= PCI_VPD_ADDR_F;
713 *paddr = cpu_to_le16(addr);
718 /* Permissions for Vital Product Data capability */
719 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
721 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
724 perm->writefn = vfio_vpd_config_write;
727 * We always virtualize the next field so we can remove
728 * capabilities from the chain if we want to.
730 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
733 * Both the address and data registers are virtualized to
734 * enable access through the pci_vpd_read/write functions
736 p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
737 p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
742 /* Permissions for PCI-X capability */
743 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
745 /* Alloc 24, but only 8 are used in v0 */
746 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))
749 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
751 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);
752 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);
756 static int vfio_exp_config_write(struct vfio_pci_device *vdev, int pos,
757 int count, struct perm_bits *perm,
758 int offset, __le32 val)
760 __le16 *ctrl = (__le16 *)(vdev->vconfig + pos -
761 offset + PCI_EXP_DEVCTL);
762 int readrq = le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ;
764 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
769 * The FLR bit is virtualized, if set and the device supports PCIe
770 * FLR, issue a reset_function. Regardless, clear the bit, the spec
771 * requires it to be always read as zero. NB, reset_function might
772 * not use a PCIe FLR, we don't have that level of granularity.
774 if (*ctrl & cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR)) {
778 *ctrl &= ~cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR);
780 ret = pci_user_read_config_dword(vdev->pdev,
781 pos - offset + PCI_EXP_DEVCAP,
784 if (!ret && (cap & PCI_EXP_DEVCAP_FLR))
785 pci_try_reset_function(vdev->pdev);
789 * MPS is virtualized to the user, writes do not change the physical
790 * register since determining a proper MPS value requires a system wide
791 * device view. The MRRS is largely independent of MPS, but since the
792 * user does not have that system-wide view, they might set a safe, but
793 * inefficiently low value. Here we allow writes through to hardware,
794 * but we set the floor to the physical device MPS setting, so that
795 * we can at least use full TLPs, as defined by the MPS value.
797 * NB, if any devices actually depend on an artificially low MRRS
798 * setting, this will need to be revisited, perhaps with a quirk
799 * though pcie_set_readrq().
801 if (readrq != (le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ)) {
803 ((le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ) >> 12);
804 readrq = max(readrq, pcie_get_mps(vdev->pdev));
806 pcie_set_readrq(vdev->pdev, readrq);
812 /* Permissions for PCI Express capability */
813 static int __init init_pci_cap_exp_perm(struct perm_bits *perm)
815 /* Alloc larger of two possible sizes */
816 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))
819 perm->writefn = vfio_exp_config_write;
821 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
824 * Allow writes to device control fields, except devctl_phantom,
825 * which could confuse IOMMU, MPS, which can break communication
826 * with other physical devices, and the ARI bit in devctl2, which
827 * is set at probe time. FLR and MRRS get virtualized via our
830 p_setw(perm, PCI_EXP_DEVCTL,
831 PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_PAYLOAD |
832 PCI_EXP_DEVCTL_READRQ, ~PCI_EXP_DEVCTL_PHANTOM);
833 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
837 static int vfio_af_config_write(struct vfio_pci_device *vdev, int pos,
838 int count, struct perm_bits *perm,
839 int offset, __le32 val)
841 u8 *ctrl = vdev->vconfig + pos - offset + PCI_AF_CTRL;
843 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
848 * The FLR bit is virtualized, if set and the device supports AF
849 * FLR, issue a reset_function. Regardless, clear the bit, the spec
850 * requires it to be always read as zero. NB, reset_function might
851 * not use an AF FLR, we don't have that level of granularity.
853 if (*ctrl & PCI_AF_CTRL_FLR) {
857 *ctrl &= ~PCI_AF_CTRL_FLR;
859 ret = pci_user_read_config_byte(vdev->pdev,
860 pos - offset + PCI_AF_CAP,
863 if (!ret && (cap & PCI_AF_CAP_FLR) && (cap & PCI_AF_CAP_TP))
864 pci_try_reset_function(vdev->pdev);
870 /* Permissions for Advanced Function capability */
871 static int __init init_pci_cap_af_perm(struct perm_bits *perm)
873 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))
876 perm->writefn = vfio_af_config_write;
878 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
879 p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR);
883 /* Permissions for Advanced Error Reporting extended capability */
884 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
888 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))
892 * Virtualize the first dword of all express capabilities
893 * because it includes the next pointer. This lets us later
894 * remove capabilities from the chain if we need to.
896 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
898 /* Writable bits mask */
899 mask = PCI_ERR_UNC_UND | /* Undefined */
900 PCI_ERR_UNC_DLP | /* Data Link Protocol */
901 PCI_ERR_UNC_SURPDN | /* Surprise Down */
902 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */
903 PCI_ERR_UNC_FCP | /* Flow Control Protocol */
904 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */
905 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */
906 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */
907 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */
908 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */
909 PCI_ERR_UNC_ECRC | /* ECRC Error Status */
910 PCI_ERR_UNC_UNSUP | /* Unsupported Request */
911 PCI_ERR_UNC_ACSV | /* ACS Violation */
912 PCI_ERR_UNC_INTN | /* internal error */
913 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */
914 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */
915 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */
916 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);
917 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);
918 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);
920 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */
921 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */
922 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */
923 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */
924 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */
925 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */
926 PCI_ERR_COR_INTERNAL | /* Corrected Internal */
927 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */
928 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);
929 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);
931 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */
932 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */
933 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);
937 /* Permissions for Power Budgeting extended capability */
938 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)
940 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))
943 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
945 /* Writing the data selector is OK, the info is still read-only */
946 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);
951 * Initialize the shared permission tables
953 void vfio_pci_uninit_perm_bits(void)
955 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]);
957 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]);
958 free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]);
959 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]);
960 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]);
961 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]);
963 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
964 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
967 int __init vfio_pci_init_perm_bits(void)
971 /* Basic config space */
972 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]);
975 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]);
976 ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]);
977 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]);
978 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write;
979 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]);
980 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]);
982 /* Extended capabilities */
983 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
984 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
985 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write;
988 vfio_pci_uninit_perm_bits();
993 static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos)
996 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE :
997 PCI_STD_HEADER_SIZEOF;
998 cap = vdev->pci_config_map[pos];
1000 if (cap == PCI_CAP_ID_BASIC)
1003 /* XXX Can we have to abutting capabilities of the same type? */
1004 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap)
1010 static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos,
1011 int count, struct perm_bits *perm,
1012 int offset, __le32 *val)
1014 /* Update max available queue size from msi_qmax */
1015 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1019 start = vfio_find_cap_start(vdev, pos);
1021 flags = (__le16 *)&vdev->vconfig[start];
1023 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK);
1024 *flags |= cpu_to_le16(vdev->msi_qmax << 1);
1027 return vfio_default_config_read(vdev, pos, count, perm, offset, val);
1030 static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos,
1031 int count, struct perm_bits *perm,
1032 int offset, __le32 val)
1034 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
1038 /* Fixup and write configured queue size and enable to hardware */
1039 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1044 start = vfio_find_cap_start(vdev, pos);
1046 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS];
1048 flags = le16_to_cpu(*pflags);
1050 /* MSI is enabled via ioctl */
1052 flags &= ~PCI_MSI_FLAGS_ENABLE;
1054 /* Check queue size */
1055 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) {
1056 flags &= ~PCI_MSI_FLAGS_QSIZE;
1057 flags |= vdev->msi_qmax << 4;
1060 /* Write back to virt and to hardware */
1061 *pflags = cpu_to_le16(flags);
1062 ret = pci_user_write_config_word(vdev->pdev,
1063 start + PCI_MSI_FLAGS,
1066 return pcibios_err_to_errno(ret);
1073 * MSI determination is per-device, so this routine gets used beyond
1074 * initialization time. Don't add __init
1076 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)
1078 if (alloc_perm_bits(perm, len))
1081 perm->readfn = vfio_msi_config_read;
1082 perm->writefn = vfio_msi_config_write;
1084 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
1087 * The upper byte of the control register is reserved,
1088 * just setup the lower byte.
1090 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);
1091 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);
1092 if (flags & PCI_MSI_FLAGS_64BIT) {
1093 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);
1094 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);
1095 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1096 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);
1097 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);
1100 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);
1101 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1102 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);
1103 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);
1109 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
1110 static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos)
1112 struct pci_dev *pdev = vdev->pdev;
1116 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags);
1118 return pcibios_err_to_errno(ret);
1120 len = 10; /* Minimum size */
1121 if (flags & PCI_MSI_FLAGS_64BIT)
1123 if (flags & PCI_MSI_FLAGS_MASKBIT)
1129 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL);
1130 if (!vdev->msi_perm)
1133 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);
1135 kfree(vdev->msi_perm);
1142 /* Determine extended capability length for VC (2 & 9) and MFVC */
1143 static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos)
1145 struct pci_dev *pdev = vdev->pdev;
1147 int ret, evcc, phases, vc_arb;
1148 int len = PCI_CAP_VC_BASE_SIZEOF;
1150 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp);
1152 return pcibios_err_to_errno(ret);
1154 evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */
1155 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp);
1157 return pcibios_err_to_errno(ret);
1159 if (tmp & PCI_VC_CAP2_128_PHASE)
1161 else if (tmp & PCI_VC_CAP2_64_PHASE)
1163 else if (tmp & PCI_VC_CAP2_32_PHASE)
1168 vc_arb = phases * 4;
1171 * Port arbitration tables are root & switch only;
1172 * function arbitration tables are function 0 only.
1173 * In either case, we'll never let user write them so
1174 * we don't care how big they are
1176 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF;
1178 len = round_up(len, 16);
1184 static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos)
1186 struct pci_dev *pdev = vdev->pdev;
1193 case PCI_CAP_ID_MSI:
1194 return vfio_msi_cap_len(vdev, pos);
1195 case PCI_CAP_ID_PCIX:
1196 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word);
1198 return pcibios_err_to_errno(ret);
1200 if (PCI_X_CMD_VERSION(word)) {
1201 /* Test for extended capabilities */
1202 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
1203 vdev->extended_caps = (dword != 0);
1204 return PCI_CAP_PCIX_SIZEOF_V2;
1206 return PCI_CAP_PCIX_SIZEOF_V0;
1207 case PCI_CAP_ID_VNDR:
1208 /* length follows next field */
1209 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte);
1211 return pcibios_err_to_errno(ret);
1214 case PCI_CAP_ID_EXP:
1215 /* Test for extended capabilities */
1216 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
1217 vdev->extended_caps = (dword != 0);
1219 /* length based on version */
1220 if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1)
1221 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1;
1223 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2;
1225 ret = pci_read_config_byte(pdev, pos + 3, &byte);
1227 return pcibios_err_to_errno(ret);
1229 return (byte & HT_3BIT_CAP_MASK) ?
1230 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG;
1231 case PCI_CAP_ID_SATA:
1232 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte);
1234 return pcibios_err_to_errno(ret);
1236 byte &= PCI_SATA_REGS_MASK;
1237 if (byte == PCI_SATA_REGS_INLINE)
1238 return PCI_SATA_SIZEOF_LONG;
1240 return PCI_SATA_SIZEOF_SHORT;
1242 pr_warn("%s: %s unknown length for pci cap 0x%x@0x%x\n",
1243 dev_name(&pdev->dev), __func__, cap, pos);
1249 static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos)
1251 struct pci_dev *pdev = vdev->pdev;
1257 case PCI_EXT_CAP_ID_VNDR:
1258 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword);
1260 return pcibios_err_to_errno(ret);
1262 return dword >> PCI_VSEC_HDR_LEN_SHIFT;
1263 case PCI_EXT_CAP_ID_VC:
1264 case PCI_EXT_CAP_ID_VC9:
1265 case PCI_EXT_CAP_ID_MFVC:
1266 return vfio_vc_cap_len(vdev, epos);
1267 case PCI_EXT_CAP_ID_ACS:
1268 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte);
1270 return pcibios_err_to_errno(ret);
1272 if (byte & PCI_ACS_EC) {
1275 ret = pci_read_config_byte(pdev,
1276 epos + PCI_ACS_EGRESS_BITS,
1279 return pcibios_err_to_errno(ret);
1281 bits = byte ? round_up(byte, 32) : 256;
1282 return 8 + (bits / 8);
1286 case PCI_EXT_CAP_ID_REBAR:
1287 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte);
1289 return pcibios_err_to_errno(ret);
1291 byte &= PCI_REBAR_CTRL_NBAR_MASK;
1292 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT;
1294 return 4 + (byte * 8);
1295 case PCI_EXT_CAP_ID_DPA:
1296 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte);
1298 return pcibios_err_to_errno(ret);
1300 byte &= PCI_DPA_CAP_SUBSTATE_MASK;
1301 return PCI_DPA_BASE_SIZEOF + byte + 1;
1302 case PCI_EXT_CAP_ID_TPH:
1303 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword);
1305 return pcibios_err_to_errno(ret);
1307 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) {
1310 sts = dword & PCI_TPH_CAP_ST_MASK;
1311 sts >>= PCI_TPH_CAP_ST_SHIFT;
1312 return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2;
1314 return PCI_TPH_BASE_SIZEOF;
1316 pr_warn("%s: %s unknown length for pci ecap 0x%x@0x%x\n",
1317 dev_name(&pdev->dev), __func__, ecap, epos);
1323 static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev,
1324 int offset, int size)
1326 struct pci_dev *pdev = vdev->pdev;
1330 * We try to read physical config space in the largest chunks
1331 * we can, assuming that all of the fields support dword access.
1332 * pci_save_state() makes this same assumption and seems to do ok.
1337 if (size >= 4 && !(offset % 4)) {
1338 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset];
1341 ret = pci_read_config_dword(pdev, offset, &dword);
1344 *dwordp = cpu_to_le32(dword);
1346 } else if (size >= 2 && !(offset % 2)) {
1347 __le16 *wordp = (__le16 *)&vdev->vconfig[offset];
1350 ret = pci_read_config_word(pdev, offset, &word);
1353 *wordp = cpu_to_le16(word);
1356 u8 *byte = &vdev->vconfig[offset];
1357 ret = pci_read_config_byte(pdev, offset, byte);
1370 static int vfio_cap_init(struct vfio_pci_device *vdev)
1372 struct pci_dev *pdev = vdev->pdev;
1373 u8 *map = vdev->pci_config_map;
1376 int loops, ret, caps = 0;
1378 /* Any capabilities? */
1379 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
1383 if (!(status & PCI_STATUS_CAP_LIST))
1384 return 0; /* Done */
1386 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
1390 /* Mark the previous position in case we want to skip a capability */
1391 prev = &vdev->vconfig[PCI_CAPABILITY_LIST];
1393 /* We can bound our loop, capabilities are dword aligned */
1394 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;
1395 while (pos && loops--) {
1399 ret = pci_read_config_byte(pdev, pos, &cap);
1403 ret = pci_read_config_byte(pdev,
1404 pos + PCI_CAP_LIST_NEXT, &next);
1409 * ID 0 is a NULL capability, conflicting with our fake
1410 * PCI_CAP_ID_BASIC. As it has no content, consider it
1413 if (cap && cap <= PCI_CAP_ID_MAX) {
1414 len = pci_cap_length[cap];
1415 if (len == 0xFF) { /* Variable length */
1416 len = vfio_cap_len(vdev, cap, pos);
1423 pr_info("%s: %s hiding cap 0x%x\n",
1424 __func__, dev_name(&pdev->dev), cap);
1430 /* Sanity check, do we overlap other capabilities? */
1431 for (i = 0; i < len; i++) {
1432 if (likely(map[pos + i] == PCI_CAP_ID_INVALID))
1435 pr_warn("%s: %s pci config conflict @0x%x, was cap 0x%x now cap 0x%x\n",
1436 __func__, dev_name(&pdev->dev),
1437 pos + i, map[pos + i], cap);
1440 memset(map + pos, cap, len);
1441 ret = vfio_fill_vconfig_bytes(vdev, pos, len);
1445 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT];
1450 /* If we didn't fill any capabilities, clear the status flag */
1452 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS];
1453 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST);
1459 static int vfio_ecap_init(struct vfio_pci_device *vdev)
1461 struct pci_dev *pdev = vdev->pdev;
1462 u8 *map = vdev->pci_config_map;
1464 __le32 *prev = NULL;
1465 int loops, ret, ecaps = 0;
1467 if (!vdev->extended_caps)
1470 epos = PCI_CFG_SPACE_SIZE;
1472 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF;
1474 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) {
1478 bool hidden = false;
1480 ret = pci_read_config_dword(pdev, epos, &header);
1484 ecap = PCI_EXT_CAP_ID(header);
1486 if (ecap <= PCI_EXT_CAP_ID_MAX) {
1487 len = pci_ext_cap_length[ecap];
1489 len = vfio_ext_cap_len(vdev, ecap, epos);
1496 pr_info("%s: %s hiding ecap 0x%x@0x%x\n",
1497 __func__, dev_name(&pdev->dev), ecap, epos);
1499 /* If not the first in the chain, we can skip over it */
1501 u32 val = epos = PCI_EXT_CAP_NEXT(header);
1502 *prev &= cpu_to_le32(~(0xffcU << 20));
1503 *prev |= cpu_to_le32(val << 20);
1508 * Otherwise, fill in a placeholder, the direct
1509 * readfn will virtualize this automatically
1511 len = PCI_CAP_SIZEOF;
1515 for (i = 0; i < len; i++) {
1516 if (likely(map[epos + i] == PCI_CAP_ID_INVALID))
1519 pr_warn("%s: %s pci config conflict @0x%x, was ecap 0x%x now ecap 0x%x\n",
1520 __func__, dev_name(&pdev->dev),
1521 epos + i, map[epos + i], ecap);
1525 * Even though ecap is 2 bytes, we're currently a long way
1526 * from exceeding 1 byte capabilities. If we ever make it
1527 * up to 0xFF we'll need to up this to a two-byte, byte map.
1529 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID);
1531 memset(map + epos, ecap, len);
1532 ret = vfio_fill_vconfig_bytes(vdev, epos, len);
1537 * If we're just using this capability to anchor the list,
1538 * hide the real ID. Only count real ecaps. XXX PCI spec
1539 * indicates to use cap id = 0, version = 0, next = 0 if
1540 * ecaps are absent, hope users check all the way to next.
1543 *(__le32 *)&vdev->vconfig[epos] &=
1544 cpu_to_le32((0xffcU << 20));
1548 prev = (__le32 *)&vdev->vconfig[epos];
1549 epos = PCI_EXT_CAP_NEXT(header);
1553 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;
1559 * For each device we allocate a pci_config_map that indicates the
1560 * capability occupying each dword and thus the struct perm_bits we
1561 * use for read and write. We also allocate a virtualized config
1562 * space which tracks reads and writes to bits that we emulate for
1563 * the user. Initial values filled from device.
1565 * Using shared stuct perm_bits between all vfio-pci devices saves
1566 * us from allocating cfg_size buffers for virt and write for every
1567 * device. We could remove vconfig and allocate individual buffers
1568 * for each area requring emulated bits, but the array of pointers
1569 * would be comparable in size (at least for standard config space).
1571 int vfio_config_init(struct vfio_pci_device *vdev)
1573 struct pci_dev *pdev = vdev->pdev;
1578 * Config space, caps and ecaps are all dword aligned, so we could
1579 * use one byte per dword to record the type. However, there are
1580 * no requiremenst on the length of a capability, so the gap between
1581 * capabilities needs byte granularity.
1583 map = kmalloc(pdev->cfg_size, GFP_KERNEL);
1587 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL);
1593 vdev->pci_config_map = map;
1594 vdev->vconfig = vconfig;
1596 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF);
1597 memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID,
1598 pdev->cfg_size - PCI_STD_HEADER_SIZEOF);
1600 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF);
1604 vdev->bardirty = true;
1607 * XXX can we just pci_load_saved_state/pci_restore_state?
1608 * may need to rebuild vconfig after that
1611 /* For restore after reset */
1612 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
1613 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]);
1614 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);
1615 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]);
1616 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]);
1617 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]);
1618 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);
1620 if (pdev->is_virtfn) {
1621 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);
1622 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
1625 if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX))
1626 vconfig[PCI_INTERRUPT_PIN] = 0;
1628 ret = vfio_cap_init(vdev);
1632 ret = vfio_ecap_init(vdev);
1640 vdev->pci_config_map = NULL;
1642 vdev->vconfig = NULL;
1643 return pcibios_err_to_errno(ret);
1646 void vfio_config_free(struct vfio_pci_device *vdev)
1648 kfree(vdev->vconfig);
1649 vdev->vconfig = NULL;
1650 kfree(vdev->pci_config_map);
1651 vdev->pci_config_map = NULL;
1652 if (vdev->msi_perm) {
1653 free_perm_bits(vdev->msi_perm);
1654 kfree(vdev->msi_perm);
1655 vdev->msi_perm = NULL;
1660 * Find the remaining number of bytes in a dword that match the given
1661 * position. Stop at either the end of the capability or the dword boundary.
1663 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev,
1666 u8 cap = vdev->pci_config_map[pos];
1669 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++)
1675 static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf,
1676 size_t count, loff_t *ppos, bool iswrite)
1678 struct pci_dev *pdev = vdev->pdev;
1679 struct perm_bits *perm;
1681 int cap_start = 0, offset;
1685 if (*ppos < 0 || *ppos >= pdev->cfg_size ||
1686 *ppos + count > pdev->cfg_size)
1690 * Chop accesses into aligned chunks containing no more than a
1691 * single capability. Caller increments to the next chunk.
1693 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos));
1694 if (count >= 4 && !(*ppos % 4))
1696 else if (count >= 2 && !(*ppos % 2))
1703 cap_id = vdev->pci_config_map[*ppos];
1705 if (cap_id == PCI_CAP_ID_INVALID) {
1706 perm = &unassigned_perms;
1709 if (*ppos >= PCI_CFG_SPACE_SIZE) {
1710 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX);
1712 perm = &ecap_perms[cap_id];
1713 cap_start = vfio_find_cap_start(vdev, *ppos);
1715 WARN_ON(cap_id > PCI_CAP_ID_MAX);
1717 perm = &cap_perms[cap_id];
1719 if (cap_id == PCI_CAP_ID_MSI)
1720 perm = vdev->msi_perm;
1722 if (cap_id > PCI_CAP_ID_BASIC)
1723 cap_start = vfio_find_cap_start(vdev, *ppos);
1727 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC);
1728 WARN_ON(cap_start > *ppos);
1730 offset = *ppos - cap_start;
1736 if (copy_from_user(&val, buf, count))
1739 ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
1742 ret = perm->readfn(vdev, *ppos, count,
1743 perm, offset, &val);
1748 if (copy_to_user(buf, &val, count))
1755 ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf,
1756 size_t count, loff_t *ppos, bool iswrite)
1762 pos &= VFIO_PCI_OFFSET_MASK;
1765 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite);