1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2020 Mellanox Technologies Ltd. */
4 #include <linux/vdpa.h>
5 #include <uapi/linux/virtio_ids.h>
6 #include <linux/virtio_config.h>
7 #include <linux/mlx5/qp.h>
8 #include <linux/mlx5/device.h>
9 #include <linux/mlx5/vport.h>
10 #include <linux/mlx5/fs.h>
11 #include <linux/mlx5/device.h>
12 #include <linux/mlx5/mpfs.h>
13 #include "mlx5_vnet.h"
14 #include "mlx5_vdpa_ifc.h"
15 #include "mlx5_vdpa.h"
17 #define to_mvdev(__vdev) container_of((__vdev), struct mlx5_vdpa_dev, vdev)
19 #define VALID_FEATURES_MASK \
20 (BIT_ULL(VIRTIO_NET_F_CSUM) | BIT_ULL(VIRTIO_NET_F_GUEST_CSUM) | \
21 BIT_ULL(VIRTIO_NET_F_CTRL_GUEST_OFFLOADS) | BIT_ULL(VIRTIO_NET_F_MTU) | BIT_ULL(VIRTIO_NET_F_MAC) | \
22 BIT_ULL(VIRTIO_NET_F_GUEST_TSO4) | BIT_ULL(VIRTIO_NET_F_GUEST_TSO6) | \
23 BIT_ULL(VIRTIO_NET_F_GUEST_ECN) | BIT_ULL(VIRTIO_NET_F_GUEST_UFO) | BIT_ULL(VIRTIO_NET_F_HOST_TSO4) | \
24 BIT_ULL(VIRTIO_NET_F_HOST_TSO6) | BIT_ULL(VIRTIO_NET_F_HOST_ECN) | BIT_ULL(VIRTIO_NET_F_HOST_UFO) | \
25 BIT_ULL(VIRTIO_NET_F_MRG_RXBUF) | BIT_ULL(VIRTIO_NET_F_STATUS) | BIT_ULL(VIRTIO_NET_F_CTRL_VQ) | \
26 BIT_ULL(VIRTIO_NET_F_CTRL_RX) | BIT_ULL(VIRTIO_NET_F_CTRL_VLAN) | \
27 BIT_ULL(VIRTIO_NET_F_CTRL_RX_EXTRA) | BIT_ULL(VIRTIO_NET_F_GUEST_ANNOUNCE) | \
28 BIT_ULL(VIRTIO_NET_F_MQ) | BIT_ULL(VIRTIO_NET_F_CTRL_MAC_ADDR) | BIT_ULL(VIRTIO_NET_F_HASH_REPORT) | \
29 BIT_ULL(VIRTIO_NET_F_RSS) | BIT_ULL(VIRTIO_NET_F_RSC_EXT) | BIT_ULL(VIRTIO_NET_F_STANDBY) | \
30 BIT_ULL(VIRTIO_NET_F_SPEED_DUPLEX) | BIT_ULL(VIRTIO_F_NOTIFY_ON_EMPTY) | \
31 BIT_ULL(VIRTIO_F_ANY_LAYOUT) | BIT_ULL(VIRTIO_F_VERSION_1) | BIT_ULL(VIRTIO_F_ACCESS_PLATFORM) | \
32 BIT_ULL(VIRTIO_F_RING_PACKED) | BIT_ULL(VIRTIO_F_ORDER_PLATFORM) | BIT_ULL(VIRTIO_F_SR_IOV))
34 #define VALID_STATUS_MASK \
35 (VIRTIO_CONFIG_S_ACKNOWLEDGE | VIRTIO_CONFIG_S_DRIVER | VIRTIO_CONFIG_S_DRIVER_OK | \
36 VIRTIO_CONFIG_S_FEATURES_OK | VIRTIO_CONFIG_S_NEEDS_RESET | VIRTIO_CONFIG_S_FAILED)
38 struct mlx5_vdpa_net_resources {
46 struct mlx5_vdpa_cq_buf {
47 struct mlx5_frag_buf_ctrl fbc;
48 struct mlx5_frag_buf frag_buf;
54 struct mlx5_core_cq mcq;
55 struct mlx5_vdpa_cq_buf buf;
60 struct mlx5_vdpa_umem {
61 struct mlx5_frag_buf_ctrl fbc;
62 struct mlx5_frag_buf frag_buf;
68 struct mlx5_core_qp mqp;
69 struct mlx5_frag_buf frag_buf;
75 struct mlx5_vq_restore_info {
83 struct vdpa_callback cb;
87 struct mlx5_vdpa_virtqueue {
93 struct vdpa_callback event_cb;
95 /* Resources for implementing the notification channel from the device
96 * to the driver. fwqp is the firmware end of an RC connection; the
97 * other end is vqqp used by the driver. cq is is where completions are
100 struct mlx5_vdpa_cq cq;
101 struct mlx5_vdpa_qp fwqp;
102 struct mlx5_vdpa_qp vqqp;
104 /* umem resources are required for the virtqueue operation. They're use
105 * is internal and they must be provided by the driver.
107 struct mlx5_vdpa_umem umem1;
108 struct mlx5_vdpa_umem umem2;
109 struct mlx5_vdpa_umem umem3;
114 struct mlx5_vdpa_net *ndev;
119 /* keep last in the struct */
120 struct mlx5_vq_restore_info ri;
123 /* We will remove this limitation once mlx5_vdpa_alloc_resources()
124 * provides for driver space allocation
126 #define MLX5_MAX_SUPPORTED_VQS 16
128 struct mlx5_vdpa_net {
129 struct mlx5_vdpa_dev mvdev;
130 struct mlx5_vdpa_net_resources res;
131 struct virtio_net_config config;
132 struct mlx5_vdpa_virtqueue vqs[MLX5_MAX_SUPPORTED_VQS];
134 /* Serialize vq resources creation and destruction. This is required
135 * since memory map might change and we need to destroy and create
136 * resources while driver in operational.
138 struct mutex reslock;
139 struct mlx5_flow_table *rxft;
140 struct mlx5_fc *rx_counter;
141 struct mlx5_flow_handle *rx_rule;
146 static void free_resources(struct mlx5_vdpa_net *ndev);
147 static void init_mvqs(struct mlx5_vdpa_net *ndev);
148 static int setup_driver(struct mlx5_vdpa_net *ndev);
149 static void teardown_driver(struct mlx5_vdpa_net *ndev);
151 static bool mlx5_vdpa_debug;
153 #define MLX5_LOG_VIO_FLAG(_feature) \
155 if (features & BIT_ULL(_feature)) \
156 mlx5_vdpa_info(mvdev, "%s\n", #_feature); \
159 #define MLX5_LOG_VIO_STAT(_status) \
161 if (status & (_status)) \
162 mlx5_vdpa_info(mvdev, "%s\n", #_status); \
165 static void print_status(struct mlx5_vdpa_dev *mvdev, u8 status, bool set)
167 if (status & ~VALID_STATUS_MASK)
168 mlx5_vdpa_warn(mvdev, "Warning: there are invalid status bits 0x%x\n",
169 status & ~VALID_STATUS_MASK);
171 if (!mlx5_vdpa_debug)
174 mlx5_vdpa_info(mvdev, "driver status %s", set ? "set" : "get");
175 if (set && !status) {
176 mlx5_vdpa_info(mvdev, "driver resets the device\n");
180 MLX5_LOG_VIO_STAT(VIRTIO_CONFIG_S_ACKNOWLEDGE);
181 MLX5_LOG_VIO_STAT(VIRTIO_CONFIG_S_DRIVER);
182 MLX5_LOG_VIO_STAT(VIRTIO_CONFIG_S_DRIVER_OK);
183 MLX5_LOG_VIO_STAT(VIRTIO_CONFIG_S_FEATURES_OK);
184 MLX5_LOG_VIO_STAT(VIRTIO_CONFIG_S_NEEDS_RESET);
185 MLX5_LOG_VIO_STAT(VIRTIO_CONFIG_S_FAILED);
188 static void print_features(struct mlx5_vdpa_dev *mvdev, u64 features, bool set)
190 if (features & ~VALID_FEATURES_MASK)
191 mlx5_vdpa_warn(mvdev, "There are invalid feature bits 0x%llx\n",
192 features & ~VALID_FEATURES_MASK);
194 if (!mlx5_vdpa_debug)
197 mlx5_vdpa_info(mvdev, "driver %s feature bits:\n", set ? "sets" : "reads");
199 mlx5_vdpa_info(mvdev, "all feature bits are cleared\n");
201 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_CSUM);
202 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_GUEST_CSUM);
203 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_CTRL_GUEST_OFFLOADS);
204 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_MTU);
205 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_MAC);
206 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_GUEST_TSO4);
207 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_GUEST_TSO6);
208 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_GUEST_ECN);
209 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_GUEST_UFO);
210 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_HOST_TSO4);
211 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_HOST_TSO6);
212 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_HOST_ECN);
213 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_HOST_UFO);
214 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_MRG_RXBUF);
215 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_STATUS);
216 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_CTRL_VQ);
217 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_CTRL_RX);
218 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_CTRL_VLAN);
219 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_CTRL_RX_EXTRA);
220 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_GUEST_ANNOUNCE);
221 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_MQ);
222 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_CTRL_MAC_ADDR);
223 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_HASH_REPORT);
224 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_RSS);
225 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_RSC_EXT);
226 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_STANDBY);
227 MLX5_LOG_VIO_FLAG(VIRTIO_NET_F_SPEED_DUPLEX);
228 MLX5_LOG_VIO_FLAG(VIRTIO_F_NOTIFY_ON_EMPTY);
229 MLX5_LOG_VIO_FLAG(VIRTIO_F_ANY_LAYOUT);
230 MLX5_LOG_VIO_FLAG(VIRTIO_F_VERSION_1);
231 MLX5_LOG_VIO_FLAG(VIRTIO_F_ACCESS_PLATFORM);
232 MLX5_LOG_VIO_FLAG(VIRTIO_F_RING_PACKED);
233 MLX5_LOG_VIO_FLAG(VIRTIO_F_ORDER_PLATFORM);
234 MLX5_LOG_VIO_FLAG(VIRTIO_F_SR_IOV);
237 static int create_tis(struct mlx5_vdpa_net *ndev)
239 struct mlx5_vdpa_dev *mvdev = &ndev->mvdev;
240 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
244 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
245 MLX5_SET(tisc, tisc, transport_domain, ndev->res.tdn);
246 err = mlx5_vdpa_create_tis(mvdev, in, &ndev->res.tisn);
248 mlx5_vdpa_warn(mvdev, "create TIS (%d)\n", err);
253 static void destroy_tis(struct mlx5_vdpa_net *ndev)
255 mlx5_vdpa_destroy_tis(&ndev->mvdev, ndev->res.tisn);
258 #define MLX5_VDPA_CQE_SIZE 64
259 #define MLX5_VDPA_LOG_CQE_SIZE ilog2(MLX5_VDPA_CQE_SIZE)
261 static int cq_frag_buf_alloc(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_cq_buf *buf, int nent)
263 struct mlx5_frag_buf *frag_buf = &buf->frag_buf;
264 u8 log_wq_stride = MLX5_VDPA_LOG_CQE_SIZE;
265 u8 log_wq_sz = MLX5_VDPA_LOG_CQE_SIZE;
268 err = mlx5_frag_buf_alloc_node(ndev->mvdev.mdev, nent * MLX5_VDPA_CQE_SIZE, frag_buf,
269 ndev->mvdev.mdev->priv.numa_node);
273 mlx5_init_fbc(frag_buf->frags, log_wq_stride, log_wq_sz, &buf->fbc);
275 buf->cqe_size = MLX5_VDPA_CQE_SIZE;
281 static int umem_frag_buf_alloc(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_umem *umem, int size)
283 struct mlx5_frag_buf *frag_buf = &umem->frag_buf;
285 return mlx5_frag_buf_alloc_node(ndev->mvdev.mdev, size, frag_buf,
286 ndev->mvdev.mdev->priv.numa_node);
289 static void cq_frag_buf_free(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_cq_buf *buf)
291 mlx5_frag_buf_free(ndev->mvdev.mdev, &buf->frag_buf);
294 static void *get_cqe(struct mlx5_vdpa_cq *vcq, int n)
296 return mlx5_frag_buf_get_wqe(&vcq->buf.fbc, n);
299 static void cq_frag_buf_init(struct mlx5_vdpa_cq *vcq, struct mlx5_vdpa_cq_buf *buf)
301 struct mlx5_cqe64 *cqe64;
305 for (i = 0; i < buf->nent; i++) {
306 cqe = get_cqe(vcq, i);
308 cqe64->op_own = MLX5_CQE_INVALID << 4;
312 static void *get_sw_cqe(struct mlx5_vdpa_cq *cq, int n)
314 struct mlx5_cqe64 *cqe64 = get_cqe(cq, n & (cq->cqe - 1));
316 if (likely(get_cqe_opcode(cqe64) != MLX5_CQE_INVALID) &&
317 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & cq->cqe)))
323 static void rx_post(struct mlx5_vdpa_qp *vqp, int n)
326 vqp->db.db[0] = cpu_to_be32(vqp->head);
329 static void qp_prepare(struct mlx5_vdpa_net *ndev, bool fw, void *in,
330 struct mlx5_vdpa_virtqueue *mvq, u32 num_ent)
332 struct mlx5_vdpa_qp *vqp;
336 vqp = fw ? &mvq->fwqp : &mvq->vqqp;
337 MLX5_SET(create_qp_in, in, uid, ndev->mvdev.res.uid);
338 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
340 /* Firmware QP is allocated by the driver for the firmware's
341 * use so we can skip part of the params as they will be chosen by firmware
343 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
344 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
345 MLX5_SET(qpc, qpc, no_sq, 1);
349 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
350 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
351 MLX5_SET(qpc, qpc, pd, ndev->mvdev.res.pdn);
352 MLX5_SET(qpc, qpc, mtu, MLX5_QPC_MTU_256_BYTES);
353 MLX5_SET(qpc, qpc, uar_page, ndev->mvdev.res.uar->index);
354 MLX5_SET(qpc, qpc, log_page_size, vqp->frag_buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
355 MLX5_SET(qpc, qpc, no_sq, 1);
356 MLX5_SET(qpc, qpc, cqn_rcv, mvq->cq.mcq.cqn);
357 MLX5_SET(qpc, qpc, log_rq_size, ilog2(num_ent));
358 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
359 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, in, pas);
360 mlx5_fill_page_frag_array(&vqp->frag_buf, pas);
363 static int rq_buf_alloc(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_qp *vqp, u32 num_ent)
365 return mlx5_frag_buf_alloc_node(ndev->mvdev.mdev,
366 num_ent * sizeof(struct mlx5_wqe_data_seg), &vqp->frag_buf,
367 ndev->mvdev.mdev->priv.numa_node);
370 static void rq_buf_free(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_qp *vqp)
372 mlx5_frag_buf_free(ndev->mvdev.mdev, &vqp->frag_buf);
375 static int qp_create(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq,
376 struct mlx5_vdpa_qp *vqp)
378 struct mlx5_core_dev *mdev = ndev->mvdev.mdev;
379 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
380 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
387 err = rq_buf_alloc(ndev, vqp, mvq->num_ent);
391 err = mlx5_db_alloc(ndev->mvdev.mdev, &vqp->db);
394 inlen += vqp->frag_buf.npages * sizeof(__be64);
397 in = kzalloc(inlen, GFP_KERNEL);
403 qp_prepare(ndev, vqp->fw, in, mvq, mvq->num_ent);
404 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
405 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
406 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
407 MLX5_SET(qpc, qpc, pd, ndev->mvdev.res.pdn);
408 MLX5_SET(qpc, qpc, mtu, MLX5_QPC_MTU_256_BYTES);
410 MLX5_SET64(qpc, qpc, dbr_addr, vqp->db.dma);
411 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
412 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
417 vqp->mqp.uid = ndev->mvdev.res.uid;
418 vqp->mqp.qpn = MLX5_GET(create_qp_out, out, qpn);
421 rx_post(vqp, mvq->num_ent);
427 mlx5_db_free(ndev->mvdev.mdev, &vqp->db);
430 rq_buf_free(ndev, vqp);
435 static void qp_destroy(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_qp *vqp)
437 u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {};
439 MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP);
440 MLX5_SET(destroy_qp_in, in, qpn, vqp->mqp.qpn);
441 MLX5_SET(destroy_qp_in, in, uid, ndev->mvdev.res.uid);
442 if (mlx5_cmd_exec_in(ndev->mvdev.mdev, destroy_qp, in))
443 mlx5_vdpa_warn(&ndev->mvdev, "destroy qp 0x%x\n", vqp->mqp.qpn);
445 mlx5_db_free(ndev->mvdev.mdev, &vqp->db);
446 rq_buf_free(ndev, vqp);
450 static void *next_cqe_sw(struct mlx5_vdpa_cq *cq)
452 return get_sw_cqe(cq, cq->mcq.cons_index);
455 static int mlx5_vdpa_poll_one(struct mlx5_vdpa_cq *vcq)
457 struct mlx5_cqe64 *cqe64;
459 cqe64 = next_cqe_sw(vcq);
463 vcq->mcq.cons_index++;
467 static void mlx5_vdpa_handle_completions(struct mlx5_vdpa_virtqueue *mvq, int num)
469 mlx5_cq_set_ci(&mvq->cq.mcq);
471 /* make sure CQ cosumer update is visible to the hardware before updating
472 * RX doorbell record.
475 rx_post(&mvq->vqqp, num);
476 if (mvq->event_cb.callback)
477 mvq->event_cb.callback(mvq->event_cb.private);
480 static void mlx5_vdpa_cq_comp(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe)
482 struct mlx5_vdpa_virtqueue *mvq = container_of(mcq, struct mlx5_vdpa_virtqueue, cq.mcq);
483 struct mlx5_vdpa_net *ndev = mvq->ndev;
484 void __iomem *uar_page = ndev->mvdev.res.uar->map;
487 while (!mlx5_vdpa_poll_one(&mvq->cq)) {
489 if (num > mvq->num_ent / 2) {
490 /* If completions keep coming while we poll, we want to
491 * let the hardware know that we consumed them by
492 * updating the doorbell record. We also let vdpa core
493 * know about this so it passes it on the virtio driver
496 mlx5_vdpa_handle_completions(mvq, num);
502 mlx5_vdpa_handle_completions(mvq, num);
504 mlx5_cq_arm(&mvq->cq.mcq, MLX5_CQ_DB_REQ_NOT, uar_page, mvq->cq.mcq.cons_index);
507 static int cq_create(struct mlx5_vdpa_net *ndev, u16 idx, u32 num_ent)
509 struct mlx5_vdpa_virtqueue *mvq = &ndev->vqs[idx];
510 struct mlx5_core_dev *mdev = ndev->mvdev.mdev;
511 void __iomem *uar_page = ndev->mvdev.res.uar->map;
512 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
513 struct mlx5_vdpa_cq *vcq = &mvq->cq;
521 err = mlx5_db_alloc(mdev, &vcq->db);
525 vcq->mcq.set_ci_db = vcq->db.db;
526 vcq->mcq.arm_db = vcq->db.db + 1;
527 vcq->mcq.cqe_sz = 64;
529 err = cq_frag_buf_alloc(ndev, &vcq->buf, num_ent);
533 cq_frag_buf_init(vcq, &vcq->buf);
535 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
536 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * vcq->buf.frag_buf.npages;
537 in = kzalloc(inlen, GFP_KERNEL);
543 MLX5_SET(create_cq_in, in, uid, ndev->mvdev.res.uid);
544 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas);
545 mlx5_fill_page_frag_array(&vcq->buf.frag_buf, pas);
547 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
548 MLX5_SET(cqc, cqc, log_page_size, vcq->buf.frag_buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
550 /* Use vector 0 by default. Consider adding code to choose least used
553 err = mlx5_vector2eqn(mdev, 0, &eqn);
557 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
558 MLX5_SET(cqc, cqc, log_cq_size, ilog2(num_ent));
559 MLX5_SET(cqc, cqc, uar_page, ndev->mvdev.res.uar->index);
560 MLX5_SET(cqc, cqc, c_eqn, eqn);
561 MLX5_SET64(cqc, cqc, dbr_addr, vcq->db.dma);
563 err = mlx5_core_create_cq(mdev, &vcq->mcq, in, inlen, out, sizeof(out));
567 vcq->mcq.comp = mlx5_vdpa_cq_comp;
569 vcq->mcq.set_ci_db = vcq->db.db;
570 vcq->mcq.arm_db = vcq->db.db + 1;
571 mlx5_cq_arm(&mvq->cq.mcq, MLX5_CQ_DB_REQ_NOT, uar_page, mvq->cq.mcq.cons_index);
578 cq_frag_buf_free(ndev, &vcq->buf);
580 mlx5_db_free(ndev->mvdev.mdev, &vcq->db);
584 static void cq_destroy(struct mlx5_vdpa_net *ndev, u16 idx)
586 struct mlx5_vdpa_virtqueue *mvq = &ndev->vqs[idx];
587 struct mlx5_core_dev *mdev = ndev->mvdev.mdev;
588 struct mlx5_vdpa_cq *vcq = &mvq->cq;
590 if (mlx5_core_destroy_cq(mdev, &vcq->mcq)) {
591 mlx5_vdpa_warn(&ndev->mvdev, "destroy CQ 0x%x\n", vcq->mcq.cqn);
594 cq_frag_buf_free(ndev, &vcq->buf);
595 mlx5_db_free(ndev->mvdev.mdev, &vcq->db);
598 static void set_umem_size(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq, int num,
599 struct mlx5_vdpa_umem **umemp)
601 struct mlx5_core_dev *mdev = ndev->mvdev.mdev;
607 p_a = MLX5_CAP_DEV_VDPA_EMULATION(mdev, umem_1_buffer_param_a);
608 p_b = MLX5_CAP_DEV_VDPA_EMULATION(mdev, umem_1_buffer_param_b);
609 *umemp = &mvq->umem1;
612 p_a = MLX5_CAP_DEV_VDPA_EMULATION(mdev, umem_2_buffer_param_a);
613 p_b = MLX5_CAP_DEV_VDPA_EMULATION(mdev, umem_2_buffer_param_b);
614 *umemp = &mvq->umem2;
617 p_a = MLX5_CAP_DEV_VDPA_EMULATION(mdev, umem_3_buffer_param_a);
618 p_b = MLX5_CAP_DEV_VDPA_EMULATION(mdev, umem_3_buffer_param_b);
619 *umemp = &mvq->umem3;
622 (*umemp)->size = p_a * mvq->num_ent + p_b;
625 static void umem_frag_buf_free(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_umem *umem)
627 mlx5_frag_buf_free(ndev->mvdev.mdev, &umem->frag_buf);
630 static int create_umem(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq, int num)
633 u32 out[MLX5_ST_SZ_DW(create_umem_out)] = {};
638 struct mlx5_vdpa_umem *umem;
640 set_umem_size(ndev, mvq, num, &umem);
641 err = umem_frag_buf_alloc(ndev, umem, umem->size);
645 inlen = MLX5_ST_SZ_BYTES(create_umem_in) + MLX5_ST_SZ_BYTES(mtt) * umem->frag_buf.npages;
647 in = kzalloc(inlen, GFP_KERNEL);
653 MLX5_SET(create_umem_in, in, opcode, MLX5_CMD_OP_CREATE_UMEM);
654 MLX5_SET(create_umem_in, in, uid, ndev->mvdev.res.uid);
655 um = MLX5_ADDR_OF(create_umem_in, in, umem);
656 MLX5_SET(umem, um, log_page_size, umem->frag_buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
657 MLX5_SET64(umem, um, num_of_mtt, umem->frag_buf.npages);
659 pas = (__be64 *)MLX5_ADDR_OF(umem, um, mtt[0]);
660 mlx5_fill_page_frag_array_perm(&umem->frag_buf, pas, MLX5_MTT_PERM_RW);
662 err = mlx5_cmd_exec(ndev->mvdev.mdev, in, inlen, out, sizeof(out));
664 mlx5_vdpa_warn(&ndev->mvdev, "create umem(%d)\n", err);
669 umem->id = MLX5_GET(create_umem_out, out, umem_id);
676 umem_frag_buf_free(ndev, umem);
680 static void umem_destroy(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq, int num)
682 u32 in[MLX5_ST_SZ_DW(destroy_umem_in)] = {};
683 u32 out[MLX5_ST_SZ_DW(destroy_umem_out)] = {};
684 struct mlx5_vdpa_umem *umem;
698 MLX5_SET(destroy_umem_in, in, opcode, MLX5_CMD_OP_DESTROY_UMEM);
699 MLX5_SET(destroy_umem_in, in, umem_id, umem->id);
700 if (mlx5_cmd_exec(ndev->mvdev.mdev, in, sizeof(in), out, sizeof(out)))
703 umem_frag_buf_free(ndev, umem);
706 static int umems_create(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq)
711 for (num = 1; num <= 3; num++) {
712 err = create_umem(ndev, mvq, num);
719 for (num--; num > 0; num--)
720 umem_destroy(ndev, mvq, num);
725 static void umems_destroy(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq)
729 for (num = 3; num > 0; num--)
730 umem_destroy(ndev, mvq, num);
733 static int get_queue_type(struct mlx5_vdpa_net *ndev)
737 type_mask = MLX5_CAP_DEV_VDPA_EMULATION(ndev->mvdev.mdev, virtio_queue_type);
739 /* prefer split queue */
740 if (type_mask & MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE_TYPE_PACKED)
741 return MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_PACKED;
743 WARN_ON(!(type_mask & MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE_TYPE_SPLIT));
745 return MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_SPLIT;
748 static bool vq_is_tx(u16 idx)
753 static u16 get_features_12_3(u64 features)
755 return (!!(features & BIT_ULL(VIRTIO_NET_F_HOST_TSO4)) << 9) |
756 (!!(features & BIT_ULL(VIRTIO_NET_F_HOST_TSO6)) << 8) |
757 (!!(features & BIT_ULL(VIRTIO_NET_F_CSUM)) << 7) |
758 (!!(features & BIT_ULL(VIRTIO_NET_F_GUEST_CSUM)) << 6);
761 static int create_virtqueue(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq)
763 int inlen = MLX5_ST_SZ_BYTES(create_virtio_net_q_in);
764 u32 out[MLX5_ST_SZ_DW(create_virtio_net_q_out)] = {};
771 err = umems_create(ndev, mvq);
775 in = kzalloc(inlen, GFP_KERNEL);
781 cmd_hdr = MLX5_ADDR_OF(create_virtio_net_q_in, in, general_obj_in_cmd_hdr);
783 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, opcode, MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
784 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, obj_type, MLX5_OBJ_TYPE_VIRTIO_NET_Q);
785 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, uid, ndev->mvdev.res.uid);
787 obj_context = MLX5_ADDR_OF(create_virtio_net_q_in, in, obj_context);
788 MLX5_SET(virtio_net_q_object, obj_context, hw_available_index, mvq->avail_idx);
789 MLX5_SET(virtio_net_q_object, obj_context, hw_used_index, mvq->used_idx);
790 MLX5_SET(virtio_net_q_object, obj_context, queue_feature_bit_mask_12_3,
791 get_features_12_3(ndev->mvdev.actual_features));
792 vq_ctx = MLX5_ADDR_OF(virtio_net_q_object, obj_context, virtio_q_context);
793 MLX5_SET(virtio_q, vq_ctx, virtio_q_type, get_queue_type(ndev));
795 if (vq_is_tx(mvq->index))
796 MLX5_SET(virtio_net_q_object, obj_context, tisn_or_qpn, ndev->res.tisn);
798 MLX5_SET(virtio_q, vq_ctx, event_mode, MLX5_VIRTIO_Q_EVENT_MODE_QP_MODE);
799 MLX5_SET(virtio_q, vq_ctx, queue_index, mvq->index);
800 MLX5_SET(virtio_q, vq_ctx, event_qpn_or_msix, mvq->fwqp.mqp.qpn);
801 MLX5_SET(virtio_q, vq_ctx, queue_size, mvq->num_ent);
802 MLX5_SET(virtio_q, vq_ctx, virtio_version_1_0,
803 !!(ndev->mvdev.actual_features & BIT_ULL(VIRTIO_F_VERSION_1)));
804 MLX5_SET64(virtio_q, vq_ctx, desc_addr, mvq->desc_addr);
805 MLX5_SET64(virtio_q, vq_ctx, used_addr, mvq->device_addr);
806 MLX5_SET64(virtio_q, vq_ctx, available_addr, mvq->driver_addr);
807 MLX5_SET(virtio_q, vq_ctx, virtio_q_mkey, ndev->mvdev.mr.mkey.key);
808 MLX5_SET(virtio_q, vq_ctx, umem_1_id, mvq->umem1.id);
809 MLX5_SET(virtio_q, vq_ctx, umem_1_size, mvq->umem1.size);
810 MLX5_SET(virtio_q, vq_ctx, umem_2_id, mvq->umem2.id);
811 MLX5_SET(virtio_q, vq_ctx, umem_2_size, mvq->umem2.size);
812 MLX5_SET(virtio_q, vq_ctx, umem_3_id, mvq->umem3.id);
813 MLX5_SET(virtio_q, vq_ctx, umem_3_size, mvq->umem3.size);
814 MLX5_SET(virtio_q, vq_ctx, pd, ndev->mvdev.res.pdn);
816 err = mlx5_cmd_exec(ndev->mvdev.mdev, in, inlen, out, sizeof(out));
821 mvq->virtq_id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
828 umems_destroy(ndev, mvq);
832 static void destroy_virtqueue(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq)
834 u32 in[MLX5_ST_SZ_DW(destroy_virtio_net_q_in)] = {};
835 u32 out[MLX5_ST_SZ_DW(destroy_virtio_net_q_out)] = {};
837 MLX5_SET(destroy_virtio_net_q_in, in, general_obj_out_cmd_hdr.opcode,
838 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT);
839 MLX5_SET(destroy_virtio_net_q_in, in, general_obj_out_cmd_hdr.obj_id, mvq->virtq_id);
840 MLX5_SET(destroy_virtio_net_q_in, in, general_obj_out_cmd_hdr.uid, ndev->mvdev.res.uid);
841 MLX5_SET(destroy_virtio_net_q_in, in, general_obj_out_cmd_hdr.obj_type,
842 MLX5_OBJ_TYPE_VIRTIO_NET_Q);
843 if (mlx5_cmd_exec(ndev->mvdev.mdev, in, sizeof(in), out, sizeof(out))) {
844 mlx5_vdpa_warn(&ndev->mvdev, "destroy virtqueue 0x%x\n", mvq->virtq_id);
847 umems_destroy(ndev, mvq);
850 static u32 get_rqpn(struct mlx5_vdpa_virtqueue *mvq, bool fw)
852 return fw ? mvq->vqqp.mqp.qpn : mvq->fwqp.mqp.qpn;
855 static u32 get_qpn(struct mlx5_vdpa_virtqueue *mvq, bool fw)
857 return fw ? mvq->fwqp.mqp.qpn : mvq->vqqp.mqp.qpn;
860 static void alloc_inout(struct mlx5_vdpa_net *ndev, int cmd, void **in, int *inlen, void **out,
861 int *outlen, u32 qpn, u32 rqpn)
867 case MLX5_CMD_OP_2RST_QP:
868 *inlen = MLX5_ST_SZ_BYTES(qp_2rst_in);
869 *outlen = MLX5_ST_SZ_BYTES(qp_2rst_out);
870 *in = kzalloc(*inlen, GFP_KERNEL);
871 *out = kzalloc(*outlen, GFP_KERNEL);
875 MLX5_SET(qp_2rst_in, *in, opcode, cmd);
876 MLX5_SET(qp_2rst_in, *in, uid, ndev->mvdev.res.uid);
877 MLX5_SET(qp_2rst_in, *in, qpn, qpn);
879 case MLX5_CMD_OP_RST2INIT_QP:
880 *inlen = MLX5_ST_SZ_BYTES(rst2init_qp_in);
881 *outlen = MLX5_ST_SZ_BYTES(rst2init_qp_out);
882 *in = kzalloc(*inlen, GFP_KERNEL);
883 *out = kzalloc(MLX5_ST_SZ_BYTES(rst2init_qp_out), GFP_KERNEL);
887 MLX5_SET(rst2init_qp_in, *in, opcode, cmd);
888 MLX5_SET(rst2init_qp_in, *in, uid, ndev->mvdev.res.uid);
889 MLX5_SET(rst2init_qp_in, *in, qpn, qpn);
890 qpc = MLX5_ADDR_OF(rst2init_qp_in, *in, qpc);
891 MLX5_SET(qpc, qpc, remote_qpn, rqpn);
892 MLX5_SET(qpc, qpc, rwe, 1);
893 pp = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
894 MLX5_SET(ads, pp, vhca_port_num, 1);
896 case MLX5_CMD_OP_INIT2RTR_QP:
897 *inlen = MLX5_ST_SZ_BYTES(init2rtr_qp_in);
898 *outlen = MLX5_ST_SZ_BYTES(init2rtr_qp_out);
899 *in = kzalloc(*inlen, GFP_KERNEL);
900 *out = kzalloc(MLX5_ST_SZ_BYTES(init2rtr_qp_out), GFP_KERNEL);
904 MLX5_SET(init2rtr_qp_in, *in, opcode, cmd);
905 MLX5_SET(init2rtr_qp_in, *in, uid, ndev->mvdev.res.uid);
906 MLX5_SET(init2rtr_qp_in, *in, qpn, qpn);
907 qpc = MLX5_ADDR_OF(rst2init_qp_in, *in, qpc);
908 MLX5_SET(qpc, qpc, mtu, MLX5_QPC_MTU_256_BYTES);
909 MLX5_SET(qpc, qpc, log_msg_max, 30);
910 MLX5_SET(qpc, qpc, remote_qpn, rqpn);
911 pp = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
912 MLX5_SET(ads, pp, fl, 1);
914 case MLX5_CMD_OP_RTR2RTS_QP:
915 *inlen = MLX5_ST_SZ_BYTES(rtr2rts_qp_in);
916 *outlen = MLX5_ST_SZ_BYTES(rtr2rts_qp_out);
917 *in = kzalloc(*inlen, GFP_KERNEL);
918 *out = kzalloc(MLX5_ST_SZ_BYTES(rtr2rts_qp_out), GFP_KERNEL);
922 MLX5_SET(rtr2rts_qp_in, *in, opcode, cmd);
923 MLX5_SET(rtr2rts_qp_in, *in, uid, ndev->mvdev.res.uid);
924 MLX5_SET(rtr2rts_qp_in, *in, qpn, qpn);
925 qpc = MLX5_ADDR_OF(rst2init_qp_in, *in, qpc);
926 pp = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
927 MLX5_SET(ads, pp, ack_timeout, 14);
928 MLX5_SET(qpc, qpc, retry_count, 7);
929 MLX5_SET(qpc, qpc, rnr_retry, 7);
945 static void free_inout(void *in, void *out)
951 /* Two QPs are used by each virtqueue. One is used by the driver and one by
952 * firmware. The fw argument indicates whether the subjected QP is the one used
955 static int modify_qp(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq, bool fw, int cmd)
963 alloc_inout(ndev, cmd, &in, &inlen, &out, &outlen, get_qpn(mvq, fw), get_rqpn(mvq, fw));
967 err = mlx5_cmd_exec(ndev->mvdev.mdev, in, inlen, out, outlen);
972 static int connect_qps(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq)
976 err = modify_qp(ndev, mvq, true, MLX5_CMD_OP_2RST_QP);
980 err = modify_qp(ndev, mvq, false, MLX5_CMD_OP_2RST_QP);
984 err = modify_qp(ndev, mvq, true, MLX5_CMD_OP_RST2INIT_QP);
988 err = modify_qp(ndev, mvq, false, MLX5_CMD_OP_RST2INIT_QP);
992 err = modify_qp(ndev, mvq, true, MLX5_CMD_OP_INIT2RTR_QP);
996 err = modify_qp(ndev, mvq, false, MLX5_CMD_OP_INIT2RTR_QP);
1000 return modify_qp(ndev, mvq, true, MLX5_CMD_OP_RTR2RTS_QP);
1003 struct mlx5_virtq_attr {
1005 u16 available_index;
1009 static int query_virtqueue(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq,
1010 struct mlx5_virtq_attr *attr)
1012 int outlen = MLX5_ST_SZ_BYTES(query_virtio_net_q_out);
1013 u32 in[MLX5_ST_SZ_DW(query_virtio_net_q_in)] = {};
1019 out = kzalloc(outlen, GFP_KERNEL);
1023 cmd_hdr = MLX5_ADDR_OF(query_virtio_net_q_in, in, general_obj_in_cmd_hdr);
1025 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, opcode, MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1026 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, obj_type, MLX5_OBJ_TYPE_VIRTIO_NET_Q);
1027 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, obj_id, mvq->virtq_id);
1028 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, uid, ndev->mvdev.res.uid);
1029 err = mlx5_cmd_exec(ndev->mvdev.mdev, in, sizeof(in), out, outlen);
1033 obj_context = MLX5_ADDR_OF(query_virtio_net_q_out, out, obj_context);
1034 memset(attr, 0, sizeof(*attr));
1035 attr->state = MLX5_GET(virtio_net_q_object, obj_context, state);
1036 attr->available_index = MLX5_GET(virtio_net_q_object, obj_context, hw_available_index);
1037 attr->used_index = MLX5_GET(virtio_net_q_object, obj_context, hw_used_index);
1046 static int modify_virtqueue(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq, int state)
1048 int inlen = MLX5_ST_SZ_BYTES(modify_virtio_net_q_in);
1049 u32 out[MLX5_ST_SZ_DW(modify_virtio_net_q_out)] = {};
1055 in = kzalloc(inlen, GFP_KERNEL);
1059 cmd_hdr = MLX5_ADDR_OF(modify_virtio_net_q_in, in, general_obj_in_cmd_hdr);
1061 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, opcode, MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1062 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, obj_type, MLX5_OBJ_TYPE_VIRTIO_NET_Q);
1063 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, obj_id, mvq->virtq_id);
1064 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, uid, ndev->mvdev.res.uid);
1066 obj_context = MLX5_ADDR_OF(modify_virtio_net_q_in, in, obj_context);
1067 MLX5_SET64(virtio_net_q_object, obj_context, modify_field_select,
1068 MLX5_VIRTQ_MODIFY_MASK_STATE);
1069 MLX5_SET(virtio_net_q_object, obj_context, state, state);
1070 err = mlx5_cmd_exec(ndev->mvdev.mdev, in, inlen, out, sizeof(out));
1073 mvq->fw_state = state;
1078 static int setup_vq(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq)
1080 u16 idx = mvq->index;
1086 if (mvq->initialized) {
1087 mlx5_vdpa_warn(&ndev->mvdev, "attempt re init\n");
1091 err = cq_create(ndev, idx, mvq->num_ent);
1095 err = qp_create(ndev, mvq, &mvq->fwqp);
1099 err = qp_create(ndev, mvq, &mvq->vqqp);
1103 err = connect_qps(ndev, mvq);
1107 err = create_virtqueue(ndev, mvq);
1112 err = modify_virtqueue(ndev, mvq, MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY);
1114 mlx5_vdpa_warn(&ndev->mvdev, "failed to modify to ready vq idx %d(%d)\n",
1120 mvq->initialized = true;
1124 qp_destroy(ndev, &mvq->vqqp);
1126 qp_destroy(ndev, &mvq->fwqp);
1128 cq_destroy(ndev, idx);
1132 static void suspend_vq(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq)
1134 struct mlx5_virtq_attr attr;
1136 if (!mvq->initialized)
1139 if (mvq->fw_state != MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY)
1142 if (modify_virtqueue(ndev, mvq, MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND))
1143 mlx5_vdpa_warn(&ndev->mvdev, "modify to suspend failed\n");
1145 if (query_virtqueue(ndev, mvq, &attr)) {
1146 mlx5_vdpa_warn(&ndev->mvdev, "failed to query virtqueue\n");
1149 mvq->avail_idx = attr.available_index;
1150 mvq->used_idx = attr.used_index;
1153 static void suspend_vqs(struct mlx5_vdpa_net *ndev)
1157 for (i = 0; i < MLX5_MAX_SUPPORTED_VQS; i++)
1158 suspend_vq(ndev, &ndev->vqs[i]);
1161 static void teardown_vq(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq)
1163 if (!mvq->initialized)
1166 suspend_vq(ndev, mvq);
1167 destroy_virtqueue(ndev, mvq);
1168 qp_destroy(ndev, &mvq->vqqp);
1169 qp_destroy(ndev, &mvq->fwqp);
1170 cq_destroy(ndev, mvq->index);
1171 mvq->initialized = false;
1174 static int create_rqt(struct mlx5_vdpa_net *ndev)
1184 log_max_rqt = min_t(int, 1, MLX5_CAP_GEN(ndev->mvdev.mdev, log_max_rqt_size));
1185 if (log_max_rqt < 1)
1188 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + (1 << log_max_rqt) * MLX5_ST_SZ_BYTES(rq_num);
1189 in = kzalloc(inlen, GFP_KERNEL);
1193 MLX5_SET(create_rqt_in, in, uid, ndev->mvdev.res.uid);
1194 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1196 MLX5_SET(rqtc, rqtc, list_q_type, MLX5_RQTC_LIST_Q_TYPE_VIRTIO_NET_Q);
1197 MLX5_SET(rqtc, rqtc, rqt_max_size, 1 << log_max_rqt);
1198 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1);
1199 list = MLX5_ADDR_OF(rqtc, rqtc, rq_num[0]);
1200 for (i = 0, j = 0; j < ndev->mvdev.max_vqs; j++) {
1201 if (!ndev->vqs[j].initialized)
1204 if (!vq_is_tx(ndev->vqs[j].index)) {
1205 list[i] = cpu_to_be32(ndev->vqs[j].virtq_id);
1210 err = mlx5_vdpa_create_rqt(&ndev->mvdev, in, inlen, &ndev->res.rqtn);
1218 static void destroy_rqt(struct mlx5_vdpa_net *ndev)
1220 mlx5_vdpa_destroy_rqt(&ndev->mvdev, ndev->res.rqtn);
1223 static int create_tir(struct mlx5_vdpa_net *ndev)
1225 #define HASH_IP_L4PORTS \
1226 (MLX5_HASH_FIELD_SEL_SRC_IP | MLX5_HASH_FIELD_SEL_DST_IP | MLX5_HASH_FIELD_SEL_L4_SPORT | \
1227 MLX5_HASH_FIELD_SEL_L4_DPORT)
1228 static const u8 rx_hash_toeplitz_key[] = { 0x2c, 0xc6, 0x81, 0xd1, 0x5b, 0xdb, 0xf4, 0xf7,
1229 0xfc, 0xa2, 0x83, 0x19, 0xdb, 0x1a, 0x3e, 0x94,
1230 0x6b, 0x9e, 0x38, 0xd9, 0x2c, 0x9c, 0x03, 0xd1,
1231 0xad, 0x99, 0x44, 0xa7, 0xd9, 0x56, 0x3d, 0x59,
1232 0x06, 0x3c, 0x25, 0xf3, 0xfc, 0x1f, 0xdc, 0x2a };
1239 in = kzalloc(MLX5_ST_SZ_BYTES(create_tir_in), GFP_KERNEL);
1243 MLX5_SET(create_tir_in, in, uid, ndev->mvdev.res.uid);
1244 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1245 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1247 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1248 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1249 rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1250 memcpy(rss_key, rx_hash_toeplitz_key, sizeof(rx_hash_toeplitz_key));
1252 outer = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1253 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, MLX5_L3_PROT_TYPE_IPV4);
1254 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, MLX5_L4_PROT_TYPE_TCP);
1255 MLX5_SET(rx_hash_field_select, outer, selected_fields, HASH_IP_L4PORTS);
1257 MLX5_SET(tirc, tirc, indirect_table, ndev->res.rqtn);
1258 MLX5_SET(tirc, tirc, transport_domain, ndev->res.tdn);
1260 err = mlx5_vdpa_create_tir(&ndev->mvdev, in, &ndev->res.tirn);
1265 static void destroy_tir(struct mlx5_vdpa_net *ndev)
1267 mlx5_vdpa_destroy_tir(&ndev->mvdev, ndev->res.tirn);
1270 static int add_fwd_to_tir(struct mlx5_vdpa_net *ndev)
1272 struct mlx5_flow_destination dest[2] = {};
1273 struct mlx5_flow_table_attr ft_attr = {};
1274 struct mlx5_flow_act flow_act = {};
1275 struct mlx5_flow_namespace *ns;
1278 /* for now, one entry, match all, forward to tir */
1279 ft_attr.max_fte = 1;
1280 ft_attr.autogroup.max_num_groups = 1;
1282 ns = mlx5_get_flow_namespace(ndev->mvdev.mdev, MLX5_FLOW_NAMESPACE_BYPASS);
1284 mlx5_vdpa_warn(&ndev->mvdev, "get flow namespace\n");
1288 ndev->rxft = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
1289 if (IS_ERR(ndev->rxft))
1290 return PTR_ERR(ndev->rxft);
1292 ndev->rx_counter = mlx5_fc_create(ndev->mvdev.mdev, false);
1293 if (IS_ERR(ndev->rx_counter)) {
1294 err = PTR_ERR(ndev->rx_counter);
1298 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_COUNT;
1299 dest[0].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1300 dest[0].tir_num = ndev->res.tirn;
1301 dest[1].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
1302 dest[1].counter_id = mlx5_fc_id(ndev->rx_counter);
1303 ndev->rx_rule = mlx5_add_flow_rules(ndev->rxft, NULL, &flow_act, dest, 2);
1304 if (IS_ERR(ndev->rx_rule)) {
1305 err = PTR_ERR(ndev->rx_rule);
1306 ndev->rx_rule = NULL;
1313 mlx5_fc_destroy(ndev->mvdev.mdev, ndev->rx_counter);
1315 mlx5_destroy_flow_table(ndev->rxft);
1319 static void remove_fwd_to_tir(struct mlx5_vdpa_net *ndev)
1324 mlx5_del_flow_rules(ndev->rx_rule);
1325 mlx5_fc_destroy(ndev->mvdev.mdev, ndev->rx_counter);
1326 mlx5_destroy_flow_table(ndev->rxft);
1328 ndev->rx_rule = NULL;
1331 static void mlx5_vdpa_kick_vq(struct vdpa_device *vdev, u16 idx)
1333 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1334 struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
1335 struct mlx5_vdpa_virtqueue *mvq = &ndev->vqs[idx];
1337 if (unlikely(!mvq->ready))
1340 iowrite16(idx, ndev->mvdev.res.kick_addr);
1343 static int mlx5_vdpa_set_vq_address(struct vdpa_device *vdev, u16 idx, u64 desc_area,
1344 u64 driver_area, u64 device_area)
1346 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1347 struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
1348 struct mlx5_vdpa_virtqueue *mvq = &ndev->vqs[idx];
1350 mvq->desc_addr = desc_area;
1351 mvq->device_addr = device_area;
1352 mvq->driver_addr = driver_area;
1356 static void mlx5_vdpa_set_vq_num(struct vdpa_device *vdev, u16 idx, u32 num)
1358 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1359 struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
1360 struct mlx5_vdpa_virtqueue *mvq;
1362 mvq = &ndev->vqs[idx];
1366 static void mlx5_vdpa_set_vq_cb(struct vdpa_device *vdev, u16 idx, struct vdpa_callback *cb)
1368 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1369 struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
1370 struct mlx5_vdpa_virtqueue *vq = &ndev->vqs[idx];
1375 static void mlx5_vdpa_set_vq_ready(struct vdpa_device *vdev, u16 idx, bool ready)
1377 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1378 struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
1379 struct mlx5_vdpa_virtqueue *mvq = &ndev->vqs[idx];
1382 suspend_vq(ndev, mvq);
1387 static bool mlx5_vdpa_get_vq_ready(struct vdpa_device *vdev, u16 idx)
1389 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1390 struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
1391 struct mlx5_vdpa_virtqueue *mvq = &ndev->vqs[idx];
1396 static int mlx5_vdpa_set_vq_state(struct vdpa_device *vdev, u16 idx,
1397 const struct vdpa_vq_state *state)
1399 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1400 struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
1401 struct mlx5_vdpa_virtqueue *mvq = &ndev->vqs[idx];
1403 if (mvq->fw_state == MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY) {
1404 mlx5_vdpa_warn(mvdev, "can't modify available index\n");
1408 mvq->used_idx = state->avail_index;
1409 mvq->avail_idx = state->avail_index;
1413 static int mlx5_vdpa_get_vq_state(struct vdpa_device *vdev, u16 idx, struct vdpa_vq_state *state)
1415 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1416 struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
1417 struct mlx5_vdpa_virtqueue *mvq = &ndev->vqs[idx];
1418 struct mlx5_virtq_attr attr;
1421 /* If the virtq object was destroyed, use the value saved at
1422 * the last minute of suspend_vq. This caters for userspace
1423 * that cares about emulating the index after vq is stopped.
1425 if (!mvq->initialized) {
1426 /* Firmware returns a wrong value for the available index.
1427 * Since both values should be identical, we take the value of
1428 * used_idx which is reported correctly.
1430 state->avail_index = mvq->used_idx;
1434 err = query_virtqueue(ndev, mvq, &attr);
1436 mlx5_vdpa_warn(mvdev, "failed to query virtqueue\n");
1439 state->avail_index = attr.used_index;
1443 static u32 mlx5_vdpa_get_vq_align(struct vdpa_device *vdev)
1448 enum { MLX5_VIRTIO_NET_F_GUEST_CSUM = 1 << 9,
1449 MLX5_VIRTIO_NET_F_CSUM = 1 << 10,
1450 MLX5_VIRTIO_NET_F_HOST_TSO6 = 1 << 11,
1451 MLX5_VIRTIO_NET_F_HOST_TSO4 = 1 << 12,
1454 static u64 mlx_to_vritio_features(u16 dev_features)
1458 if (dev_features & MLX5_VIRTIO_NET_F_GUEST_CSUM)
1459 result |= BIT_ULL(VIRTIO_NET_F_GUEST_CSUM);
1460 if (dev_features & MLX5_VIRTIO_NET_F_CSUM)
1461 result |= BIT_ULL(VIRTIO_NET_F_CSUM);
1462 if (dev_features & MLX5_VIRTIO_NET_F_HOST_TSO6)
1463 result |= BIT_ULL(VIRTIO_NET_F_HOST_TSO6);
1464 if (dev_features & MLX5_VIRTIO_NET_F_HOST_TSO4)
1465 result |= BIT_ULL(VIRTIO_NET_F_HOST_TSO4);
1470 static u64 mlx5_vdpa_get_features(struct vdpa_device *vdev)
1472 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1473 struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
1476 dev_features = MLX5_CAP_DEV_VDPA_EMULATION(mvdev->mdev, device_features_bits_mask);
1477 ndev->mvdev.mlx_features = mlx_to_vritio_features(dev_features);
1478 if (MLX5_CAP_DEV_VDPA_EMULATION(mvdev->mdev, virtio_version_1_0))
1479 ndev->mvdev.mlx_features |= BIT_ULL(VIRTIO_F_VERSION_1);
1480 ndev->mvdev.mlx_features |= BIT_ULL(VIRTIO_F_ACCESS_PLATFORM);
1481 print_features(mvdev, ndev->mvdev.mlx_features, false);
1482 return ndev->mvdev.mlx_features;
1485 static int verify_driver_features(struct mlx5_vdpa_dev *mvdev, u64 features)
1487 /* Minimum features to expect */
1488 if (!(features & BIT_ULL(VIRTIO_F_ACCESS_PLATFORM)))
1491 /* Double check features combination sent down by the driver.
1492 * Fail invalid features due to absence of the depended feature.
1494 * Per VIRTIO v1.1 specification, section 5.1.3.1 Feature bit
1495 * requirements: "VIRTIO_NET_F_MQ Requires VIRTIO_NET_F_CTRL_VQ".
1496 * By failing the invalid features sent down by untrusted drivers,
1497 * we're assured the assumption made upon is_index_valid() and
1498 * is_ctrl_vq_idx() will not be compromised.
1500 if ((features & (BIT_ULL(VIRTIO_NET_F_MQ) | BIT_ULL(VIRTIO_NET_F_CTRL_VQ))) ==
1501 BIT_ULL(VIRTIO_NET_F_MQ))
1507 static int setup_virtqueues(struct mlx5_vdpa_net *ndev)
1512 for (i = 0; i < 2 * mlx5_vdpa_max_qps(ndev->mvdev.max_vqs); i++) {
1513 err = setup_vq(ndev, &ndev->vqs[i]);
1521 for (--i; i >= 0; i--)
1522 teardown_vq(ndev, &ndev->vqs[i]);
1527 static void teardown_virtqueues(struct mlx5_vdpa_net *ndev)
1529 struct mlx5_vdpa_virtqueue *mvq;
1532 for (i = ndev->mvdev.max_vqs - 1; i >= 0; i--) {
1533 mvq = &ndev->vqs[i];
1534 if (!mvq->initialized)
1537 teardown_vq(ndev, mvq);
1541 /* TODO: cross-endian support */
1542 static inline bool mlx5_vdpa_is_little_endian(struct mlx5_vdpa_dev *mvdev)
1544 return virtio_legacy_is_little_endian() ||
1545 (mvdev->actual_features & BIT_ULL(VIRTIO_F_VERSION_1));
1548 static __virtio16 cpu_to_mlx5vdpa16(struct mlx5_vdpa_dev *mvdev, u16 val)
1550 return __cpu_to_virtio16(mlx5_vdpa_is_little_endian(mvdev), val);
1553 static int mlx5_vdpa_set_features(struct vdpa_device *vdev, u64 features)
1555 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1556 struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
1559 print_features(mvdev, features, true);
1561 err = verify_driver_features(mvdev, features);
1565 ndev->mvdev.actual_features = features & ndev->mvdev.mlx_features;
1566 ndev->config.mtu = cpu_to_mlx5vdpa16(mvdev, ndev->mtu);
1567 ndev->config.status |= cpu_to_mlx5vdpa16(mvdev, VIRTIO_NET_S_LINK_UP);
1571 static void mlx5_vdpa_set_config_cb(struct vdpa_device *vdev, struct vdpa_callback *cb)
1573 /* not implemented */
1574 mlx5_vdpa_warn(to_mvdev(vdev), "set config callback not supported\n");
1577 #define MLX5_VDPA_MAX_VQ_ENTRIES 256
1578 static u16 mlx5_vdpa_get_vq_num_max(struct vdpa_device *vdev)
1580 return MLX5_VDPA_MAX_VQ_ENTRIES;
1583 static u32 mlx5_vdpa_get_device_id(struct vdpa_device *vdev)
1585 return VIRTIO_ID_NET;
1588 static u32 mlx5_vdpa_get_vendor_id(struct vdpa_device *vdev)
1590 return PCI_VENDOR_ID_MELLANOX;
1593 static u8 mlx5_vdpa_get_status(struct vdpa_device *vdev)
1595 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1596 struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
1598 print_status(mvdev, ndev->mvdev.status, false);
1599 return ndev->mvdev.status;
1602 static int save_channel_info(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq)
1604 struct mlx5_vq_restore_info *ri = &mvq->ri;
1605 struct mlx5_virtq_attr attr;
1608 if (!mvq->initialized)
1611 err = query_virtqueue(ndev, mvq, &attr);
1615 ri->avail_index = attr.available_index;
1616 ri->used_index = attr.used_index;
1617 ri->ready = mvq->ready;
1618 ri->num_ent = mvq->num_ent;
1619 ri->desc_addr = mvq->desc_addr;
1620 ri->device_addr = mvq->device_addr;
1621 ri->driver_addr = mvq->driver_addr;
1622 ri->cb = mvq->event_cb;
1627 static int save_channels_info(struct mlx5_vdpa_net *ndev)
1631 for (i = 0; i < ndev->mvdev.max_vqs; i++) {
1632 memset(&ndev->vqs[i].ri, 0, sizeof(ndev->vqs[i].ri));
1633 save_channel_info(ndev, &ndev->vqs[i]);
1638 static void mlx5_clear_vqs(struct mlx5_vdpa_net *ndev)
1642 for (i = 0; i < ndev->mvdev.max_vqs; i++)
1643 memset(&ndev->vqs[i], 0, offsetof(struct mlx5_vdpa_virtqueue, ri));
1646 static void restore_channels_info(struct mlx5_vdpa_net *ndev)
1648 struct mlx5_vdpa_virtqueue *mvq;
1649 struct mlx5_vq_restore_info *ri;
1652 mlx5_clear_vqs(ndev);
1654 for (i = 0; i < ndev->mvdev.max_vqs; i++) {
1655 mvq = &ndev->vqs[i];
1660 mvq->avail_idx = ri->avail_index;
1661 mvq->used_idx = ri->used_index;
1662 mvq->ready = ri->ready;
1663 mvq->num_ent = ri->num_ent;
1664 mvq->desc_addr = ri->desc_addr;
1665 mvq->device_addr = ri->device_addr;
1666 mvq->driver_addr = ri->driver_addr;
1667 mvq->event_cb = ri->cb;
1671 static int mlx5_vdpa_change_map(struct mlx5_vdpa_net *ndev, struct vhost_iotlb *iotlb)
1676 err = save_channels_info(ndev);
1680 teardown_driver(ndev);
1681 mlx5_vdpa_destroy_mr(&ndev->mvdev);
1682 err = mlx5_vdpa_create_mr(&ndev->mvdev, iotlb);
1686 if (!(ndev->mvdev.status & VIRTIO_CONFIG_S_DRIVER_OK))
1689 restore_channels_info(ndev);
1690 err = setup_driver(ndev);
1697 mlx5_vdpa_destroy_mr(&ndev->mvdev);
1702 static int setup_driver(struct mlx5_vdpa_net *ndev)
1706 mutex_lock(&ndev->reslock);
1708 mlx5_vdpa_warn(&ndev->mvdev, "setup driver called for already setup driver\n");
1712 err = setup_virtqueues(ndev);
1714 mlx5_vdpa_warn(&ndev->mvdev, "setup_virtqueues\n");
1718 err = create_rqt(ndev);
1720 mlx5_vdpa_warn(&ndev->mvdev, "create_rqt\n");
1724 err = create_tir(ndev);
1726 mlx5_vdpa_warn(&ndev->mvdev, "create_tir\n");
1730 err = add_fwd_to_tir(ndev);
1732 mlx5_vdpa_warn(&ndev->mvdev, "add_fwd_to_tir\n");
1736 mutex_unlock(&ndev->reslock);
1745 teardown_virtqueues(ndev);
1747 mutex_unlock(&ndev->reslock);
1751 static void teardown_driver(struct mlx5_vdpa_net *ndev)
1753 mutex_lock(&ndev->reslock);
1757 remove_fwd_to_tir(ndev);
1760 teardown_virtqueues(ndev);
1761 ndev->setup = false;
1763 mutex_unlock(&ndev->reslock);
1766 static void clear_vqs_ready(struct mlx5_vdpa_net *ndev)
1770 for (i = 0; i < ndev->mvdev.max_vqs; i++)
1771 ndev->vqs[i].ready = false;
1774 static void mlx5_vdpa_set_status(struct vdpa_device *vdev, u8 status)
1776 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1777 struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
1780 print_status(mvdev, status, true);
1782 mlx5_vdpa_info(mvdev, "performing device reset\n");
1783 teardown_driver(ndev);
1784 clear_vqs_ready(ndev);
1785 mlx5_vdpa_destroy_mr(&ndev->mvdev);
1786 ndev->mvdev.status = 0;
1787 ndev->mvdev.mlx_features = 0;
1788 ++mvdev->generation;
1792 if ((status ^ ndev->mvdev.status) & VIRTIO_CONFIG_S_DRIVER_OK) {
1793 if (status & VIRTIO_CONFIG_S_DRIVER_OK) {
1794 err = setup_driver(ndev);
1796 mlx5_vdpa_warn(mvdev, "failed to setup driver\n");
1800 mlx5_vdpa_warn(mvdev, "did not expect DRIVER_OK to be cleared\n");
1805 ndev->mvdev.status = status;
1809 mlx5_vdpa_destroy_mr(&ndev->mvdev);
1810 ndev->mvdev.status |= VIRTIO_CONFIG_S_FAILED;
1813 static void mlx5_vdpa_get_config(struct vdpa_device *vdev, unsigned int offset, void *buf,
1816 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1817 struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
1819 if (offset + len <= sizeof(struct virtio_net_config))
1820 memcpy(buf, (u8 *)&ndev->config + offset, len);
1823 static void mlx5_vdpa_set_config(struct vdpa_device *vdev, unsigned int offset, const void *buf,
1829 static u32 mlx5_vdpa_get_generation(struct vdpa_device *vdev)
1831 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1833 return mvdev->generation;
1836 static int mlx5_vdpa_set_map(struct vdpa_device *vdev, struct vhost_iotlb *iotlb)
1838 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1839 struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
1843 err = mlx5_vdpa_handle_set_map(mvdev, iotlb, &change_map);
1845 mlx5_vdpa_warn(mvdev, "set map failed(%d)\n", err);
1850 return mlx5_vdpa_change_map(ndev, iotlb);
1855 static void mlx5_vdpa_free(struct vdpa_device *vdev)
1857 struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev);
1858 struct mlx5_core_dev *pfmdev;
1859 struct mlx5_vdpa_net *ndev;
1861 ndev = to_mlx5_vdpa_ndev(mvdev);
1863 free_resources(ndev);
1864 if (!is_zero_ether_addr(ndev->config.mac)) {
1865 pfmdev = pci_get_drvdata(pci_physfn(mvdev->mdev->pdev));
1866 mlx5_mpfs_del_mac(pfmdev, ndev->config.mac);
1868 mlx5_vdpa_free_resources(&ndev->mvdev);
1869 mutex_destroy(&ndev->reslock);
1872 static struct vdpa_notification_area mlx5_get_vq_notification(struct vdpa_device *vdev, u16 idx)
1874 struct vdpa_notification_area ret = {};
1879 static int mlx5_get_vq_irq(struct vdpa_device *vdv, u16 idx)
1884 static const struct vdpa_config_ops mlx5_vdpa_ops = {
1885 .set_vq_address = mlx5_vdpa_set_vq_address,
1886 .set_vq_num = mlx5_vdpa_set_vq_num,
1887 .kick_vq = mlx5_vdpa_kick_vq,
1888 .set_vq_cb = mlx5_vdpa_set_vq_cb,
1889 .set_vq_ready = mlx5_vdpa_set_vq_ready,
1890 .get_vq_ready = mlx5_vdpa_get_vq_ready,
1891 .set_vq_state = mlx5_vdpa_set_vq_state,
1892 .get_vq_state = mlx5_vdpa_get_vq_state,
1893 .get_vq_notification = mlx5_get_vq_notification,
1894 .get_vq_irq = mlx5_get_vq_irq,
1895 .get_vq_align = mlx5_vdpa_get_vq_align,
1896 .get_features = mlx5_vdpa_get_features,
1897 .set_features = mlx5_vdpa_set_features,
1898 .set_config_cb = mlx5_vdpa_set_config_cb,
1899 .get_vq_num_max = mlx5_vdpa_get_vq_num_max,
1900 .get_device_id = mlx5_vdpa_get_device_id,
1901 .get_vendor_id = mlx5_vdpa_get_vendor_id,
1902 .get_status = mlx5_vdpa_get_status,
1903 .set_status = mlx5_vdpa_set_status,
1904 .get_config = mlx5_vdpa_get_config,
1905 .set_config = mlx5_vdpa_set_config,
1906 .get_generation = mlx5_vdpa_get_generation,
1907 .set_map = mlx5_vdpa_set_map,
1908 .free = mlx5_vdpa_free,
1911 static int query_mtu(struct mlx5_core_dev *mdev, u16 *mtu)
1916 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1920 *mtu = hw_mtu - MLX5V_ETH_HARD_MTU;
1924 static int alloc_resources(struct mlx5_vdpa_net *ndev)
1926 struct mlx5_vdpa_net_resources *res = &ndev->res;
1930 mlx5_vdpa_warn(&ndev->mvdev, "resources already allocated\n");
1934 err = mlx5_vdpa_alloc_transport_domain(&ndev->mvdev, &res->tdn);
1938 err = create_tis(ndev);
1947 mlx5_vdpa_dealloc_transport_domain(&ndev->mvdev, res->tdn);
1951 static void free_resources(struct mlx5_vdpa_net *ndev)
1953 struct mlx5_vdpa_net_resources *res = &ndev->res;
1959 mlx5_vdpa_dealloc_transport_domain(&ndev->mvdev, res->tdn);
1963 static void init_mvqs(struct mlx5_vdpa_net *ndev)
1965 struct mlx5_vdpa_virtqueue *mvq;
1968 for (i = 0; i < 2 * mlx5_vdpa_max_qps(ndev->mvdev.max_vqs); ++i) {
1969 mvq = &ndev->vqs[i];
1970 memset(mvq, 0, offsetof(struct mlx5_vdpa_virtqueue, ri));
1973 mvq->fwqp.fw = true;
1975 for (; i < ndev->mvdev.max_vqs; i++) {
1976 mvq = &ndev->vqs[i];
1977 memset(mvq, 0, offsetof(struct mlx5_vdpa_virtqueue, ri));
1983 void *mlx5_vdpa_add_dev(struct mlx5_core_dev *mdev)
1985 struct virtio_net_config *config;
1986 struct mlx5_core_dev *pfmdev;
1987 struct mlx5_vdpa_dev *mvdev;
1988 struct mlx5_vdpa_net *ndev;
1992 /* we save one virtqueue for control virtqueue should we require it */
1993 max_vqs = MLX5_CAP_DEV_VDPA_EMULATION(mdev, max_num_virtio_queues);
1994 max_vqs = min_t(u32, max_vqs, MLX5_MAX_SUPPORTED_VQS);
1996 ndev = vdpa_alloc_device(struct mlx5_vdpa_net, mvdev.vdev, mdev->device, &mlx5_vdpa_ops,
1997 2 * mlx5_vdpa_max_qps(max_vqs));
2001 ndev->mvdev.max_vqs = max_vqs;
2002 mvdev = &ndev->mvdev;
2005 mutex_init(&ndev->reslock);
2006 config = &ndev->config;
2007 err = query_mtu(mdev, &ndev->mtu);
2011 err = mlx5_query_nic_vport_mac_address(mdev, 0, 0, config->mac);
2015 if (!is_zero_ether_addr(config->mac)) {
2016 pfmdev = pci_get_drvdata(pci_physfn(mdev->pdev));
2017 err = mlx5_mpfs_add_mac(pfmdev, config->mac);
2022 mvdev->vdev.dma_dev = mdev->device;
2023 err = mlx5_vdpa_alloc_resources(&ndev->mvdev);
2027 err = alloc_resources(ndev);
2031 err = vdpa_register_device(&mvdev->vdev);
2038 free_resources(ndev);
2040 mlx5_vdpa_free_resources(&ndev->mvdev);
2042 if (!is_zero_ether_addr(config->mac))
2043 mlx5_mpfs_del_mac(pfmdev, config->mac);
2045 mutex_destroy(&ndev->reslock);
2046 put_device(&mvdev->vdev.dev);
2047 return ERR_PTR(err);
2050 void mlx5_vdpa_remove_dev(struct mlx5_vdpa_dev *mvdev)
2052 vdpa_unregister_device(&mvdev->vdev);