drivers/usb/phy/phy-tegra-usb.c

   1 /*
   2  * Copyright (C) 2010 Google, Inc.
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  *
   5  * Author:
   6  *      Erik Gilling <konkers@google.com>
   7  *      Benoit Goby <benoit@android.com>
   8  *      Venu Byravarasu <vbyravarasu@nvidia.com>
   9  *
  10  * This software is licensed under the terms of the GNU General Public
  11  * License version 2, as published by the Free Software Foundation, and
  12  * may be copied, distributed, and modified under those terms.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  */
  20
  21 #include <linux/resource.h>
  22 #include <linux/delay.h>
  23 #include <linux/slab.h>
  24 #include <linux/err.h>
  25 #include <linux/export.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/gpio.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_gpio.h>
  33 #include <linux/usb/otg.h>
  34 #include <linux/usb/ulpi.h>
  35 #include <linux/usb/of.h>
  36 #include <linux/usb/ehci_def.h>
  37 #include <linux/usb/tegra_usb_phy.h>
  38 #include <linux/regulator/consumer.h>
  39
  40 #define ULPI_VIEWPORT           0x170
  41
  42 /* PORTSC PTS/PHCD bits, Tegra20 only */
  43 #define TEGRA_USB_PORTSC1                               0x184
  44 #define TEGRA_USB_PORTSC1_PTS(x)                        (((x) & 0x3) << 30)
  45 #define TEGRA_USB_PORTSC1_PHCD                          (1 << 23)
  46
  47 /* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
  48 #define TEGRA_USB_HOSTPC1_DEVLC         0x1b4
  49 #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x)  (((x) & 0x7) << 29)
  50 #define TEGRA_USB_HOSTPC1_DEVLC_PHCD    (1 << 22)
  51
  52 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
  53 #define TEGRA_PORTSC1_RWC_BITS  (PORT_CSC | PORT_PEC | PORT_OCC)
  54
  55 #define USB_SUSP_CTRL           0x400
  56 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
  57 #define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
  58 #define   USB_SUSP_CLR          (1 << 5)
  59 #define   USB_PHY_CLK_VALID     (1 << 7)
  60 #define   UTMIP_RESET                   (1 << 11)
  61 #define   UHSIC_RESET                   (1 << 11)
  62 #define   UTMIP_PHY_ENABLE              (1 << 12)
  63 #define   ULPI_PHY_ENABLE       (1 << 13)
  64 #define   USB_SUSP_SET          (1 << 14)
  65 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
  66
  67 #define USB1_LEGACY_CTRL        0x410
  68 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
  69 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
  70 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
  71 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
  72                                                 (1 << 1)
  73 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
  74 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
  75
  76 #define ULPI_TIMING_CTRL_0      0x424
  77 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
  78 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
  79
  80 #define ULPI_TIMING_CTRL_1      0x428
  81 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
  82 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
  83 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
  84 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
  85 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
  86 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
  87
  88 #define UTMIP_PLL_CFG1          0x804
  89 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
  90 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
  91
  92 #define UTMIP_XCVR_CFG0         0x808
  93 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
  94 #define   UTMIP_XCVR_SETUP_MSB(x)               ((((x) & 0x70) >> 4) << 22)
  95 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
  96 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
  97 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
  98 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
  99 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
 100 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
 101 #define   UTMIP_XCVR_HSSLEW(x)                  (((x) & 0x3) << 4)
 102 #define   UTMIP_XCVR_HSSLEW_MSB(x)              ((((x) & 0x1fc) >> 2) << 25)
 103
 104 #define UTMIP_BIAS_CFG0         0x80c
 105 #define   UTMIP_OTGPD                   (1 << 11)
 106 #define   UTMIP_BIASPD                  (1 << 10)
 107 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
 108 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
 109 #define   UTMIP_HSDISCON_LEVEL_MSB(x)   ((((x) & 0x4) >> 2) << 24)
 110
 111 #define UTMIP_HSRX_CFG0         0x810
 112 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
 113 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
 114
 115 #define UTMIP_HSRX_CFG1         0x814
 116 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
 117
 118 #define UTMIP_TX_CFG0           0x820
 119 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
 120 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
 121
 122 #define UTMIP_MISC_CFG0         0x824
 123 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
 124 #define   UTMIP_DPDM_OBSERVE_SEL(x)     (((x) & 0xf) << 27)
 125 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
 126 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
 127 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
 128 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
 129 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
 130
 131 #define UTMIP_MISC_CFG1         0x828
 132 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
 133 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
 134
 135 #define UTMIP_DEBOUNCE_CFG0     0x82c
 136 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
 137
 138 #define UTMIP_BAT_CHRG_CFG0     0x830
 139 #define   UTMIP_PD_CHRG                 (1 << 0)
 140
 141 #define UTMIP_SPARE_CFG0        0x834
 142 #define   FUSE_SETUP_SEL                (1 << 3)
 143
 144 #define UTMIP_XCVR_CFG1         0x838
 145 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
 146 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
 147 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
 148 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
 149
 150 #define UTMIP_BIAS_CFG1         0x83c
 151 #define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
 152
 153 /* For Tegra30 and above only, the address is different in Tegra20 */
 154 #define USB_USBMODE             0x1f8
 155 #define   USB_USBMODE_MASK              (3 << 0)
 156 #define   USB_USBMODE_HOST              (3 << 0)
 157 #define   USB_USBMODE_DEVICE            (2 << 0)
 158
 159 static DEFINE_SPINLOCK(utmip_pad_lock);
 160 static int utmip_pad_count;
 161
 162 struct tegra_xtal_freq {
 163         int freq;
 164         u8 enable_delay;
 165         u8 stable_count;
 166         u8 active_delay;
 167         u8 xtal_freq_count;
 168         u16 debounce;
 169 };
 170
 171 static const struct tegra_xtal_freq tegra_freq_table[] = {
 172         {
 173                 .freq = 12000000,
 174                 .enable_delay = 0x02,
 175                 .stable_count = 0x2F,
 176                 .active_delay = 0x04,
 177                 .xtal_freq_count = 0x76,
 178                 .debounce = 0x7530,
 179         },
 180         {
 181                 .freq = 13000000,
 182                 .enable_delay = 0x02,
 183                 .stable_count = 0x33,
 184                 .active_delay = 0x05,
 185                 .xtal_freq_count = 0x7F,
 186                 .debounce = 0x7EF4,
 187         },
 188         {
 189                 .freq = 19200000,
 190                 .enable_delay = 0x03,
 191                 .stable_count = 0x4B,
 192                 .active_delay = 0x06,
 193                 .xtal_freq_count = 0xBB,
 194                 .debounce = 0xBB80,
 195         },
 196         {
 197                 .freq = 26000000,
 198                 .enable_delay = 0x04,
 199                 .stable_count = 0x66,
 200                 .active_delay = 0x09,
 201                 .xtal_freq_count = 0xFE,
 202                 .debounce = 0xFDE8,
 203         },
 204 };
 205
 206 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
 207 {
 208         void __iomem *base = phy->regs;
 209         unsigned long val;
 210
 211         if (phy->soc_config->has_hostpc) {
 212                 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
 213                 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
 214                 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
 215                 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
 216         } else {
 217                 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
 218                 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
 219                 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
 220                 writel(val, base + TEGRA_USB_PORTSC1);
 221         }
 222 }
 223
 224 static void set_phcd(struct tegra_usb_phy *phy, bool enable)
 225 {
 226         void __iomem *base = phy->regs;
 227         unsigned long val;
 228
 229         if (phy->soc_config->has_hostpc) {
 230                 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
 231                 if (enable)
 232                         val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
 233                 else
 234                         val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
 235                 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
 236         } else {
 237                 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
 238                 if (enable)
 239                         val |= TEGRA_USB_PORTSC1_PHCD;
 240                 else
 241                         val &= ~TEGRA_USB_PORTSC1_PHCD;
 242                 writel(val, base + TEGRA_USB_PORTSC1);
 243         }
 244 }
 245
 246 static int utmip_pad_open(struct tegra_usb_phy *phy)
 247 {
 248         phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads");
 249         if (IS_ERR(phy->pad_clk)) {
 250                 pr_err("%s: can't get utmip pad clock\n", __func__);
 251                 return PTR_ERR(phy->pad_clk);
 252         }
 253
 254         return 0;
 255 }
 256
 257 static void utmip_pad_power_on(struct tegra_usb_phy *phy)
 258 {
 259         unsigned long val, flags;
 260         void __iomem *base = phy->pad_regs;
 261         struct tegra_utmip_config *config = phy->config;
 262
 263         clk_prepare_enable(phy->pad_clk);
 264
 265         spin_lock_irqsave(&utmip_pad_lock, flags);
 266
 267         if (utmip_pad_count++ == 0) {
 268                 val = readl(base + UTMIP_BIAS_CFG0);
 269                 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
 270
 271                 if (phy->soc_config->requires_extra_tuning_parameters) {
 272                         val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
 273                                 UTMIP_HSDISCON_LEVEL(~0) |
 274                                 UTMIP_HSDISCON_LEVEL_MSB(~0));
 275
 276                         val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
 277                         val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
 278                         val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
 279                 }
 280                 writel(val, base + UTMIP_BIAS_CFG0);
 281         }
 282
 283         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 284
 285         clk_disable_unprepare(phy->pad_clk);
 286 }
 287
 288 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
 289 {
 290         unsigned long val, flags;
 291         void __iomem *base = phy->pad_regs;
 292
 293         if (!utmip_pad_count) {
 294                 pr_err("%s: utmip pad already powered off\n", __func__);
 295                 return -EINVAL;
 296         }
 297
 298         clk_prepare_enable(phy->pad_clk);
 299
 300         spin_lock_irqsave(&utmip_pad_lock, flags);
 301
 302         if (--utmip_pad_count == 0) {
 303                 val = readl(base + UTMIP_BIAS_CFG0);
 304                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
 305                 writel(val, base + UTMIP_BIAS_CFG0);
 306         }
 307
 308         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 309
 310         clk_disable_unprepare(phy->pad_clk);
 311
 312         return 0;
 313 }
 314
 315 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
 316 {
 317         unsigned long timeout = 2000;
 318         do {
 319                 if ((readl(reg) & mask) == result)
 320                         return 0;
 321                 udelay(1);
 322                 timeout--;
 323         } while (timeout);
 324         return -1;
 325 }
 326
 327 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
 328 {
 329         unsigned long val;
 330         void __iomem *base = phy->regs;
 331
 332         /*
 333          * The USB driver may have already initiated the phy clock
 334          * disable so wait to see if the clock turns off and if not
 335          * then proceed with gating the clock.
 336          */
 337         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0)
 338                 return;
 339
 340         if (phy->is_legacy_phy) {
 341                 val = readl(base + USB_SUSP_CTRL);
 342                 val |= USB_SUSP_SET;
 343                 writel(val, base + USB_SUSP_CTRL);
 344
 345                 udelay(10);
 346
 347                 val = readl(base + USB_SUSP_CTRL);
 348                 val &= ~USB_SUSP_SET;
 349                 writel(val, base + USB_SUSP_CTRL);
 350         } else
 351                 set_phcd(phy, true);
 352
 353         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
 354                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 355 }
 356
 357 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
 358 {
 359         unsigned long val;
 360         void __iomem *base = phy->regs;
 361
 362         /*
 363          * The USB driver may have already initiated the phy clock
 364          * enable so wait to see if the clock turns on and if not
 365          * then proceed with ungating the clock.
 366          */
 367         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 368                                USB_PHY_CLK_VALID) == 0)
 369                 return;
 370
 371         if (phy->is_legacy_phy) {
 372                 val = readl(base + USB_SUSP_CTRL);
 373                 val |= USB_SUSP_CLR;
 374                 writel(val, base + USB_SUSP_CTRL);
 375
 376                 udelay(10);
 377
 378                 val = readl(base + USB_SUSP_CTRL);
 379                 val &= ~USB_SUSP_CLR;
 380                 writel(val, base + USB_SUSP_CTRL);
 381         } else
 382                 set_phcd(phy, false);
 383
 384         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 385                                                      USB_PHY_CLK_VALID))
 386                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 387 }
 388
 389 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
 390 {
 391         unsigned long val;
 392         void __iomem *base = phy->regs;
 393         struct tegra_utmip_config *config = phy->config;
 394
 395         val = readl(base + USB_SUSP_CTRL);
 396         val |= UTMIP_RESET;
 397         writel(val, base + USB_SUSP_CTRL);
 398
 399         if (phy->is_legacy_phy) {
 400                 val = readl(base + USB1_LEGACY_CTRL);
 401                 val |= USB1_NO_LEGACY_MODE;
 402                 writel(val, base + USB1_LEGACY_CTRL);
 403         }
 404
 405         val = readl(base + UTMIP_TX_CFG0);
 406         val |= UTMIP_FS_PREABMLE_J;
 407         writel(val, base + UTMIP_TX_CFG0);
 408
 409         val = readl(base + UTMIP_HSRX_CFG0);
 410         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
 411         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
 412         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
 413         writel(val, base + UTMIP_HSRX_CFG0);
 414
 415         val = readl(base + UTMIP_HSRX_CFG1);
 416         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
 417         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
 418         writel(val, base + UTMIP_HSRX_CFG1);
 419
 420         val = readl(base + UTMIP_DEBOUNCE_CFG0);
 421         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
 422         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
 423         writel(val, base + UTMIP_DEBOUNCE_CFG0);
 424
 425         val = readl(base + UTMIP_MISC_CFG0);
 426         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
 427         writel(val, base + UTMIP_MISC_CFG0);
 428
 429         if (!phy->soc_config->utmi_pll_config_in_car_module) {
 430                 val = readl(base + UTMIP_MISC_CFG1);
 431                 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
 432                         UTMIP_PLLU_STABLE_COUNT(~0));
 433                 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
 434                         UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
 435                 writel(val, base + UTMIP_MISC_CFG1);
 436
 437                 val = readl(base + UTMIP_PLL_CFG1);
 438                 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
 439                         UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
 440                 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
 441                         UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
 442                 writel(val, base + UTMIP_PLL_CFG1);
 443         }
 444
 445         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
 446                 val = readl(base + USB_SUSP_CTRL);
 447                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
 448                 writel(val, base + USB_SUSP_CTRL);
 449
 450                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
 451                 val &= ~UTMIP_PD_CHRG;
 452                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
 453         } else {
 454                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
 455                 val |= UTMIP_PD_CHRG;
 456                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
 457         }
 458
 459         utmip_pad_power_on(phy);
 460
 461         val = readl(base + UTMIP_XCVR_CFG0);
 462         val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 463                  UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
 464                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
 465                  UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
 466
 467         if (!config->xcvr_setup_use_fuses) {
 468                 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
 469                 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
 470         }
 471         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
 472         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
 473
 474         if (phy->soc_config->requires_extra_tuning_parameters) {
 475                 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
 476                 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
 477                 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
 478         }
 479         writel(val, base + UTMIP_XCVR_CFG0);
 480
 481         val = readl(base + UTMIP_XCVR_CFG1);
 482         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 483                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
 484         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
 485         writel(val, base + UTMIP_XCVR_CFG1);
 486
 487         val = readl(base + UTMIP_BIAS_CFG1);
 488         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
 489         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
 490         writel(val, base + UTMIP_BIAS_CFG1);
 491
 492         val = readl(base + UTMIP_SPARE_CFG0);
 493         if (config->xcvr_setup_use_fuses)
 494                 val |= FUSE_SETUP_SEL;
 495         else
 496                 val &= ~FUSE_SETUP_SEL;
 497         writel(val, base + UTMIP_SPARE_CFG0);
 498
 499         if (!phy->is_legacy_phy) {
 500                 val = readl(base + USB_SUSP_CTRL);
 501                 val |= UTMIP_PHY_ENABLE;
 502                 writel(val, base + USB_SUSP_CTRL);
 503         }
 504
 505         val = readl(base + USB_SUSP_CTRL);
 506         val &= ~UTMIP_RESET;
 507         writel(val, base + USB_SUSP_CTRL);
 508
 509         if (phy->is_legacy_phy) {
 510                 val = readl(base + USB1_LEGACY_CTRL);
 511                 val &= ~USB1_VBUS_SENSE_CTL_MASK;
 512                 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
 513                 writel(val, base + USB1_LEGACY_CTRL);
 514
 515                 val = readl(base + USB_SUSP_CTRL);
 516                 val &= ~USB_SUSP_SET;
 517                 writel(val, base + USB_SUSP_CTRL);
 518         }
 519
 520         utmi_phy_clk_enable(phy);
 521
 522         if (phy->soc_config->requires_usbmode_setup) {
 523                 val = readl(base + USB_USBMODE);
 524                 val &= ~USB_USBMODE_MASK;
 525                 if (phy->mode == USB_DR_MODE_HOST)
 526                         val |= USB_USBMODE_HOST;
 527                 else
 528                         val |= USB_USBMODE_DEVICE;
 529                 writel(val, base + USB_USBMODE);
 530         }
 531
 532         if (!phy->is_legacy_phy)
 533                 set_pts(phy, 0);
 534
 535         return 0;
 536 }
 537
 538 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
 539 {
 540         unsigned long val;
 541         void __iomem *base = phy->regs;
 542
 543         utmi_phy_clk_disable(phy);
 544
 545         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
 546                 val = readl(base + USB_SUSP_CTRL);
 547                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
 548                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
 549                 writel(val, base + USB_SUSP_CTRL);
 550         }
 551
 552         val = readl(base + USB_SUSP_CTRL);
 553         val |= UTMIP_RESET;
 554         writel(val, base + USB_SUSP_CTRL);
 555
 556         val = readl(base + UTMIP_BAT_CHRG_CFG0);
 557         val |= UTMIP_PD_CHRG;
 558         writel(val, base + UTMIP_BAT_CHRG_CFG0);
 559
 560         val = readl(base + UTMIP_XCVR_CFG0);
 561         val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 562                UTMIP_FORCE_PDZI_POWERDOWN;
 563         writel(val, base + UTMIP_XCVR_CFG0);
 564
 565         val = readl(base + UTMIP_XCVR_CFG1);
 566         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 567                UTMIP_FORCE_PDDR_POWERDOWN;
 568         writel(val, base + UTMIP_XCVR_CFG1);
 569
 570         return utmip_pad_power_off(phy);
 571 }
 572
 573 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
 574 {
 575         unsigned long val;
 576         void __iomem *base = phy->regs;
 577
 578         val = readl(base + UTMIP_TX_CFG0);
 579         val |= UTMIP_HS_DISCON_DISABLE;
 580         writel(val, base + UTMIP_TX_CFG0);
 581 }
 582
 583 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
 584 {
 585         unsigned long val;
 586         void __iomem *base = phy->regs;
 587
 588         val = readl(base + UTMIP_TX_CFG0);
 589         val &= ~UTMIP_HS_DISCON_DISABLE;
 590         writel(val, base + UTMIP_TX_CFG0);
 591 }
 592
 593 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
 594                                    enum tegra_usb_phy_port_speed port_speed)
 595 {
 596         unsigned long val;
 597         void __iomem *base = phy->regs;
 598
 599         val = readl(base + UTMIP_MISC_CFG0);
 600         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
 601         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 602                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
 603         else
 604                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
 605         writel(val, base + UTMIP_MISC_CFG0);
 606         udelay(1);
 607
 608         val = readl(base + UTMIP_MISC_CFG0);
 609         val |= UTMIP_DPDM_OBSERVE;
 610         writel(val, base + UTMIP_MISC_CFG0);
 611         udelay(10);
 612 }
 613
 614 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
 615 {
 616         unsigned long val;
 617         void __iomem *base = phy->regs;
 618
 619         val = readl(base + UTMIP_MISC_CFG0);
 620         val &= ~UTMIP_DPDM_OBSERVE;
 621         writel(val, base + UTMIP_MISC_CFG0);
 622         udelay(10);
 623 }
 624
 625 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
 626 {
 627         int ret;
 628         unsigned long val;
 629         void __iomem *base = phy->regs;
 630
 631         ret = gpio_direction_output(phy->reset_gpio, 0);
 632         if (ret < 0) {
 633                 dev_err(phy->u_phy.dev, "gpio %d not set to 0\n",
 634                         phy->reset_gpio);
 635                 return ret;
 636         }
 637         msleep(5);
 638         ret = gpio_direction_output(phy->reset_gpio, 1);
 639         if (ret < 0) {
 640                 dev_err(phy->u_phy.dev, "gpio %d not set to 1\n",
 641                         phy->reset_gpio);
 642                 return ret;
 643         }
 644
 645         clk_prepare_enable(phy->clk);
 646         msleep(1);
 647
 648         val = readl(base + USB_SUSP_CTRL);
 649         val |= UHSIC_RESET;
 650         writel(val, base + USB_SUSP_CTRL);
 651
 652         val = readl(base + ULPI_TIMING_CTRL_0);
 653         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
 654         writel(val, base + ULPI_TIMING_CTRL_0);
 655
 656         val = readl(base + USB_SUSP_CTRL);
 657         val |= ULPI_PHY_ENABLE;
 658         writel(val, base + USB_SUSP_CTRL);
 659
 660         val = 0;
 661         writel(val, base + ULPI_TIMING_CTRL_1);
 662
 663         val |= ULPI_DATA_TRIMMER_SEL(4);
 664         val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
 665         val |= ULPI_DIR_TRIMMER_SEL(4);
 666         writel(val, base + ULPI_TIMING_CTRL_1);
 667         udelay(10);
 668
 669         val |= ULPI_DATA_TRIMMER_LOAD;
 670         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
 671         val |= ULPI_DIR_TRIMMER_LOAD;
 672         writel(val, base + ULPI_TIMING_CTRL_1);
 673
 674         /* Fix VbusInvalid due to floating VBUS */
 675         ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
 676         if (ret) {
 677                 pr_err("%s: ulpi write failed\n", __func__);
 678                 return ret;
 679         }
 680
 681         ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
 682         if (ret) {
 683                 pr_err("%s: ulpi write failed\n", __func__);
 684                 return ret;
 685         }
 686
 687         val = readl(base + USB_SUSP_CTRL);
 688         val |= USB_SUSP_CLR;
 689         writel(val, base + USB_SUSP_CTRL);
 690         udelay(100);
 691
 692         val = readl(base + USB_SUSP_CTRL);
 693         val &= ~USB_SUSP_CLR;
 694         writel(val, base + USB_SUSP_CTRL);
 695
 696         return 0;
 697 }
 698
 699 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
 700 {
 701         clk_disable(phy->clk);
 702         return gpio_direction_output(phy->reset_gpio, 0);
 703 }
 704
 705 static void tegra_usb_phy_close(struct tegra_usb_phy *phy)
 706 {
 707         if (!IS_ERR(phy->vbus))
 708                 regulator_disable(phy->vbus);
 709
 710         clk_disable_unprepare(phy->pll_u);
 711 }
 712
 713 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 714 {
 715         if (phy->is_ulpi_phy)
 716                 return ulpi_phy_power_on(phy);
 717         else
 718                 return utmi_phy_power_on(phy);
 719 }
 720
 721 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 722 {
 723         if (phy->is_ulpi_phy)
 724                 return ulpi_phy_power_off(phy);
 725         else
 726                 return utmi_phy_power_off(phy);
 727 }
 728
 729 static int      tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
 730 {
 731         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 732         if (suspend)
 733                 return tegra_usb_phy_power_off(phy);
 734         else
 735                 return tegra_usb_phy_power_on(phy);
 736 }
 737
 738 static int ulpi_open(struct tegra_usb_phy *phy)
 739 {
 740         int err;
 741
 742         phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link");
 743         if (IS_ERR(phy->clk)) {
 744                 pr_err("%s: can't get ulpi clock\n", __func__);
 745                 return PTR_ERR(phy->clk);
 746         }
 747
 748         err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio,
 749                 "ulpi_phy_reset_b");
 750         if (err < 0) {
 751                 dev_err(phy->u_phy.dev, "request failed for gpio: %d\n",
 752                        phy->reset_gpio);
 753                 return err;
 754         }
 755
 756         err = gpio_direction_output(phy->reset_gpio, 0);
 757         if (err < 0) {
 758                 dev_err(phy->u_phy.dev, "gpio %d direction not set to output\n",
 759                        phy->reset_gpio);
 760                 return err;
 761         }
 762
 763         phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
 764         if (!phy->ulpi) {
 765                 dev_err(phy->u_phy.dev, "otg_ulpi_create returned NULL\n");
 766                 err = -ENOMEM;
 767                 return err;
 768         }
 769
 770         phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
 771         return 0;
 772 }
 773
 774 static int tegra_usb_phy_init(struct tegra_usb_phy *phy)
 775 {
 776         unsigned long parent_rate;
 777         int i;
 778         int err;
 779
 780         phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u");
 781         if (IS_ERR(phy->pll_u)) {
 782                 pr_err("Can't get pll_u clock\n");
 783                 return PTR_ERR(phy->pll_u);
 784         }
 785
 786         err = clk_prepare_enable(phy->pll_u);
 787         if (err)
 788                 return err;
 789
 790         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
 791         for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
 792                 if (tegra_freq_table[i].freq == parent_rate) {
 793                         phy->freq = &tegra_freq_table[i];
 794                         break;
 795                 }
 796         }
 797         if (!phy->freq) {
 798                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
 799                 err = -EINVAL;
 800                 goto fail;
 801         }
 802
 803         if (!IS_ERR(phy->vbus)) {
 804                 err = regulator_enable(phy->vbus);
 805                 if (err) {
 806                         dev_err(phy->u_phy.dev,
 807                                 "failed to enable usb vbus regulator: %d\n",
 808                                 err);
 809                         goto fail;
 810                 }
 811         }
 812
 813         if (phy->is_ulpi_phy)
 814                 err = ulpi_open(phy);
 815         else
 816                 err = utmip_pad_open(phy);
 817         if (err < 0)
 818                 goto fail;
 819
 820         return 0;
 821
 822 fail:
 823         clk_disable_unprepare(phy->pll_u);
 824         return err;
 825 }
 826
 827 void tegra_usb_phy_preresume(struct usb_phy *x)
 828 {
 829         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 830
 831         if (!phy->is_ulpi_phy)
 832                 utmi_phy_preresume(phy);
 833 }
 834 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
 835
 836 void tegra_usb_phy_postresume(struct usb_phy *x)
 837 {
 838         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 839
 840         if (!phy->is_ulpi_phy)
 841                 utmi_phy_postresume(phy);
 842 }
 843 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
 844
 845 void tegra_ehci_phy_restore_start(struct usb_phy *x,
 846                                  enum tegra_usb_phy_port_speed port_speed)
 847 {
 848         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 849
 850         if (!phy->is_ulpi_phy)
 851                 utmi_phy_restore_start(phy, port_speed);
 852 }
 853 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
 854
 855 void tegra_ehci_phy_restore_end(struct usb_phy *x)
 856 {
 857         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 858
 859         if (!phy->is_ulpi_phy)
 860                 utmi_phy_restore_end(phy);
 861 }
 862 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
 863
 864 static int read_utmi_param(struct platform_device *pdev, const char *param,
 865                            u8 *dest)
 866 {
 867         u32 value;
 868         int err = of_property_read_u32(pdev->dev.of_node, param, &value);
 869         *dest = (u8)value;
 870         if (err < 0)
 871                 dev_err(&pdev->dev, "Failed to read USB UTMI parameter %s: %d\n",
 872                         param, err);
 873         return err;
 874 }
 875
 876 static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
 877                           struct platform_device *pdev)
 878 {
 879         struct resource *res;
 880         int err;
 881         struct tegra_utmip_config *config;
 882
 883         tegra_phy->is_ulpi_phy = false;
 884
 885         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 886         if (!res) {
 887                 dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n");
 888                 return  -ENXIO;
 889         }
 890
 891         tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
 892                 resource_size(res));
 893         if (!tegra_phy->pad_regs) {
 894                 dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n");
 895                 return -ENOMEM;
 896         }
 897
 898         tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
 899                                          GFP_KERNEL);
 900         if (!tegra_phy->config)
 901                 return -ENOMEM;
 902
 903         config = tegra_phy->config;
 904
 905         err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
 906                 &config->hssync_start_delay);
 907         if (err < 0)
 908                 return err;
 909
 910         err = read_utmi_param(pdev, "nvidia,elastic-limit",
 911                 &config->elastic_limit);
 912         if (err < 0)
 913                 return err;
 914
 915         err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
 916                 &config->idle_wait_delay);
 917         if (err < 0)
 918                 return err;
 919
 920         err = read_utmi_param(pdev, "nvidia,term-range-adj",
 921                 &config->term_range_adj);
 922         if (err < 0)
 923                 return err;
 924
 925         err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
 926                 &config->xcvr_lsfslew);
 927         if (err < 0)
 928                 return err;
 929
 930         err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
 931                 &config->xcvr_lsrslew);
 932         if (err < 0)
 933                 return err;
 934
 935         if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
 936                 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
 937                         &config->xcvr_hsslew);
 938                 if (err < 0)
 939                         return err;
 940
 941                 err = read_utmi_param(pdev, "nvidia,hssquelch-level",
 942                         &config->hssquelch_level);
 943                 if (err < 0)
 944                         return err;
 945
 946                 err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
 947                         &config->hsdiscon_level);
 948                 if (err < 0)
 949                         return err;
 950         }
 951
 952         config->xcvr_setup_use_fuses = of_property_read_bool(
 953                 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
 954
 955         if (!config->xcvr_setup_use_fuses) {
 956                 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
 957                         &config->xcvr_setup);
 958                 if (err < 0)
 959                         return err;
 960         }
 961
 962         return 0;
 963 }
 964
 965 static const struct tegra_phy_soc_config tegra20_soc_config = {
 966         .utmi_pll_config_in_car_module = false,
 967         .has_hostpc = false,
 968         .requires_usbmode_setup = false,
 969         .requires_extra_tuning_parameters = false,
 970 };
 971
 972 static const struct tegra_phy_soc_config tegra30_soc_config = {
 973         .utmi_pll_config_in_car_module = true,
 974         .has_hostpc = true,
 975         .requires_usbmode_setup = true,
 976         .requires_extra_tuning_parameters = true,
 977 };
 978
 979 static const struct of_device_id tegra_usb_phy_id_table[] = {
 980         { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
 981         { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
 982         { },
 983 };
 984 MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
 985
 986 static int tegra_usb_phy_probe(struct platform_device *pdev)
 987 {
 988         const struct of_device_id *match;
 989         struct resource *res;
 990         struct tegra_usb_phy *tegra_phy = NULL;
 991         struct device_node *np = pdev->dev.of_node;
 992         enum usb_phy_interface phy_type;
 993         int err;
 994
 995         tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
 996         if (!tegra_phy)
 997                 return -ENOMEM;
 998
 999         match = of_match_device(tegra_usb_phy_id_table, &pdev->dev);
1000         if (!match) {
1001                 dev_err(&pdev->dev, "Error: No device match found\n");
1002                 return -ENODEV;
1003         }
1004         tegra_phy->soc_config = match->data;
1005
1006         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1007         if (!res) {
1008                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1009                 return  -ENXIO;
1010         }
1011
1012         tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
1013                 resource_size(res));
1014         if (!tegra_phy->regs) {
1015                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1016                 return -ENOMEM;
1017         }
1018
1019         tegra_phy->is_legacy_phy =
1020                 of_property_read_bool(np, "nvidia,has-legacy-mode");
1021
1022         phy_type = of_usb_get_phy_mode(np);
1023         switch (phy_type) {
1024         case USBPHY_INTERFACE_MODE_UTMI:
1025                 err = utmi_phy_probe(tegra_phy, pdev);
1026                 if (err < 0)
1027                         return err;
1028                 break;
1029
1030         case USBPHY_INTERFACE_MODE_ULPI:
1031                 tegra_phy->is_ulpi_phy = true;
1032
1033                 tegra_phy->reset_gpio =
1034                         of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0);
1035                 if (!gpio_is_valid(tegra_phy->reset_gpio)) {
1036                         dev_err(&pdev->dev, "invalid gpio: %d\n",
1037                                 tegra_phy->reset_gpio);
1038                         return tegra_phy->reset_gpio;
1039                 }
1040                 tegra_phy->config = NULL;
1041                 break;
1042
1043         default:
1044                 dev_err(&pdev->dev, "phy_type is invalid or unsupported\n");
1045                 return -EINVAL;
1046         }
1047
1048         if (of_find_property(np, "dr_mode", NULL))
1049                 tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
1050         else
1051                 tegra_phy->mode = USB_DR_MODE_HOST;
1052
1053         if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1054                 dev_err(&pdev->dev, "dr_mode is invalid\n");
1055                 return -EINVAL;
1056         }
1057
1058         /* On some boards, the VBUS regulator doesn't need to be controlled */
1059         if (of_find_property(np, "vbus-supply", NULL)) {
1060                 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1061                 if (IS_ERR(tegra_phy->vbus))
1062                         return PTR_ERR(tegra_phy->vbus);
1063         } else {
1064                 dev_notice(&pdev->dev, "no vbus regulator");
1065                 tegra_phy->vbus = ERR_PTR(-ENODEV);
1066         }
1067
1068         tegra_phy->u_phy.dev = &pdev->dev;
1069         err = tegra_usb_phy_init(tegra_phy);
1070         if (err < 0)
1071                 return err;
1072
1073         tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend;
1074
1075         platform_set_drvdata(pdev, tegra_phy);
1076
1077         err = usb_add_phy_dev(&tegra_phy->u_phy);
1078         if (err < 0) {
1079                 tegra_usb_phy_close(tegra_phy);
1080                 return err;
1081         }
1082
1083         return 0;
1084 }
1085
1086 static int tegra_usb_phy_remove(struct platform_device *pdev)
1087 {
1088         struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1089
1090         usb_remove_phy(&tegra_phy->u_phy);
1091         tegra_usb_phy_close(tegra_phy);
1092
1093         return 0;
1094 }
1095
1096 static struct platform_driver tegra_usb_phy_driver = {
1097         .probe          = tegra_usb_phy_probe,
1098         .remove         = tegra_usb_phy_remove,
1099         .driver         = {
1100                 .name   = "tegra-phy",
1101                 .of_match_table = tegra_usb_phy_id_table,
1102         },
1103 };
1104 module_platform_driver(tegra_usb_phy_driver);
1105
1106 MODULE_DESCRIPTION("Tegra USB PHY driver");
1107 MODULE_LICENSE("GPL v2");