drivers/usb/phy/phy-mxs-usb.c

   1 /*
   2  * Copyright 2012-2014 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2012 Marek Vasut <marex@denx.de>
   4  * on behalf of DENX Software Engineering GmbH
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/clk.h>
  18 #include <linux/usb/otg.h>
  19 #include <linux/stmp_device.h>
  20 #include <linux/delay.h>
  21 #include <linux/err.h>
  22 #include <linux/io.h>
  23 #include <linux/of_device.h>
  24 #include <linux/regmap.h>
  25 #include <linux/mfd/syscon.h>
  26
  27 #define DRIVER_NAME "mxs_phy"
  28
  29 #define HW_USBPHY_PWD                           0x00
  30 #define HW_USBPHY_TX                            0x10
  31 #define HW_USBPHY_CTRL                          0x30
  32 #define HW_USBPHY_CTRL_SET                      0x34
  33 #define HW_USBPHY_CTRL_CLR                      0x38
  34
  35 #define HW_USBPHY_DEBUG_SET                     0x54
  36 #define HW_USBPHY_DEBUG_CLR                     0x58
  37
  38 #define HW_USBPHY_IP                            0x90
  39 #define HW_USBPHY_IP_SET                        0x94
  40 #define HW_USBPHY_IP_CLR                        0x98
  41
  42 #define GM_USBPHY_TX_TXCAL45DP(x)            (((x) & 0xf) << 16)
  43 #define GM_USBPHY_TX_TXCAL45DN(x)            (((x) & 0xf) << 8)
  44 #define GM_USBPHY_TX_D_CAL(x)                (((x) & 0xf) << 0)
  45
  46 #define BM_USBPHY_CTRL_SFTRST                   BIT(31)
  47 #define BM_USBPHY_CTRL_CLKGATE                  BIT(30)
  48 #define BM_USBPHY_CTRL_OTG_ID_VALUE             BIT(27)
  49 #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS        BIT(26)
  50 #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE     BIT(25)
  51 #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP           BIT(23)
  52 #define BM_USBPHY_CTRL_ENIDCHG_WKUP             BIT(22)
  53 #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP           BIT(21)
  54 #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD        BIT(20)
  55 #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE        BIT(19)
  56 #define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL         BIT(18)
  57 #define BM_USBPHY_CTRL_ENUTMILEVEL3             BIT(15)
  58 #define BM_USBPHY_CTRL_ENUTMILEVEL2             BIT(14)
  59 #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT       BIT(1)
  60
  61 #define BM_USBPHY_IP_FIX                       (BIT(17) | BIT(18))
  62
  63 #define BM_USBPHY_DEBUG_CLKGATE                 BIT(30)
  64
  65 /* Anatop Registers */
  66 #define ANADIG_ANA_MISC0                        0x150
  67 #define ANADIG_ANA_MISC0_SET                    0x154
  68 #define ANADIG_ANA_MISC0_CLR                    0x158
  69
  70 #define ANADIG_USB1_VBUS_DET_STAT               0x1c0
  71 #define ANADIG_USB2_VBUS_DET_STAT               0x220
  72
  73 #define ANADIG_USB1_LOOPBACK_SET                0x1e4
  74 #define ANADIG_USB1_LOOPBACK_CLR                0x1e8
  75 #define ANADIG_USB2_LOOPBACK_SET                0x244
  76 #define ANADIG_USB2_LOOPBACK_CLR                0x248
  77
  78 #define ANADIG_USB1_MISC                        0x1f0
  79 #define ANADIG_USB2_MISC                        0x250
  80
  81 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG    BIT(12)
  82 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11)
  83
  84 #define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3)
  85 #define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3)
  86
  87 #define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1   BIT(2)
  88 #define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN      BIT(5)
  89 #define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1   BIT(2)
  90 #define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN      BIT(5)
  91
  92 #define BM_ANADIG_USB1_MISC_RX_VPIN_FS          BIT(29)
  93 #define BM_ANADIG_USB1_MISC_RX_VMIN_FS          BIT(28)
  94 #define BM_ANADIG_USB2_MISC_RX_VPIN_FS          BIT(29)
  95 #define BM_ANADIG_USB2_MISC_RX_VMIN_FS          BIT(28)
  96
  97 #define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
  98
  99 /* Do disconnection between PHY and controller without vbus */
 100 #define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS    BIT(0)
 101
 102 /*
 103  * The PHY will be in messy if there is a wakeup after putting
 104  * bus to suspend (set portsc.suspendM) but before setting PHY to low
 105  * power mode (set portsc.phcd).
 106  */
 107 #define MXS_PHY_ABNORMAL_IN_SUSPEND             BIT(1)
 108
 109 /*
 110  * The SOF sends too fast after resuming, it will cause disconnection
 111  * between host and high speed device.
 112  */
 113 #define MXS_PHY_SENDING_SOF_TOO_FAST            BIT(2)
 114
 115 /*
 116  * IC has bug fixes logic, they include
 117  * MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST
 118  * which are described at above flags, the RTL will handle it
 119  * according to different versions.
 120  */
 121 #define MXS_PHY_NEED_IP_FIX                     BIT(3)
 122
 123 /* Minimum and maximum values for device tree entries */
 124 #define MXS_PHY_TX_CAL45_MIN                    30
 125 #define MXS_PHY_TX_CAL45_MAX                    55
 126 #define MXS_PHY_TX_D_CAL_MIN                    79
 127 #define MXS_PHY_TX_D_CAL_MAX                    119
 128
 129 struct mxs_phy_data {
 130         unsigned int flags;
 131 };
 132
 133 static const struct mxs_phy_data imx23_phy_data = {
 134         .flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST,
 135 };
 136
 137 static const struct mxs_phy_data imx6q_phy_data = {
 138         .flags = MXS_PHY_SENDING_SOF_TOO_FAST |
 139                 MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
 140                 MXS_PHY_NEED_IP_FIX,
 141 };
 142
 143 static const struct mxs_phy_data imx6sl_phy_data = {
 144         .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
 145                 MXS_PHY_NEED_IP_FIX,
 146 };
 147
 148 static const struct mxs_phy_data vf610_phy_data = {
 149         .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
 150                 MXS_PHY_NEED_IP_FIX,
 151 };
 152
 153 static const struct mxs_phy_data imx6sx_phy_data = {
 154         .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
 155 };
 156
 157 static const struct mxs_phy_data imx6ul_phy_data = {
 158         .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
 159 };
 160
 161 static const struct of_device_id mxs_phy_dt_ids[] = {
 162         { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, },
 163         { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
 164         { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
 165         { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
 166         { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, },
 167         { .compatible = "fsl,imx6ul-usbphy", .data = &imx6ul_phy_data, },
 168         { /* sentinel */ }
 169 };
 170 MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
 171
 172 struct mxs_phy {
 173         struct usb_phy phy;
 174         struct clk *clk;
 175         const struct mxs_phy_data *data;
 176         struct regmap *regmap_anatop;
 177         int port_id;
 178         u32 tx_reg_set;
 179         u32 tx_reg_mask;
 180 };
 181
 182 static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy)
 183 {
 184         return mxs_phy->data == &imx6q_phy_data;
 185 }
 186
 187 static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy)
 188 {
 189         return mxs_phy->data == &imx6sl_phy_data;
 190 }
 191
 192 /*
 193  * PHY needs some 32K cycles to switch from 32K clock to
 194  * bus (such as AHB/AXI, etc) clock.
 195  */
 196 static void mxs_phy_clock_switch_delay(void)
 197 {
 198         usleep_range(300, 400);
 199 }
 200
 201 static void mxs_phy_tx_init(struct mxs_phy *mxs_phy)
 202 {
 203         void __iomem *base = mxs_phy->phy.io_priv;
 204         u32 phytx;
 205
 206         /* Update TX register if there is anything to write */
 207         if (mxs_phy->tx_reg_mask) {
 208                 phytx = readl(base + HW_USBPHY_TX);
 209                 phytx &= ~mxs_phy->tx_reg_mask;
 210                 phytx |= mxs_phy->tx_reg_set;
 211                 writel(phytx, base + HW_USBPHY_TX);
 212         }
 213 }
 214
 215 static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
 216 {
 217         int ret;
 218         void __iomem *base = mxs_phy->phy.io_priv;
 219
 220         ret = stmp_reset_block(base + HW_USBPHY_CTRL);
 221         if (ret)
 222                 return ret;
 223
 224         /* Power up the PHY */
 225         writel(0, base + HW_USBPHY_PWD);
 226
 227         /*
 228          * USB PHY Ctrl Setting
 229          * - Auto clock/power on
 230          * - Enable full/low speed support
 231          */
 232         writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
 233                 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
 234                 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
 235                 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
 236                 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL |
 237                 BM_USBPHY_CTRL_ENUTMILEVEL2 |
 238                 BM_USBPHY_CTRL_ENUTMILEVEL3,
 239                base + HW_USBPHY_CTRL_SET);
 240
 241         if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX)
 242                 writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET);
 243
 244         mxs_phy_tx_init(mxs_phy);
 245
 246         return 0;
 247 }
 248
 249 /* Return true if the vbus is there */
 250 static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy)
 251 {
 252         unsigned int vbus_value = 0;
 253
 254         if (!mxs_phy->regmap_anatop)
 255                 return false;
 256
 257         if (mxs_phy->port_id == 0)
 258                 regmap_read(mxs_phy->regmap_anatop,
 259                         ANADIG_USB1_VBUS_DET_STAT,
 260                         &vbus_value);
 261         else if (mxs_phy->port_id == 1)
 262                 regmap_read(mxs_phy->regmap_anatop,
 263                         ANADIG_USB2_VBUS_DET_STAT,
 264                         &vbus_value);
 265
 266         if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)
 267                 return true;
 268         else
 269                 return false;
 270 }
 271
 272 static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect)
 273 {
 274         void __iomem *base = mxs_phy->phy.io_priv;
 275         u32 reg;
 276
 277         if (disconnect)
 278                 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
 279                         base + HW_USBPHY_DEBUG_CLR);
 280
 281         if (mxs_phy->port_id == 0) {
 282                 reg = disconnect ? ANADIG_USB1_LOOPBACK_SET
 283                         : ANADIG_USB1_LOOPBACK_CLR;
 284                 regmap_write(mxs_phy->regmap_anatop, reg,
 285                         BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 |
 286                         BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN);
 287         } else if (mxs_phy->port_id == 1) {
 288                 reg = disconnect ? ANADIG_USB2_LOOPBACK_SET
 289                         : ANADIG_USB2_LOOPBACK_CLR;
 290                 regmap_write(mxs_phy->regmap_anatop, reg,
 291                         BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 |
 292                         BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN);
 293         }
 294
 295         if (!disconnect)
 296                 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
 297                         base + HW_USBPHY_DEBUG_SET);
 298
 299         /* Delay some time, and let Linestate be SE0 for controller */
 300         if (disconnect)
 301                 usleep_range(500, 1000);
 302 }
 303
 304 static bool mxs_phy_is_otg_host(struct mxs_phy *mxs_phy)
 305 {
 306         return IS_ENABLED(CONFIG_USB_OTG) &&
 307                 mxs_phy->phy.last_event == USB_EVENT_ID;
 308 }
 309
 310 static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on)
 311 {
 312         bool vbus_is_on = false;
 313
 314         /* If the SoCs don't need to disconnect line without vbus, quit */
 315         if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS))
 316                 return;
 317
 318         /* If the SoCs don't have anatop, quit */
 319         if (!mxs_phy->regmap_anatop)
 320                 return;
 321
 322         vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
 323
 324         if (on && !vbus_is_on && !mxs_phy_is_otg_host(mxs_phy))
 325                 __mxs_phy_disconnect_line(mxs_phy, true);
 326         else
 327                 __mxs_phy_disconnect_line(mxs_phy, false);
 328
 329 }
 330
 331 static int mxs_phy_init(struct usb_phy *phy)
 332 {
 333         int ret;
 334         struct mxs_phy *mxs_phy = to_mxs_phy(phy);
 335
 336         mxs_phy_clock_switch_delay();
 337         ret = clk_prepare_enable(mxs_phy->clk);
 338         if (ret)
 339                 return ret;
 340
 341         return mxs_phy_hw_init(mxs_phy);
 342 }
 343
 344 static void mxs_phy_shutdown(struct usb_phy *phy)
 345 {
 346         struct mxs_phy *mxs_phy = to_mxs_phy(phy);
 347         u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP |
 348                         BM_USBPHY_CTRL_ENDPDMCHG_WKUP |
 349                         BM_USBPHY_CTRL_ENIDCHG_WKUP |
 350                         BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
 351                         BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
 352                         BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
 353                         BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
 354                         BM_USBPHY_CTRL_ENAUTO_PWRON_PLL;
 355
 356         writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR);
 357         writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD);
 358
 359         writel(BM_USBPHY_CTRL_CLKGATE,
 360                phy->io_priv + HW_USBPHY_CTRL_SET);
 361
 362         clk_disable_unprepare(mxs_phy->clk);
 363 }
 364
 365 static bool mxs_phy_is_low_speed_connection(struct mxs_phy *mxs_phy)
 366 {
 367         unsigned int line_state;
 368         /* bit definition is the same for all controllers */
 369         unsigned int dp_bit = BM_ANADIG_USB1_MISC_RX_VPIN_FS,
 370                      dm_bit = BM_ANADIG_USB1_MISC_RX_VMIN_FS;
 371         unsigned int reg = ANADIG_USB1_MISC;
 372
 373         /* If the SoCs don't have anatop, quit */
 374         if (!mxs_phy->regmap_anatop)
 375                 return false;
 376
 377         if (mxs_phy->port_id == 0)
 378                 reg = ANADIG_USB1_MISC;
 379         else if (mxs_phy->port_id == 1)
 380                 reg = ANADIG_USB2_MISC;
 381
 382         regmap_read(mxs_phy->regmap_anatop, reg, &line_state);
 383
 384         if ((line_state & (dp_bit | dm_bit)) ==  dm_bit)
 385                 return true;
 386         else
 387                 return false;
 388 }
 389
 390 static int mxs_phy_suspend(struct usb_phy *x, int suspend)
 391 {
 392         int ret;
 393         struct mxs_phy *mxs_phy = to_mxs_phy(x);
 394         bool low_speed_connection, vbus_is_on;
 395
 396         low_speed_connection = mxs_phy_is_low_speed_connection(mxs_phy);
 397         vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
 398
 399         if (suspend) {
 400                 /*
 401                  * FIXME: Do not power down RXPWD1PT1 bit for low speed
 402                  * connect. The low speed connection will have problem at
 403                  * very rare cases during usb suspend and resume process.
 404                  */
 405                 if (low_speed_connection & vbus_is_on) {
 406                         /*
 407                          * If value to be set as pwd value is not 0xffffffff,
 408                          * several 32Khz cycles are needed.
 409                          */
 410                         mxs_phy_clock_switch_delay();
 411                         writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD);
 412                 } else {
 413                         writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
 414                 }
 415                 writel(BM_USBPHY_CTRL_CLKGATE,
 416                        x->io_priv + HW_USBPHY_CTRL_SET);
 417                 clk_disable_unprepare(mxs_phy->clk);
 418         } else {
 419                 mxs_phy_clock_switch_delay();
 420                 ret = clk_prepare_enable(mxs_phy->clk);
 421                 if (ret)
 422                         return ret;
 423                 writel(BM_USBPHY_CTRL_CLKGATE,
 424                        x->io_priv + HW_USBPHY_CTRL_CLR);
 425                 writel(0, x->io_priv + HW_USBPHY_PWD);
 426         }
 427
 428         return 0;
 429 }
 430
 431 static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled)
 432 {
 433         struct mxs_phy *mxs_phy = to_mxs_phy(x);
 434         u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP |
 435                         BM_USBPHY_CTRL_ENDPDMCHG_WKUP |
 436                                 BM_USBPHY_CTRL_ENIDCHG_WKUP;
 437         if (enabled) {
 438                 mxs_phy_disconnect_line(mxs_phy, true);
 439                 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET);
 440         } else {
 441                 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR);
 442                 mxs_phy_disconnect_line(mxs_phy, false);
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int mxs_phy_on_connect(struct usb_phy *phy,
 449                 enum usb_device_speed speed)
 450 {
 451         dev_dbg(phy->dev, "%s device has connected\n",
 452                 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
 453
 454         if (speed == USB_SPEED_HIGH)
 455                 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
 456                        phy->io_priv + HW_USBPHY_CTRL_SET);
 457
 458         return 0;
 459 }
 460
 461 static int mxs_phy_on_disconnect(struct usb_phy *phy,
 462                 enum usb_device_speed speed)
 463 {
 464         dev_dbg(phy->dev, "%s device has disconnected\n",
 465                 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
 466
 467         /* Sometimes, the speed is not high speed when the error occurs */
 468         if (readl(phy->io_priv + HW_USBPHY_CTRL) &
 469                         BM_USBPHY_CTRL_ENHOSTDISCONDETECT)
 470                 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
 471                        phy->io_priv + HW_USBPHY_CTRL_CLR);
 472
 473         return 0;
 474 }
 475
 476 static int mxs_phy_probe(struct platform_device *pdev)
 477 {
 478         struct resource *res;
 479         void __iomem *base;
 480         struct clk *clk;
 481         struct mxs_phy *mxs_phy;
 482         int ret;
 483         const struct of_device_id *of_id;
 484         struct device_node *np = pdev->dev.of_node;
 485         u32 val;
 486
 487         of_id = of_match_device(mxs_phy_dt_ids, &pdev->dev);
 488         if (!of_id)
 489                 return -ENODEV;
 490
 491         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 492         base = devm_ioremap_resource(&pdev->dev, res);
 493         if (IS_ERR(base))
 494                 return PTR_ERR(base);
 495
 496         clk = devm_clk_get(&pdev->dev, NULL);
 497         if (IS_ERR(clk)) {
 498                 dev_err(&pdev->dev,
 499                         "can't get the clock, err=%ld", PTR_ERR(clk));
 500                 return PTR_ERR(clk);
 501         }
 502
 503         mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL);
 504         if (!mxs_phy)
 505                 return -ENOMEM;
 506
 507         /* Some SoCs don't have anatop registers */
 508         if (of_get_property(np, "fsl,anatop", NULL)) {
 509                 mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle
 510                         (np, "fsl,anatop");
 511                 if (IS_ERR(mxs_phy->regmap_anatop)) {
 512                         dev_dbg(&pdev->dev,
 513                                 "failed to find regmap for anatop\n");
 514                         return PTR_ERR(mxs_phy->regmap_anatop);
 515                 }
 516         }
 517
 518         /* Precompute which bits of the TX register are to be updated, if any */
 519         if (!of_property_read_u32(np, "fsl,tx-cal-45-dn-ohms", &val) &&
 520             val >= MXS_PHY_TX_CAL45_MIN && val <= MXS_PHY_TX_CAL45_MAX) {
 521                 /* Scale to a 4-bit value */
 522                 val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF
 523                         / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN);
 524                 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DN(~0);
 525                 mxs_phy->tx_reg_set  |= GM_USBPHY_TX_TXCAL45DN(val);
 526         }
 527
 528         if (!of_property_read_u32(np, "fsl,tx-cal-45-dp-ohms", &val) &&
 529             val >= MXS_PHY_TX_CAL45_MIN && val <= MXS_PHY_TX_CAL45_MAX) {
 530                 /* Scale to a 4-bit value. */
 531                 val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF
 532                         / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN);
 533                 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DP(~0);
 534                 mxs_phy->tx_reg_set  |= GM_USBPHY_TX_TXCAL45DP(val);
 535         }
 536
 537         if (!of_property_read_u32(np, "fsl,tx-d-cal", &val) &&
 538             val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) {
 539                 /* Scale to a 4-bit value.  Round up the values and heavily
 540                  * weight the rounding by adding 2/3 of the denominator.
 541                  */
 542                 val = ((MXS_PHY_TX_D_CAL_MAX - val) * 0xF
 543                         + (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN) * 2/3)
 544                         / (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN);
 545                 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0);
 546                 mxs_phy->tx_reg_set  |= GM_USBPHY_TX_D_CAL(val);
 547         }
 548
 549         ret = of_alias_get_id(np, "usbphy");
 550         if (ret < 0)
 551                 dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret);
 552         mxs_phy->port_id = ret;
 553
 554         mxs_phy->phy.io_priv            = base;
 555         mxs_phy->phy.dev                = &pdev->dev;
 556         mxs_phy->phy.label              = DRIVER_NAME;
 557         mxs_phy->phy.init               = mxs_phy_init;
 558         mxs_phy->phy.shutdown           = mxs_phy_shutdown;
 559         mxs_phy->phy.set_suspend        = mxs_phy_suspend;
 560         mxs_phy->phy.notify_connect     = mxs_phy_on_connect;
 561         mxs_phy->phy.notify_disconnect  = mxs_phy_on_disconnect;
 562         mxs_phy->phy.type               = USB_PHY_TYPE_USB2;
 563         mxs_phy->phy.set_wakeup         = mxs_phy_set_wakeup;
 564
 565         mxs_phy->clk = clk;
 566         mxs_phy->data = of_id->data;
 567
 568         platform_set_drvdata(pdev, mxs_phy);
 569
 570         device_set_wakeup_capable(&pdev->dev, true);
 571
 572         return usb_add_phy_dev(&mxs_phy->phy);
 573 }
 574
 575 static int mxs_phy_remove(struct platform_device *pdev)
 576 {
 577         struct mxs_phy *mxs_phy = platform_get_drvdata(pdev);
 578
 579         usb_remove_phy(&mxs_phy->phy);
 580
 581         return 0;
 582 }
 583
 584 #ifdef CONFIG_PM_SLEEP
 585 static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on)
 586 {
 587         unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR;
 588
 589         /* If the SoCs don't have anatop, quit */
 590         if (!mxs_phy->regmap_anatop)
 591                 return;
 592
 593         if (is_imx6q_phy(mxs_phy))
 594                 regmap_write(mxs_phy->regmap_anatop, reg,
 595                         BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG);
 596         else if (is_imx6sl_phy(mxs_phy))
 597                 regmap_write(mxs_phy->regmap_anatop,
 598                         reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL);
 599 }
 600
 601 static int mxs_phy_system_suspend(struct device *dev)
 602 {
 603         struct mxs_phy *mxs_phy = dev_get_drvdata(dev);
 604
 605         if (device_may_wakeup(dev))
 606                 mxs_phy_enable_ldo_in_suspend(mxs_phy, true);
 607
 608         return 0;
 609 }
 610
 611 static int mxs_phy_system_resume(struct device *dev)
 612 {
 613         struct mxs_phy *mxs_phy = dev_get_drvdata(dev);
 614
 615         if (device_may_wakeup(dev))
 616                 mxs_phy_enable_ldo_in_suspend(mxs_phy, false);
 617
 618         return 0;
 619 }
 620 #endif /* CONFIG_PM_SLEEP */
 621
 622 static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend,
 623                 mxs_phy_system_resume);
 624
 625 static struct platform_driver mxs_phy_driver = {
 626         .probe = mxs_phy_probe,
 627         .remove = mxs_phy_remove,
 628         .driver = {
 629                 .name = DRIVER_NAME,
 630                 .of_match_table = mxs_phy_dt_ids,
 631                 .pm = &mxs_phy_pm,
 632          },
 633 };
 634
 635 static int __init mxs_phy_module_init(void)
 636 {
 637         return platform_driver_register(&mxs_phy_driver);
 638 }
 639 postcore_initcall(mxs_phy_module_init);
 640
 641 static void __exit mxs_phy_module_exit(void)
 642 {
 643         platform_driver_unregister(&mxs_phy_driver);
 644 }
 645 module_exit(mxs_phy_module_exit);
 646
 647 MODULE_ALIAS("platform:mxs-usb-phy");
 648 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
 649 MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>");
 650 MODULE_DESCRIPTION("Freescale MXS USB PHY driver");
 651 MODULE_LICENSE("GPL");