2 * MUSB OTG peripheral driver ep0 handling
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/spinlock.h>
40 #include <linux/device.h>
41 #include <linux/interrupt.h>
43 #include "musb_core.h"
45 /* ep0 is always musb->endpoints[0].ep_in */
46 #define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
49 * locking note: we use only the controller lock, for simpler correctness.
50 * It's always held with IRQs blocked.
52 * It protects the ep0 request queue as well as ep0_state, not just the
53 * controller and indexed registers. And that lock stays held unless it
54 * needs to be dropped to allow reentering this driver ... like upcalls to
55 * the gadget driver, or adjusting endpoint halt status.
58 static char *decode_ep0stage(u8 stage)
61 case MUSB_EP0_STAGE_IDLE: return "idle";
62 case MUSB_EP0_STAGE_SETUP: return "setup";
63 case MUSB_EP0_STAGE_TX: return "in";
64 case MUSB_EP0_STAGE_RX: return "out";
65 case MUSB_EP0_STAGE_ACKWAIT: return "wait";
66 case MUSB_EP0_STAGE_STATUSIN: return "in/status";
67 case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
72 /* handle a standard GET_STATUS request
73 * Context: caller holds controller lock
75 static int service_tx_status_request(
77 const struct usb_ctrlrequest *ctrlrequest)
79 void __iomem *mbase = musb->mregs;
81 u8 result[2], epnum = 0;
82 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
87 case USB_RECIP_DEVICE:
88 result[0] = musb->g.is_selfpowered << USB_DEVICE_SELF_POWERED;
89 result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
91 result[0] |= musb->g.b_hnp_enable
92 << USB_DEVICE_B_HNP_ENABLE;
93 result[0] |= musb->g.a_alt_hnp_support
94 << USB_DEVICE_A_ALT_HNP_SUPPORT;
95 result[0] |= musb->g.a_hnp_support
96 << USB_DEVICE_A_HNP_SUPPORT;
100 case USB_RECIP_INTERFACE:
104 case USB_RECIP_ENDPOINT: {
110 epnum = (u8) ctrlrequest->wIndex;
116 is_in = epnum & USB_DIR_IN;
118 if (epnum >= MUSB_C_NUM_EPS) {
124 ep = &musb->endpoints[epnum].ep_in;
126 ep = &musb->endpoints[epnum].ep_out;
127 regs = musb->endpoints[epnum].regs;
134 musb_ep_select(mbase, epnum);
136 tmp = musb_readw(regs, MUSB_TXCSR)
137 & MUSB_TXCSR_P_SENDSTALL;
139 tmp = musb_readw(regs, MUSB_RXCSR)
140 & MUSB_RXCSR_P_SENDSTALL;
141 musb_ep_select(mbase, 0);
143 result[0] = tmp ? 1 : 0;
147 /* class, vendor, etc ... delegate */
152 /* fill up the fifo; caller updates csr0 */
154 u16 len = le16_to_cpu(ctrlrequest->wLength);
158 musb_write_fifo(&musb->endpoints[0], len, result);
165 * handle a control-IN request, the end0 buffer contains the current request
166 * that is supposed to be a standard control request. Assumes the fifo to
167 * be at least 2 bytes long.
169 * @return 0 if the request was NOT HANDLED,
171 * > 0 when the request is processed
173 * Context: caller holds controller lock
176 service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
178 int handled = 0; /* not handled */
180 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
181 == USB_TYPE_STANDARD) {
182 switch (ctrlrequest->bRequest) {
183 case USB_REQ_GET_STATUS:
184 handled = service_tx_status_request(musb,
188 /* case USB_REQ_SYNC_FRAME: */
198 * Context: caller holds controller lock
200 static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
202 musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
206 * Tries to start B-device HNP negotiation if enabled via sysfs
208 static inline void musb_try_b_hnp_enable(struct musb *musb)
210 void __iomem *mbase = musb->mregs;
213 musb_dbg(musb, "HNP: Setting HR");
214 devctl = musb_readb(mbase, MUSB_DEVCTL);
215 musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
219 * Handle all control requests with no DATA stage, including standard
221 * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
222 * always delegated to the gadget driver
223 * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
224 * always handled here, except for class/vendor/... features
226 * Context: caller holds controller lock
229 service_zero_data_request(struct musb *musb,
230 struct usb_ctrlrequest *ctrlrequest)
231 __releases(musb->lock)
232 __acquires(musb->lock)
234 int handled = -EINVAL;
235 void __iomem *mbase = musb->mregs;
236 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
238 /* the gadget driver handles everything except what we MUST handle */
239 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
240 == USB_TYPE_STANDARD) {
241 switch (ctrlrequest->bRequest) {
242 case USB_REQ_SET_ADDRESS:
243 /* change it after the status stage */
244 musb->set_address = true;
245 musb->address = (u8) (ctrlrequest->wValue & 0x7f);
249 case USB_REQ_CLEAR_FEATURE:
251 case USB_RECIP_DEVICE:
252 if (ctrlrequest->wValue
253 != USB_DEVICE_REMOTE_WAKEUP)
255 musb->may_wakeup = 0;
258 case USB_RECIP_INTERFACE:
260 case USB_RECIP_ENDPOINT:{
262 ctrlrequest->wIndex & 0x0f;
263 struct musb_ep *musb_ep;
264 struct musb_hw_ep *ep;
265 struct musb_request *request;
270 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
271 ctrlrequest->wValue != USB_ENDPOINT_HALT)
274 ep = musb->endpoints + epnum;
276 is_in = ctrlrequest->wIndex & USB_DIR_IN;
278 musb_ep = &ep->ep_in;
280 musb_ep = &ep->ep_out;
285 /* Ignore request if endpoint is wedged */
289 musb_ep_select(mbase, epnum);
291 csr = musb_readw(regs, MUSB_TXCSR);
292 csr |= MUSB_TXCSR_CLRDATATOG |
293 MUSB_TXCSR_P_WZC_BITS;
294 csr &= ~(MUSB_TXCSR_P_SENDSTALL |
295 MUSB_TXCSR_P_SENTSTALL |
296 MUSB_TXCSR_TXPKTRDY);
297 musb_writew(regs, MUSB_TXCSR, csr);
299 csr = musb_readw(regs, MUSB_RXCSR);
300 csr |= MUSB_RXCSR_CLRDATATOG |
301 MUSB_RXCSR_P_WZC_BITS;
302 csr &= ~(MUSB_RXCSR_P_SENDSTALL |
303 MUSB_RXCSR_P_SENTSTALL);
304 musb_writew(regs, MUSB_RXCSR, csr);
307 /* Maybe start the first request in the queue */
308 request = next_request(musb_ep);
309 if (!musb_ep->busy && request) {
310 musb_dbg(musb, "restarting the request");
311 musb_ep_restart(musb, request);
314 /* select ep0 again */
315 musb_ep_select(mbase, 0);
318 /* class, vendor, etc ... delegate */
324 case USB_REQ_SET_FEATURE:
326 case USB_RECIP_DEVICE:
328 switch (ctrlrequest->wValue) {
329 case USB_DEVICE_REMOTE_WAKEUP:
330 musb->may_wakeup = 1;
332 case USB_DEVICE_TEST_MODE:
333 if (musb->g.speed != USB_SPEED_HIGH)
335 if (ctrlrequest->wIndex & 0xff)
338 switch (ctrlrequest->wIndex >> 8) {
340 pr_debug("TEST_J\n");
347 pr_debug("TEST_K\n");
353 pr_debug("TEST_SE0_NAK\n");
359 pr_debug("TEST_PACKET\n");
366 pr_debug("TEST_FORCE_HS\n");
372 pr_debug("TEST_FORCE_FS\n");
377 /* TEST_FIFO_ACCESS */
378 pr_debug("TEST_FIFO_ACCESS\n");
380 MUSB_TEST_FIFO_ACCESS;
383 /* TEST_FORCE_HOST */
384 pr_debug("TEST_FORCE_HOST\n");
386 MUSB_TEST_FORCE_HOST;
392 /* enter test mode after irq */
394 musb->test_mode = true;
396 case USB_DEVICE_B_HNP_ENABLE:
399 musb->g.b_hnp_enable = 1;
400 musb_try_b_hnp_enable(musb);
402 case USB_DEVICE_A_HNP_SUPPORT:
405 musb->g.a_hnp_support = 1;
407 case USB_DEVICE_A_ALT_HNP_SUPPORT:
410 musb->g.a_alt_hnp_support = 1;
412 case USB_DEVICE_DEBUG_MODE:
422 case USB_RECIP_INTERFACE:
425 case USB_RECIP_ENDPOINT:{
427 ctrlrequest->wIndex & 0x0f;
428 struct musb_ep *musb_ep;
429 struct musb_hw_ep *ep;
434 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
435 ctrlrequest->wValue != USB_ENDPOINT_HALT)
438 ep = musb->endpoints + epnum;
440 is_in = ctrlrequest->wIndex & USB_DIR_IN;
442 musb_ep = &ep->ep_in;
444 musb_ep = &ep->ep_out;
448 musb_ep_select(mbase, epnum);
450 csr = musb_readw(regs, MUSB_TXCSR);
451 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
452 csr |= MUSB_TXCSR_FLUSHFIFO;
453 csr |= MUSB_TXCSR_P_SENDSTALL
454 | MUSB_TXCSR_CLRDATATOG
455 | MUSB_TXCSR_P_WZC_BITS;
456 musb_writew(regs, MUSB_TXCSR, csr);
458 csr = musb_readw(regs, MUSB_RXCSR);
459 csr |= MUSB_RXCSR_P_SENDSTALL
460 | MUSB_RXCSR_FLUSHFIFO
461 | MUSB_RXCSR_CLRDATATOG
462 | MUSB_RXCSR_P_WZC_BITS;
463 musb_writew(regs, MUSB_RXCSR, csr);
466 /* select ep0 again */
467 musb_ep_select(mbase, 0);
472 /* class, vendor, etc ... delegate */
478 /* delegate SET_CONFIGURATION, etc */
486 /* we have an ep0out data packet
487 * Context: caller holds controller lock
489 static void ep0_rxstate(struct musb *musb)
491 void __iomem *regs = musb->control_ep->regs;
492 struct musb_request *request;
493 struct usb_request *req;
496 request = next_ep0_request(musb);
497 req = &request->request;
499 /* read packet and ack; or stall because of gadget driver bug:
500 * should have provided the rx buffer before setup() returned.
503 void *buf = req->buf + req->actual;
504 unsigned len = req->length - req->actual;
506 /* read the buffer */
507 count = musb_readb(regs, MUSB_COUNT0);
509 req->status = -EOVERFLOW;
513 musb_read_fifo(&musb->endpoints[0], count, buf);
514 req->actual += count;
516 csr = MUSB_CSR0_P_SVDRXPKTRDY;
517 if (count < 64 || req->actual == req->length) {
518 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
519 csr |= MUSB_CSR0_P_DATAEND;
523 csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
526 /* Completion handler may choose to stall, e.g. because the
527 * message just received holds invalid data.
531 musb_g_ep0_giveback(musb, req);
536 musb_ep_select(musb->mregs, 0);
537 musb_writew(regs, MUSB_CSR0, csr);
541 * transmitting to the host (IN), this code might be called from IRQ
542 * and from kernel thread.
544 * Context: caller holds controller lock
546 static void ep0_txstate(struct musb *musb)
548 void __iomem *regs = musb->control_ep->regs;
549 struct musb_request *req = next_ep0_request(musb);
550 struct usb_request *request;
551 u16 csr = MUSB_CSR0_TXPKTRDY;
557 musb_dbg(musb, "odd; csr0 %04x", musb_readw(regs, MUSB_CSR0));
561 request = &req->request;
564 fifo_src = (u8 *) request->buf + request->actual;
565 fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
566 request->length - request->actual);
567 musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
568 request->actual += fifo_count;
570 /* update the flags */
571 if (fifo_count < MUSB_MAX_END0_PACKET
572 || (request->actual == request->length
573 && !request->zero)) {
574 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
575 csr |= MUSB_CSR0_P_DATAEND;
579 /* report completions as soon as the fifo's loaded; there's no
580 * win in waiting till this last packet gets acked. (other than
581 * very precise fault reporting, needed by USB TMC; possible with
582 * this hardware, but not usable from portable gadget drivers.)
586 musb_g_ep0_giveback(musb, request);
592 /* send it out, triggering a "txpktrdy cleared" irq */
593 musb_ep_select(musb->mregs, 0);
594 musb_writew(regs, MUSB_CSR0, csr);
598 * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
599 * Fields are left in USB byte-order.
601 * Context: caller holds controller lock.
604 musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
606 struct musb_request *r;
607 void __iomem *regs = musb->control_ep->regs;
609 musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
611 /* NOTE: earlier 2.6 versions changed setup packets to host
612 * order, but now USB packets always stay in USB byte order.
614 musb_dbg(musb, "SETUP req%02x.%02x v%04x i%04x l%d",
617 le16_to_cpu(req->wValue),
618 le16_to_cpu(req->wIndex),
619 le16_to_cpu(req->wLength));
621 /* clean up any leftover transfers */
622 r = next_ep0_request(musb);
624 musb_g_ep0_giveback(musb, &r->request);
626 /* For zero-data requests we want to delay the STATUS stage to
627 * avoid SETUPEND errors. If we read data (OUT), delay accepting
628 * packets until there's a buffer to store them in.
630 * If we write data, the controller acts happier if we enable
631 * the TX FIFO right away, and give the controller a moment
634 musb->set_address = false;
635 musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
636 if (req->wLength == 0) {
637 if (req->bRequestType & USB_DIR_IN)
638 musb->ackpend |= MUSB_CSR0_TXPKTRDY;
639 musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
640 } else if (req->bRequestType & USB_DIR_IN) {
641 musb->ep0_state = MUSB_EP0_STAGE_TX;
642 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
643 while ((musb_readw(regs, MUSB_CSR0)
644 & MUSB_CSR0_RXPKTRDY) != 0)
648 musb->ep0_state = MUSB_EP0_STAGE_RX;
652 forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
653 __releases(musb->lock)
654 __acquires(musb->lock)
657 if (!musb->gadget_driver)
659 spin_unlock(&musb->lock);
660 retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
661 spin_lock(&musb->lock);
666 * Handle peripheral ep0 interrupt
668 * Context: irq handler; we won't re-enter the driver that way.
670 irqreturn_t musb_g_ep0_irq(struct musb *musb)
674 void __iomem *mbase = musb->mregs;
675 void __iomem *regs = musb->endpoints[0].regs;
676 irqreturn_t retval = IRQ_NONE;
678 musb_ep_select(mbase, 0); /* select ep0 */
679 csr = musb_readw(regs, MUSB_CSR0);
680 len = musb_readb(regs, MUSB_COUNT0);
682 musb_dbg(musb, "csr %04x, count %d, ep0stage %s",
683 csr, len, decode_ep0stage(musb->ep0_state));
685 if (csr & MUSB_CSR0_P_DATAEND) {
687 * If DATAEND is set we should not call the callback,
688 * hence the status stage is not complete.
693 /* I sent a stall.. need to acknowledge it now.. */
694 if (csr & MUSB_CSR0_P_SENTSTALL) {
695 musb_writew(regs, MUSB_CSR0,
696 csr & ~MUSB_CSR0_P_SENTSTALL);
697 retval = IRQ_HANDLED;
698 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
699 csr = musb_readw(regs, MUSB_CSR0);
702 /* request ended "early" */
703 if (csr & MUSB_CSR0_P_SETUPEND) {
704 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
705 retval = IRQ_HANDLED;
706 /* Transition into the early status phase */
707 switch (musb->ep0_state) {
708 case MUSB_EP0_STAGE_TX:
709 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
711 case MUSB_EP0_STAGE_RX:
712 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
715 ERR("SetupEnd came in a wrong ep0stage %s\n",
716 decode_ep0stage(musb->ep0_state));
718 csr = musb_readw(regs, MUSB_CSR0);
719 /* NOTE: request may need completion */
722 /* docs from Mentor only describe tx, rx, and idle/setup states.
723 * we need to handle nuances around status stages, and also the
724 * case where status and setup stages come back-to-back ...
726 switch (musb->ep0_state) {
728 case MUSB_EP0_STAGE_TX:
729 /* irq on clearing txpktrdy */
730 if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
732 retval = IRQ_HANDLED;
736 case MUSB_EP0_STAGE_RX:
737 /* irq on set rxpktrdy */
738 if (csr & MUSB_CSR0_RXPKTRDY) {
740 retval = IRQ_HANDLED;
744 case MUSB_EP0_STAGE_STATUSIN:
745 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
747 /* update address (if needed) only @ the end of the
748 * status phase per usb spec, which also guarantees
749 * we get 10 msec to receive this irq... until this
750 * is done we won't see the next packet.
752 if (musb->set_address) {
753 musb->set_address = false;
754 musb_writeb(mbase, MUSB_FADDR, musb->address);
757 /* enter test mode if needed (exit by reset) */
758 else if (musb->test_mode) {
759 musb_dbg(musb, "entering TESTMODE");
761 if (MUSB_TEST_PACKET == musb->test_mode_nr)
762 musb_load_testpacket(musb);
764 musb_writeb(mbase, MUSB_TESTMODE,
769 case MUSB_EP0_STAGE_STATUSOUT:
770 /* end of sequence #1: write to host (TX state) */
772 struct musb_request *req;
774 req = next_ep0_request(musb);
776 musb_g_ep0_giveback(musb, &req->request);
780 * In case when several interrupts can get coalesced,
781 * check to see if we've already received a SETUP packet...
783 if (csr & MUSB_CSR0_RXPKTRDY)
786 retval = IRQ_HANDLED;
787 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
790 case MUSB_EP0_STAGE_IDLE:
792 * This state is typically (but not always) indiscernible
793 * from the status states since the corresponding interrupts
794 * tend to happen within too little period of time (with only
795 * a zero-length packet in between) and so get coalesced...
797 retval = IRQ_HANDLED;
798 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
801 case MUSB_EP0_STAGE_SETUP:
803 if (csr & MUSB_CSR0_RXPKTRDY) {
804 struct usb_ctrlrequest setup;
808 ERR("SETUP packet len %d != 8 ?\n", len);
811 musb_read_setup(musb, &setup);
812 retval = IRQ_HANDLED;
814 /* sometimes the RESET won't be reported */
815 if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
818 printk(KERN_NOTICE "%s: peripheral reset "
821 power = musb_readb(mbase, MUSB_POWER);
822 musb->g.speed = (power & MUSB_POWER_HSMODE)
823 ? USB_SPEED_HIGH : USB_SPEED_FULL;
827 switch (musb->ep0_state) {
829 /* sequence #3 (no data stage), includes requests
830 * we can't forward (notably SET_ADDRESS and the
831 * device/endpoint feature set/clear operations)
832 * plus SET_CONFIGURATION and others we must
834 case MUSB_EP0_STAGE_ACKWAIT:
835 handled = service_zero_data_request(
839 * We're expecting no data in any case, so
840 * always set the DATAEND bit -- doing this
841 * here helps avoid SetupEnd interrupt coming
842 * in the idle stage when we're stalling...
844 musb->ackpend |= MUSB_CSR0_P_DATAEND;
846 /* status stage might be immediate */
849 MUSB_EP0_STAGE_STATUSIN;
852 /* sequence #1 (IN to host), includes GET_STATUS
853 * requests that we can't forward, GET_DESCRIPTOR
854 * and others that we must
856 case MUSB_EP0_STAGE_TX:
857 handled = service_in_request(musb, &setup);
859 musb->ackpend = MUSB_CSR0_TXPKTRDY
860 | MUSB_CSR0_P_DATAEND;
862 MUSB_EP0_STAGE_STATUSOUT;
866 /* sequence #2 (OUT from host), always forward */
867 default: /* MUSB_EP0_STAGE_RX */
871 musb_dbg(musb, "handled %d, csr %04x, ep0stage %s",
873 decode_ep0stage(musb->ep0_state));
875 /* unless we need to delegate this to the gadget
876 * driver, we know how to wrap this up: csr0 has
877 * not yet been written.
881 else if (handled > 0)
884 handled = forward_to_driver(musb, &setup);
886 musb_ep_select(mbase, 0);
888 musb_dbg(musb, "stall (%d)", handled);
889 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
890 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
892 musb_writew(regs, MUSB_CSR0,
899 case MUSB_EP0_STAGE_ACKWAIT:
900 /* This should not happen. But happens with tusb6010 with
901 * g_file_storage and high speed. Do nothing.
903 retval = IRQ_HANDLED;
909 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
910 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
919 musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
925 static int musb_g_ep0_disable(struct usb_ep *e)
932 musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
935 struct musb_request *req;
938 unsigned long lockflags;
946 regs = musb->control_ep->regs;
948 req = to_musb_request(r);
950 req->request.actual = 0;
951 req->request.status = -EINPROGRESS;
954 spin_lock_irqsave(&musb->lock, lockflags);
956 if (!list_empty(&ep->req_list)) {
961 switch (musb->ep0_state) {
962 case MUSB_EP0_STAGE_RX: /* control-OUT data */
963 case MUSB_EP0_STAGE_TX: /* control-IN data */
964 case MUSB_EP0_STAGE_ACKWAIT: /* zero-length data */
968 musb_dbg(musb, "ep0 request queued in state %d",
974 /* add request to the list */
975 list_add_tail(&req->list, &ep->req_list);
977 musb_dbg(musb, "queue to %s (%s), length=%d",
978 ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
979 req->request.length);
981 musb_ep_select(musb->mregs, 0);
983 /* sequence #1, IN ... start writing the data */
984 if (musb->ep0_state == MUSB_EP0_STAGE_TX)
987 /* sequence #3, no-data ... issue IN status */
988 else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
989 if (req->request.length)
992 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
993 musb_writew(regs, MUSB_CSR0,
994 musb->ackpend | MUSB_CSR0_P_DATAEND);
996 musb_g_ep0_giveback(ep->musb, r);
999 /* else for sequence #2 (OUT), caller provides a buffer
1000 * before the next packet arrives. deferred responses
1001 * (after SETUP is acked) are racey.
1003 } else if (musb->ackpend) {
1004 musb_writew(regs, MUSB_CSR0, musb->ackpend);
1009 spin_unlock_irqrestore(&musb->lock, lockflags);
1013 static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
1015 /* we just won't support this */
1019 static int musb_g_ep0_halt(struct usb_ep *e, int value)
1023 void __iomem *base, *regs;
1024 unsigned long flags;
1034 regs = musb->control_ep->regs;
1037 spin_lock_irqsave(&musb->lock, flags);
1039 if (!list_empty(&ep->req_list)) {
1044 musb_ep_select(base, 0);
1045 csr = musb->ackpend;
1047 switch (musb->ep0_state) {
1049 /* Stalls are usually issued after parsing SETUP packet, either
1050 * directly in irq context from setup() or else later.
1052 case MUSB_EP0_STAGE_TX: /* control-IN data */
1053 case MUSB_EP0_STAGE_ACKWAIT: /* STALL for zero-length data */
1054 case MUSB_EP0_STAGE_RX: /* control-OUT data */
1055 csr = musb_readw(regs, MUSB_CSR0);
1058 /* It's also OK to issue stalls during callbacks when a non-empty
1059 * DATA stage buffer has been read (or even written).
1061 case MUSB_EP0_STAGE_STATUSIN: /* control-OUT status */
1062 case MUSB_EP0_STAGE_STATUSOUT: /* control-IN status */
1064 csr |= MUSB_CSR0_P_SENDSTALL;
1065 musb_writew(regs, MUSB_CSR0, csr);
1066 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
1070 musb_dbg(musb, "ep0 can't halt in state %d", musb->ep0_state);
1075 spin_unlock_irqrestore(&musb->lock, flags);
1079 const struct usb_ep_ops musb_g_ep0_ops = {
1080 .enable = musb_g_ep0_enable,
1081 .disable = musb_g_ep0_disable,
1082 .alloc_request = musb_alloc_request,
1083 .free_request = musb_free_request,
1084 .queue = musb_g_ep0_queue,
1085 .dequeue = musb_g_ep0_dequeue,
1086 .set_halt = musb_g_ep0_halt,