2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
46 #include "musb_core.h"
47 #include "musb_trace.h"
50 /* ----------------------------------------------------------------------- */
52 #define is_buffer_mapped(req) (is_dma_capable() && \
53 (req->map_state != UN_MAPPED))
55 /* Maps the buffer to dma */
57 static inline void map_dma_buffer(struct musb_request *request,
58 struct musb *musb, struct musb_ep *musb_ep)
60 int compatible = true;
61 struct dma_controller *dma = musb->dma_controller;
63 request->map_state = UN_MAPPED;
65 if (!is_dma_capable() || !musb_ep->dma)
68 /* Check if DMA engine can handle this request.
69 * DMA code must reject the USB request explicitly.
70 * Default behaviour is to map the request.
72 if (dma->is_compatible)
73 compatible = dma->is_compatible(musb_ep->dma,
74 musb_ep->packet_sz, request->request.buf,
75 request->request.length);
79 if (request->request.dma == DMA_ADDR_INVALID) {
83 dma_addr = dma_map_single(
86 request->request.length,
90 ret = dma_mapping_error(musb->controller, dma_addr);
94 request->request.dma = dma_addr;
95 request->map_state = MUSB_MAPPED;
97 dma_sync_single_for_device(musb->controller,
99 request->request.length,
103 request->map_state = PRE_MAPPED;
107 /* Unmap the buffer from dma and maps it back to cpu */
108 static inline void unmap_dma_buffer(struct musb_request *request,
111 struct musb_ep *musb_ep = request->ep;
113 if (!is_buffer_mapped(request) || !musb_ep->dma)
116 if (request->request.dma == DMA_ADDR_INVALID) {
117 dev_vdbg(musb->controller,
118 "not unmapping a never mapped buffer\n");
121 if (request->map_state == MUSB_MAPPED) {
122 dma_unmap_single(musb->controller,
123 request->request.dma,
124 request->request.length,
128 request->request.dma = DMA_ADDR_INVALID;
129 } else { /* PRE_MAPPED */
130 dma_sync_single_for_cpu(musb->controller,
131 request->request.dma,
132 request->request.length,
137 request->map_state = UN_MAPPED;
141 * Immediately complete a request.
143 * @param request the request to complete
144 * @param status the status to complete the request with
145 * Context: controller locked, IRQs blocked.
147 void musb_g_giveback(
149 struct usb_request *request,
151 __releases(ep->musb->lock)
152 __acquires(ep->musb->lock)
154 struct musb_request *req;
158 req = to_musb_request(request);
160 list_del(&req->list);
161 if (req->request.status == -EINPROGRESS)
162 req->request.status = status;
166 spin_unlock(&musb->lock);
168 if (!dma_mapping_error(&musb->g.dev, request->dma))
169 unmap_dma_buffer(req, musb);
171 trace_musb_req_gb(req);
172 usb_gadget_giveback_request(&req->ep->end_point, &req->request);
173 spin_lock(&musb->lock);
177 /* ----------------------------------------------------------------------- */
180 * Abort requests queued to an endpoint using the status. Synchronous.
181 * caller locked controller and blocked irqs, and selected this ep.
183 static void nuke(struct musb_ep *ep, const int status)
185 struct musb *musb = ep->musb;
186 struct musb_request *req = NULL;
187 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
191 if (is_dma_capable() && ep->dma) {
192 struct dma_controller *c = ep->musb->dma_controller;
197 * The programming guide says that we must not clear
198 * the DMAMODE bit before DMAENAB, so we only
199 * clear it in the second write...
201 musb_writew(epio, MUSB_TXCSR,
202 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
203 musb_writew(epio, MUSB_TXCSR,
204 0 | MUSB_TXCSR_FLUSHFIFO);
206 musb_writew(epio, MUSB_RXCSR,
207 0 | MUSB_RXCSR_FLUSHFIFO);
208 musb_writew(epio, MUSB_RXCSR,
209 0 | MUSB_RXCSR_FLUSHFIFO);
212 value = c->channel_abort(ep->dma);
213 musb_dbg(musb, "%s: abort DMA --> %d", ep->name, value);
214 c->channel_release(ep->dma);
218 while (!list_empty(&ep->req_list)) {
219 req = list_first_entry(&ep->req_list, struct musb_request, list);
220 musb_g_giveback(ep, &req->request, status);
224 /* ----------------------------------------------------------------------- */
226 /* Data transfers - pure PIO, pure DMA, or mixed mode */
229 * This assumes the separate CPPI engine is responding to DMA requests
230 * from the usb core ... sequenced a bit differently from mentor dma.
233 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
235 if (can_bulk_split(musb, ep->type))
236 return ep->hw_ep->max_packet_sz_tx;
238 return ep->packet_sz;
242 * An endpoint is transmitting data. This can be called either from
243 * the IRQ routine or from ep.queue() to kickstart a request on an
246 * Context: controller locked, IRQs blocked, endpoint selected
248 static void txstate(struct musb *musb, struct musb_request *req)
250 u8 epnum = req->epnum;
251 struct musb_ep *musb_ep;
252 void __iomem *epio = musb->endpoints[epnum].regs;
253 struct usb_request *request;
254 u16 fifo_count = 0, csr;
259 /* Check if EP is disabled */
260 if (!musb_ep->desc) {
261 musb_dbg(musb, "ep:%s disabled - ignore request",
262 musb_ep->end_point.name);
266 /* we shouldn't get here while DMA is active ... but we do ... */
267 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
268 musb_dbg(musb, "dma pending...");
272 /* read TXCSR before */
273 csr = musb_readw(epio, MUSB_TXCSR);
275 request = &req->request;
276 fifo_count = min(max_ep_writesize(musb, musb_ep),
277 (int)(request->length - request->actual));
279 if (csr & MUSB_TXCSR_TXPKTRDY) {
280 musb_dbg(musb, "%s old packet still ready , txcsr %03x",
281 musb_ep->end_point.name, csr);
285 if (csr & MUSB_TXCSR_P_SENDSTALL) {
286 musb_dbg(musb, "%s stalling, txcsr %03x",
287 musb_ep->end_point.name, csr);
291 musb_dbg(musb, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x",
292 epnum, musb_ep->packet_sz, fifo_count,
295 #ifndef CONFIG_MUSB_PIO_ONLY
296 if (is_buffer_mapped(req)) {
297 struct dma_controller *c = musb->dma_controller;
300 /* setup DMA, then program endpoint CSR */
301 request_size = min_t(size_t, request->length - request->actual,
302 musb_ep->dma->max_len);
304 use_dma = (request->dma != DMA_ADDR_INVALID && request_size);
306 /* MUSB_TXCSR_P_ISO is still set correctly */
308 if (musb_dma_inventra(musb) || musb_dma_ux500(musb)) {
309 if (request_size < musb_ep->packet_sz)
310 musb_ep->dma->desired_mode = 0;
312 musb_ep->dma->desired_mode = 1;
314 use_dma = use_dma && c->channel_program(
315 musb_ep->dma, musb_ep->packet_sz,
316 musb_ep->dma->desired_mode,
317 request->dma + request->actual, request_size);
319 if (musb_ep->dma->desired_mode == 0) {
321 * We must not clear the DMAMODE bit
322 * before the DMAENAB bit -- and the
323 * latter doesn't always get cleared
324 * before we get here...
326 csr &= ~(MUSB_TXCSR_AUTOSET
327 | MUSB_TXCSR_DMAENAB);
328 musb_writew(epio, MUSB_TXCSR, csr
329 | MUSB_TXCSR_P_WZC_BITS);
330 csr &= ~MUSB_TXCSR_DMAMODE;
331 csr |= (MUSB_TXCSR_DMAENAB |
333 /* against programming guide */
335 csr |= (MUSB_TXCSR_DMAENAB
339 * Enable Autoset according to table
341 * bulk_split hb_mult Autoset_Enable
343 * 0 >0 No(High BW ISO)
347 if (!musb_ep->hb_mult ||
350 csr |= MUSB_TXCSR_AUTOSET;
352 csr &= ~MUSB_TXCSR_P_UNDERRUN;
354 musb_writew(epio, MUSB_TXCSR, csr);
358 if (is_cppi_enabled(musb)) {
359 /* program endpoint CSR first, then setup DMA */
360 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
361 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
363 musb_writew(epio, MUSB_TXCSR, (MUSB_TXCSR_P_WZC_BITS &
364 ~MUSB_TXCSR_P_UNDERRUN) | csr);
366 /* ensure writebuffer is empty */
367 csr = musb_readw(epio, MUSB_TXCSR);
370 * NOTE host side sets DMAENAB later than this; both are
371 * OK since the transfer dma glue (between CPPI and
372 * Mentor fifos) just tells CPPI it could start. Data
373 * only moves to the USB TX fifo when both fifos are
377 * "mode" is irrelevant here; handle terminating ZLPs
378 * like PIO does, since the hardware RNDIS mode seems
379 * unreliable except for the
380 * last-packet-is-already-short case.
382 use_dma = use_dma && c->channel_program(
383 musb_ep->dma, musb_ep->packet_sz,
385 request->dma + request->actual,
388 c->channel_release(musb_ep->dma);
390 csr &= ~MUSB_TXCSR_DMAENAB;
391 musb_writew(epio, MUSB_TXCSR, csr);
392 /* invariant: prequest->buf is non-null */
394 } else if (tusb_dma_omap(musb))
395 use_dma = use_dma && c->channel_program(
396 musb_ep->dma, musb_ep->packet_sz,
398 request->dma + request->actual,
405 * Unmap the dma buffer back to cpu if dma channel
408 unmap_dma_buffer(req, musb);
410 musb_write_fifo(musb_ep->hw_ep, fifo_count,
411 (u8 *) (request->buf + request->actual));
412 request->actual += fifo_count;
413 csr |= MUSB_TXCSR_TXPKTRDY;
414 csr &= ~MUSB_TXCSR_P_UNDERRUN;
415 musb_writew(epio, MUSB_TXCSR, csr);
418 /* host may already have the data when this message shows... */
419 musb_dbg(musb, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d",
420 musb_ep->end_point.name, use_dma ? "dma" : "pio",
421 request->actual, request->length,
422 musb_readw(epio, MUSB_TXCSR),
424 musb_readw(epio, MUSB_TXMAXP));
428 * FIFO state update (e.g. data ready).
429 * Called from IRQ, with controller locked.
431 void musb_g_tx(struct musb *musb, u8 epnum)
434 struct musb_request *req;
435 struct usb_request *request;
436 u8 __iomem *mbase = musb->mregs;
437 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
438 void __iomem *epio = musb->endpoints[epnum].regs;
439 struct dma_channel *dma;
441 musb_ep_select(mbase, epnum);
442 req = next_request(musb_ep);
443 request = &req->request;
445 csr = musb_readw(epio, MUSB_TXCSR);
446 musb_dbg(musb, "<== %s, txcsr %04x", musb_ep->end_point.name, csr);
448 dma = is_dma_capable() ? musb_ep->dma : NULL;
451 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
452 * probably rates reporting as a host error.
454 if (csr & MUSB_TXCSR_P_SENTSTALL) {
455 csr |= MUSB_TXCSR_P_WZC_BITS;
456 csr &= ~MUSB_TXCSR_P_SENTSTALL;
457 musb_writew(epio, MUSB_TXCSR, csr);
461 if (csr & MUSB_TXCSR_P_UNDERRUN) {
462 /* We NAKed, no big deal... little reason to care. */
463 csr |= MUSB_TXCSR_P_WZC_BITS;
464 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
465 musb_writew(epio, MUSB_TXCSR, csr);
466 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
470 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
472 * SHOULD NOT HAPPEN... has with CPPI though, after
473 * changing SENDSTALL (and other cases); harmless?
475 musb_dbg(musb, "%s dma still busy?", musb_ep->end_point.name);
481 trace_musb_req_tx(req);
483 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
484 csr |= MUSB_TXCSR_P_WZC_BITS;
485 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
486 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
487 musb_writew(epio, MUSB_TXCSR, csr);
488 /* Ensure writebuffer is empty. */
489 csr = musb_readw(epio, MUSB_TXCSR);
490 request->actual += musb_ep->dma->actual_len;
491 musb_dbg(musb, "TXCSR%d %04x, DMA off, len %zu, req %p",
492 epnum, csr, musb_ep->dma->actual_len, request);
496 * First, maybe a terminating short packet. Some DMA
497 * engines might handle this by themselves.
499 if ((request->zero && request->length)
500 && (request->length % musb_ep->packet_sz == 0)
501 && (request->actual == request->length)) {
504 * On DMA completion, FIFO may not be
507 if (csr & MUSB_TXCSR_TXPKTRDY)
510 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
511 | MUSB_TXCSR_TXPKTRDY);
515 if (request->actual == request->length) {
516 musb_g_giveback(musb_ep, request, 0);
518 * In the giveback function the MUSB lock is
519 * released and acquired after sometime. During
520 * this time period the INDEX register could get
521 * changed by the gadget_queue function especially
522 * on SMP systems. Reselect the INDEX to be sure
523 * we are reading/modifying the right registers
525 musb_ep_select(mbase, epnum);
526 req = musb_ep->desc ? next_request(musb_ep) : NULL;
528 musb_dbg(musb, "%s idle now",
529 musb_ep->end_point.name);
538 /* ------------------------------------------------------------ */
541 * Context: controller locked, IRQs blocked, endpoint selected
543 static void rxstate(struct musb *musb, struct musb_request *req)
545 const u8 epnum = req->epnum;
546 struct usb_request *request = &req->request;
547 struct musb_ep *musb_ep;
548 void __iomem *epio = musb->endpoints[epnum].regs;
551 u16 csr = musb_readw(epio, MUSB_RXCSR);
552 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
555 if (hw_ep->is_shared_fifo)
556 musb_ep = &hw_ep->ep_in;
558 musb_ep = &hw_ep->ep_out;
560 fifo_count = musb_ep->packet_sz;
562 /* Check if EP is disabled */
563 if (!musb_ep->desc) {
564 musb_dbg(musb, "ep:%s disabled - ignore request",
565 musb_ep->end_point.name);
569 /* We shouldn't get here while DMA is active, but we do... */
570 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
571 musb_dbg(musb, "DMA pending...");
575 if (csr & MUSB_RXCSR_P_SENDSTALL) {
576 musb_dbg(musb, "%s stalling, RXCSR %04x",
577 musb_ep->end_point.name, csr);
581 if (is_cppi_enabled(musb) && is_buffer_mapped(req)) {
582 struct dma_controller *c = musb->dma_controller;
583 struct dma_channel *channel = musb_ep->dma;
585 /* NOTE: CPPI won't actually stop advancing the DMA
586 * queue after short packet transfers, so this is almost
587 * always going to run as IRQ-per-packet DMA so that
588 * faults will be handled correctly.
590 if (c->channel_program(channel,
592 !request->short_not_ok,
593 request->dma + request->actual,
594 request->length - request->actual)) {
596 /* make sure that if an rxpkt arrived after the irq,
597 * the cppi engine will be ready to take it as soon
600 csr &= ~(MUSB_RXCSR_AUTOCLEAR
601 | MUSB_RXCSR_DMAMODE);
602 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
603 musb_writew(epio, MUSB_RXCSR, csr);
608 if (csr & MUSB_RXCSR_RXPKTRDY) {
609 fifo_count = musb_readw(epio, MUSB_RXCOUNT);
612 * Enable Mode 1 on RX transfers only when short_not_ok flag
613 * is set. Currently short_not_ok flag is set only from
614 * file_storage and f_mass_storage drivers
617 if (request->short_not_ok && fifo_count == musb_ep->packet_sz)
622 if (request->actual < request->length) {
623 if (!is_buffer_mapped(req))
624 goto buffer_aint_mapped;
626 if (musb_dma_inventra(musb)) {
627 struct dma_controller *c;
628 struct dma_channel *channel;
630 unsigned int transfer_size;
632 c = musb->dma_controller;
633 channel = musb_ep->dma;
635 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
636 * mode 0 only. So we do not get endpoint interrupts due to DMA
637 * completion. We only get interrupts from DMA controller.
639 * We could operate in DMA mode 1 if we knew the size of the tranfer
640 * in advance. For mass storage class, request->length = what the host
641 * sends, so that'd work. But for pretty much everything else,
642 * request->length is routinely more than what the host sends. For
643 * most these gadgets, end of is signified either by a short packet,
644 * or filling the last byte of the buffer. (Sending extra data in
645 * that last pckate should trigger an overflow fault.) But in mode 1,
646 * we don't get DMA completion interrupt for short packets.
648 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
649 * to get endpoint interrupt on every DMA req, but that didn't seem
652 * REVISIT an updated g_file_storage can set req->short_not_ok, which
653 * then becomes usable as a runtime "use mode 1" hint...
656 /* Experimental: Mode1 works with mass storage use cases */
658 csr |= MUSB_RXCSR_AUTOCLEAR;
659 musb_writew(epio, MUSB_RXCSR, csr);
660 csr |= MUSB_RXCSR_DMAENAB;
661 musb_writew(epio, MUSB_RXCSR, csr);
664 * this special sequence (enabling and then
665 * disabling MUSB_RXCSR_DMAMODE) is required
666 * to get DMAReq to activate
668 musb_writew(epio, MUSB_RXCSR,
669 csr | MUSB_RXCSR_DMAMODE);
670 musb_writew(epio, MUSB_RXCSR, csr);
672 transfer_size = min_t(unsigned int,
676 musb_ep->dma->desired_mode = 1;
678 if (!musb_ep->hb_mult &&
679 musb_ep->hw_ep->rx_double_buffered)
680 csr |= MUSB_RXCSR_AUTOCLEAR;
681 csr |= MUSB_RXCSR_DMAENAB;
682 musb_writew(epio, MUSB_RXCSR, csr);
684 transfer_size = min(request->length - request->actual,
685 (unsigned)fifo_count);
686 musb_ep->dma->desired_mode = 0;
689 use_dma = c->channel_program(
692 channel->desired_mode,
701 if ((musb_dma_ux500(musb)) &&
702 (request->actual < request->length)) {
704 struct dma_controller *c;
705 struct dma_channel *channel;
706 unsigned int transfer_size = 0;
708 c = musb->dma_controller;
709 channel = musb_ep->dma;
711 /* In case first packet is short */
712 if (fifo_count < musb_ep->packet_sz)
713 transfer_size = fifo_count;
714 else if (request->short_not_ok)
715 transfer_size = min_t(unsigned int,
720 transfer_size = min_t(unsigned int,
723 (unsigned)fifo_count);
725 csr &= ~MUSB_RXCSR_DMAMODE;
726 csr |= (MUSB_RXCSR_DMAENAB |
727 MUSB_RXCSR_AUTOCLEAR);
729 musb_writew(epio, MUSB_RXCSR, csr);
731 if (transfer_size <= musb_ep->packet_sz) {
732 musb_ep->dma->desired_mode = 0;
734 musb_ep->dma->desired_mode = 1;
735 /* Mode must be set after DMAENAB */
736 csr |= MUSB_RXCSR_DMAMODE;
737 musb_writew(epio, MUSB_RXCSR, csr);
740 if (c->channel_program(channel,
742 channel->desired_mode,
750 len = request->length - request->actual;
751 musb_dbg(musb, "%s OUT/RX pio fifo %d/%d, maxpacket %d",
752 musb_ep->end_point.name,
756 fifo_count = min_t(unsigned, len, fifo_count);
758 if (tusb_dma_omap(musb)) {
759 struct dma_controller *c = musb->dma_controller;
760 struct dma_channel *channel = musb_ep->dma;
761 u32 dma_addr = request->dma + request->actual;
764 ret = c->channel_program(channel,
766 channel->desired_mode,
774 * Unmap the dma buffer back to cpu if dma channel
775 * programming fails. This buffer is mapped if the
776 * channel allocation is successful
778 unmap_dma_buffer(req, musb);
781 * Clear DMAENAB and AUTOCLEAR for the
784 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
785 musb_writew(epio, MUSB_RXCSR, csr);
788 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
789 (request->buf + request->actual));
790 request->actual += fifo_count;
792 /* REVISIT if we left anything in the fifo, flush
793 * it and report -EOVERFLOW
797 csr |= MUSB_RXCSR_P_WZC_BITS;
798 csr &= ~MUSB_RXCSR_RXPKTRDY;
799 musb_writew(epio, MUSB_RXCSR, csr);
803 /* reach the end or short packet detected */
804 if (request->actual == request->length ||
805 fifo_count < musb_ep->packet_sz)
806 musb_g_giveback(musb_ep, request, 0);
810 * Data ready for a request; called from IRQ
812 void musb_g_rx(struct musb *musb, u8 epnum)
815 struct musb_request *req;
816 struct usb_request *request;
817 void __iomem *mbase = musb->mregs;
818 struct musb_ep *musb_ep;
819 void __iomem *epio = musb->endpoints[epnum].regs;
820 struct dma_channel *dma;
821 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
823 if (hw_ep->is_shared_fifo)
824 musb_ep = &hw_ep->ep_in;
826 musb_ep = &hw_ep->ep_out;
828 musb_ep_select(mbase, epnum);
830 req = next_request(musb_ep);
834 trace_musb_req_rx(req);
835 request = &req->request;
837 csr = musb_readw(epio, MUSB_RXCSR);
838 dma = is_dma_capable() ? musb_ep->dma : NULL;
840 musb_dbg(musb, "<== %s, rxcsr %04x%s %p", musb_ep->end_point.name,
841 csr, dma ? " (dma)" : "", request);
843 if (csr & MUSB_RXCSR_P_SENTSTALL) {
844 csr |= MUSB_RXCSR_P_WZC_BITS;
845 csr &= ~MUSB_RXCSR_P_SENTSTALL;
846 musb_writew(epio, MUSB_RXCSR, csr);
850 if (csr & MUSB_RXCSR_P_OVERRUN) {
851 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
852 csr &= ~MUSB_RXCSR_P_OVERRUN;
853 musb_writew(epio, MUSB_RXCSR, csr);
855 musb_dbg(musb, "%s iso overrun on %p", musb_ep->name, request);
856 if (request->status == -EINPROGRESS)
857 request->status = -EOVERFLOW;
859 if (csr & MUSB_RXCSR_INCOMPRX) {
860 /* REVISIT not necessarily an error */
861 musb_dbg(musb, "%s, incomprx", musb_ep->end_point.name);
864 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
865 /* "should not happen"; likely RXPKTRDY pending for DMA */
866 musb_dbg(musb, "%s busy, csr %04x",
867 musb_ep->end_point.name, csr);
871 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
872 csr &= ~(MUSB_RXCSR_AUTOCLEAR
874 | MUSB_RXCSR_DMAMODE);
875 musb_writew(epio, MUSB_RXCSR,
876 MUSB_RXCSR_P_WZC_BITS | csr);
878 request->actual += musb_ep->dma->actual_len;
880 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
881 defined(CONFIG_USB_UX500_DMA)
882 /* Autoclear doesn't clear RxPktRdy for short packets */
883 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
885 & (musb_ep->packet_sz - 1))) {
887 csr &= ~MUSB_RXCSR_RXPKTRDY;
888 musb_writew(epio, MUSB_RXCSR, csr);
891 /* incomplete, and not short? wait for next IN packet */
892 if ((request->actual < request->length)
893 && (musb_ep->dma->actual_len
894 == musb_ep->packet_sz)) {
895 /* In double buffer case, continue to unload fifo if
896 * there is Rx packet in FIFO.
898 csr = musb_readw(epio, MUSB_RXCSR);
899 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
900 hw_ep->rx_double_buffered)
905 musb_g_giveback(musb_ep, request, 0);
907 * In the giveback function the MUSB lock is
908 * released and acquired after sometime. During
909 * this time period the INDEX register could get
910 * changed by the gadget_queue function especially
911 * on SMP systems. Reselect the INDEX to be sure
912 * we are reading/modifying the right registers
914 musb_ep_select(mbase, epnum);
916 req = next_request(musb_ep);
920 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
921 defined(CONFIG_USB_UX500_DMA)
924 /* Analyze request */
928 /* ------------------------------------------------------------ */
930 static int musb_gadget_enable(struct usb_ep *ep,
931 const struct usb_endpoint_descriptor *desc)
934 struct musb_ep *musb_ep;
935 struct musb_hw_ep *hw_ep;
942 int status = -EINVAL;
947 musb_ep = to_musb_ep(ep);
948 hw_ep = musb_ep->hw_ep;
950 musb = musb_ep->musb;
952 epnum = musb_ep->current_epnum;
954 spin_lock_irqsave(&musb->lock, flags);
960 musb_ep->type = usb_endpoint_type(desc);
962 /* check direction and (later) maxpacket size against endpoint */
963 if (usb_endpoint_num(desc) != epnum)
966 /* REVISIT this rules out high bandwidth periodic transfers */
967 tmp = usb_endpoint_maxp_mult(desc) - 1;
971 if (usb_endpoint_dir_in(desc))
972 ok = musb->hb_iso_tx;
974 ok = musb->hb_iso_rx;
977 musb_dbg(musb, "no support for high bandwidth ISO");
980 musb_ep->hb_mult = tmp;
982 musb_ep->hb_mult = 0;
985 musb_ep->packet_sz = usb_endpoint_maxp(desc);
986 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
988 /* enable the interrupts for the endpoint, set the endpoint
989 * packet size (or fail), set the mode, clear the fifo
991 musb_ep_select(mbase, epnum);
992 if (usb_endpoint_dir_in(desc)) {
994 if (hw_ep->is_shared_fifo)
999 if (tmp > hw_ep->max_packet_sz_tx) {
1000 musb_dbg(musb, "packet size beyond hardware FIFO size");
1004 musb->intrtxe |= (1 << epnum);
1005 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1007 /* REVISIT if can_bulk_split(), use by updating "tmp";
1008 * likewise high bandwidth periodic tx
1010 /* Set TXMAXP with the FIFO size of the endpoint
1011 * to disable double buffering mode.
1013 if (musb->double_buffer_not_ok) {
1014 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1016 if (can_bulk_split(musb, musb_ep->type))
1017 musb_ep->hb_mult = (hw_ep->max_packet_sz_tx /
1018 musb_ep->packet_sz) - 1;
1019 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1020 | (musb_ep->hb_mult << 11));
1023 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1024 if (musb_readw(regs, MUSB_TXCSR)
1025 & MUSB_TXCSR_FIFONOTEMPTY)
1026 csr |= MUSB_TXCSR_FLUSHFIFO;
1027 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1028 csr |= MUSB_TXCSR_P_ISO;
1030 /* set twice in case of double buffering */
1031 musb_writew(regs, MUSB_TXCSR, csr);
1032 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1033 musb_writew(regs, MUSB_TXCSR, csr);
1037 if (hw_ep->is_shared_fifo)
1042 if (tmp > hw_ep->max_packet_sz_rx) {
1043 musb_dbg(musb, "packet size beyond hardware FIFO size");
1047 musb->intrrxe |= (1 << epnum);
1048 musb_writew(mbase, MUSB_INTRRXE, musb->intrrxe);
1050 /* REVISIT if can_bulk_combine() use by updating "tmp"
1051 * likewise high bandwidth periodic rx
1053 /* Set RXMAXP with the FIFO size of the endpoint
1054 * to disable double buffering mode.
1056 if (musb->double_buffer_not_ok)
1057 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1059 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1060 | (musb_ep->hb_mult << 11));
1062 /* force shared fifo to OUT-only mode */
1063 if (hw_ep->is_shared_fifo) {
1064 csr = musb_readw(regs, MUSB_TXCSR);
1065 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1066 musb_writew(regs, MUSB_TXCSR, csr);
1069 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1070 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1071 csr |= MUSB_RXCSR_P_ISO;
1072 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1073 csr |= MUSB_RXCSR_DISNYET;
1075 /* set twice in case of double buffering */
1076 musb_writew(regs, MUSB_RXCSR, csr);
1077 musb_writew(regs, MUSB_RXCSR, csr);
1080 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1081 * for some reason you run out of channels here.
1083 if (is_dma_capable() && musb->dma_controller) {
1084 struct dma_controller *c = musb->dma_controller;
1086 musb_ep->dma = c->channel_alloc(c, hw_ep,
1087 (desc->bEndpointAddress & USB_DIR_IN));
1089 musb_ep->dma = NULL;
1091 musb_ep->desc = desc;
1093 musb_ep->wedged = 0;
1096 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1097 musb_driver_name, musb_ep->end_point.name,
1098 musb_ep_xfertype_string(musb_ep->type),
1099 musb_ep->is_in ? "IN" : "OUT",
1100 musb_ep->dma ? "dma, " : "",
1101 musb_ep->packet_sz);
1103 schedule_delayed_work(&musb->irq_work, 0);
1106 spin_unlock_irqrestore(&musb->lock, flags);
1111 * Disable an endpoint flushing all requests queued.
1113 static int musb_gadget_disable(struct usb_ep *ep)
1115 unsigned long flags;
1118 struct musb_ep *musb_ep;
1122 musb_ep = to_musb_ep(ep);
1123 musb = musb_ep->musb;
1124 epnum = musb_ep->current_epnum;
1125 epio = musb->endpoints[epnum].regs;
1127 spin_lock_irqsave(&musb->lock, flags);
1128 musb_ep_select(musb->mregs, epnum);
1130 /* zero the endpoint sizes */
1131 if (musb_ep->is_in) {
1132 musb->intrtxe &= ~(1 << epnum);
1133 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
1134 musb_writew(epio, MUSB_TXMAXP, 0);
1136 musb->intrrxe &= ~(1 << epnum);
1137 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
1138 musb_writew(epio, MUSB_RXMAXP, 0);
1141 /* abort all pending DMA and requests */
1142 nuke(musb_ep, -ESHUTDOWN);
1144 musb_ep->desc = NULL;
1145 musb_ep->end_point.desc = NULL;
1147 schedule_delayed_work(&musb->irq_work, 0);
1149 spin_unlock_irqrestore(&(musb->lock), flags);
1151 musb_dbg(musb, "%s", musb_ep->end_point.name);
1157 * Allocate a request for an endpoint.
1158 * Reused by ep0 code.
1160 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1162 struct musb_ep *musb_ep = to_musb_ep(ep);
1163 struct musb_request *request = NULL;
1165 request = kzalloc(sizeof *request, gfp_flags);
1169 request->request.dma = DMA_ADDR_INVALID;
1170 request->epnum = musb_ep->current_epnum;
1171 request->ep = musb_ep;
1173 trace_musb_req_alloc(request);
1174 return &request->request;
1179 * Reused by ep0 code.
1181 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1183 struct musb_request *request = to_musb_request(req);
1185 trace_musb_req_free(request);
1189 static LIST_HEAD(buffers);
1191 struct free_record {
1192 struct list_head list;
1199 * Context: controller locked, IRQs blocked.
1201 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1203 trace_musb_req_start(req);
1204 musb_ep_select(musb->mregs, req->epnum);
1211 static int musb_ep_restart_resume_work(struct musb *musb, void *data)
1213 struct musb_request *req = data;
1215 musb_ep_restart(musb, req);
1220 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1223 struct musb_ep *musb_ep;
1224 struct musb_request *request;
1227 unsigned long lockflags;
1234 musb_ep = to_musb_ep(ep);
1235 musb = musb_ep->musb;
1237 request = to_musb_request(req);
1238 request->musb = musb;
1240 if (request->ep != musb_ep)
1243 status = pm_runtime_get(musb->controller);
1244 if ((status != -EINPROGRESS) && status < 0) {
1245 dev_err(musb->controller,
1246 "pm runtime get failed in %s\n",
1248 pm_runtime_put_noidle(musb->controller);
1254 trace_musb_req_enq(request);
1256 /* request is mine now... */
1257 request->request.actual = 0;
1258 request->request.status = -EINPROGRESS;
1259 request->epnum = musb_ep->current_epnum;
1260 request->tx = musb_ep->is_in;
1262 map_dma_buffer(request, musb, musb_ep);
1264 spin_lock_irqsave(&musb->lock, lockflags);
1266 /* don't queue if the ep is down */
1267 if (!musb_ep->desc) {
1268 musb_dbg(musb, "req %p queued to %s while ep %s",
1269 req, ep->name, "disabled");
1270 status = -ESHUTDOWN;
1271 unmap_dma_buffer(request, musb);
1275 /* add request to the list */
1276 list_add_tail(&request->list, &musb_ep->req_list);
1278 /* it this is the head of the queue, start i/o ... */
1279 if (!musb_ep->busy && &request->list == musb_ep->req_list.next) {
1280 status = musb_queue_resume_work(musb,
1281 musb_ep_restart_resume_work,
1284 dev_err(musb->controller, "%s resume work: %i\n",
1289 spin_unlock_irqrestore(&musb->lock, lockflags);
1290 pm_runtime_mark_last_busy(musb->controller);
1291 pm_runtime_put_autosuspend(musb->controller);
1296 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1298 struct musb_ep *musb_ep = to_musb_ep(ep);
1299 struct musb_request *req = to_musb_request(request);
1300 struct musb_request *r;
1301 unsigned long flags;
1303 struct musb *musb = musb_ep->musb;
1305 if (!ep || !request || req->ep != musb_ep)
1308 trace_musb_req_deq(req);
1310 spin_lock_irqsave(&musb->lock, flags);
1312 list_for_each_entry(r, &musb_ep->req_list, list) {
1317 dev_err(musb->controller, "request %p not queued to %s\n",
1323 /* if the hardware doesn't have the request, easy ... */
1324 if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1325 musb_g_giveback(musb_ep, request, -ECONNRESET);
1327 /* ... else abort the dma transfer ... */
1328 else if (is_dma_capable() && musb_ep->dma) {
1329 struct dma_controller *c = musb->dma_controller;
1331 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1332 if (c->channel_abort)
1333 status = c->channel_abort(musb_ep->dma);
1337 musb_g_giveback(musb_ep, request, -ECONNRESET);
1339 /* NOTE: by sticking to easily tested hardware/driver states,
1340 * we leave counting of in-flight packets imprecise.
1342 musb_g_giveback(musb_ep, request, -ECONNRESET);
1346 spin_unlock_irqrestore(&musb->lock, flags);
1351 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1352 * data but will queue requests.
1354 * exported to ep0 code
1356 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1358 struct musb_ep *musb_ep = to_musb_ep(ep);
1359 u8 epnum = musb_ep->current_epnum;
1360 struct musb *musb = musb_ep->musb;
1361 void __iomem *epio = musb->endpoints[epnum].regs;
1362 void __iomem *mbase;
1363 unsigned long flags;
1365 struct musb_request *request;
1370 mbase = musb->mregs;
1372 spin_lock_irqsave(&musb->lock, flags);
1374 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1379 musb_ep_select(mbase, epnum);
1381 request = next_request(musb_ep);
1384 musb_dbg(musb, "request in progress, cannot halt %s",
1389 /* Cannot portably stall with non-empty FIFO */
1390 if (musb_ep->is_in) {
1391 csr = musb_readw(epio, MUSB_TXCSR);
1392 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1393 musb_dbg(musb, "FIFO busy, cannot halt %s",
1400 musb_ep->wedged = 0;
1402 /* set/clear the stall and toggle bits */
1403 musb_dbg(musb, "%s: %s stall", ep->name, value ? "set" : "clear");
1404 if (musb_ep->is_in) {
1405 csr = musb_readw(epio, MUSB_TXCSR);
1406 csr |= MUSB_TXCSR_P_WZC_BITS
1407 | MUSB_TXCSR_CLRDATATOG;
1409 csr |= MUSB_TXCSR_P_SENDSTALL;
1411 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1412 | MUSB_TXCSR_P_SENTSTALL);
1413 csr &= ~MUSB_TXCSR_TXPKTRDY;
1414 musb_writew(epio, MUSB_TXCSR, csr);
1416 csr = musb_readw(epio, MUSB_RXCSR);
1417 csr |= MUSB_RXCSR_P_WZC_BITS
1418 | MUSB_RXCSR_FLUSHFIFO
1419 | MUSB_RXCSR_CLRDATATOG;
1421 csr |= MUSB_RXCSR_P_SENDSTALL;
1423 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1424 | MUSB_RXCSR_P_SENTSTALL);
1425 musb_writew(epio, MUSB_RXCSR, csr);
1428 /* maybe start the first request in the queue */
1429 if (!musb_ep->busy && !value && request) {
1430 musb_dbg(musb, "restarting the request");
1431 musb_ep_restart(musb, request);
1435 spin_unlock_irqrestore(&musb->lock, flags);
1440 * Sets the halt feature with the clear requests ignored
1442 static int musb_gadget_set_wedge(struct usb_ep *ep)
1444 struct musb_ep *musb_ep = to_musb_ep(ep);
1449 musb_ep->wedged = 1;
1451 return usb_ep_set_halt(ep);
1454 static int musb_gadget_fifo_status(struct usb_ep *ep)
1456 struct musb_ep *musb_ep = to_musb_ep(ep);
1457 void __iomem *epio = musb_ep->hw_ep->regs;
1458 int retval = -EINVAL;
1460 if (musb_ep->desc && !musb_ep->is_in) {
1461 struct musb *musb = musb_ep->musb;
1462 int epnum = musb_ep->current_epnum;
1463 void __iomem *mbase = musb->mregs;
1464 unsigned long flags;
1466 spin_lock_irqsave(&musb->lock, flags);
1468 musb_ep_select(mbase, epnum);
1469 /* FIXME return zero unless RXPKTRDY is set */
1470 retval = musb_readw(epio, MUSB_RXCOUNT);
1472 spin_unlock_irqrestore(&musb->lock, flags);
1477 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1479 struct musb_ep *musb_ep = to_musb_ep(ep);
1480 struct musb *musb = musb_ep->musb;
1481 u8 epnum = musb_ep->current_epnum;
1482 void __iomem *epio = musb->endpoints[epnum].regs;
1483 void __iomem *mbase;
1484 unsigned long flags;
1487 mbase = musb->mregs;
1489 spin_lock_irqsave(&musb->lock, flags);
1490 musb_ep_select(mbase, (u8) epnum);
1492 /* disable interrupts */
1493 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe & ~(1 << epnum));
1495 if (musb_ep->is_in) {
1496 csr = musb_readw(epio, MUSB_TXCSR);
1497 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1498 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1500 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1501 * to interrupt current FIFO loading, but not flushing
1502 * the already loaded ones.
1504 csr &= ~MUSB_TXCSR_TXPKTRDY;
1505 musb_writew(epio, MUSB_TXCSR, csr);
1506 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1507 musb_writew(epio, MUSB_TXCSR, csr);
1510 csr = musb_readw(epio, MUSB_RXCSR);
1511 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1512 musb_writew(epio, MUSB_RXCSR, csr);
1513 musb_writew(epio, MUSB_RXCSR, csr);
1516 /* re-enable interrupt */
1517 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1518 spin_unlock_irqrestore(&musb->lock, flags);
1521 static const struct usb_ep_ops musb_ep_ops = {
1522 .enable = musb_gadget_enable,
1523 .disable = musb_gadget_disable,
1524 .alloc_request = musb_alloc_request,
1525 .free_request = musb_free_request,
1526 .queue = musb_gadget_queue,
1527 .dequeue = musb_gadget_dequeue,
1528 .set_halt = musb_gadget_set_halt,
1529 .set_wedge = musb_gadget_set_wedge,
1530 .fifo_status = musb_gadget_fifo_status,
1531 .fifo_flush = musb_gadget_fifo_flush
1534 /* ----------------------------------------------------------------------- */
1536 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1538 struct musb *musb = gadget_to_musb(gadget);
1540 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1543 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1545 struct musb *musb = gadget_to_musb(gadget);
1546 void __iomem *mregs = musb->mregs;
1547 unsigned long flags;
1548 int status = -EINVAL;
1552 spin_lock_irqsave(&musb->lock, flags);
1554 switch (musb->xceiv->otg->state) {
1555 case OTG_STATE_B_PERIPHERAL:
1556 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1557 * that's part of the standard usb 1.1 state machine, and
1558 * doesn't affect OTG transitions.
1560 if (musb->may_wakeup && musb->is_suspended)
1563 case OTG_STATE_B_IDLE:
1564 /* Start SRP ... OTG not required. */
1565 devctl = musb_readb(mregs, MUSB_DEVCTL);
1566 musb_dbg(musb, "Sending SRP: devctl: %02x", devctl);
1567 devctl |= MUSB_DEVCTL_SESSION;
1568 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1569 devctl = musb_readb(mregs, MUSB_DEVCTL);
1571 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1572 devctl = musb_readb(mregs, MUSB_DEVCTL);
1577 while (devctl & MUSB_DEVCTL_SESSION) {
1578 devctl = musb_readb(mregs, MUSB_DEVCTL);
1583 spin_unlock_irqrestore(&musb->lock, flags);
1584 otg_start_srp(musb->xceiv->otg);
1585 spin_lock_irqsave(&musb->lock, flags);
1587 /* Block idling for at least 1s */
1588 musb_platform_try_idle(musb,
1589 jiffies + msecs_to_jiffies(1 * HZ));
1594 musb_dbg(musb, "Unhandled wake: %s",
1595 usb_otg_state_string(musb->xceiv->otg->state));
1601 power = musb_readb(mregs, MUSB_POWER);
1602 power |= MUSB_POWER_RESUME;
1603 musb_writeb(mregs, MUSB_POWER, power);
1604 musb_dbg(musb, "issue wakeup");
1606 /* FIXME do this next chunk in a timer callback, no udelay */
1609 power = musb_readb(mregs, MUSB_POWER);
1610 power &= ~MUSB_POWER_RESUME;
1611 musb_writeb(mregs, MUSB_POWER, power);
1613 spin_unlock_irqrestore(&musb->lock, flags);
1618 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1620 gadget->is_selfpowered = !!is_selfpowered;
1624 static void musb_pullup(struct musb *musb, int is_on)
1628 power = musb_readb(musb->mregs, MUSB_POWER);
1630 power |= MUSB_POWER_SOFTCONN;
1632 power &= ~MUSB_POWER_SOFTCONN;
1634 /* FIXME if on, HdrcStart; if off, HdrcStop */
1636 musb_dbg(musb, "gadget D+ pullup %s",
1637 is_on ? "on" : "off");
1638 musb_writeb(musb->mregs, MUSB_POWER, power);
1642 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1644 musb_dbg(musb, "<= %s =>\n", __func__);
1647 * FIXME iff driver's softconnect flag is set (as it is during probe,
1648 * though that can clear it), just musb_pullup().
1655 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1657 struct musb *musb = gadget_to_musb(gadget);
1659 if (!musb->xceiv->set_power)
1661 return usb_phy_set_power(musb->xceiv, mA);
1664 static void musb_gadget_work(struct work_struct *work)
1667 unsigned long flags;
1669 musb = container_of(work, struct musb, gadget_work.work);
1670 pm_runtime_get_sync(musb->controller);
1671 spin_lock_irqsave(&musb->lock, flags);
1672 musb_pullup(musb, musb->softconnect);
1673 spin_unlock_irqrestore(&musb->lock, flags);
1674 pm_runtime_mark_last_busy(musb->controller);
1675 pm_runtime_put_autosuspend(musb->controller);
1678 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1680 struct musb *musb = gadget_to_musb(gadget);
1681 unsigned long flags;
1685 /* NOTE: this assumes we are sensing vbus; we'd rather
1686 * not pullup unless the B-session is active.
1688 spin_lock_irqsave(&musb->lock, flags);
1689 if (is_on != musb->softconnect) {
1690 musb->softconnect = is_on;
1691 schedule_delayed_work(&musb->gadget_work, 0);
1693 spin_unlock_irqrestore(&musb->lock, flags);
1698 #ifdef CONFIG_BLACKFIN
1699 static struct usb_ep *musb_match_ep(struct usb_gadget *g,
1700 struct usb_endpoint_descriptor *desc,
1701 struct usb_ss_ep_comp_descriptor *ep_comp)
1703 struct usb_ep *ep = NULL;
1705 switch (usb_endpoint_type(desc)) {
1706 case USB_ENDPOINT_XFER_ISOC:
1707 case USB_ENDPOINT_XFER_BULK:
1708 if (usb_endpoint_dir_in(desc))
1709 ep = gadget_find_ep_by_name(g, "ep5in");
1711 ep = gadget_find_ep_by_name(g, "ep6out");
1713 case USB_ENDPOINT_XFER_INT:
1714 if (usb_endpoint_dir_in(desc))
1715 ep = gadget_find_ep_by_name(g, "ep1in");
1717 ep = gadget_find_ep_by_name(g, "ep2out");
1723 if (ep && usb_gadget_ep_match_desc(g, ep, desc, ep_comp))
1729 #define musb_match_ep NULL
1732 static int musb_gadget_start(struct usb_gadget *g,
1733 struct usb_gadget_driver *driver);
1734 static int musb_gadget_stop(struct usb_gadget *g);
1736 static const struct usb_gadget_ops musb_gadget_operations = {
1737 .get_frame = musb_gadget_get_frame,
1738 .wakeup = musb_gadget_wakeup,
1739 .set_selfpowered = musb_gadget_set_self_powered,
1740 /* .vbus_session = musb_gadget_vbus_session, */
1741 .vbus_draw = musb_gadget_vbus_draw,
1742 .pullup = musb_gadget_pullup,
1743 .udc_start = musb_gadget_start,
1744 .udc_stop = musb_gadget_stop,
1745 .match_ep = musb_match_ep,
1748 /* ----------------------------------------------------------------------- */
1752 /* Only this registration code "knows" the rule (from USB standards)
1753 * about there being only one external upstream port. It assumes
1754 * all peripheral ports are external...
1758 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1760 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1762 memset(ep, 0, sizeof *ep);
1764 ep->current_epnum = epnum;
1769 INIT_LIST_HEAD(&ep->req_list);
1771 sprintf(ep->name, "ep%d%s", epnum,
1772 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1773 is_in ? "in" : "out"));
1774 ep->end_point.name = ep->name;
1775 INIT_LIST_HEAD(&ep->end_point.ep_list);
1777 usb_ep_set_maxpacket_limit(&ep->end_point, 64);
1778 ep->end_point.caps.type_control = true;
1779 ep->end_point.ops = &musb_g_ep0_ops;
1780 musb->g.ep0 = &ep->end_point;
1783 usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_tx);
1785 usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_rx);
1786 ep->end_point.caps.type_iso = true;
1787 ep->end_point.caps.type_bulk = true;
1788 ep->end_point.caps.type_int = true;
1789 ep->end_point.ops = &musb_ep_ops;
1790 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1793 if (!epnum || hw_ep->is_shared_fifo) {
1794 ep->end_point.caps.dir_in = true;
1795 ep->end_point.caps.dir_out = true;
1797 ep->end_point.caps.dir_in = true;
1799 ep->end_point.caps.dir_out = true;
1803 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1804 * to the rest of the driver state.
1806 static inline void musb_g_init_endpoints(struct musb *musb)
1809 struct musb_hw_ep *hw_ep;
1812 /* initialize endpoint list just once */
1813 INIT_LIST_HEAD(&(musb->g.ep_list));
1815 for (epnum = 0, hw_ep = musb->endpoints;
1816 epnum < musb->nr_endpoints;
1818 if (hw_ep->is_shared_fifo /* || !epnum */) {
1819 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1822 if (hw_ep->max_packet_sz_tx) {
1823 init_peripheral_ep(musb, &hw_ep->ep_in,
1827 if (hw_ep->max_packet_sz_rx) {
1828 init_peripheral_ep(musb, &hw_ep->ep_out,
1836 /* called once during driver setup to initialize and link into
1837 * the driver model; memory is zeroed.
1839 int musb_gadget_setup(struct musb *musb)
1843 /* REVISIT minor race: if (erroneously) setting up two
1844 * musb peripherals at the same time, only the bus lock
1848 musb->g.ops = &musb_gadget_operations;
1849 musb->g.max_speed = USB_SPEED_HIGH;
1850 musb->g.speed = USB_SPEED_UNKNOWN;
1852 MUSB_DEV_MODE(musb);
1853 musb->xceiv->otg->default_a = 0;
1854 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
1856 /* this "gadget" abstracts/virtualizes the controller */
1857 musb->g.name = musb_driver_name;
1858 #if IS_ENABLED(CONFIG_USB_MUSB_DUAL_ROLE)
1860 #elif IS_ENABLED(CONFIG_USB_MUSB_GADGET)
1863 INIT_DELAYED_WORK(&musb->gadget_work, musb_gadget_work);
1864 musb_g_init_endpoints(musb);
1866 musb->is_active = 0;
1867 musb_platform_try_idle(musb, 0);
1869 status = usb_add_gadget_udc(musb->controller, &musb->g);
1875 musb->g.dev.parent = NULL;
1876 device_unregister(&musb->g.dev);
1880 void musb_gadget_cleanup(struct musb *musb)
1882 if (musb->port_mode == MUSB_PORT_MODE_HOST)
1885 cancel_delayed_work_sync(&musb->gadget_work);
1886 usb_del_gadget_udc(&musb->g);
1890 * Register the gadget driver. Used by gadget drivers when
1891 * registering themselves with the controller.
1893 * -EINVAL something went wrong (not driver)
1894 * -EBUSY another gadget is already using the controller
1895 * -ENOMEM no memory to perform the operation
1897 * @param driver the gadget driver
1898 * @return <0 if error, 0 if everything is fine
1900 static int musb_gadget_start(struct usb_gadget *g,
1901 struct usb_gadget_driver *driver)
1903 struct musb *musb = gadget_to_musb(g);
1904 struct usb_otg *otg = musb->xceiv->otg;
1905 unsigned long flags;
1908 if (driver->max_speed < USB_SPEED_HIGH) {
1913 pm_runtime_get_sync(musb->controller);
1915 musb->softconnect = 0;
1916 musb->gadget_driver = driver;
1918 spin_lock_irqsave(&musb->lock, flags);
1919 musb->is_active = 1;
1921 otg_set_peripheral(otg, &musb->g);
1922 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
1923 spin_unlock_irqrestore(&musb->lock, flags);
1927 /* REVISIT: funcall to other code, which also
1928 * handles power budgeting ... this way also
1929 * ensures HdrcStart is indirectly called.
1931 if (musb->xceiv->last_event == USB_EVENT_ID)
1932 musb_platform_set_vbus(musb, 1);
1934 pm_runtime_mark_last_busy(musb->controller);
1935 pm_runtime_put_autosuspend(musb->controller);
1944 * Unregister the gadget driver. Used by gadget drivers when
1945 * unregistering themselves from the controller.
1947 * @param driver the gadget driver to unregister
1949 static int musb_gadget_stop(struct usb_gadget *g)
1951 struct musb *musb = gadget_to_musb(g);
1952 unsigned long flags;
1954 pm_runtime_get_sync(musb->controller);
1957 * REVISIT always use otg_set_peripheral() here too;
1958 * this needs to shut down the OTG engine.
1961 spin_lock_irqsave(&musb->lock, flags);
1963 musb_hnp_stop(musb);
1965 (void) musb_gadget_vbus_draw(&musb->g, 0);
1967 musb->xceiv->otg->state = OTG_STATE_UNDEFINED;
1969 otg_set_peripheral(musb->xceiv->otg, NULL);
1971 musb->is_active = 0;
1972 musb->gadget_driver = NULL;
1973 musb_platform_try_idle(musb, 0);
1974 spin_unlock_irqrestore(&musb->lock, flags);
1977 * FIXME we need to be able to register another
1978 * gadget driver here and have everything work;
1979 * that currently misbehaves.
1982 /* Force check of devctl register for PM runtime */
1983 schedule_delayed_work(&musb->irq_work, 0);
1985 pm_runtime_mark_last_busy(musb->controller);
1986 pm_runtime_put_autosuspend(musb->controller);
1991 /* ----------------------------------------------------------------------- */
1993 /* lifecycle operations called through plat_uds.c */
1995 void musb_g_resume(struct musb *musb)
1997 musb->is_suspended = 0;
1998 switch (musb->xceiv->otg->state) {
1999 case OTG_STATE_B_IDLE:
2001 case OTG_STATE_B_WAIT_ACON:
2002 case OTG_STATE_B_PERIPHERAL:
2003 musb->is_active = 1;
2004 if (musb->gadget_driver && musb->gadget_driver->resume) {
2005 spin_unlock(&musb->lock);
2006 musb->gadget_driver->resume(&musb->g);
2007 spin_lock(&musb->lock);
2011 WARNING("unhandled RESUME transition (%s)\n",
2012 usb_otg_state_string(musb->xceiv->otg->state));
2016 /* called when SOF packets stop for 3+ msec */
2017 void musb_g_suspend(struct musb *musb)
2021 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2022 musb_dbg(musb, "musb_g_suspend: devctl %02x", devctl);
2024 switch (musb->xceiv->otg->state) {
2025 case OTG_STATE_B_IDLE:
2026 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2027 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2029 case OTG_STATE_B_PERIPHERAL:
2030 musb->is_suspended = 1;
2031 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2032 spin_unlock(&musb->lock);
2033 musb->gadget_driver->suspend(&musb->g);
2034 spin_lock(&musb->lock);
2038 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2039 * A_PERIPHERAL may need care too
2041 WARNING("unhandled SUSPEND transition (%s)",
2042 usb_otg_state_string(musb->xceiv->otg->state));
2046 /* Called during SRP */
2047 void musb_g_wakeup(struct musb *musb)
2049 musb_gadget_wakeup(&musb->g);
2052 /* called when VBUS drops below session threshold, and in other cases */
2053 void musb_g_disconnect(struct musb *musb)
2055 void __iomem *mregs = musb->mregs;
2056 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2058 musb_dbg(musb, "musb_g_disconnect: devctl %02x", devctl);
2061 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2063 /* don't draw vbus until new b-default session */
2064 (void) musb_gadget_vbus_draw(&musb->g, 0);
2066 musb->g.speed = USB_SPEED_UNKNOWN;
2067 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2068 spin_unlock(&musb->lock);
2069 musb->gadget_driver->disconnect(&musb->g);
2070 spin_lock(&musb->lock);
2073 switch (musb->xceiv->otg->state) {
2075 musb_dbg(musb, "Unhandled disconnect %s, setting a_idle",
2076 usb_otg_state_string(musb->xceiv->otg->state));
2077 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2078 MUSB_HST_MODE(musb);
2080 case OTG_STATE_A_PERIPHERAL:
2081 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
2082 MUSB_HST_MODE(musb);
2084 case OTG_STATE_B_WAIT_ACON:
2085 case OTG_STATE_B_HOST:
2086 case OTG_STATE_B_PERIPHERAL:
2087 case OTG_STATE_B_IDLE:
2088 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2090 case OTG_STATE_B_SRP_INIT:
2094 musb->is_active = 0;
2097 void musb_g_reset(struct musb *musb)
2098 __releases(musb->lock)
2099 __acquires(musb->lock)
2101 void __iomem *mbase = musb->mregs;
2102 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2105 musb_dbg(musb, "<== %s driver '%s'",
2106 (devctl & MUSB_DEVCTL_BDEVICE)
2107 ? "B-Device" : "A-Device",
2109 ? musb->gadget_driver->driver.name
2113 /* report reset, if we didn't already (flushing EP state) */
2114 if (musb->gadget_driver && musb->g.speed != USB_SPEED_UNKNOWN) {
2115 spin_unlock(&musb->lock);
2116 usb_gadget_udc_reset(&musb->g, musb->gadget_driver);
2117 spin_lock(&musb->lock);
2121 else if (devctl & MUSB_DEVCTL_HR)
2122 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2125 /* what speed did we negotiate? */
2126 power = musb_readb(mbase, MUSB_POWER);
2127 musb->g.speed = (power & MUSB_POWER_HSMODE)
2128 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2130 /* start in USB_STATE_DEFAULT */
2131 musb->is_active = 1;
2132 musb->is_suspended = 0;
2133 MUSB_DEV_MODE(musb);
2135 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2137 musb->may_wakeup = 0;
2138 musb->g.b_hnp_enable = 0;
2139 musb->g.a_alt_hnp_support = 0;
2140 musb->g.a_hnp_support = 0;
2141 musb->g.quirk_zlp_not_supp = 1;
2143 /* Normal reset, as B-Device;
2144 * or else after HNP, as A-Device
2146 if (!musb->g.is_otg) {
2147 /* USB device controllers that are not OTG compatible
2148 * may not have DEVCTL register in silicon.
2149 * In that case, do not rely on devctl for setting
2152 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2153 musb->g.is_a_peripheral = 0;
2154 } else if (devctl & MUSB_DEVCTL_BDEVICE) {
2155 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2156 musb->g.is_a_peripheral = 0;
2158 musb->xceiv->otg->state = OTG_STATE_A_PERIPHERAL;
2159 musb->g.is_a_peripheral = 1;
2162 /* start with default limits on VBUS power draw */
2163 (void) musb_gadget_vbus_draw(&musb->g, 8);