1 // SPDX-License-Identifier: GPL-2.0
3 * MUSB OTG driver peripheral support
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
8 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
11 #include <linux/kernel.h>
12 #include <linux/list.h>
13 #include <linux/timer.h>
14 #include <linux/module.h>
15 #include <linux/smp.h>
16 #include <linux/spinlock.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/slab.h>
21 #include "musb_core.h"
22 #include "musb_trace.h"
25 /* ----------------------------------------------------------------------- */
27 #define is_buffer_mapped(req) (is_dma_capable() && \
28 (req->map_state != UN_MAPPED))
30 /* Maps the buffer to dma */
32 static inline void map_dma_buffer(struct musb_request *request,
33 struct musb *musb, struct musb_ep *musb_ep)
35 int compatible = true;
36 struct dma_controller *dma = musb->dma_controller;
38 request->map_state = UN_MAPPED;
40 if (!is_dma_capable() || !musb_ep->dma)
43 /* Check if DMA engine can handle this request.
44 * DMA code must reject the USB request explicitly.
45 * Default behaviour is to map the request.
47 if (dma->is_compatible)
48 compatible = dma->is_compatible(musb_ep->dma,
49 musb_ep->packet_sz, request->request.buf,
50 request->request.length);
54 if (request->request.dma == DMA_ADDR_INVALID) {
58 dma_addr = dma_map_single(
61 request->request.length,
65 ret = dma_mapping_error(musb->controller, dma_addr);
69 request->request.dma = dma_addr;
70 request->map_state = MUSB_MAPPED;
72 dma_sync_single_for_device(musb->controller,
74 request->request.length,
78 request->map_state = PRE_MAPPED;
82 /* Unmap the buffer from dma and maps it back to cpu */
83 static inline void unmap_dma_buffer(struct musb_request *request,
86 struct musb_ep *musb_ep = request->ep;
88 if (!is_buffer_mapped(request) || !musb_ep->dma)
91 if (request->request.dma == DMA_ADDR_INVALID) {
92 dev_vdbg(musb->controller,
93 "not unmapping a never mapped buffer\n");
96 if (request->map_state == MUSB_MAPPED) {
97 dma_unmap_single(musb->controller,
99 request->request.length,
103 request->request.dma = DMA_ADDR_INVALID;
104 } else { /* PRE_MAPPED */
105 dma_sync_single_for_cpu(musb->controller,
106 request->request.dma,
107 request->request.length,
112 request->map_state = UN_MAPPED;
116 * Immediately complete a request.
118 * @param request the request to complete
119 * @param status the status to complete the request with
120 * Context: controller locked, IRQs blocked.
122 void musb_g_giveback(
124 struct usb_request *request,
126 __releases(ep->musb->lock)
127 __acquires(ep->musb->lock)
129 struct musb_request *req;
133 req = to_musb_request(request);
135 list_del(&req->list);
136 if (req->request.status == -EINPROGRESS)
137 req->request.status = status;
141 spin_unlock(&musb->lock);
143 if (!dma_mapping_error(&musb->g.dev, request->dma))
144 unmap_dma_buffer(req, musb);
146 trace_musb_req_gb(req);
147 usb_gadget_giveback_request(&req->ep->end_point, &req->request);
148 spin_lock(&musb->lock);
152 /* ----------------------------------------------------------------------- */
155 * Abort requests queued to an endpoint using the status. Synchronous.
156 * caller locked controller and blocked irqs, and selected this ep.
158 static void nuke(struct musb_ep *ep, const int status)
160 struct musb *musb = ep->musb;
161 struct musb_request *req = NULL;
162 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
166 if (is_dma_capable() && ep->dma) {
167 struct dma_controller *c = ep->musb->dma_controller;
172 * The programming guide says that we must not clear
173 * the DMAMODE bit before DMAENAB, so we only
174 * clear it in the second write...
176 musb_writew(epio, MUSB_TXCSR,
177 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
178 musb_writew(epio, MUSB_TXCSR,
179 0 | MUSB_TXCSR_FLUSHFIFO);
181 musb_writew(epio, MUSB_RXCSR,
182 0 | MUSB_RXCSR_FLUSHFIFO);
183 musb_writew(epio, MUSB_RXCSR,
184 0 | MUSB_RXCSR_FLUSHFIFO);
187 value = c->channel_abort(ep->dma);
188 musb_dbg(musb, "%s: abort DMA --> %d", ep->name, value);
189 c->channel_release(ep->dma);
193 while (!list_empty(&ep->req_list)) {
194 req = list_first_entry(&ep->req_list, struct musb_request, list);
195 musb_g_giveback(ep, &req->request, status);
199 /* ----------------------------------------------------------------------- */
201 /* Data transfers - pure PIO, pure DMA, or mixed mode */
204 * This assumes the separate CPPI engine is responding to DMA requests
205 * from the usb core ... sequenced a bit differently from mentor dma.
208 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
210 if (can_bulk_split(musb, ep->type))
211 return ep->hw_ep->max_packet_sz_tx;
213 return ep->packet_sz;
217 * An endpoint is transmitting data. This can be called either from
218 * the IRQ routine or from ep.queue() to kickstart a request on an
221 * Context: controller locked, IRQs blocked, endpoint selected
223 static void txstate(struct musb *musb, struct musb_request *req)
225 u8 epnum = req->epnum;
226 struct musb_ep *musb_ep;
227 void __iomem *epio = musb->endpoints[epnum].regs;
228 struct usb_request *request;
229 u16 fifo_count = 0, csr;
234 /* Check if EP is disabled */
235 if (!musb_ep->desc) {
236 musb_dbg(musb, "ep:%s disabled - ignore request",
237 musb_ep->end_point.name);
241 /* we shouldn't get here while DMA is active ... but we do ... */
242 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
243 musb_dbg(musb, "dma pending...");
247 /* read TXCSR before */
248 csr = musb_readw(epio, MUSB_TXCSR);
250 request = &req->request;
251 fifo_count = min(max_ep_writesize(musb, musb_ep),
252 (int)(request->length - request->actual));
254 if (csr & MUSB_TXCSR_TXPKTRDY) {
255 musb_dbg(musb, "%s old packet still ready , txcsr %03x",
256 musb_ep->end_point.name, csr);
260 if (csr & MUSB_TXCSR_P_SENDSTALL) {
261 musb_dbg(musb, "%s stalling, txcsr %03x",
262 musb_ep->end_point.name, csr);
266 musb_dbg(musb, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x",
267 epnum, musb_ep->packet_sz, fifo_count,
270 #ifndef CONFIG_MUSB_PIO_ONLY
271 if (is_buffer_mapped(req)) {
272 struct dma_controller *c = musb->dma_controller;
275 /* setup DMA, then program endpoint CSR */
276 request_size = min_t(size_t, request->length - request->actual,
277 musb_ep->dma->max_len);
279 use_dma = (request->dma != DMA_ADDR_INVALID && request_size);
281 /* MUSB_TXCSR_P_ISO is still set correctly */
283 if (musb_dma_inventra(musb) || musb_dma_ux500(musb)) {
284 if (request_size < musb_ep->packet_sz)
285 musb_ep->dma->desired_mode = 0;
287 musb_ep->dma->desired_mode = 1;
289 use_dma = use_dma && c->channel_program(
290 musb_ep->dma, musb_ep->packet_sz,
291 musb_ep->dma->desired_mode,
292 request->dma + request->actual, request_size);
294 if (musb_ep->dma->desired_mode == 0) {
296 * We must not clear the DMAMODE bit
297 * before the DMAENAB bit -- and the
298 * latter doesn't always get cleared
299 * before we get here...
301 csr &= ~(MUSB_TXCSR_AUTOSET
302 | MUSB_TXCSR_DMAENAB);
303 musb_writew(epio, MUSB_TXCSR, csr
304 | MUSB_TXCSR_P_WZC_BITS);
305 csr &= ~MUSB_TXCSR_DMAMODE;
306 csr |= (MUSB_TXCSR_DMAENAB |
308 /* against programming guide */
310 csr |= (MUSB_TXCSR_DMAENAB
314 * Enable Autoset according to table
316 * bulk_split hb_mult Autoset_Enable
318 * 0 >0 No(High BW ISO)
322 if (!musb_ep->hb_mult ||
325 csr |= MUSB_TXCSR_AUTOSET;
327 csr &= ~MUSB_TXCSR_P_UNDERRUN;
329 musb_writew(epio, MUSB_TXCSR, csr);
333 if (is_cppi_enabled(musb)) {
334 /* program endpoint CSR first, then setup DMA */
335 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
336 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
338 musb_writew(epio, MUSB_TXCSR, (MUSB_TXCSR_P_WZC_BITS &
339 ~MUSB_TXCSR_P_UNDERRUN) | csr);
341 /* ensure writebuffer is empty */
342 csr = musb_readw(epio, MUSB_TXCSR);
345 * NOTE host side sets DMAENAB later than this; both are
346 * OK since the transfer dma glue (between CPPI and
347 * Mentor fifos) just tells CPPI it could start. Data
348 * only moves to the USB TX fifo when both fifos are
352 * "mode" is irrelevant here; handle terminating ZLPs
353 * like PIO does, since the hardware RNDIS mode seems
354 * unreliable except for the
355 * last-packet-is-already-short case.
357 use_dma = use_dma && c->channel_program(
358 musb_ep->dma, musb_ep->packet_sz,
360 request->dma + request->actual,
363 c->channel_release(musb_ep->dma);
365 csr &= ~MUSB_TXCSR_DMAENAB;
366 musb_writew(epio, MUSB_TXCSR, csr);
367 /* invariant: prequest->buf is non-null */
369 } else if (tusb_dma_omap(musb))
370 use_dma = use_dma && c->channel_program(
371 musb_ep->dma, musb_ep->packet_sz,
373 request->dma + request->actual,
380 * Unmap the dma buffer back to cpu if dma channel
383 unmap_dma_buffer(req, musb);
385 musb_write_fifo(musb_ep->hw_ep, fifo_count,
386 (u8 *) (request->buf + request->actual));
387 request->actual += fifo_count;
388 csr |= MUSB_TXCSR_TXPKTRDY;
389 csr &= ~MUSB_TXCSR_P_UNDERRUN;
390 musb_writew(epio, MUSB_TXCSR, csr);
393 /* host may already have the data when this message shows... */
394 musb_dbg(musb, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d",
395 musb_ep->end_point.name, use_dma ? "dma" : "pio",
396 request->actual, request->length,
397 musb_readw(epio, MUSB_TXCSR),
399 musb_readw(epio, MUSB_TXMAXP));
403 * FIFO state update (e.g. data ready).
404 * Called from IRQ, with controller locked.
406 void musb_g_tx(struct musb *musb, u8 epnum)
409 struct musb_request *req;
410 struct usb_request *request;
411 u8 __iomem *mbase = musb->mregs;
412 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
413 void __iomem *epio = musb->endpoints[epnum].regs;
414 struct dma_channel *dma;
416 musb_ep_select(mbase, epnum);
417 req = next_request(musb_ep);
418 request = &req->request;
420 csr = musb_readw(epio, MUSB_TXCSR);
421 musb_dbg(musb, "<== %s, txcsr %04x", musb_ep->end_point.name, csr);
423 dma = is_dma_capable() ? musb_ep->dma : NULL;
426 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
427 * probably rates reporting as a host error.
429 if (csr & MUSB_TXCSR_P_SENTSTALL) {
430 csr |= MUSB_TXCSR_P_WZC_BITS;
431 csr &= ~MUSB_TXCSR_P_SENTSTALL;
432 musb_writew(epio, MUSB_TXCSR, csr);
436 if (csr & MUSB_TXCSR_P_UNDERRUN) {
437 /* We NAKed, no big deal... little reason to care. */
438 csr |= MUSB_TXCSR_P_WZC_BITS;
439 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
440 musb_writew(epio, MUSB_TXCSR, csr);
441 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
445 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
447 * SHOULD NOT HAPPEN... has with CPPI though, after
448 * changing SENDSTALL (and other cases); harmless?
450 musb_dbg(musb, "%s dma still busy?", musb_ep->end_point.name);
456 trace_musb_req_tx(req);
458 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
459 csr |= MUSB_TXCSR_P_WZC_BITS;
460 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
461 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
462 musb_writew(epio, MUSB_TXCSR, csr);
463 /* Ensure writebuffer is empty. */
464 csr = musb_readw(epio, MUSB_TXCSR);
465 request->actual += musb_ep->dma->actual_len;
466 musb_dbg(musb, "TXCSR%d %04x, DMA off, len %zu, req %p",
467 epnum, csr, musb_ep->dma->actual_len, request);
471 * First, maybe a terminating short packet. Some DMA
472 * engines might handle this by themselves.
474 if ((request->zero && request->length)
475 && (request->length % musb_ep->packet_sz == 0)
476 && (request->actual == request->length)) {
479 * On DMA completion, FIFO may not be
482 if (csr & MUSB_TXCSR_TXPKTRDY)
485 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
486 | MUSB_TXCSR_TXPKTRDY);
490 if (request->actual == request->length) {
491 musb_g_giveback(musb_ep, request, 0);
493 * In the giveback function the MUSB lock is
494 * released and acquired after sometime. During
495 * this time period the INDEX register could get
496 * changed by the gadget_queue function especially
497 * on SMP systems. Reselect the INDEX to be sure
498 * we are reading/modifying the right registers
500 musb_ep_select(mbase, epnum);
501 req = musb_ep->desc ? next_request(musb_ep) : NULL;
503 musb_dbg(musb, "%s idle now",
504 musb_ep->end_point.name);
513 /* ------------------------------------------------------------ */
516 * Context: controller locked, IRQs blocked, endpoint selected
518 static void rxstate(struct musb *musb, struct musb_request *req)
520 const u8 epnum = req->epnum;
521 struct usb_request *request = &req->request;
522 struct musb_ep *musb_ep;
523 void __iomem *epio = musb->endpoints[epnum].regs;
526 u16 csr = musb_readw(epio, MUSB_RXCSR);
527 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
530 if (hw_ep->is_shared_fifo)
531 musb_ep = &hw_ep->ep_in;
533 musb_ep = &hw_ep->ep_out;
535 fifo_count = musb_ep->packet_sz;
537 /* Check if EP is disabled */
538 if (!musb_ep->desc) {
539 musb_dbg(musb, "ep:%s disabled - ignore request",
540 musb_ep->end_point.name);
544 /* We shouldn't get here while DMA is active, but we do... */
545 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
546 musb_dbg(musb, "DMA pending...");
550 if (csr & MUSB_RXCSR_P_SENDSTALL) {
551 musb_dbg(musb, "%s stalling, RXCSR %04x",
552 musb_ep->end_point.name, csr);
556 if (is_cppi_enabled(musb) && is_buffer_mapped(req)) {
557 struct dma_controller *c = musb->dma_controller;
558 struct dma_channel *channel = musb_ep->dma;
560 /* NOTE: CPPI won't actually stop advancing the DMA
561 * queue after short packet transfers, so this is almost
562 * always going to run as IRQ-per-packet DMA so that
563 * faults will be handled correctly.
565 if (c->channel_program(channel,
567 !request->short_not_ok,
568 request->dma + request->actual,
569 request->length - request->actual)) {
571 /* make sure that if an rxpkt arrived after the irq,
572 * the cppi engine will be ready to take it as soon
575 csr &= ~(MUSB_RXCSR_AUTOCLEAR
576 | MUSB_RXCSR_DMAMODE);
577 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
578 musb_writew(epio, MUSB_RXCSR, csr);
583 if (csr & MUSB_RXCSR_RXPKTRDY) {
584 fifo_count = musb_readw(epio, MUSB_RXCOUNT);
587 * Enable Mode 1 on RX transfers only when short_not_ok flag
588 * is set. Currently short_not_ok flag is set only from
589 * file_storage and f_mass_storage drivers
592 if (request->short_not_ok && fifo_count == musb_ep->packet_sz)
597 if (request->actual < request->length) {
598 if (!is_buffer_mapped(req))
599 goto buffer_aint_mapped;
601 if (musb_dma_inventra(musb)) {
602 struct dma_controller *c;
603 struct dma_channel *channel;
605 unsigned int transfer_size;
607 c = musb->dma_controller;
608 channel = musb_ep->dma;
610 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
611 * mode 0 only. So we do not get endpoint interrupts due to DMA
612 * completion. We only get interrupts from DMA controller.
614 * We could operate in DMA mode 1 if we knew the size of the tranfer
615 * in advance. For mass storage class, request->length = what the host
616 * sends, so that'd work. But for pretty much everything else,
617 * request->length is routinely more than what the host sends. For
618 * most these gadgets, end of is signified either by a short packet,
619 * or filling the last byte of the buffer. (Sending extra data in
620 * that last pckate should trigger an overflow fault.) But in mode 1,
621 * we don't get DMA completion interrupt for short packets.
623 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
624 * to get endpoint interrupt on every DMA req, but that didn't seem
627 * REVISIT an updated g_file_storage can set req->short_not_ok, which
628 * then becomes usable as a runtime "use mode 1" hint...
631 /* Experimental: Mode1 works with mass storage use cases */
633 csr |= MUSB_RXCSR_AUTOCLEAR;
634 musb_writew(epio, MUSB_RXCSR, csr);
635 csr |= MUSB_RXCSR_DMAENAB;
636 musb_writew(epio, MUSB_RXCSR, csr);
639 * this special sequence (enabling and then
640 * disabling MUSB_RXCSR_DMAMODE) is required
641 * to get DMAReq to activate
643 musb_writew(epio, MUSB_RXCSR,
644 csr | MUSB_RXCSR_DMAMODE);
645 musb_writew(epio, MUSB_RXCSR, csr);
647 transfer_size = min_t(unsigned int,
651 musb_ep->dma->desired_mode = 1;
653 if (!musb_ep->hb_mult &&
654 musb_ep->hw_ep->rx_double_buffered)
655 csr |= MUSB_RXCSR_AUTOCLEAR;
656 csr |= MUSB_RXCSR_DMAENAB;
657 musb_writew(epio, MUSB_RXCSR, csr);
659 transfer_size = min(request->length - request->actual,
660 (unsigned)fifo_count);
661 musb_ep->dma->desired_mode = 0;
664 use_dma = c->channel_program(
667 channel->desired_mode,
676 if ((musb_dma_ux500(musb)) &&
677 (request->actual < request->length)) {
679 struct dma_controller *c;
680 struct dma_channel *channel;
681 unsigned int transfer_size = 0;
683 c = musb->dma_controller;
684 channel = musb_ep->dma;
686 /* In case first packet is short */
687 if (fifo_count < musb_ep->packet_sz)
688 transfer_size = fifo_count;
689 else if (request->short_not_ok)
690 transfer_size = min_t(unsigned int,
695 transfer_size = min_t(unsigned int,
698 (unsigned)fifo_count);
700 csr &= ~MUSB_RXCSR_DMAMODE;
701 csr |= (MUSB_RXCSR_DMAENAB |
702 MUSB_RXCSR_AUTOCLEAR);
704 musb_writew(epio, MUSB_RXCSR, csr);
706 if (transfer_size <= musb_ep->packet_sz) {
707 musb_ep->dma->desired_mode = 0;
709 musb_ep->dma->desired_mode = 1;
710 /* Mode must be set after DMAENAB */
711 csr |= MUSB_RXCSR_DMAMODE;
712 musb_writew(epio, MUSB_RXCSR, csr);
715 if (c->channel_program(channel,
717 channel->desired_mode,
725 len = request->length - request->actual;
726 musb_dbg(musb, "%s OUT/RX pio fifo %d/%d, maxpacket %d",
727 musb_ep->end_point.name,
731 fifo_count = min_t(unsigned, len, fifo_count);
733 if (tusb_dma_omap(musb)) {
734 struct dma_controller *c = musb->dma_controller;
735 struct dma_channel *channel = musb_ep->dma;
736 u32 dma_addr = request->dma + request->actual;
739 ret = c->channel_program(channel,
741 channel->desired_mode,
749 * Unmap the dma buffer back to cpu if dma channel
750 * programming fails. This buffer is mapped if the
751 * channel allocation is successful
753 unmap_dma_buffer(req, musb);
756 * Clear DMAENAB and AUTOCLEAR for the
759 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
760 musb_writew(epio, MUSB_RXCSR, csr);
763 fifo_count = min_t(unsigned int,
764 request->length - request->actual,
765 (unsigned int)fifo_count);
766 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
767 (request->buf + request->actual));
768 request->actual += fifo_count;
770 /* REVISIT if we left anything in the fifo, flush
771 * it and report -EOVERFLOW
775 csr |= MUSB_RXCSR_P_WZC_BITS;
776 csr &= ~MUSB_RXCSR_RXPKTRDY;
777 musb_writew(epio, MUSB_RXCSR, csr);
781 /* reach the end or short packet detected */
782 if (request->actual == request->length ||
783 fifo_count < musb_ep->packet_sz)
784 musb_g_giveback(musb_ep, request, 0);
788 * Data ready for a request; called from IRQ
790 void musb_g_rx(struct musb *musb, u8 epnum)
793 struct musb_request *req;
794 struct usb_request *request;
795 void __iomem *mbase = musb->mregs;
796 struct musb_ep *musb_ep;
797 void __iomem *epio = musb->endpoints[epnum].regs;
798 struct dma_channel *dma;
799 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
801 if (hw_ep->is_shared_fifo)
802 musb_ep = &hw_ep->ep_in;
804 musb_ep = &hw_ep->ep_out;
806 musb_ep_select(mbase, epnum);
808 req = next_request(musb_ep);
812 trace_musb_req_rx(req);
813 request = &req->request;
815 csr = musb_readw(epio, MUSB_RXCSR);
816 dma = is_dma_capable() ? musb_ep->dma : NULL;
818 musb_dbg(musb, "<== %s, rxcsr %04x%s %p", musb_ep->end_point.name,
819 csr, dma ? " (dma)" : "", request);
821 if (csr & MUSB_RXCSR_P_SENTSTALL) {
822 csr |= MUSB_RXCSR_P_WZC_BITS;
823 csr &= ~MUSB_RXCSR_P_SENTSTALL;
824 musb_writew(epio, MUSB_RXCSR, csr);
828 if (csr & MUSB_RXCSR_P_OVERRUN) {
829 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
830 csr &= ~MUSB_RXCSR_P_OVERRUN;
831 musb_writew(epio, MUSB_RXCSR, csr);
833 musb_dbg(musb, "%s iso overrun on %p", musb_ep->name, request);
834 if (request->status == -EINPROGRESS)
835 request->status = -EOVERFLOW;
837 if (csr & MUSB_RXCSR_INCOMPRX) {
838 /* REVISIT not necessarily an error */
839 musb_dbg(musb, "%s, incomprx", musb_ep->end_point.name);
842 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
843 /* "should not happen"; likely RXPKTRDY pending for DMA */
844 musb_dbg(musb, "%s busy, csr %04x",
845 musb_ep->end_point.name, csr);
849 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
850 csr &= ~(MUSB_RXCSR_AUTOCLEAR
852 | MUSB_RXCSR_DMAMODE);
853 musb_writew(epio, MUSB_RXCSR,
854 MUSB_RXCSR_P_WZC_BITS | csr);
856 request->actual += musb_ep->dma->actual_len;
858 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
859 defined(CONFIG_USB_UX500_DMA)
860 /* Autoclear doesn't clear RxPktRdy for short packets */
861 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
863 & (musb_ep->packet_sz - 1))) {
865 csr &= ~MUSB_RXCSR_RXPKTRDY;
866 musb_writew(epio, MUSB_RXCSR, csr);
869 /* incomplete, and not short? wait for next IN packet */
870 if ((request->actual < request->length)
871 && (musb_ep->dma->actual_len
872 == musb_ep->packet_sz)) {
873 /* In double buffer case, continue to unload fifo if
874 * there is Rx packet in FIFO.
876 csr = musb_readw(epio, MUSB_RXCSR);
877 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
878 hw_ep->rx_double_buffered)
883 musb_g_giveback(musb_ep, request, 0);
885 * In the giveback function the MUSB lock is
886 * released and acquired after sometime. During
887 * this time period the INDEX register could get
888 * changed by the gadget_queue function especially
889 * on SMP systems. Reselect the INDEX to be sure
890 * we are reading/modifying the right registers
892 musb_ep_select(mbase, epnum);
894 req = next_request(musb_ep);
898 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
899 defined(CONFIG_USB_UX500_DMA)
902 /* Analyze request */
906 /* ------------------------------------------------------------ */
908 static int musb_gadget_enable(struct usb_ep *ep,
909 const struct usb_endpoint_descriptor *desc)
912 struct musb_ep *musb_ep;
913 struct musb_hw_ep *hw_ep;
920 int status = -EINVAL;
925 musb_ep = to_musb_ep(ep);
926 hw_ep = musb_ep->hw_ep;
928 musb = musb_ep->musb;
930 epnum = musb_ep->current_epnum;
932 spin_lock_irqsave(&musb->lock, flags);
938 musb_ep->type = usb_endpoint_type(desc);
940 /* check direction and (later) maxpacket size against endpoint */
941 if (usb_endpoint_num(desc) != epnum)
944 /* REVISIT this rules out high bandwidth periodic transfers */
945 tmp = usb_endpoint_maxp_mult(desc) - 1;
949 if (usb_endpoint_dir_in(desc))
950 ok = musb->hb_iso_tx;
952 ok = musb->hb_iso_rx;
955 musb_dbg(musb, "no support for high bandwidth ISO");
958 musb_ep->hb_mult = tmp;
960 musb_ep->hb_mult = 0;
963 musb_ep->packet_sz = usb_endpoint_maxp(desc);
964 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
966 /* enable the interrupts for the endpoint, set the endpoint
967 * packet size (or fail), set the mode, clear the fifo
969 musb_ep_select(mbase, epnum);
970 if (usb_endpoint_dir_in(desc)) {
972 if (hw_ep->is_shared_fifo)
977 if (tmp > hw_ep->max_packet_sz_tx) {
978 musb_dbg(musb, "packet size beyond hardware FIFO size");
982 musb->intrtxe |= (1 << epnum);
983 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
985 /* REVISIT if can_bulk_split(), use by updating "tmp";
986 * likewise high bandwidth periodic tx
988 /* Set TXMAXP with the FIFO size of the endpoint
989 * to disable double buffering mode.
991 if (can_bulk_split(musb, musb_ep->type))
992 musb_ep->hb_mult = (hw_ep->max_packet_sz_tx /
993 musb_ep->packet_sz) - 1;
994 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
995 | (musb_ep->hb_mult << 11));
997 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
998 if (musb_readw(regs, MUSB_TXCSR)
999 & MUSB_TXCSR_FIFONOTEMPTY)
1000 csr |= MUSB_TXCSR_FLUSHFIFO;
1001 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1002 csr |= MUSB_TXCSR_P_ISO;
1004 /* set twice in case of double buffering */
1005 musb_writew(regs, MUSB_TXCSR, csr);
1006 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1007 musb_writew(regs, MUSB_TXCSR, csr);
1011 if (hw_ep->is_shared_fifo)
1016 if (tmp > hw_ep->max_packet_sz_rx) {
1017 musb_dbg(musb, "packet size beyond hardware FIFO size");
1021 musb->intrrxe |= (1 << epnum);
1022 musb_writew(mbase, MUSB_INTRRXE, musb->intrrxe);
1024 /* REVISIT if can_bulk_combine() use by updating "tmp"
1025 * likewise high bandwidth periodic rx
1027 /* Set RXMAXP with the FIFO size of the endpoint
1028 * to disable double buffering mode.
1030 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1031 | (musb_ep->hb_mult << 11));
1033 /* force shared fifo to OUT-only mode */
1034 if (hw_ep->is_shared_fifo) {
1035 csr = musb_readw(regs, MUSB_TXCSR);
1036 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1037 musb_writew(regs, MUSB_TXCSR, csr);
1040 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1041 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1042 csr |= MUSB_RXCSR_P_ISO;
1043 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1044 csr |= MUSB_RXCSR_DISNYET;
1046 /* set twice in case of double buffering */
1047 musb_writew(regs, MUSB_RXCSR, csr);
1048 musb_writew(regs, MUSB_RXCSR, csr);
1051 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1052 * for some reason you run out of channels here.
1054 if (is_dma_capable() && musb->dma_controller) {
1055 struct dma_controller *c = musb->dma_controller;
1057 musb_ep->dma = c->channel_alloc(c, hw_ep,
1058 (desc->bEndpointAddress & USB_DIR_IN));
1060 musb_ep->dma = NULL;
1062 musb_ep->desc = desc;
1064 musb_ep->wedged = 0;
1067 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1068 musb_driver_name, musb_ep->end_point.name,
1069 musb_ep_xfertype_string(musb_ep->type),
1070 musb_ep->is_in ? "IN" : "OUT",
1071 musb_ep->dma ? "dma, " : "",
1072 musb_ep->packet_sz);
1074 schedule_delayed_work(&musb->irq_work, 0);
1077 spin_unlock_irqrestore(&musb->lock, flags);
1082 * Disable an endpoint flushing all requests queued.
1084 static int musb_gadget_disable(struct usb_ep *ep)
1086 unsigned long flags;
1089 struct musb_ep *musb_ep;
1093 musb_ep = to_musb_ep(ep);
1094 musb = musb_ep->musb;
1095 epnum = musb_ep->current_epnum;
1096 epio = musb->endpoints[epnum].regs;
1098 spin_lock_irqsave(&musb->lock, flags);
1099 musb_ep_select(musb->mregs, epnum);
1101 /* zero the endpoint sizes */
1102 if (musb_ep->is_in) {
1103 musb->intrtxe &= ~(1 << epnum);
1104 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
1105 musb_writew(epio, MUSB_TXMAXP, 0);
1107 musb->intrrxe &= ~(1 << epnum);
1108 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
1109 musb_writew(epio, MUSB_RXMAXP, 0);
1112 /* abort all pending DMA and requests */
1113 nuke(musb_ep, -ESHUTDOWN);
1115 musb_ep->desc = NULL;
1116 musb_ep->end_point.desc = NULL;
1118 schedule_delayed_work(&musb->irq_work, 0);
1120 spin_unlock_irqrestore(&(musb->lock), flags);
1122 musb_dbg(musb, "%s", musb_ep->end_point.name);
1128 * Allocate a request for an endpoint.
1129 * Reused by ep0 code.
1131 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1133 struct musb_ep *musb_ep = to_musb_ep(ep);
1134 struct musb_request *request = NULL;
1136 request = kzalloc(sizeof *request, gfp_flags);
1140 request->request.dma = DMA_ADDR_INVALID;
1141 request->epnum = musb_ep->current_epnum;
1142 request->ep = musb_ep;
1144 trace_musb_req_alloc(request);
1145 return &request->request;
1150 * Reused by ep0 code.
1152 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1154 struct musb_request *request = to_musb_request(req);
1156 trace_musb_req_free(request);
1160 static LIST_HEAD(buffers);
1162 struct free_record {
1163 struct list_head list;
1170 * Context: controller locked, IRQs blocked.
1172 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1174 trace_musb_req_start(req);
1175 musb_ep_select(musb->mregs, req->epnum);
1182 static int musb_ep_restart_resume_work(struct musb *musb, void *data)
1184 struct musb_request *req = data;
1186 musb_ep_restart(musb, req);
1191 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1194 struct musb_ep *musb_ep;
1195 struct musb_request *request;
1198 unsigned long lockflags;
1205 musb_ep = to_musb_ep(ep);
1206 musb = musb_ep->musb;
1208 request = to_musb_request(req);
1209 request->musb = musb;
1211 if (request->ep != musb_ep)
1214 status = pm_runtime_get(musb->controller);
1215 if ((status != -EINPROGRESS) && status < 0) {
1216 dev_err(musb->controller,
1217 "pm runtime get failed in %s\n",
1219 pm_runtime_put_noidle(musb->controller);
1225 trace_musb_req_enq(request);
1227 /* request is mine now... */
1228 request->request.actual = 0;
1229 request->request.status = -EINPROGRESS;
1230 request->epnum = musb_ep->current_epnum;
1231 request->tx = musb_ep->is_in;
1233 map_dma_buffer(request, musb, musb_ep);
1235 spin_lock_irqsave(&musb->lock, lockflags);
1237 /* don't queue if the ep is down */
1238 if (!musb_ep->desc) {
1239 musb_dbg(musb, "req %p queued to %s while ep %s",
1240 req, ep->name, "disabled");
1241 status = -ESHUTDOWN;
1242 unmap_dma_buffer(request, musb);
1246 /* add request to the list */
1247 list_add_tail(&request->list, &musb_ep->req_list);
1249 /* it this is the head of the queue, start i/o ... */
1250 if (!musb_ep->busy && &request->list == musb_ep->req_list.next) {
1251 status = musb_queue_resume_work(musb,
1252 musb_ep_restart_resume_work,
1255 dev_err(musb->controller, "%s resume work: %i\n",
1257 list_del(&request->list);
1262 spin_unlock_irqrestore(&musb->lock, lockflags);
1263 pm_runtime_mark_last_busy(musb->controller);
1264 pm_runtime_put_autosuspend(musb->controller);
1269 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1271 struct musb_ep *musb_ep = to_musb_ep(ep);
1272 struct musb_request *req = to_musb_request(request);
1273 struct musb_request *r;
1274 unsigned long flags;
1276 struct musb *musb = musb_ep->musb;
1278 if (!ep || !request || req->ep != musb_ep)
1281 trace_musb_req_deq(req);
1283 spin_lock_irqsave(&musb->lock, flags);
1285 list_for_each_entry(r, &musb_ep->req_list, list) {
1290 dev_err(musb->controller, "request %p not queued to %s\n",
1296 /* if the hardware doesn't have the request, easy ... */
1297 if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1298 musb_g_giveback(musb_ep, request, -ECONNRESET);
1300 /* ... else abort the dma transfer ... */
1301 else if (is_dma_capable() && musb_ep->dma) {
1302 struct dma_controller *c = musb->dma_controller;
1304 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1305 if (c->channel_abort)
1306 status = c->channel_abort(musb_ep->dma);
1310 musb_g_giveback(musb_ep, request, -ECONNRESET);
1312 /* NOTE: by sticking to easily tested hardware/driver states,
1313 * we leave counting of in-flight packets imprecise.
1315 musb_g_giveback(musb_ep, request, -ECONNRESET);
1319 spin_unlock_irqrestore(&musb->lock, flags);
1324 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1325 * data but will queue requests.
1327 * exported to ep0 code
1329 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1331 struct musb_ep *musb_ep = to_musb_ep(ep);
1332 u8 epnum = musb_ep->current_epnum;
1333 struct musb *musb = musb_ep->musb;
1334 void __iomem *epio = musb->endpoints[epnum].regs;
1335 void __iomem *mbase;
1336 unsigned long flags;
1338 struct musb_request *request;
1343 mbase = musb->mregs;
1345 spin_lock_irqsave(&musb->lock, flags);
1347 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1352 musb_ep_select(mbase, epnum);
1354 request = next_request(musb_ep);
1357 musb_dbg(musb, "request in progress, cannot halt %s",
1362 /* Cannot portably stall with non-empty FIFO */
1363 if (musb_ep->is_in) {
1364 csr = musb_readw(epio, MUSB_TXCSR);
1365 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1366 musb_dbg(musb, "FIFO busy, cannot halt %s",
1373 musb_ep->wedged = 0;
1375 /* set/clear the stall and toggle bits */
1376 musb_dbg(musb, "%s: %s stall", ep->name, value ? "set" : "clear");
1377 if (musb_ep->is_in) {
1378 csr = musb_readw(epio, MUSB_TXCSR);
1379 csr |= MUSB_TXCSR_P_WZC_BITS
1380 | MUSB_TXCSR_CLRDATATOG;
1382 csr |= MUSB_TXCSR_P_SENDSTALL;
1384 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1385 | MUSB_TXCSR_P_SENTSTALL);
1386 csr &= ~MUSB_TXCSR_TXPKTRDY;
1387 musb_writew(epio, MUSB_TXCSR, csr);
1389 csr = musb_readw(epio, MUSB_RXCSR);
1390 csr |= MUSB_RXCSR_P_WZC_BITS
1391 | MUSB_RXCSR_FLUSHFIFO
1392 | MUSB_RXCSR_CLRDATATOG;
1394 csr |= MUSB_RXCSR_P_SENDSTALL;
1396 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1397 | MUSB_RXCSR_P_SENTSTALL);
1398 musb_writew(epio, MUSB_RXCSR, csr);
1401 /* maybe start the first request in the queue */
1402 if (!musb_ep->busy && !value && request) {
1403 musb_dbg(musb, "restarting the request");
1404 musb_ep_restart(musb, request);
1408 spin_unlock_irqrestore(&musb->lock, flags);
1413 * Sets the halt feature with the clear requests ignored
1415 static int musb_gadget_set_wedge(struct usb_ep *ep)
1417 struct musb_ep *musb_ep = to_musb_ep(ep);
1422 musb_ep->wedged = 1;
1424 return usb_ep_set_halt(ep);
1427 static int musb_gadget_fifo_status(struct usb_ep *ep)
1429 struct musb_ep *musb_ep = to_musb_ep(ep);
1430 void __iomem *epio = musb_ep->hw_ep->regs;
1431 int retval = -EINVAL;
1433 if (musb_ep->desc && !musb_ep->is_in) {
1434 struct musb *musb = musb_ep->musb;
1435 int epnum = musb_ep->current_epnum;
1436 void __iomem *mbase = musb->mregs;
1437 unsigned long flags;
1439 spin_lock_irqsave(&musb->lock, flags);
1441 musb_ep_select(mbase, epnum);
1442 /* FIXME return zero unless RXPKTRDY is set */
1443 retval = musb_readw(epio, MUSB_RXCOUNT);
1445 spin_unlock_irqrestore(&musb->lock, flags);
1450 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1452 struct musb_ep *musb_ep = to_musb_ep(ep);
1453 struct musb *musb = musb_ep->musb;
1454 u8 epnum = musb_ep->current_epnum;
1455 void __iomem *epio = musb->endpoints[epnum].regs;
1456 void __iomem *mbase;
1457 unsigned long flags;
1460 mbase = musb->mregs;
1462 spin_lock_irqsave(&musb->lock, flags);
1463 musb_ep_select(mbase, (u8) epnum);
1465 /* disable interrupts */
1466 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe & ~(1 << epnum));
1468 if (musb_ep->is_in) {
1469 csr = musb_readw(epio, MUSB_TXCSR);
1470 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1471 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1473 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1474 * to interrupt current FIFO loading, but not flushing
1475 * the already loaded ones.
1477 csr &= ~MUSB_TXCSR_TXPKTRDY;
1478 musb_writew(epio, MUSB_TXCSR, csr);
1479 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1480 musb_writew(epio, MUSB_TXCSR, csr);
1483 csr = musb_readw(epio, MUSB_RXCSR);
1484 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1485 musb_writew(epio, MUSB_RXCSR, csr);
1486 musb_writew(epio, MUSB_RXCSR, csr);
1489 /* re-enable interrupt */
1490 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1491 spin_unlock_irqrestore(&musb->lock, flags);
1494 static const struct usb_ep_ops musb_ep_ops = {
1495 .enable = musb_gadget_enable,
1496 .disable = musb_gadget_disable,
1497 .alloc_request = musb_alloc_request,
1498 .free_request = musb_free_request,
1499 .queue = musb_gadget_queue,
1500 .dequeue = musb_gadget_dequeue,
1501 .set_halt = musb_gadget_set_halt,
1502 .set_wedge = musb_gadget_set_wedge,
1503 .fifo_status = musb_gadget_fifo_status,
1504 .fifo_flush = musb_gadget_fifo_flush
1507 /* ----------------------------------------------------------------------- */
1509 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1511 struct musb *musb = gadget_to_musb(gadget);
1513 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1516 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1518 struct musb *musb = gadget_to_musb(gadget);
1519 void __iomem *mregs = musb->mregs;
1520 unsigned long flags;
1521 int status = -EINVAL;
1525 spin_lock_irqsave(&musb->lock, flags);
1527 switch (musb->xceiv->otg->state) {
1528 case OTG_STATE_B_PERIPHERAL:
1529 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1530 * that's part of the standard usb 1.1 state machine, and
1531 * doesn't affect OTG transitions.
1533 if (musb->may_wakeup && musb->is_suspended)
1536 case OTG_STATE_B_IDLE:
1537 /* Start SRP ... OTG not required. */
1538 devctl = musb_readb(mregs, MUSB_DEVCTL);
1539 musb_dbg(musb, "Sending SRP: devctl: %02x", devctl);
1540 devctl |= MUSB_DEVCTL_SESSION;
1541 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1542 devctl = musb_readb(mregs, MUSB_DEVCTL);
1544 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1545 devctl = musb_readb(mregs, MUSB_DEVCTL);
1550 while (devctl & MUSB_DEVCTL_SESSION) {
1551 devctl = musb_readb(mregs, MUSB_DEVCTL);
1556 spin_unlock_irqrestore(&musb->lock, flags);
1557 otg_start_srp(musb->xceiv->otg);
1558 spin_lock_irqsave(&musb->lock, flags);
1560 /* Block idling for at least 1s */
1561 musb_platform_try_idle(musb,
1562 jiffies + msecs_to_jiffies(1 * HZ));
1567 musb_dbg(musb, "Unhandled wake: %s",
1568 usb_otg_state_string(musb->xceiv->otg->state));
1574 power = musb_readb(mregs, MUSB_POWER);
1575 power |= MUSB_POWER_RESUME;
1576 musb_writeb(mregs, MUSB_POWER, power);
1577 musb_dbg(musb, "issue wakeup");
1579 /* FIXME do this next chunk in a timer callback, no udelay */
1582 power = musb_readb(mregs, MUSB_POWER);
1583 power &= ~MUSB_POWER_RESUME;
1584 musb_writeb(mregs, MUSB_POWER, power);
1586 spin_unlock_irqrestore(&musb->lock, flags);
1591 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1593 gadget->is_selfpowered = !!is_selfpowered;
1597 static void musb_pullup(struct musb *musb, int is_on)
1601 power = musb_readb(musb->mregs, MUSB_POWER);
1603 power |= MUSB_POWER_SOFTCONN;
1605 power &= ~MUSB_POWER_SOFTCONN;
1607 /* FIXME if on, HdrcStart; if off, HdrcStop */
1609 musb_dbg(musb, "gadget D+ pullup %s",
1610 is_on ? "on" : "off");
1611 musb_writeb(musb->mregs, MUSB_POWER, power);
1615 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1617 musb_dbg(musb, "<= %s =>\n", __func__);
1620 * FIXME iff driver's softconnect flag is set (as it is during probe,
1621 * though that can clear it), just musb_pullup().
1628 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1630 struct musb *musb = gadget_to_musb(gadget);
1632 if (!musb->xceiv->set_power)
1634 return usb_phy_set_power(musb->xceiv, mA);
1637 static void musb_gadget_work(struct work_struct *work)
1640 unsigned long flags;
1642 musb = container_of(work, struct musb, gadget_work.work);
1643 pm_runtime_get_sync(musb->controller);
1644 spin_lock_irqsave(&musb->lock, flags);
1645 musb_pullup(musb, musb->softconnect);
1646 spin_unlock_irqrestore(&musb->lock, flags);
1647 pm_runtime_mark_last_busy(musb->controller);
1648 pm_runtime_put_autosuspend(musb->controller);
1651 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1653 struct musb *musb = gadget_to_musb(gadget);
1654 unsigned long flags;
1658 /* NOTE: this assumes we are sensing vbus; we'd rather
1659 * not pullup unless the B-session is active.
1661 spin_lock_irqsave(&musb->lock, flags);
1662 if (is_on != musb->softconnect) {
1663 musb->softconnect = is_on;
1664 schedule_delayed_work(&musb->gadget_work, 0);
1666 spin_unlock_irqrestore(&musb->lock, flags);
1671 static int musb_gadget_start(struct usb_gadget *g,
1672 struct usb_gadget_driver *driver);
1673 static int musb_gadget_stop(struct usb_gadget *g);
1675 static const struct usb_gadget_ops musb_gadget_operations = {
1676 .get_frame = musb_gadget_get_frame,
1677 .wakeup = musb_gadget_wakeup,
1678 .set_selfpowered = musb_gadget_set_self_powered,
1679 /* .vbus_session = musb_gadget_vbus_session, */
1680 .vbus_draw = musb_gadget_vbus_draw,
1681 .pullup = musb_gadget_pullup,
1682 .udc_start = musb_gadget_start,
1683 .udc_stop = musb_gadget_stop,
1686 /* ----------------------------------------------------------------------- */
1690 /* Only this registration code "knows" the rule (from USB standards)
1691 * about there being only one external upstream port. It assumes
1692 * all peripheral ports are external...
1696 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1698 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1700 memset(ep, 0, sizeof *ep);
1702 ep->current_epnum = epnum;
1707 INIT_LIST_HEAD(&ep->req_list);
1709 sprintf(ep->name, "ep%d%s", epnum,
1710 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1711 is_in ? "in" : "out"));
1712 ep->end_point.name = ep->name;
1713 INIT_LIST_HEAD(&ep->end_point.ep_list);
1715 usb_ep_set_maxpacket_limit(&ep->end_point, 64);
1716 ep->end_point.caps.type_control = true;
1717 ep->end_point.ops = &musb_g_ep0_ops;
1718 musb->g.ep0 = &ep->end_point;
1721 usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_tx);
1723 usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_rx);
1724 ep->end_point.caps.type_iso = true;
1725 ep->end_point.caps.type_bulk = true;
1726 ep->end_point.caps.type_int = true;
1727 ep->end_point.ops = &musb_ep_ops;
1728 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1731 if (!epnum || hw_ep->is_shared_fifo) {
1732 ep->end_point.caps.dir_in = true;
1733 ep->end_point.caps.dir_out = true;
1735 ep->end_point.caps.dir_in = true;
1737 ep->end_point.caps.dir_out = true;
1741 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1742 * to the rest of the driver state.
1744 static inline void musb_g_init_endpoints(struct musb *musb)
1747 struct musb_hw_ep *hw_ep;
1750 /* initialize endpoint list just once */
1751 INIT_LIST_HEAD(&(musb->g.ep_list));
1753 for (epnum = 0, hw_ep = musb->endpoints;
1754 epnum < musb->nr_endpoints;
1756 if (hw_ep->is_shared_fifo /* || !epnum */) {
1757 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1760 if (hw_ep->max_packet_sz_tx) {
1761 init_peripheral_ep(musb, &hw_ep->ep_in,
1765 if (hw_ep->max_packet_sz_rx) {
1766 init_peripheral_ep(musb, &hw_ep->ep_out,
1774 /* called once during driver setup to initialize and link into
1775 * the driver model; memory is zeroed.
1777 int musb_gadget_setup(struct musb *musb)
1781 /* REVISIT minor race: if (erroneously) setting up two
1782 * musb peripherals at the same time, only the bus lock
1786 musb->g.ops = &musb_gadget_operations;
1787 musb->g.max_speed = USB_SPEED_HIGH;
1788 musb->g.speed = USB_SPEED_UNKNOWN;
1790 MUSB_DEV_MODE(musb);
1791 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
1793 /* this "gadget" abstracts/virtualizes the controller */
1794 musb->g.name = musb_driver_name;
1795 /* don't support otg protocols */
1797 INIT_DELAYED_WORK(&musb->gadget_work, musb_gadget_work);
1798 musb_g_init_endpoints(musb);
1800 musb->is_active = 0;
1801 musb_platform_try_idle(musb, 0);
1803 status = usb_add_gadget_udc(musb->controller, &musb->g);
1809 musb->g.dev.parent = NULL;
1810 device_unregister(&musb->g.dev);
1814 void musb_gadget_cleanup(struct musb *musb)
1816 if (musb->port_mode == MUSB_HOST)
1819 cancel_delayed_work_sync(&musb->gadget_work);
1820 usb_del_gadget_udc(&musb->g);
1824 * Register the gadget driver. Used by gadget drivers when
1825 * registering themselves with the controller.
1827 * -EINVAL something went wrong (not driver)
1828 * -EBUSY another gadget is already using the controller
1829 * -ENOMEM no memory to perform the operation
1831 * @param driver the gadget driver
1832 * @return <0 if error, 0 if everything is fine
1834 static int musb_gadget_start(struct usb_gadget *g,
1835 struct usb_gadget_driver *driver)
1837 struct musb *musb = gadget_to_musb(g);
1838 struct usb_otg *otg = musb->xceiv->otg;
1839 unsigned long flags;
1842 if (driver->max_speed < USB_SPEED_HIGH) {
1847 pm_runtime_get_sync(musb->controller);
1849 musb->softconnect = 0;
1850 musb->gadget_driver = driver;
1852 spin_lock_irqsave(&musb->lock, flags);
1853 musb->is_active = 1;
1855 otg_set_peripheral(otg, &musb->g);
1856 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
1857 spin_unlock_irqrestore(&musb->lock, flags);
1861 /* REVISIT: funcall to other code, which also
1862 * handles power budgeting ... this way also
1863 * ensures HdrcStart is indirectly called.
1865 if (musb->xceiv->last_event == USB_EVENT_ID)
1866 musb_platform_set_vbus(musb, 1);
1868 pm_runtime_mark_last_busy(musb->controller);
1869 pm_runtime_put_autosuspend(musb->controller);
1878 * Unregister the gadget driver. Used by gadget drivers when
1879 * unregistering themselves from the controller.
1881 * @param driver the gadget driver to unregister
1883 static int musb_gadget_stop(struct usb_gadget *g)
1885 struct musb *musb = gadget_to_musb(g);
1886 unsigned long flags;
1888 pm_runtime_get_sync(musb->controller);
1891 * REVISIT always use otg_set_peripheral() here too;
1892 * this needs to shut down the OTG engine.
1895 spin_lock_irqsave(&musb->lock, flags);
1897 musb_hnp_stop(musb);
1899 (void) musb_gadget_vbus_draw(&musb->g, 0);
1901 musb->xceiv->otg->state = OTG_STATE_UNDEFINED;
1903 otg_set_peripheral(musb->xceiv->otg, NULL);
1905 musb->is_active = 0;
1906 musb->gadget_driver = NULL;
1907 musb_platform_try_idle(musb, 0);
1908 spin_unlock_irqrestore(&musb->lock, flags);
1911 * FIXME we need to be able to register another
1912 * gadget driver here and have everything work;
1913 * that currently misbehaves.
1916 /* Force check of devctl register for PM runtime */
1917 schedule_delayed_work(&musb->irq_work, 0);
1919 pm_runtime_mark_last_busy(musb->controller);
1920 pm_runtime_put_autosuspend(musb->controller);
1925 /* ----------------------------------------------------------------------- */
1927 /* lifecycle operations called through plat_uds.c */
1929 void musb_g_resume(struct musb *musb)
1931 musb->is_suspended = 0;
1932 switch (musb->xceiv->otg->state) {
1933 case OTG_STATE_B_IDLE:
1935 case OTG_STATE_B_WAIT_ACON:
1936 case OTG_STATE_B_PERIPHERAL:
1937 musb->is_active = 1;
1938 if (musb->gadget_driver && musb->gadget_driver->resume) {
1939 spin_unlock(&musb->lock);
1940 musb->gadget_driver->resume(&musb->g);
1941 spin_lock(&musb->lock);
1945 WARNING("unhandled RESUME transition (%s)\n",
1946 usb_otg_state_string(musb->xceiv->otg->state));
1950 /* called when SOF packets stop for 3+ msec */
1951 void musb_g_suspend(struct musb *musb)
1955 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1956 musb_dbg(musb, "musb_g_suspend: devctl %02x", devctl);
1958 switch (musb->xceiv->otg->state) {
1959 case OTG_STATE_B_IDLE:
1960 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1961 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
1963 case OTG_STATE_B_PERIPHERAL:
1964 musb->is_suspended = 1;
1965 if (musb->gadget_driver && musb->gadget_driver->suspend) {
1966 spin_unlock(&musb->lock);
1967 musb->gadget_driver->suspend(&musb->g);
1968 spin_lock(&musb->lock);
1972 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
1973 * A_PERIPHERAL may need care too
1975 WARNING("unhandled SUSPEND transition (%s)",
1976 usb_otg_state_string(musb->xceiv->otg->state));
1980 /* Called during SRP */
1981 void musb_g_wakeup(struct musb *musb)
1983 musb_gadget_wakeup(&musb->g);
1986 /* called when VBUS drops below session threshold, and in other cases */
1987 void musb_g_disconnect(struct musb *musb)
1989 void __iomem *mregs = musb->mregs;
1990 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
1992 musb_dbg(musb, "musb_g_disconnect: devctl %02x", devctl);
1995 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
1997 /* don't draw vbus until new b-default session */
1998 (void) musb_gadget_vbus_draw(&musb->g, 0);
2000 musb->g.speed = USB_SPEED_UNKNOWN;
2001 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2002 spin_unlock(&musb->lock);
2003 musb->gadget_driver->disconnect(&musb->g);
2004 spin_lock(&musb->lock);
2007 switch (musb->xceiv->otg->state) {
2009 musb_dbg(musb, "Unhandled disconnect %s, setting a_idle",
2010 usb_otg_state_string(musb->xceiv->otg->state));
2011 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2012 MUSB_HST_MODE(musb);
2014 case OTG_STATE_A_PERIPHERAL:
2015 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
2016 MUSB_HST_MODE(musb);
2018 case OTG_STATE_B_WAIT_ACON:
2019 case OTG_STATE_B_HOST:
2020 case OTG_STATE_B_PERIPHERAL:
2021 case OTG_STATE_B_IDLE:
2022 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2024 case OTG_STATE_B_SRP_INIT:
2028 musb->is_active = 0;
2031 void musb_g_reset(struct musb *musb)
2032 __releases(musb->lock)
2033 __acquires(musb->lock)
2035 void __iomem *mbase = musb->mregs;
2036 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2039 musb_dbg(musb, "<== %s driver '%s'",
2040 (devctl & MUSB_DEVCTL_BDEVICE)
2041 ? "B-Device" : "A-Device",
2043 ? musb->gadget_driver->driver.name
2047 /* report reset, if we didn't already (flushing EP state) */
2048 if (musb->gadget_driver && musb->g.speed != USB_SPEED_UNKNOWN) {
2049 spin_unlock(&musb->lock);
2050 usb_gadget_udc_reset(&musb->g, musb->gadget_driver);
2051 spin_lock(&musb->lock);
2055 else if (devctl & MUSB_DEVCTL_HR)
2056 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2059 /* what speed did we negotiate? */
2060 power = musb_readb(mbase, MUSB_POWER);
2061 musb->g.speed = (power & MUSB_POWER_HSMODE)
2062 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2064 /* start in USB_STATE_DEFAULT */
2065 musb->is_active = 1;
2066 musb->is_suspended = 0;
2067 MUSB_DEV_MODE(musb);
2069 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2071 musb->may_wakeup = 0;
2072 musb->g.b_hnp_enable = 0;
2073 musb->g.a_alt_hnp_support = 0;
2074 musb->g.a_hnp_support = 0;
2075 musb->g.quirk_zlp_not_supp = 1;
2077 /* Normal reset, as B-Device;
2078 * or else after HNP, as A-Device
2080 if (!musb->g.is_otg) {
2081 /* USB device controllers that are not OTG compatible
2082 * may not have DEVCTL register in silicon.
2083 * In that case, do not rely on devctl for setting
2086 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2087 musb->g.is_a_peripheral = 0;
2088 } else if (devctl & MUSB_DEVCTL_BDEVICE) {
2089 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
2090 musb->g.is_a_peripheral = 0;
2092 musb->xceiv->otg->state = OTG_STATE_A_PERIPHERAL;
2093 musb->g.is_a_peripheral = 1;
2096 /* start with default limits on VBUS power draw */
2097 (void) musb_gadget_vbus_draw(&musb->g, 8);