2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/list.h>
97 #include <linux/kobject.h>
98 #include <linux/prefetch.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
102 #include <linux/usb.h>
104 #include "musb_core.h"
106 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
109 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
110 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
112 #define MUSB_VERSION "6.0"
114 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
116 #define MUSB_DRIVER_NAME "musb-hdrc"
117 const char musb_driver_name[] = MUSB_DRIVER_NAME;
119 MODULE_DESCRIPTION(DRIVER_INFO);
120 MODULE_AUTHOR(DRIVER_AUTHOR);
121 MODULE_LICENSE("GPL");
122 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
125 /*-------------------------------------------------------------------------*/
127 static inline struct musb *dev_to_musb(struct device *dev)
129 return dev_get_drvdata(dev);
132 /*-------------------------------------------------------------------------*/
134 #ifndef CONFIG_BLACKFIN
135 static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
137 void __iomem *addr = phy->io_priv;
143 pm_runtime_get_sync(phy->io_dev);
145 /* Make sure the transceiver is not in low power mode */
146 power = musb_readb(addr, MUSB_POWER);
147 power &= ~MUSB_POWER_SUSPENDM;
148 musb_writeb(addr, MUSB_POWER, power);
150 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
151 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
154 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
155 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
156 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
158 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
159 & MUSB_ULPI_REG_CMPLT)) {
167 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
168 r &= ~MUSB_ULPI_REG_CMPLT;
169 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
171 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
174 pm_runtime_put(phy->io_dev);
179 static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
181 void __iomem *addr = phy->io_priv;
187 pm_runtime_get_sync(phy->io_dev);
189 /* Make sure the transceiver is not in low power mode */
190 power = musb_readb(addr, MUSB_POWER);
191 power &= ~MUSB_POWER_SUSPENDM;
192 musb_writeb(addr, MUSB_POWER, power);
194 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
195 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
196 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
198 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
199 & MUSB_ULPI_REG_CMPLT)) {
207 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
208 r &= ~MUSB_ULPI_REG_CMPLT;
209 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
212 pm_runtime_put(phy->io_dev);
217 #define musb_ulpi_read NULL
218 #define musb_ulpi_write NULL
221 static struct usb_phy_io_ops musb_ulpi_access = {
222 .read = musb_ulpi_read,
223 .write = musb_ulpi_write,
226 /*-------------------------------------------------------------------------*/
228 static u32 musb_default_fifo_offset(u8 epnum)
230 return 0x20 + (epnum * 4);
233 /* "flat" mapping: each endpoint has its own i/o address */
234 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
238 static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
240 return 0x100 + (0x10 * epnum) + offset;
243 /* "indexed" mapping: INDEX register controls register bank select */
244 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
246 musb_writeb(mbase, MUSB_INDEX, epnum);
249 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
251 return 0x10 + offset;
254 static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
256 return 0x80 + (0x08 * epnum) + offset;
259 static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
261 return __raw_readb(addr + offset);
264 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
266 __raw_writeb(data, addr + offset);
269 static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
271 return __raw_readw(addr + offset);
274 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
276 __raw_writew(data, addr + offset);
279 static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
281 return __raw_readl(addr + offset);
284 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
286 __raw_writel(data, addr + offset);
290 * Load an endpoint's FIFO
292 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
295 struct musb *musb = hw_ep->musb;
296 void __iomem *fifo = hw_ep->fifo;
298 if (unlikely(len == 0))
303 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
304 'T', hw_ep->epnum, fifo, len, src);
306 /* we can't assume unaligned reads work */
307 if (likely((0x01 & (unsigned long) src) == 0)) {
310 /* best case is 32bit-aligned source address */
311 if ((0x02 & (unsigned long) src) == 0) {
313 iowrite32_rep(fifo, src + index, len >> 2);
314 index += len & ~0x03;
317 __raw_writew(*(u16 *)&src[index], fifo);
322 iowrite16_rep(fifo, src + index, len >> 1);
323 index += len & ~0x01;
327 __raw_writeb(src[index], fifo);
330 iowrite8_rep(fifo, src, len);
335 * Unload an endpoint's FIFO
337 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
339 struct musb *musb = hw_ep->musb;
340 void __iomem *fifo = hw_ep->fifo;
342 if (unlikely(len == 0))
345 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
346 'R', hw_ep->epnum, fifo, len, dst);
348 /* we can't assume unaligned writes work */
349 if (likely((0x01 & (unsigned long) dst) == 0)) {
352 /* best case is 32bit-aligned destination address */
353 if ((0x02 & (unsigned long) dst) == 0) {
355 ioread32_rep(fifo, dst, len >> 2);
359 *(u16 *)&dst[index] = __raw_readw(fifo);
364 ioread16_rep(fifo, dst, len >> 1);
369 dst[index] = __raw_readb(fifo);
372 ioread8_rep(fifo, dst, len);
377 * Old style IO functions
379 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
380 EXPORT_SYMBOL_GPL(musb_readb);
382 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
383 EXPORT_SYMBOL_GPL(musb_writeb);
385 u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
386 EXPORT_SYMBOL_GPL(musb_readw);
388 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
389 EXPORT_SYMBOL_GPL(musb_writew);
391 u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
392 EXPORT_SYMBOL_GPL(musb_readl);
394 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
395 EXPORT_SYMBOL_GPL(musb_writel);
397 #ifndef CONFIG_MUSB_PIO_ONLY
398 struct dma_controller *
399 (*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
400 EXPORT_SYMBOL(musb_dma_controller_create);
402 void (*musb_dma_controller_destroy)(struct dma_controller *c);
403 EXPORT_SYMBOL(musb_dma_controller_destroy);
407 * New style IO functions
409 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
411 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
414 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
416 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
419 /*-------------------------------------------------------------------------*/
421 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
422 static const u8 musb_test_packet[53] = {
423 /* implicit SYNC then DATA0 to start */
426 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
428 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
430 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
431 /* JJJJJJJKKKKKKK x8 */
432 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
434 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
435 /* JKKKKKKK x10, JK */
436 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
438 /* implicit CRC16 then EOP to end */
441 void musb_load_testpacket(struct musb *musb)
443 void __iomem *regs = musb->endpoints[0].regs;
445 musb_ep_select(musb->mregs, 0);
446 musb_write_fifo(musb->control_ep,
447 sizeof(musb_test_packet), musb_test_packet);
448 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
451 /*-------------------------------------------------------------------------*/
454 * Handles OTG hnp timeouts, such as b_ase0_brst
456 static void musb_otg_timer_func(unsigned long data)
458 struct musb *musb = (struct musb *)data;
461 spin_lock_irqsave(&musb->lock, flags);
462 switch (musb->xceiv->otg->state) {
463 case OTG_STATE_B_WAIT_ACON:
464 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
465 musb_g_disconnect(musb);
466 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
469 case OTG_STATE_A_SUSPEND:
470 case OTG_STATE_A_WAIT_BCON:
471 dev_dbg(musb->controller, "HNP: %s timeout\n",
472 usb_otg_state_string(musb->xceiv->otg->state));
473 musb_platform_set_vbus(musb, 0);
474 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
477 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
478 usb_otg_state_string(musb->xceiv->otg->state));
480 spin_unlock_irqrestore(&musb->lock, flags);
484 * Stops the HNP transition. Caller must take care of locking.
486 void musb_hnp_stop(struct musb *musb)
488 struct usb_hcd *hcd = musb->hcd;
489 void __iomem *mbase = musb->mregs;
492 dev_dbg(musb->controller, "HNP: stop from %s\n",
493 usb_otg_state_string(musb->xceiv->otg->state));
495 switch (musb->xceiv->otg->state) {
496 case OTG_STATE_A_PERIPHERAL:
497 musb_g_disconnect(musb);
498 dev_dbg(musb->controller, "HNP: back to %s\n",
499 usb_otg_state_string(musb->xceiv->otg->state));
501 case OTG_STATE_B_HOST:
502 dev_dbg(musb->controller, "HNP: Disabling HR\n");
504 hcd->self.is_b_host = 0;
505 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
507 reg = musb_readb(mbase, MUSB_POWER);
508 reg |= MUSB_POWER_SUSPENDM;
509 musb_writeb(mbase, MUSB_POWER, reg);
510 /* REVISIT: Start SESSION_REQUEST here? */
513 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
514 usb_otg_state_string(musb->xceiv->otg->state));
518 * When returning to A state after HNP, avoid hub_port_rebounce(),
519 * which cause occasional OPT A "Did not receive reset after connect"
522 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
525 static void musb_recover_from_babble(struct musb *musb);
528 * Interrupt Service Routine to record USB "global" interrupts.
529 * Since these do not happen often and signify things of
530 * paramount importance, it seems OK to check them individually;
531 * the order of the tests is specified in the manual
533 * @param musb instance pointer
534 * @param int_usb register contents
539 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
542 irqreturn_t handled = IRQ_NONE;
544 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
547 /* in host mode, the peripheral may issue remote wakeup.
548 * in peripheral mode, the host may resume the link.
549 * spurious RESUME irqs happen too, paired with SUSPEND.
551 if (int_usb & MUSB_INTR_RESUME) {
552 handled = IRQ_HANDLED;
553 dev_dbg(musb->controller, "RESUME (%s)\n",
554 usb_otg_state_string(musb->xceiv->otg->state));
556 if (devctl & MUSB_DEVCTL_HM) {
557 switch (musb->xceiv->otg->state) {
558 case OTG_STATE_A_SUSPEND:
559 /* remote wakeup? later, GetPortStatus
560 * will stop RESUME signaling
563 musb->port1_status |=
564 (USB_PORT_STAT_C_SUSPEND << 16)
565 | MUSB_PORT_STAT_RESUME;
566 musb->rh_timer = jiffies
567 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
568 musb->need_finish_resume = 1;
570 musb->xceiv->otg->state = OTG_STATE_A_HOST;
572 musb_host_resume_root_hub(musb);
574 case OTG_STATE_B_WAIT_ACON:
575 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
580 WARNING("bogus %s RESUME (%s)\n",
582 usb_otg_state_string(musb->xceiv->otg->state));
585 switch (musb->xceiv->otg->state) {
586 case OTG_STATE_A_SUSPEND:
587 /* possibly DISCONNECT is upcoming */
588 musb->xceiv->otg->state = OTG_STATE_A_HOST;
589 musb_host_resume_root_hub(musb);
591 case OTG_STATE_B_WAIT_ACON:
592 case OTG_STATE_B_PERIPHERAL:
593 /* disconnect while suspended? we may
594 * not get a disconnect irq...
596 if ((devctl & MUSB_DEVCTL_VBUS)
597 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
599 musb->int_usb |= MUSB_INTR_DISCONNECT;
600 musb->int_usb &= ~MUSB_INTR_SUSPEND;
605 case OTG_STATE_B_IDLE:
606 musb->int_usb &= ~MUSB_INTR_SUSPEND;
609 WARNING("bogus %s RESUME (%s)\n",
611 usb_otg_state_string(musb->xceiv->otg->state));
616 /* see manual for the order of the tests */
617 if (int_usb & MUSB_INTR_SESSREQ) {
618 void __iomem *mbase = musb->mregs;
620 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
621 && (devctl & MUSB_DEVCTL_BDEVICE)) {
622 dev_dbg(musb->controller, "SessReq while on B state\n");
626 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
627 usb_otg_state_string(musb->xceiv->otg->state));
629 /* IRQ arrives from ID pin sense or (later, if VBUS power
630 * is removed) SRP. responses are time critical:
631 * - turn on VBUS (with silicon-specific mechanism)
632 * - go through A_WAIT_VRISE
633 * - ... to A_WAIT_BCON.
634 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
636 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
637 musb->ep0_stage = MUSB_EP0_START;
638 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
640 musb_platform_set_vbus(musb, 1);
642 handled = IRQ_HANDLED;
645 if (int_usb & MUSB_INTR_VBUSERROR) {
648 /* During connection as an A-Device, we may see a short
649 * current spikes causing voltage drop, because of cable
650 * and peripheral capacitance combined with vbus draw.
651 * (So: less common with truly self-powered devices, where
652 * vbus doesn't act like a power supply.)
654 * Such spikes are short; usually less than ~500 usec, max
655 * of ~2 msec. That is, they're not sustained overcurrent
656 * errors, though they're reported using VBUSERROR irqs.
658 * Workarounds: (a) hardware: use self powered devices.
659 * (b) software: ignore non-repeated VBUS errors.
661 * REVISIT: do delays from lots of DEBUG_KERNEL checks
662 * make trouble here, keeping VBUS < 4.4V ?
664 switch (musb->xceiv->otg->state) {
665 case OTG_STATE_A_HOST:
666 /* recovery is dicey once we've gotten past the
667 * initial stages of enumeration, but if VBUS
668 * stayed ok at the other end of the link, and
669 * another reset is due (at least for high speed,
670 * to redo the chirp etc), it might work OK...
672 case OTG_STATE_A_WAIT_BCON:
673 case OTG_STATE_A_WAIT_VRISE:
674 if (musb->vbuserr_retry) {
675 void __iomem *mbase = musb->mregs;
677 musb->vbuserr_retry--;
679 devctl |= MUSB_DEVCTL_SESSION;
680 musb_writeb(mbase, MUSB_DEVCTL, devctl);
682 musb->port1_status |=
683 USB_PORT_STAT_OVERCURRENT
684 | (USB_PORT_STAT_C_OVERCURRENT << 16);
691 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
692 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
693 usb_otg_state_string(musb->xceiv->otg->state),
696 switch (devctl & MUSB_DEVCTL_VBUS) {
697 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
698 s = "<SessEnd"; break;
699 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
700 s = "<AValid"; break;
701 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
702 s = "<VBusValid"; break;
703 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
707 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
710 /* go through A_WAIT_VFALL then start a new session */
712 musb_platform_set_vbus(musb, 0);
713 handled = IRQ_HANDLED;
716 if (int_usb & MUSB_INTR_SUSPEND) {
717 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
718 usb_otg_state_string(musb->xceiv->otg->state), devctl);
719 handled = IRQ_HANDLED;
721 switch (musb->xceiv->otg->state) {
722 case OTG_STATE_A_PERIPHERAL:
723 /* We also come here if the cable is removed, since
724 * this silicon doesn't report ID-no-longer-grounded.
726 * We depend on T(a_wait_bcon) to shut us down, and
727 * hope users don't do anything dicey during this
728 * undesired detour through A_WAIT_BCON.
731 musb_host_resume_root_hub(musb);
732 musb_root_disconnect(musb);
733 musb_platform_try_idle(musb, jiffies
734 + msecs_to_jiffies(musb->a_wait_bcon
735 ? : OTG_TIME_A_WAIT_BCON));
738 case OTG_STATE_B_IDLE:
739 if (!musb->is_active)
741 case OTG_STATE_B_PERIPHERAL:
742 musb_g_suspend(musb);
743 musb->is_active = musb->g.b_hnp_enable;
744 if (musb->is_active) {
745 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
746 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
747 mod_timer(&musb->otg_timer, jiffies
749 OTG_TIME_B_ASE0_BRST));
752 case OTG_STATE_A_WAIT_BCON:
753 if (musb->a_wait_bcon != 0)
754 musb_platform_try_idle(musb, jiffies
755 + msecs_to_jiffies(musb->a_wait_bcon));
757 case OTG_STATE_A_HOST:
758 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
759 musb->is_active = musb->hcd->self.b_hnp_enable;
761 case OTG_STATE_B_HOST:
762 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
763 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
766 /* "should not happen" */
772 if (int_usb & MUSB_INTR_CONNECT) {
773 struct usb_hcd *hcd = musb->hcd;
775 handled = IRQ_HANDLED;
778 musb->ep0_stage = MUSB_EP0_START;
780 musb->intrtxe = musb->epmask;
781 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
782 musb->intrrxe = musb->epmask & 0xfffe;
783 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
784 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
785 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
786 |USB_PORT_STAT_HIGH_SPEED
787 |USB_PORT_STAT_ENABLE
789 musb->port1_status |= USB_PORT_STAT_CONNECTION
790 |(USB_PORT_STAT_C_CONNECTION << 16);
792 /* high vs full speed is just a guess until after reset */
793 if (devctl & MUSB_DEVCTL_LSDEV)
794 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
796 /* indicate new connection to OTG machine */
797 switch (musb->xceiv->otg->state) {
798 case OTG_STATE_B_PERIPHERAL:
799 if (int_usb & MUSB_INTR_SUSPEND) {
800 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
801 int_usb &= ~MUSB_INTR_SUSPEND;
804 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
806 case OTG_STATE_B_WAIT_ACON:
807 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
809 musb->xceiv->otg->state = OTG_STATE_B_HOST;
811 musb->hcd->self.is_b_host = 1;
812 del_timer(&musb->otg_timer);
815 if ((devctl & MUSB_DEVCTL_VBUS)
816 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
817 musb->xceiv->otg->state = OTG_STATE_A_HOST;
819 hcd->self.is_b_host = 0;
824 musb_host_poke_root_hub(musb);
826 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
827 usb_otg_state_string(musb->xceiv->otg->state), devctl);
830 if (int_usb & MUSB_INTR_DISCONNECT) {
831 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
832 usb_otg_state_string(musb->xceiv->otg->state),
833 MUSB_MODE(musb), devctl);
834 handled = IRQ_HANDLED;
836 switch (musb->xceiv->otg->state) {
837 case OTG_STATE_A_HOST:
838 case OTG_STATE_A_SUSPEND:
839 musb_host_resume_root_hub(musb);
840 musb_root_disconnect(musb);
841 if (musb->a_wait_bcon != 0)
842 musb_platform_try_idle(musb, jiffies
843 + msecs_to_jiffies(musb->a_wait_bcon));
845 case OTG_STATE_B_HOST:
846 /* REVISIT this behaves for "real disconnect"
847 * cases; make sure the other transitions from
848 * from B_HOST act right too. The B_HOST code
849 * in hnp_stop() is currently not used...
851 musb_root_disconnect(musb);
853 musb->hcd->self.is_b_host = 0;
854 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
856 musb_g_disconnect(musb);
858 case OTG_STATE_A_PERIPHERAL:
860 musb_root_disconnect(musb);
862 case OTG_STATE_B_WAIT_ACON:
864 case OTG_STATE_B_PERIPHERAL:
865 case OTG_STATE_B_IDLE:
866 musb_g_disconnect(musb);
869 WARNING("unhandled DISCONNECT transition (%s)\n",
870 usb_otg_state_string(musb->xceiv->otg->state));
875 /* mentor saves a bit: bus reset and babble share the same irq.
876 * only host sees babble; only peripheral sees bus reset.
878 if (int_usb & MUSB_INTR_RESET) {
879 handled = IRQ_HANDLED;
880 if (is_host_active(musb)) {
882 * When BABBLE happens what we can depends on which
883 * platform MUSB is running, because some platforms
884 * implemented proprietary means for 'recovering' from
885 * Babble conditions. One such platform is AM335x. In
886 * most cases, however, the only thing we can do is
889 dev_err(musb->controller, "Babble\n");
890 musb_recover_from_babble(musb);
892 dev_dbg(musb->controller, "BUS RESET as %s\n",
893 usb_otg_state_string(musb->xceiv->otg->state));
894 switch (musb->xceiv->otg->state) {
895 case OTG_STATE_A_SUSPEND:
898 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
899 /* never use invalid T(a_wait_bcon) */
900 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
901 usb_otg_state_string(musb->xceiv->otg->state),
903 mod_timer(&musb->otg_timer, jiffies
904 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
906 case OTG_STATE_A_PERIPHERAL:
907 del_timer(&musb->otg_timer);
910 case OTG_STATE_B_WAIT_ACON:
911 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
912 usb_otg_state_string(musb->xceiv->otg->state));
913 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
916 case OTG_STATE_B_IDLE:
917 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
919 case OTG_STATE_B_PERIPHERAL:
923 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
924 usb_otg_state_string(musb->xceiv->otg->state));
930 /* REVISIT ... this would be for multiplexing periodic endpoints, or
931 * supporting transfer phasing to prevent exceeding ISO bandwidth
932 * limits of a given frame or microframe.
934 * It's not needed for peripheral side, which dedicates endpoints;
935 * though it _might_ use SOF irqs for other purposes.
937 * And it's not currently needed for host side, which also dedicates
938 * endpoints, relies on TX/RX interval registers, and isn't claimed
939 * to support ISO transfers yet.
941 if (int_usb & MUSB_INTR_SOF) {
942 void __iomem *mbase = musb->mregs;
943 struct musb_hw_ep *ep;
947 dev_dbg(musb->controller, "START_OF_FRAME\n");
948 handled = IRQ_HANDLED;
950 /* start any periodic Tx transfers waiting for current frame */
951 frame = musb_readw(mbase, MUSB_FRAME);
952 ep = musb->endpoints;
953 for (epnum = 1; (epnum < musb->nr_endpoints)
954 && (musb->epmask >= (1 << epnum));
957 * FIXME handle framecounter wraps (12 bits)
958 * eliminate duplicated StartUrb logic
960 if (ep->dwWaitFrame >= frame) {
962 pr_debug("SOF --> periodic TX%s on %d\n",
963 ep->tx_channel ? " DMA" : "",
966 musb_h_tx_start(musb, epnum);
968 cppi_hostdma_start(musb, epnum);
970 } /* end of for loop */
974 schedule_work(&musb->irq_work);
979 /*-------------------------------------------------------------------------*/
981 static void musb_disable_interrupts(struct musb *musb)
983 void __iomem *mbase = musb->mregs;
986 /* disable interrupts */
987 musb_writeb(mbase, MUSB_INTRUSBE, 0);
989 musb_writew(mbase, MUSB_INTRTXE, 0);
991 musb_writew(mbase, MUSB_INTRRXE, 0);
993 /* flush pending interrupts */
994 temp = musb_readb(mbase, MUSB_INTRUSB);
995 temp = musb_readw(mbase, MUSB_INTRTX);
996 temp = musb_readw(mbase, MUSB_INTRRX);
999 static void musb_enable_interrupts(struct musb *musb)
1001 void __iomem *regs = musb->mregs;
1003 /* Set INT enable registers, enable interrupts */
1004 musb->intrtxe = musb->epmask;
1005 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1006 musb->intrrxe = musb->epmask & 0xfffe;
1007 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1008 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1012 static void musb_generic_disable(struct musb *musb)
1014 void __iomem *mbase = musb->mregs;
1016 musb_disable_interrupts(musb);
1019 musb_writeb(mbase, MUSB_DEVCTL, 0);
1023 * Program the HDRC to start (enable interrupts, dma, etc.).
1025 void musb_start(struct musb *musb)
1027 void __iomem *regs = musb->mregs;
1028 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1031 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1033 musb_enable_interrupts(musb);
1034 musb_writeb(regs, MUSB_TESTMODE, 0);
1036 power = MUSB_POWER_ISOUPDATE;
1038 * treating UNKNOWN as unspecified maximum speed, in which case
1039 * we will default to high-speed.
1041 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1042 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1043 power |= MUSB_POWER_HSENAB;
1044 musb_writeb(regs, MUSB_POWER, power);
1046 musb->is_active = 0;
1047 devctl = musb_readb(regs, MUSB_DEVCTL);
1048 devctl &= ~MUSB_DEVCTL_SESSION;
1050 /* session started after:
1051 * (a) ID-grounded irq, host mode;
1052 * (b) vbus present/connect IRQ, peripheral mode;
1053 * (c) peripheral initiates, using SRP
1055 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1056 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
1057 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1058 musb->is_active = 1;
1060 devctl |= MUSB_DEVCTL_SESSION;
1063 musb_platform_enable(musb);
1064 musb_writeb(regs, MUSB_DEVCTL, devctl);
1068 * Make the HDRC stop (disable interrupts, etc.);
1069 * reversible by musb_start
1070 * called on gadget driver unregister
1071 * with controller locked, irqs blocked
1072 * acts as a NOP unless some role activated the hardware
1074 void musb_stop(struct musb *musb)
1076 /* stop IRQs, timers, ... */
1077 musb_platform_disable(musb);
1078 musb_generic_disable(musb);
1079 dev_dbg(musb->controller, "HDRC disabled\n");
1082 * - mark host and/or peripheral drivers unusable/inactive
1083 * - disable DMA (and enable it in HdrcStart)
1084 * - make sure we can musb_start() after musb_stop(); with
1085 * OTG mode, gadget driver module rmmod/modprobe cycles that
1088 musb_platform_try_idle(musb, 0);
1091 static void musb_shutdown(struct platform_device *pdev)
1093 struct musb *musb = dev_to_musb(&pdev->dev);
1094 unsigned long flags;
1096 pm_runtime_get_sync(musb->controller);
1098 musb_host_cleanup(musb);
1099 musb_gadget_cleanup(musb);
1101 spin_lock_irqsave(&musb->lock, flags);
1102 musb_platform_disable(musb);
1103 musb_generic_disable(musb);
1104 spin_unlock_irqrestore(&musb->lock, flags);
1106 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1107 musb_platform_exit(musb);
1109 pm_runtime_put(musb->controller);
1110 /* FIXME power down */
1114 /*-------------------------------------------------------------------------*/
1117 * The silicon either has hard-wired endpoint configurations, or else
1118 * "dynamic fifo" sizing. The driver has support for both, though at this
1119 * writing only the dynamic sizing is very well tested. Since we switched
1120 * away from compile-time hardware parameters, we can no longer rely on
1121 * dead code elimination to leave only the relevant one in the object file.
1123 * We don't currently use dynamic fifo setup capability to do anything
1124 * more than selecting one of a bunch of predefined configurations.
1126 static ushort fifo_mode;
1128 /* "modprobe ... fifo_mode=1" etc */
1129 module_param(fifo_mode, ushort, 0);
1130 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1133 * tables defining fifo_mode values. define more if you like.
1134 * for host side, make sure both halves of ep1 are set up.
1137 /* mode 0 - fits in 2KB */
1138 static struct musb_fifo_cfg mode_0_cfg[] = {
1139 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1140 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1141 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1142 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1143 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1146 /* mode 1 - fits in 4KB */
1147 static struct musb_fifo_cfg mode_1_cfg[] = {
1148 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1149 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1150 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1151 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1152 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1155 /* mode 2 - fits in 4KB */
1156 static struct musb_fifo_cfg mode_2_cfg[] = {
1157 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1158 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1159 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1160 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1161 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1162 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1165 /* mode 3 - fits in 4KB */
1166 static struct musb_fifo_cfg mode_3_cfg[] = {
1167 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1168 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1169 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1170 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1171 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1172 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1175 /* mode 4 - fits in 16KB */
1176 static struct musb_fifo_cfg mode_4_cfg[] = {
1177 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1178 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1179 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1180 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1181 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1182 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1183 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1184 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1185 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1186 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1187 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1188 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1189 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1190 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1191 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1192 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1193 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1194 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1195 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1196 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1197 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1198 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1199 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1200 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1201 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1202 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1203 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1206 /* mode 5 - fits in 8KB */
1207 static struct musb_fifo_cfg mode_5_cfg[] = {
1208 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1209 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1210 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1211 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1212 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1213 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1214 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1215 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1216 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1217 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1218 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1219 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1220 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1221 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1222 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1223 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1224 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1225 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1226 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1227 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1228 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1229 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1230 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1231 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1232 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1233 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1234 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1238 * configure a fifo; for non-shared endpoints, this may be called
1239 * once for a tx fifo and once for an rx fifo.
1241 * returns negative errno or offset for next fifo.
1244 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1245 const struct musb_fifo_cfg *cfg, u16 offset)
1247 void __iomem *mbase = musb->mregs;
1249 u16 maxpacket = cfg->maxpacket;
1250 u16 c_off = offset >> 3;
1253 /* expect hw_ep has already been zero-initialized */
1255 size = ffs(max(maxpacket, (u16) 8)) - 1;
1256 maxpacket = 1 << size;
1259 if (cfg->mode == BUF_DOUBLE) {
1260 if ((offset + (maxpacket << 1)) >
1261 (1 << (musb->config->ram_bits + 2)))
1263 c_size |= MUSB_FIFOSZ_DPB;
1265 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1269 /* configure the FIFO */
1270 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1272 /* EP0 reserved endpoint for control, bidirectional;
1273 * EP1 reserved for bulk, two unidirectional halves.
1275 if (hw_ep->epnum == 1)
1276 musb->bulk_ep = hw_ep;
1277 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1278 switch (cfg->style) {
1280 musb_write_txfifosz(mbase, c_size);
1281 musb_write_txfifoadd(mbase, c_off);
1282 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1283 hw_ep->max_packet_sz_tx = maxpacket;
1286 musb_write_rxfifosz(mbase, c_size);
1287 musb_write_rxfifoadd(mbase, c_off);
1288 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1289 hw_ep->max_packet_sz_rx = maxpacket;
1292 musb_write_txfifosz(mbase, c_size);
1293 musb_write_txfifoadd(mbase, c_off);
1294 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1295 hw_ep->max_packet_sz_rx = maxpacket;
1297 musb_write_rxfifosz(mbase, c_size);
1298 musb_write_rxfifoadd(mbase, c_off);
1299 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1300 hw_ep->max_packet_sz_tx = maxpacket;
1302 hw_ep->is_shared_fifo = true;
1306 /* NOTE rx and tx endpoint irqs aren't managed separately,
1307 * which happens to be ok
1309 musb->epmask |= (1 << hw_ep->epnum);
1311 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1314 static struct musb_fifo_cfg ep0_cfg = {
1315 .style = FIFO_RXTX, .maxpacket = 64,
1318 static int ep_config_from_table(struct musb *musb)
1320 const struct musb_fifo_cfg *cfg;
1323 struct musb_hw_ep *hw_ep = musb->endpoints;
1325 if (musb->config->fifo_cfg) {
1326 cfg = musb->config->fifo_cfg;
1327 n = musb->config->fifo_cfg_size;
1331 switch (fifo_mode) {
1337 n = ARRAY_SIZE(mode_0_cfg);
1341 n = ARRAY_SIZE(mode_1_cfg);
1345 n = ARRAY_SIZE(mode_2_cfg);
1349 n = ARRAY_SIZE(mode_3_cfg);
1353 n = ARRAY_SIZE(mode_4_cfg);
1357 n = ARRAY_SIZE(mode_5_cfg);
1361 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1362 musb_driver_name, fifo_mode);
1366 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1367 /* assert(offset > 0) */
1369 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1370 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1373 for (i = 0; i < n; i++) {
1374 u8 epn = cfg->hw_ep_num;
1376 if (epn >= musb->config->num_eps) {
1377 pr_debug("%s: invalid ep %d\n",
1378 musb_driver_name, epn);
1381 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1383 pr_debug("%s: mem overrun, ep %d\n",
1384 musb_driver_name, epn);
1388 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1391 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1393 n + 1, musb->config->num_eps * 2 - 1,
1394 offset, (1 << (musb->config->ram_bits + 2)));
1396 if (!musb->bulk_ep) {
1397 pr_debug("%s: missing bulk\n", musb_driver_name);
1406 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1407 * @param musb the controller
1409 static int ep_config_from_hw(struct musb *musb)
1412 struct musb_hw_ep *hw_ep;
1413 void __iomem *mbase = musb->mregs;
1416 dev_dbg(musb->controller, "<== static silicon ep config\n");
1418 /* FIXME pick up ep0 maxpacket size */
1420 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1421 musb_ep_select(mbase, epnum);
1422 hw_ep = musb->endpoints + epnum;
1424 ret = musb_read_fifosize(musb, hw_ep, epnum);
1428 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1430 /* pick an RX/TX endpoint for bulk */
1431 if (hw_ep->max_packet_sz_tx < 512
1432 || hw_ep->max_packet_sz_rx < 512)
1435 /* REVISIT: this algorithm is lazy, we should at least
1436 * try to pick a double buffered endpoint.
1440 musb->bulk_ep = hw_ep;
1443 if (!musb->bulk_ep) {
1444 pr_debug("%s: missing bulk\n", musb_driver_name);
1451 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1453 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1454 * configure endpoints, or take their config from silicon
1456 static int musb_core_init(u16 musb_type, struct musb *musb)
1460 char aInfo[90], aRevision[32], aDate[12];
1461 void __iomem *mbase = musb->mregs;
1465 /* log core options (read using indexed model) */
1466 reg = musb_read_configdata(mbase);
1468 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1469 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1470 strcat(aInfo, ", dyn FIFOs");
1471 musb->dyn_fifo = true;
1473 if (reg & MUSB_CONFIGDATA_MPRXE) {
1474 strcat(aInfo, ", bulk combine");
1475 musb->bulk_combine = true;
1477 if (reg & MUSB_CONFIGDATA_MPTXE) {
1478 strcat(aInfo, ", bulk split");
1479 musb->bulk_split = true;
1481 if (reg & MUSB_CONFIGDATA_HBRXE) {
1482 strcat(aInfo, ", HB-ISO Rx");
1483 musb->hb_iso_rx = true;
1485 if (reg & MUSB_CONFIGDATA_HBTXE) {
1486 strcat(aInfo, ", HB-ISO Tx");
1487 musb->hb_iso_tx = true;
1489 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1490 strcat(aInfo, ", SoftConn");
1492 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1493 musb_driver_name, reg, aInfo);
1496 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1497 musb->is_multipoint = 1;
1500 musb->is_multipoint = 0;
1502 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1504 "%s: kernel must blacklist external hubs\n",
1509 /* log release info */
1510 musb->hwvers = musb_read_hwvers(mbase);
1511 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1512 MUSB_HWVERS_MINOR(musb->hwvers),
1513 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1514 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1515 musb_driver_name, type, aRevision, aDate);
1518 musb_configure_ep0(musb);
1520 /* discover endpoint configuration */
1521 musb->nr_endpoints = 1;
1525 status = ep_config_from_table(musb);
1527 status = ep_config_from_hw(musb);
1532 /* finish init, and print endpoint config */
1533 for (i = 0; i < musb->nr_endpoints; i++) {
1534 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1536 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1537 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1538 if (musb->io.quirks & MUSB_IN_TUSB) {
1539 hw_ep->fifo_async = musb->async + 0x400 +
1540 musb->io.fifo_offset(i);
1541 hw_ep->fifo_sync = musb->sync + 0x400 +
1542 musb->io.fifo_offset(i);
1543 hw_ep->fifo_sync_va =
1544 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1547 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1549 hw_ep->conf = mbase + 0x400 +
1550 (((i - 1) & 0xf) << 2);
1554 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1555 hw_ep->rx_reinit = 1;
1556 hw_ep->tx_reinit = 1;
1558 if (hw_ep->max_packet_sz_tx) {
1559 dev_dbg(musb->controller,
1560 "%s: hw_ep %d%s, %smax %d\n",
1561 musb_driver_name, i,
1562 hw_ep->is_shared_fifo ? "shared" : "tx",
1563 hw_ep->tx_double_buffered
1564 ? "doublebuffer, " : "",
1565 hw_ep->max_packet_sz_tx);
1567 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1568 dev_dbg(musb->controller,
1569 "%s: hw_ep %d%s, %smax %d\n",
1570 musb_driver_name, i,
1572 hw_ep->rx_double_buffered
1573 ? "doublebuffer, " : "",
1574 hw_ep->max_packet_sz_rx);
1576 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1577 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1583 /*-------------------------------------------------------------------------*/
1586 * handle all the irqs defined by the HDRC core. for now we expect: other
1587 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1588 * will be assigned, and the irq will already have been acked.
1590 * called in irq context with spinlock held, irqs blocked
1592 irqreturn_t musb_interrupt(struct musb *musb)
1594 irqreturn_t retval = IRQ_NONE;
1595 unsigned long status;
1596 unsigned long epnum;
1599 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1602 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1604 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1605 is_host_active(musb) ? "host" : "peripheral",
1606 musb->int_usb, musb->int_tx, musb->int_rx);
1609 * According to Mentor Graphics' documentation, flowchart on page 98,
1610 * IRQ should be handled as follows:
1613 * . Session Request IRQ
1618 * . Reset/Babble IRQ
1619 * . SOF IRQ (we're not using this one)
1624 * We will be following that flowchart in order to avoid any problems
1625 * that might arise with internal Finite State Machine.
1629 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1631 if (musb->int_tx & 1) {
1632 if (is_host_active(musb))
1633 retval |= musb_h_ep0_irq(musb);
1635 retval |= musb_g_ep0_irq(musb);
1637 /* we have just handled endpoint 0 IRQ, clear it */
1638 musb->int_tx &= ~BIT(0);
1641 status = musb->int_tx;
1643 for_each_set_bit(epnum, &status, 16) {
1644 retval = IRQ_HANDLED;
1645 if (is_host_active(musb))
1646 musb_host_tx(musb, epnum);
1648 musb_g_tx(musb, epnum);
1651 status = musb->int_rx;
1653 for_each_set_bit(epnum, &status, 16) {
1654 retval = IRQ_HANDLED;
1655 if (is_host_active(musb))
1656 musb_host_rx(musb, epnum);
1658 musb_g_rx(musb, epnum);
1663 EXPORT_SYMBOL_GPL(musb_interrupt);
1665 #ifndef CONFIG_MUSB_PIO_ONLY
1666 static bool use_dma = 1;
1668 /* "modprobe ... use_dma=0" etc */
1669 module_param(use_dma, bool, 0644);
1670 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1672 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1674 /* called with controller lock already held */
1677 if (!is_cppi_enabled(musb)) {
1679 if (is_host_active(musb))
1680 musb_h_ep0_irq(musb);
1682 musb_g_ep0_irq(musb);
1685 /* endpoints 1..15 */
1687 if (is_host_active(musb))
1688 musb_host_tx(musb, epnum);
1690 musb_g_tx(musb, epnum);
1693 if (is_host_active(musb))
1694 musb_host_rx(musb, epnum);
1696 musb_g_rx(musb, epnum);
1700 EXPORT_SYMBOL_GPL(musb_dma_completion);
1706 /*-------------------------------------------------------------------------*/
1709 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1711 struct musb *musb = dev_to_musb(dev);
1712 unsigned long flags;
1715 spin_lock_irqsave(&musb->lock, flags);
1716 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1717 spin_unlock_irqrestore(&musb->lock, flags);
1723 musb_mode_store(struct device *dev, struct device_attribute *attr,
1724 const char *buf, size_t n)
1726 struct musb *musb = dev_to_musb(dev);
1727 unsigned long flags;
1730 spin_lock_irqsave(&musb->lock, flags);
1731 if (sysfs_streq(buf, "host"))
1732 status = musb_platform_set_mode(musb, MUSB_HOST);
1733 else if (sysfs_streq(buf, "peripheral"))
1734 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1735 else if (sysfs_streq(buf, "otg"))
1736 status = musb_platform_set_mode(musb, MUSB_OTG);
1739 spin_unlock_irqrestore(&musb->lock, flags);
1741 return (status == 0) ? n : status;
1743 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1746 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1747 const char *buf, size_t n)
1749 struct musb *musb = dev_to_musb(dev);
1750 unsigned long flags;
1753 if (sscanf(buf, "%lu", &val) < 1) {
1754 dev_err(dev, "Invalid VBUS timeout ms value\n");
1758 spin_lock_irqsave(&musb->lock, flags);
1759 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1760 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1761 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1762 musb->is_active = 0;
1763 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1764 spin_unlock_irqrestore(&musb->lock, flags);
1770 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1772 struct musb *musb = dev_to_musb(dev);
1773 unsigned long flags;
1778 pm_runtime_get_sync(dev);
1779 spin_lock_irqsave(&musb->lock, flags);
1780 val = musb->a_wait_bcon;
1781 vbus = musb_platform_get_vbus_status(musb);
1783 /* Use default MUSB method by means of DEVCTL register */
1784 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1785 if ((devctl & MUSB_DEVCTL_VBUS)
1786 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1791 spin_unlock_irqrestore(&musb->lock, flags);
1792 pm_runtime_put_sync(dev);
1794 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1795 vbus ? "on" : "off", val);
1797 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1799 /* Gadget drivers can't know that a host is connected so they might want
1800 * to start SRP, but users can. This allows userspace to trigger SRP.
1803 musb_srp_store(struct device *dev, struct device_attribute *attr,
1804 const char *buf, size_t n)
1806 struct musb *musb = dev_to_musb(dev);
1809 if (sscanf(buf, "%hu", &srp) != 1
1811 dev_err(dev, "SRP: Value must be 1\n");
1816 musb_g_wakeup(musb);
1820 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1822 static struct attribute *musb_attributes[] = {
1823 &dev_attr_mode.attr,
1824 &dev_attr_vbus.attr,
1829 static const struct attribute_group musb_attr_group = {
1830 .attrs = musb_attributes,
1833 /* Only used to provide driver mode change events */
1834 static void musb_irq_work(struct work_struct *data)
1836 struct musb *musb = container_of(data, struct musb, irq_work);
1838 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1839 musb->xceiv_old_state = musb->xceiv->otg->state;
1840 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1844 static void musb_recover_from_babble(struct musb *musb)
1849 musb_disable_interrupts(musb);
1852 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1853 * it some slack and wait for 10us.
1857 ret = musb_platform_recover(musb);
1859 musb_enable_interrupts(musb);
1863 /* drop session bit */
1864 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1865 devctl &= ~MUSB_DEVCTL_SESSION;
1866 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1868 /* tell usbcore about it */
1869 musb_root_disconnect(musb);
1872 * When a babble condition occurs, the musb controller
1873 * removes the session bit and the endpoint config is lost.
1876 ret = ep_config_from_table(musb);
1878 ret = ep_config_from_hw(musb);
1880 /* restart session */
1885 /* --------------------------------------------------------------------------
1889 static struct musb *allocate_instance(struct device *dev,
1890 struct musb_hdrc_config *config, void __iomem *mbase)
1893 struct musb_hw_ep *ep;
1897 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1901 INIT_LIST_HEAD(&musb->control);
1902 INIT_LIST_HEAD(&musb->in_bulk);
1903 INIT_LIST_HEAD(&musb->out_bulk);
1905 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1906 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1907 musb->mregs = mbase;
1908 musb->ctrl_base = mbase;
1909 musb->nIrq = -ENODEV;
1910 musb->config = config;
1911 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1912 for (epnum = 0, ep = musb->endpoints;
1913 epnum < musb->config->num_eps;
1919 musb->controller = dev;
1921 ret = musb_host_alloc(musb);
1925 dev_set_drvdata(dev, musb);
1933 static void musb_free(struct musb *musb)
1935 /* this has multiple entry modes. it handles fault cleanup after
1936 * probe(), where things may be partially set up, as well as rmmod
1937 * cleanup after everything's been de-activated.
1941 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1944 if (musb->nIrq >= 0) {
1946 disable_irq_wake(musb->nIrq);
1947 free_irq(musb->nIrq, musb);
1950 musb_host_free(musb);
1953 static void musb_deassert_reset(struct work_struct *work)
1956 unsigned long flags;
1958 musb = container_of(work, struct musb, deassert_reset_work.work);
1960 spin_lock_irqsave(&musb->lock, flags);
1962 if (musb->port1_status & USB_PORT_STAT_RESET)
1963 musb_port_reset(musb, false);
1965 spin_unlock_irqrestore(&musb->lock, flags);
1969 * Perform generic per-controller initialization.
1971 * @dev: the controller (already clocked, etc)
1973 * @ctrl: virtual address of controller registers,
1974 * not yet corrected for platform-specific offsets
1977 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1981 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1983 /* The driver might handle more features than the board; OK.
1984 * Fail when the board needs a feature that's not enabled.
1987 dev_dbg(dev, "no platform_data?\n");
1993 musb = allocate_instance(dev, plat->config, ctrl);
1999 spin_lock_init(&musb->lock);
2000 musb->board_set_power = plat->set_power;
2001 musb->min_power = plat->min_power;
2002 musb->ops = plat->platform_ops;
2003 musb->port_mode = plat->mode;
2006 * Initialize the default IO functions. At least omap2430 needs
2007 * these early. We initialize the platform specific IO functions
2010 musb_readb = musb_default_readb;
2011 musb_writeb = musb_default_writeb;
2012 musb_readw = musb_default_readw;
2013 musb_writew = musb_default_writew;
2014 musb_readl = musb_default_readl;
2015 musb_writel = musb_default_writel;
2017 /* We need musb_read/write functions initialized for PM */
2018 pm_runtime_use_autosuspend(musb->controller);
2019 pm_runtime_set_autosuspend_delay(musb->controller, 200);
2020 pm_runtime_enable(musb->controller);
2022 /* The musb_platform_init() call:
2023 * - adjusts musb->mregs
2024 * - sets the musb->isr
2025 * - may initialize an integrated transceiver
2026 * - initializes musb->xceiv, usually by otg_get_phy()
2027 * - stops powering VBUS
2029 * There are various transceiver configurations. Blackfin,
2030 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2031 * external/discrete ones in various flavors (twl4030 family,
2032 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2034 status = musb_platform_init(musb);
2043 if (musb->ops->quirks)
2044 musb->io.quirks = musb->ops->quirks;
2046 /* Most devices use indexed offset or flat offset */
2047 if (musb->io.quirks & MUSB_INDEXED_EP) {
2048 musb->io.ep_offset = musb_indexed_ep_offset;
2049 musb->io.ep_select = musb_indexed_ep_select;
2051 musb->io.ep_offset = musb_flat_ep_offset;
2052 musb->io.ep_select = musb_flat_ep_select;
2054 /* And override them with platform specific ops if specified. */
2055 if (musb->ops->ep_offset)
2056 musb->io.ep_offset = musb->ops->ep_offset;
2057 if (musb->ops->ep_select)
2058 musb->io.ep_select = musb->ops->ep_select;
2060 /* At least tusb6010 has its own offsets */
2061 if (musb->ops->ep_offset)
2062 musb->io.ep_offset = musb->ops->ep_offset;
2063 if (musb->ops->ep_select)
2064 musb->io.ep_select = musb->ops->ep_select;
2066 if (musb->ops->fifo_mode)
2067 fifo_mode = musb->ops->fifo_mode;
2071 if (musb->ops->fifo_offset)
2072 musb->io.fifo_offset = musb->ops->fifo_offset;
2074 musb->io.fifo_offset = musb_default_fifo_offset;
2076 if (musb->ops->busctl_offset)
2077 musb->io.busctl_offset = musb->ops->busctl_offset;
2079 musb->io.busctl_offset = musb_default_busctl_offset;
2081 if (musb->ops->readb)
2082 musb_readb = musb->ops->readb;
2083 if (musb->ops->writeb)
2084 musb_writeb = musb->ops->writeb;
2085 if (musb->ops->readw)
2086 musb_readw = musb->ops->readw;
2087 if (musb->ops->writew)
2088 musb_writew = musb->ops->writew;
2089 if (musb->ops->readl)
2090 musb_readl = musb->ops->readl;
2091 if (musb->ops->writel)
2092 musb_writel = musb->ops->writel;
2094 #ifndef CONFIG_MUSB_PIO_ONLY
2095 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2096 dev_err(dev, "DMA controller not set\n");
2100 musb_dma_controller_create = musb->ops->dma_init;
2101 musb_dma_controller_destroy = musb->ops->dma_exit;
2104 if (musb->ops->read_fifo)
2105 musb->io.read_fifo = musb->ops->read_fifo;
2107 musb->io.read_fifo = musb_default_read_fifo;
2109 if (musb->ops->write_fifo)
2110 musb->io.write_fifo = musb->ops->write_fifo;
2112 musb->io.write_fifo = musb_default_write_fifo;
2114 if (!musb->xceiv->io_ops) {
2115 musb->xceiv->io_dev = musb->controller;
2116 musb->xceiv->io_priv = musb->mregs;
2117 musb->xceiv->io_ops = &musb_ulpi_access;
2120 pm_runtime_get_sync(musb->controller);
2122 if (use_dma && dev->dma_mask) {
2123 musb->dma_controller =
2124 musb_dma_controller_create(musb, musb->mregs);
2125 if (IS_ERR(musb->dma_controller)) {
2126 status = PTR_ERR(musb->dma_controller);
2131 /* be sure interrupts are disabled before connecting ISR */
2132 musb_platform_disable(musb);
2133 musb_generic_disable(musb);
2135 /* MUSB_POWER_SOFTCONN might be already set, JZ4740 does this. */
2136 musb_writeb(musb->mregs, MUSB_POWER, 0);
2138 /* Init IRQ workqueue before request_irq */
2139 INIT_WORK(&musb->irq_work, musb_irq_work);
2140 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2141 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2143 /* setup musb parts of the core (especially endpoints) */
2144 status = musb_core_init(plat->config->multipoint
2145 ? MUSB_CONTROLLER_MHDRC
2146 : MUSB_CONTROLLER_HDRC, musb);
2150 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2152 /* attach to the IRQ */
2153 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2154 dev_err(dev, "request_irq %d failed!\n", nIrq);
2159 /* FIXME this handles wakeup irqs wrong */
2160 if (enable_irq_wake(nIrq) == 0) {
2162 device_init_wakeup(dev, 1);
2167 /* program PHY to use external vBus if required */
2168 if (plat->extvbus) {
2169 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2170 busctl |= MUSB_ULPI_USE_EXTVBUS;
2171 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2174 if (musb->xceiv->otg->default_a) {
2175 MUSB_HST_MODE(musb);
2176 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2178 MUSB_DEV_MODE(musb);
2179 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2182 switch (musb->port_mode) {
2183 case MUSB_PORT_MODE_HOST:
2184 status = musb_host_setup(musb, plat->power);
2187 status = musb_platform_set_mode(musb, MUSB_HOST);
2189 case MUSB_PORT_MODE_GADGET:
2190 status = musb_gadget_setup(musb);
2193 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2195 case MUSB_PORT_MODE_DUAL_ROLE:
2196 status = musb_host_setup(musb, plat->power);
2199 status = musb_gadget_setup(musb);
2201 musb_host_cleanup(musb);
2204 status = musb_platform_set_mode(musb, MUSB_OTG);
2207 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2214 status = musb_init_debugfs(musb);
2218 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2222 pm_runtime_put(musb->controller);
2225 * For why this is currently needed, see commit 3e43a0725637
2226 * ("usb: musb: core: add pm_runtime_irq_safe()")
2228 pm_runtime_irq_safe(musb->controller);
2233 musb_exit_debugfs(musb);
2236 musb_gadget_cleanup(musb);
2237 musb_host_cleanup(musb);
2240 cancel_work_sync(&musb->irq_work);
2241 cancel_delayed_work_sync(&musb->finish_resume_work);
2242 cancel_delayed_work_sync(&musb->deassert_reset_work);
2243 if (musb->dma_controller)
2244 musb_dma_controller_destroy(musb->dma_controller);
2246 pm_runtime_put_sync(musb->controller);
2250 device_init_wakeup(dev, 0);
2251 musb_platform_exit(musb);
2254 pm_runtime_disable(musb->controller);
2255 dev_err(musb->controller,
2256 "musb_init_controller failed with status %d\n", status);
2266 /*-------------------------------------------------------------------------*/
2268 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2269 * bridge to a platform device; this driver then suffices.
2271 static int musb_probe(struct platform_device *pdev)
2273 struct device *dev = &pdev->dev;
2274 int irq = platform_get_irq_byname(pdev, "mc");
2275 struct resource *iomem;
2281 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2282 base = devm_ioremap_resource(dev, iomem);
2284 return PTR_ERR(base);
2286 return musb_init_controller(dev, irq, base);
2289 static int musb_remove(struct platform_device *pdev)
2291 struct device *dev = &pdev->dev;
2292 struct musb *musb = dev_to_musb(dev);
2294 /* this gets called on rmmod.
2295 * - Host mode: host may still be active
2296 * - Peripheral mode: peripheral is deactivated (or never-activated)
2297 * - OTG mode: both roles are deactivated (or never-activated)
2299 musb_exit_debugfs(musb);
2300 musb_shutdown(pdev);
2302 if (musb->dma_controller)
2303 musb_dma_controller_destroy(musb->dma_controller);
2305 cancel_work_sync(&musb->irq_work);
2306 cancel_delayed_work_sync(&musb->finish_resume_work);
2307 cancel_delayed_work_sync(&musb->deassert_reset_work);
2309 device_init_wakeup(dev, 0);
2315 static void musb_save_context(struct musb *musb)
2318 void __iomem *musb_base = musb->mregs;
2321 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2322 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2323 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2324 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2325 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2326 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2327 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2329 for (i = 0; i < musb->config->num_eps; ++i) {
2330 struct musb_hw_ep *hw_ep;
2332 hw_ep = &musb->endpoints[i];
2340 musb_writeb(musb_base, MUSB_INDEX, i);
2341 musb->context.index_regs[i].txmaxp =
2342 musb_readw(epio, MUSB_TXMAXP);
2343 musb->context.index_regs[i].txcsr =
2344 musb_readw(epio, MUSB_TXCSR);
2345 musb->context.index_regs[i].rxmaxp =
2346 musb_readw(epio, MUSB_RXMAXP);
2347 musb->context.index_regs[i].rxcsr =
2348 musb_readw(epio, MUSB_RXCSR);
2350 if (musb->dyn_fifo) {
2351 musb->context.index_regs[i].txfifoadd =
2352 musb_read_txfifoadd(musb_base);
2353 musb->context.index_regs[i].rxfifoadd =
2354 musb_read_rxfifoadd(musb_base);
2355 musb->context.index_regs[i].txfifosz =
2356 musb_read_txfifosz(musb_base);
2357 musb->context.index_regs[i].rxfifosz =
2358 musb_read_rxfifosz(musb_base);
2361 musb->context.index_regs[i].txtype =
2362 musb_readb(epio, MUSB_TXTYPE);
2363 musb->context.index_regs[i].txinterval =
2364 musb_readb(epio, MUSB_TXINTERVAL);
2365 musb->context.index_regs[i].rxtype =
2366 musb_readb(epio, MUSB_RXTYPE);
2367 musb->context.index_regs[i].rxinterval =
2368 musb_readb(epio, MUSB_RXINTERVAL);
2370 musb->context.index_regs[i].txfunaddr =
2371 musb_read_txfunaddr(musb, i);
2372 musb->context.index_regs[i].txhubaddr =
2373 musb_read_txhubaddr(musb, i);
2374 musb->context.index_regs[i].txhubport =
2375 musb_read_txhubport(musb, i);
2377 musb->context.index_regs[i].rxfunaddr =
2378 musb_read_rxfunaddr(musb, i);
2379 musb->context.index_regs[i].rxhubaddr =
2380 musb_read_rxhubaddr(musb, i);
2381 musb->context.index_regs[i].rxhubport =
2382 musb_read_rxhubport(musb, i);
2386 static void musb_restore_context(struct musb *musb)
2389 void __iomem *musb_base = musb->mregs;
2393 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2394 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2395 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2397 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2398 power = musb_readb(musb_base, MUSB_POWER);
2399 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2400 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2401 power |= musb->context.power;
2402 musb_writeb(musb_base, MUSB_POWER, power);
2404 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2405 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2406 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2407 if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2408 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2410 for (i = 0; i < musb->config->num_eps; ++i) {
2411 struct musb_hw_ep *hw_ep;
2413 hw_ep = &musb->endpoints[i];
2421 musb_writeb(musb_base, MUSB_INDEX, i);
2422 musb_writew(epio, MUSB_TXMAXP,
2423 musb->context.index_regs[i].txmaxp);
2424 musb_writew(epio, MUSB_TXCSR,
2425 musb->context.index_regs[i].txcsr);
2426 musb_writew(epio, MUSB_RXMAXP,
2427 musb->context.index_regs[i].rxmaxp);
2428 musb_writew(epio, MUSB_RXCSR,
2429 musb->context.index_regs[i].rxcsr);
2431 if (musb->dyn_fifo) {
2432 musb_write_txfifosz(musb_base,
2433 musb->context.index_regs[i].txfifosz);
2434 musb_write_rxfifosz(musb_base,
2435 musb->context.index_regs[i].rxfifosz);
2436 musb_write_txfifoadd(musb_base,
2437 musb->context.index_regs[i].txfifoadd);
2438 musb_write_rxfifoadd(musb_base,
2439 musb->context.index_regs[i].rxfifoadd);
2442 musb_writeb(epio, MUSB_TXTYPE,
2443 musb->context.index_regs[i].txtype);
2444 musb_writeb(epio, MUSB_TXINTERVAL,
2445 musb->context.index_regs[i].txinterval);
2446 musb_writeb(epio, MUSB_RXTYPE,
2447 musb->context.index_regs[i].rxtype);
2448 musb_writeb(epio, MUSB_RXINTERVAL,
2450 musb->context.index_regs[i].rxinterval);
2451 musb_write_txfunaddr(musb, i,
2452 musb->context.index_regs[i].txfunaddr);
2453 musb_write_txhubaddr(musb, i,
2454 musb->context.index_regs[i].txhubaddr);
2455 musb_write_txhubport(musb, i,
2456 musb->context.index_regs[i].txhubport);
2458 musb_write_rxfunaddr(musb, i,
2459 musb->context.index_regs[i].rxfunaddr);
2460 musb_write_rxhubaddr(musb, i,
2461 musb->context.index_regs[i].rxhubaddr);
2462 musb_write_rxhubport(musb, i,
2463 musb->context.index_regs[i].rxhubport);
2465 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2468 static int musb_suspend(struct device *dev)
2470 struct musb *musb = dev_to_musb(dev);
2471 unsigned long flags;
2473 musb_platform_disable(musb);
2474 musb_generic_disable(musb);
2476 spin_lock_irqsave(&musb->lock, flags);
2478 if (is_peripheral_active(musb)) {
2479 /* FIXME force disconnect unless we know USB will wake
2480 * the system up quickly enough to respond ...
2482 } else if (is_host_active(musb)) {
2483 /* we know all the children are suspended; sometimes
2484 * they will even be wakeup-enabled.
2488 musb_save_context(musb);
2490 spin_unlock_irqrestore(&musb->lock, flags);
2494 static int musb_resume(struct device *dev)
2496 struct musb *musb = dev_to_musb(dev);
2501 * For static cmos like DaVinci, register values were preserved
2502 * unless for some reason the whole soc powered down or the USB
2503 * module got reset through the PSC (vs just being disabled).
2505 * For the DSPS glue layer though, a full register restore has to
2506 * be done. As it shouldn't harm other platforms, we do it
2510 musb_restore_context(musb);
2512 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2513 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2514 if ((devctl & mask) != (musb->context.devctl & mask))
2515 musb->port1_status = 0;
2516 if (musb->need_finish_resume) {
2517 musb->need_finish_resume = 0;
2518 schedule_delayed_work(&musb->finish_resume_work,
2519 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2523 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2526 pm_runtime_disable(dev);
2527 pm_runtime_set_active(dev);
2528 pm_runtime_enable(dev);
2530 musb_enable_interrupts(musb);
2531 musb_platform_enable(musb);
2536 static int musb_runtime_suspend(struct device *dev)
2538 struct musb *musb = dev_to_musb(dev);
2540 musb_save_context(musb);
2545 static int musb_runtime_resume(struct device *dev)
2547 struct musb *musb = dev_to_musb(dev);
2548 static int first = 1;
2551 * When pm_runtime_get_sync called for the first time in driver
2552 * init, some of the structure is still not initialized which is
2553 * used in restore function. But clock needs to be
2554 * enabled before any register access, so
2555 * pm_runtime_get_sync has to be called.
2556 * Also context restore without save does not make
2560 musb_restore_context(musb);
2563 if (musb->need_finish_resume) {
2564 musb->need_finish_resume = 0;
2565 schedule_delayed_work(&musb->finish_resume_work,
2566 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2572 static const struct dev_pm_ops musb_dev_pm_ops = {
2573 .suspend = musb_suspend,
2574 .resume = musb_resume,
2575 .runtime_suspend = musb_runtime_suspend,
2576 .runtime_resume = musb_runtime_resume,
2579 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2581 #define MUSB_DEV_PM_OPS NULL
2584 static struct platform_driver musb_driver = {
2586 .name = (char *)musb_driver_name,
2587 .bus = &platform_bus_type,
2588 .pm = MUSB_DEV_PM_OPS,
2590 .probe = musb_probe,
2591 .remove = musb_remove,
2592 .shutdown = musb_shutdown,
2595 module_platform_driver(musb_driver);