1 // SPDX-License-Identifier: GPL-2.0
3 * mtu3_qmu.c - Queue Management Unit driver for device controller
5 * Copyright (C) 2016 MediaTek Inc.
7 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
11 * Queue Management Unit (QMU) is designed to unload SW effort
12 * to serve DMA interrupts.
13 * By preparing General Purpose Descriptor (GPD) and Buffer Descriptor (BD),
14 * SW links data buffers and triggers QMU to send / receive data to
15 * host / from device at a time.
16 * And now only GPD is supported.
18 * For more detailed information, please refer to QMU Programming Guide
21 #include <linux/dmapool.h>
22 #include <linux/iopoll.h>
25 #include "mtu3_trace.h"
27 #define QMU_CHECKSUM_LEN 16
29 #define GPD_FLAGS_HWO BIT(0)
30 #define GPD_FLAGS_BDP BIT(1)
31 #define GPD_FLAGS_BPS BIT(2)
32 #define GPD_FLAGS_ZLP BIT(6)
33 #define GPD_FLAGS_IOC BIT(7)
34 #define GET_GPD_HWO(gpd) (le32_to_cpu((gpd)->dw0_info) & GPD_FLAGS_HWO)
36 #define GPD_RX_BUF_LEN_OG(x) (((x) & 0xffff) << 16)
37 #define GPD_RX_BUF_LEN_EL(x) (((x) & 0xfffff) << 12)
38 #define GPD_RX_BUF_LEN(mtu, x) \
41 ((mtu)->gen2cp) ? GPD_RX_BUF_LEN_EL(x_) : GPD_RX_BUF_LEN_OG(x_); \
44 #define GPD_DATA_LEN_OG(x) ((x) & 0xffff)
45 #define GPD_DATA_LEN_EL(x) ((x) & 0xfffff)
46 #define GPD_DATA_LEN(mtu, x) \
49 ((mtu)->gen2cp) ? GPD_DATA_LEN_EL(x_) : GPD_DATA_LEN_OG(x_); \
52 #define GPD_EXT_FLAG_ZLP BIT(29)
53 #define GPD_EXT_NGP_OG(x) (((x) & 0xf) << 20)
54 #define GPD_EXT_BUF_OG(x) (((x) & 0xf) << 16)
55 #define GPD_EXT_NGP_EL(x) (((x) & 0xf) << 28)
56 #define GPD_EXT_BUF_EL(x) (((x) & 0xf) << 24)
57 #define GPD_EXT_NGP(mtu, x) \
60 ((mtu)->gen2cp) ? GPD_EXT_NGP_EL(x_) : GPD_EXT_NGP_OG(x_); \
63 #define GPD_EXT_BUF(mtu, x) \
66 ((mtu)->gen2cp) ? GPD_EXT_BUF_EL(x_) : GPD_EXT_BUF_OG(x_); \
69 #define HILO_GEN64(hi, lo) (((u64)(hi) << 32) + (lo))
70 #define HILO_DMA(hi, lo) \
71 ((dma_addr_t)HILO_GEN64((le32_to_cpu(hi)), (le32_to_cpu(lo))))
73 static dma_addr_t read_txq_cur_addr(void __iomem *mbase, u8 epnum)
78 txcpr = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
79 txhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum));
81 return HILO_DMA(QMU_CUR_GPD_ADDR_HI(txhiar), txcpr);
84 static dma_addr_t read_rxq_cur_addr(void __iomem *mbase, u8 epnum)
89 rxcpr = mtu3_readl(mbase, USB_QMU_RQCPR(epnum));
90 rxhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum));
92 return HILO_DMA(QMU_CUR_GPD_ADDR_HI(rxhiar), rxcpr);
95 static void write_txq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma)
99 mtu3_writel(mbase, USB_QMU_TQSAR(epnum),
100 cpu_to_le32(lower_32_bits(dma)));
101 tqhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum));
102 tqhiar &= ~QMU_START_ADDR_HI_MSK;
103 tqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma));
104 mtu3_writel(mbase, USB_QMU_TQHIAR(epnum), tqhiar);
107 static void write_rxq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma)
111 mtu3_writel(mbase, USB_QMU_RQSAR(epnum),
112 cpu_to_le32(lower_32_bits(dma)));
113 rqhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum));
114 rqhiar &= ~QMU_START_ADDR_HI_MSK;
115 rqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma));
116 mtu3_writel(mbase, USB_QMU_RQHIAR(epnum), rqhiar);
119 static struct qmu_gpd *gpd_dma_to_virt(struct mtu3_gpd_ring *ring,
122 dma_addr_t dma_base = ring->dma;
123 struct qmu_gpd *gpd_head = ring->start;
124 u32 offset = (dma_addr - dma_base) / sizeof(*gpd_head);
126 if (offset >= MAX_GPD_NUM)
129 return gpd_head + offset;
132 static dma_addr_t gpd_virt_to_dma(struct mtu3_gpd_ring *ring,
135 dma_addr_t dma_base = ring->dma;
136 struct qmu_gpd *gpd_head = ring->start;
139 offset = gpd - gpd_head;
140 if (offset >= MAX_GPD_NUM)
143 return dma_base + (offset * sizeof(*gpd));
146 static void gpd_ring_init(struct mtu3_gpd_ring *ring, struct qmu_gpd *gpd)
151 ring->end = gpd + MAX_GPD_NUM - 1;
154 static void reset_gpd_list(struct mtu3_ep *mep)
156 struct mtu3_gpd_ring *ring = &mep->gpd_ring;
157 struct qmu_gpd *gpd = ring->start;
160 gpd->dw0_info &= cpu_to_le32(~GPD_FLAGS_HWO);
161 gpd_ring_init(ring, gpd);
165 int mtu3_gpd_ring_alloc(struct mtu3_ep *mep)
168 struct mtu3_gpd_ring *ring = &mep->gpd_ring;
170 /* software own all gpds as default */
171 gpd = dma_pool_zalloc(mep->mtu->qmu_gpd_pool, GFP_ATOMIC, &ring->dma);
175 gpd_ring_init(ring, gpd);
180 void mtu3_gpd_ring_free(struct mtu3_ep *mep)
182 struct mtu3_gpd_ring *ring = &mep->gpd_ring;
184 dma_pool_free(mep->mtu->qmu_gpd_pool,
185 ring->start, ring->dma);
186 memset(ring, 0, sizeof(*ring));
189 void mtu3_qmu_resume(struct mtu3_ep *mep)
191 struct mtu3 *mtu = mep->mtu;
192 void __iomem *mbase = mtu->mac_base;
193 int epnum = mep->epnum;
196 offset = mep->is_in ? USB_QMU_TQCSR(epnum) : USB_QMU_RQCSR(epnum);
198 mtu3_writel(mbase, offset, QMU_Q_RESUME);
199 if (!(mtu3_readl(mbase, offset) & QMU_Q_ACTIVE))
200 mtu3_writel(mbase, offset, QMU_Q_RESUME);
203 static struct qmu_gpd *advance_enq_gpd(struct mtu3_gpd_ring *ring)
205 if (ring->enqueue < ring->end)
208 ring->enqueue = ring->start;
210 return ring->enqueue;
213 /* @dequeue may be NULL if ring is unallocated or freed */
214 static struct qmu_gpd *advance_deq_gpd(struct mtu3_gpd_ring *ring)
216 if (ring->dequeue < ring->end)
219 ring->dequeue = ring->start;
221 return ring->dequeue;
224 /* check if a ring is emtpy */
225 static bool gpd_ring_empty(struct mtu3_gpd_ring *ring)
227 struct qmu_gpd *enq = ring->enqueue;
228 struct qmu_gpd *next;
230 if (ring->enqueue < ring->end)
235 /* one gpd is reserved to simplify gpd preparation */
236 return next == ring->dequeue;
239 int mtu3_prepare_transfer(struct mtu3_ep *mep)
241 return gpd_ring_empty(&mep->gpd_ring);
244 static int mtu3_prepare_tx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
247 struct mtu3_gpd_ring *ring = &mep->gpd_ring;
248 struct qmu_gpd *gpd = ring->enqueue;
249 struct usb_request *req = &mreq->request;
250 struct mtu3 *mtu = mep->mtu;
254 gpd->dw0_info = 0; /* SW own it */
255 gpd->buffer = cpu_to_le32(lower_32_bits(req->dma));
256 ext_addr = GPD_EXT_BUF(mtu, upper_32_bits(req->dma));
257 gpd->dw3_info = cpu_to_le32(GPD_DATA_LEN(mtu, req->length));
259 /* get the next GPD */
260 enq = advance_enq_gpd(ring);
261 enq_dma = gpd_virt_to_dma(ring, enq);
262 dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n",
263 mep->epnum, gpd, enq, &enq_dma);
265 enq->dw0_info &= cpu_to_le32(~GPD_FLAGS_HWO);
266 gpd->next_gpd = cpu_to_le32(lower_32_bits(enq_dma));
267 ext_addr |= GPD_EXT_NGP(mtu, upper_32_bits(enq_dma));
268 gpd->dw0_info = cpu_to_le32(ext_addr);
272 gpd->dw0_info |= cpu_to_le32(GPD_FLAGS_ZLP);
274 gpd->dw3_info |= cpu_to_le32(GPD_EXT_FLAG_ZLP);
277 /* prevent reorder, make sure GPD's HWO is set last */
279 gpd->dw0_info |= cpu_to_le32(GPD_FLAGS_IOC | GPD_FLAGS_HWO);
282 trace_mtu3_prepare_gpd(mep, gpd);
287 static int mtu3_prepare_rx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
290 struct mtu3_gpd_ring *ring = &mep->gpd_ring;
291 struct qmu_gpd *gpd = ring->enqueue;
292 struct usb_request *req = &mreq->request;
293 struct mtu3 *mtu = mep->mtu;
297 gpd->dw0_info = 0; /* SW own it */
298 gpd->buffer = cpu_to_le32(lower_32_bits(req->dma));
299 ext_addr = GPD_EXT_BUF(mtu, upper_32_bits(req->dma));
300 gpd->dw0_info = cpu_to_le32(GPD_RX_BUF_LEN(mtu, req->length));
302 /* get the next GPD */
303 enq = advance_enq_gpd(ring);
304 enq_dma = gpd_virt_to_dma(ring, enq);
305 dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n",
306 mep->epnum, gpd, enq, &enq_dma);
308 enq->dw0_info &= cpu_to_le32(~GPD_FLAGS_HWO);
309 gpd->next_gpd = cpu_to_le32(lower_32_bits(enq_dma));
310 ext_addr |= GPD_EXT_NGP(mtu, upper_32_bits(enq_dma));
311 gpd->dw3_info = cpu_to_le32(ext_addr);
312 /* prevent reorder, make sure GPD's HWO is set last */
314 gpd->dw0_info |= cpu_to_le32(GPD_FLAGS_IOC | GPD_FLAGS_HWO);
317 trace_mtu3_prepare_gpd(mep, gpd);
322 void mtu3_insert_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
326 mtu3_prepare_tx_gpd(mep, mreq);
328 mtu3_prepare_rx_gpd(mep, mreq);
331 int mtu3_qmu_start(struct mtu3_ep *mep)
333 struct mtu3 *mtu = mep->mtu;
334 void __iomem *mbase = mtu->mac_base;
335 struct mtu3_gpd_ring *ring = &mep->gpd_ring;
336 u8 epnum = mep->epnum;
339 /* set QMU start address */
340 write_txq_start_addr(mbase, epnum, ring->dma);
341 mtu3_setbits(mbase, MU3D_EP_TXCR0(epnum), TX_DMAREQEN);
342 /* send zero length packet according to ZLP flag in GPD */
343 mtu3_setbits(mbase, U3D_QCR1, QMU_TX_ZLP(epnum));
344 mtu3_writel(mbase, U3D_TQERRIESR0,
345 QMU_TX_LEN_ERR(epnum) | QMU_TX_CS_ERR(epnum));
347 if (mtu3_readl(mbase, USB_QMU_TQCSR(epnum)) & QMU_Q_ACTIVE) {
348 dev_warn(mtu->dev, "Tx %d Active Now!\n", epnum);
351 mtu3_writel(mbase, USB_QMU_TQCSR(epnum), QMU_Q_START);
354 write_rxq_start_addr(mbase, epnum, ring->dma);
355 mtu3_setbits(mbase, MU3D_EP_RXCR0(epnum), RX_DMAREQEN);
356 /* don't expect ZLP */
357 mtu3_clrbits(mbase, U3D_QCR3, QMU_RX_ZLP(epnum));
358 /* move to next GPD when receive ZLP */
359 mtu3_setbits(mbase, U3D_QCR3, QMU_RX_COZ(epnum));
360 mtu3_writel(mbase, U3D_RQERRIESR0,
361 QMU_RX_LEN_ERR(epnum) | QMU_RX_CS_ERR(epnum));
362 mtu3_writel(mbase, U3D_RQERRIESR1, QMU_RX_ZLP_ERR(epnum));
364 if (mtu3_readl(mbase, USB_QMU_RQCSR(epnum)) & QMU_Q_ACTIVE) {
365 dev_warn(mtu->dev, "Rx %d Active Now!\n", epnum);
368 mtu3_writel(mbase, USB_QMU_RQCSR(epnum), QMU_Q_START);
374 /* may called in atomic context */
375 void mtu3_qmu_stop(struct mtu3_ep *mep)
377 struct mtu3 *mtu = mep->mtu;
378 void __iomem *mbase = mtu->mac_base;
379 int epnum = mep->epnum;
384 qcsr = mep->is_in ? USB_QMU_TQCSR(epnum) : USB_QMU_RQCSR(epnum);
386 if (!(mtu3_readl(mbase, qcsr) & QMU_Q_ACTIVE)) {
387 dev_dbg(mtu->dev, "%s's qmu is inactive now!\n", mep->name);
390 mtu3_writel(mbase, qcsr, QMU_Q_STOP);
393 mtu3_setbits(mbase, MU3D_EP_TXCR0(epnum), TX_FLUSHFIFO);
395 ret = readl_poll_timeout_atomic(mbase + qcsr, value,
396 !(value & QMU_Q_ACTIVE), 1, 1000);
398 dev_err(mtu->dev, "stop %s's qmu failed\n", mep->name);
402 /* flush fifo again to make sure the fifo is empty */
404 mtu3_setbits(mbase, MU3D_EP_TXCR0(epnum), TX_FLUSHFIFO);
406 dev_dbg(mtu->dev, "%s's qmu stop now!\n", mep->name);
409 void mtu3_qmu_flush(struct mtu3_ep *mep)
412 dev_dbg(mep->mtu->dev, "%s flush QMU %s\n", __func__,
413 ((mep->is_in) ? "TX" : "RX"));
421 * QMU can't transfer zero length packet directly (a hardware limit
422 * on old SoCs), so when needs to send ZLP, we intentionally trigger
423 * a length error interrupt, and in the ISR sends a ZLP by BMU.
425 static void qmu_tx_zlp_error_handler(struct mtu3 *mtu, u8 epnum)
427 struct mtu3_ep *mep = mtu->in_eps + epnum;
428 struct mtu3_gpd_ring *ring = &mep->gpd_ring;
429 void __iomem *mbase = mtu->mac_base;
430 struct qmu_gpd *gpd_current = NULL;
431 struct mtu3_request *mreq;
432 dma_addr_t cur_gpd_dma;
436 mreq = next_request(mep);
437 if (mreq && mreq->request.length != 0)
440 cur_gpd_dma = read_txq_cur_addr(mbase, epnum);
441 gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
443 if (GPD_DATA_LEN(mtu, le32_to_cpu(gpd_current->dw3_info)) != 0) {
444 dev_err(mtu->dev, "TX EP%d buffer length error(!=0)\n", epnum);
448 dev_dbg(mtu->dev, "%s send ZLP for req=%p\n", __func__, mreq);
449 trace_mtu3_zlp_exp_gpd(mep, gpd_current);
451 mtu3_clrbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN);
453 ret = readl_poll_timeout_atomic(mbase + MU3D_EP_TXCR0(mep->epnum),
454 txcsr, !(txcsr & TX_FIFOFULL), 1, 1000);
456 dev_err(mtu->dev, "%s wait for fifo empty fail\n", __func__);
459 mtu3_setbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_TXPKTRDY);
460 /* prevent reorder, make sure GPD's HWO is set last */
462 /* by pass the current GDP */
463 gpd_current->dw0_info |= cpu_to_le32(GPD_FLAGS_BPS | GPD_FLAGS_HWO);
465 /*enable DMAREQEN, switch back to QMU mode */
466 mtu3_setbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN);
467 mtu3_qmu_resume(mep);
471 * when rx error happens (except zlperr), QMU will stop, and RQCPR saves
472 * the GPD encountered error, Done irq will arise after resuming QMU again.
474 static void qmu_error_rx(struct mtu3 *mtu, u8 epnum)
476 struct mtu3_ep *mep = mtu->out_eps + epnum;
477 struct mtu3_gpd_ring *ring = &mep->gpd_ring;
478 struct qmu_gpd *gpd_current = NULL;
479 struct mtu3_request *mreq;
480 dma_addr_t cur_gpd_dma;
482 cur_gpd_dma = read_rxq_cur_addr(mtu->mac_base, epnum);
483 gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
485 mreq = next_request(mep);
486 if (!mreq || mreq->gpd != gpd_current) {
487 dev_err(mtu->dev, "no correct RX req is found\n");
491 mreq->request.status = -EAGAIN;
493 /* by pass the current GDP */
494 gpd_current->dw0_info |= cpu_to_le32(GPD_FLAGS_BPS | GPD_FLAGS_HWO);
495 mtu3_qmu_resume(mep);
497 dev_dbg(mtu->dev, "%s EP%d, current=%p, req=%p\n",
498 __func__, epnum, gpd_current, mreq);
502 * NOTE: request list maybe is already empty as following case:
503 * queue_tx --> qmu_interrupt(clear interrupt pending, schedule tasklet)-->
504 * queue_tx --> process_tasklet(meanwhile, the second one is transferred,
505 * tasklet process both of them)-->qmu_interrupt for second one.
506 * To avoid upper case, put qmu_done_tx in ISR directly to process it.
508 static void qmu_done_tx(struct mtu3 *mtu, u8 epnum)
510 struct mtu3_ep *mep = mtu->in_eps + epnum;
511 struct mtu3_gpd_ring *ring = &mep->gpd_ring;
512 void __iomem *mbase = mtu->mac_base;
513 struct qmu_gpd *gpd = ring->dequeue;
514 struct qmu_gpd *gpd_current = NULL;
515 struct usb_request *request = NULL;
516 struct mtu3_request *mreq;
517 dma_addr_t cur_gpd_dma;
519 /*transfer phy address got from QMU register to virtual address */
520 cur_gpd_dma = read_txq_cur_addr(mbase, epnum);
521 gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
523 dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n",
524 __func__, epnum, gpd, gpd_current, ring->enqueue);
526 while (gpd && gpd != gpd_current && !GET_GPD_HWO(gpd)) {
528 mreq = next_request(mep);
530 if (mreq == NULL || mreq->gpd != gpd) {
531 dev_err(mtu->dev, "no correct TX req is found\n");
535 request = &mreq->request;
536 request->actual = GPD_DATA_LEN(mtu, le32_to_cpu(gpd->dw3_info));
537 trace_mtu3_complete_gpd(mep, gpd);
538 mtu3_req_complete(mep, request, 0);
540 gpd = advance_deq_gpd(ring);
543 dev_dbg(mtu->dev, "%s EP%d, deq=%p, enq=%p, complete\n",
544 __func__, epnum, ring->dequeue, ring->enqueue);
548 static void qmu_done_rx(struct mtu3 *mtu, u8 epnum)
550 struct mtu3_ep *mep = mtu->out_eps + epnum;
551 struct mtu3_gpd_ring *ring = &mep->gpd_ring;
552 void __iomem *mbase = mtu->mac_base;
553 struct qmu_gpd *gpd = ring->dequeue;
554 struct qmu_gpd *gpd_current = NULL;
555 struct usb_request *req = NULL;
556 struct mtu3_request *mreq;
557 dma_addr_t cur_gpd_dma;
559 cur_gpd_dma = read_rxq_cur_addr(mbase, epnum);
560 gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
562 dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n",
563 __func__, epnum, gpd, gpd_current, ring->enqueue);
565 while (gpd && gpd != gpd_current && !GET_GPD_HWO(gpd)) {
567 mreq = next_request(mep);
569 if (mreq == NULL || mreq->gpd != gpd) {
570 dev_err(mtu->dev, "no correct RX req is found\n");
573 req = &mreq->request;
575 req->actual = GPD_DATA_LEN(mtu, le32_to_cpu(gpd->dw3_info));
576 trace_mtu3_complete_gpd(mep, gpd);
577 mtu3_req_complete(mep, req, 0);
579 gpd = advance_deq_gpd(ring);
582 dev_dbg(mtu->dev, "%s EP%d, deq=%p, enq=%p, complete\n",
583 __func__, epnum, ring->dequeue, ring->enqueue);
586 static void qmu_done_isr(struct mtu3 *mtu, u32 done_status)
590 for (i = 1; i < mtu->num_eps; i++) {
591 if (done_status & QMU_RX_DONE_INT(i))
593 if (done_status & QMU_TX_DONE_INT(i))
598 static void qmu_exception_isr(struct mtu3 *mtu, u32 qmu_status)
600 void __iomem *mbase = mtu->mac_base;
604 if ((qmu_status & RXQ_CSERR_INT) || (qmu_status & RXQ_LENERR_INT)) {
605 errval = mtu3_readl(mbase, U3D_RQERRIR0);
606 mtu3_writel(mbase, U3D_RQERRIR0, errval);
608 for (i = 1; i < mtu->num_eps; i++) {
609 if (errval & QMU_RX_CS_ERR(i))
610 dev_err(mtu->dev, "Rx %d CS error!\n", i);
612 if (errval & QMU_RX_LEN_ERR(i))
613 dev_err(mtu->dev, "RX %d Length error\n", i);
615 if (errval & (QMU_RX_CS_ERR(i) | QMU_RX_LEN_ERR(i)))
616 qmu_error_rx(mtu, i);
620 if (qmu_status & RXQ_ZLPERR_INT) {
621 errval = mtu3_readl(mbase, U3D_RQERRIR1);
622 for (i = 1; i < mtu->num_eps; i++) {
623 if (errval & QMU_RX_ZLP_ERR(i))
624 dev_dbg(mtu->dev, "RX EP%d Recv ZLP\n", i);
626 mtu3_writel(mbase, U3D_RQERRIR1, errval);
629 if ((qmu_status & TXQ_CSERR_INT) || (qmu_status & TXQ_LENERR_INT)) {
630 errval = mtu3_readl(mbase, U3D_TQERRIR0);
631 for (i = 1; i < mtu->num_eps; i++) {
632 if (errval & QMU_TX_CS_ERR(i))
633 dev_err(mtu->dev, "Tx %d checksum error!\n", i);
635 if (errval & QMU_TX_LEN_ERR(i))
636 qmu_tx_zlp_error_handler(mtu, i);
638 mtu3_writel(mbase, U3D_TQERRIR0, errval);
642 irqreturn_t mtu3_qmu_isr(struct mtu3 *mtu)
644 void __iomem *mbase = mtu->mac_base;
648 /* U3D_QISAR1 is read update */
649 qmu_status = mtu3_readl(mbase, U3D_QISAR1);
650 qmu_status &= mtu3_readl(mbase, U3D_QIER1);
652 qmu_done_status = mtu3_readl(mbase, U3D_QISAR0);
653 qmu_done_status &= mtu3_readl(mbase, U3D_QIER0);
654 mtu3_writel(mbase, U3D_QISAR0, qmu_done_status); /* W1C */
655 dev_dbg(mtu->dev, "=== QMUdone[tx=%x, rx=%x] QMUexp[%x] ===\n",
656 (qmu_done_status & 0xFFFF), qmu_done_status >> 16,
658 trace_mtu3_qmu_isr(qmu_done_status, qmu_status);
661 qmu_done_isr(mtu, qmu_done_status);
664 qmu_exception_isr(mtu, qmu_status);
669 int mtu3_qmu_init(struct mtu3 *mtu)
672 compiletime_assert(QMU_GPD_SIZE == 16, "QMU_GPD size SHOULD be 16B");
674 mtu->qmu_gpd_pool = dma_pool_create("QMU_GPD", mtu->dev,
675 QMU_GPD_RING_SIZE, QMU_GPD_SIZE, 0);
677 if (!mtu->qmu_gpd_pool)
683 void mtu3_qmu_exit(struct mtu3 *mtu)
685 dma_pool_destroy(mtu->qmu_gpd_pool);