1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mtu3_hw_regs.h - MediaTek USB3 DRD register and field definitions
5 * Copyright (C) 2016 MediaTek Inc.
7 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
10 #ifndef _SSUSB_HW_REGS_H_
11 #define _SSUSB_HW_REGS_H_
13 /* segment offset of MAC register */
14 #define SSUSB_DEV_BASE 0x0000
15 #define SSUSB_EPCTL_CSR_BASE 0x0800
16 #define SSUSB_USB3_MAC_CSR_BASE 0x1400
17 #define SSUSB_USB3_SYS_CSR_BASE 0x1400
18 #define SSUSB_USB2_CSR_BASE 0x2400
20 /* IPPC register in Infra */
21 #define SSUSB_SIFSLV_IPPC_BASE 0x0000
23 /* --------------- SSUSB_DEV REGISTER DEFINITION --------------- */
25 #define U3D_LV1ISR (SSUSB_DEV_BASE + 0x0000)
26 #define U3D_LV1IER (SSUSB_DEV_BASE + 0x0004)
27 #define U3D_LV1IESR (SSUSB_DEV_BASE + 0x0008)
28 #define U3D_LV1IECR (SSUSB_DEV_BASE + 0x000C)
30 #define U3D_EPISR (SSUSB_DEV_BASE + 0x0080)
31 #define U3D_EPIER (SSUSB_DEV_BASE + 0x0084)
32 #define U3D_EPIESR (SSUSB_DEV_BASE + 0x0088)
33 #define U3D_EPIECR (SSUSB_DEV_BASE + 0x008C)
35 #define U3D_EP0CSR (SSUSB_DEV_BASE + 0x0100)
36 #define U3D_RXCOUNT0 (SSUSB_DEV_BASE + 0x0108)
37 #define U3D_RESERVED (SSUSB_DEV_BASE + 0x010C)
38 #define U3D_TX1CSR0 (SSUSB_DEV_BASE + 0x0110)
39 #define U3D_TX1CSR1 (SSUSB_DEV_BASE + 0x0114)
40 #define U3D_TX1CSR2 (SSUSB_DEV_BASE + 0x0118)
42 #define U3D_RX1CSR0 (SSUSB_DEV_BASE + 0x0210)
43 #define U3D_RX1CSR1 (SSUSB_DEV_BASE + 0x0214)
44 #define U3D_RX1CSR2 (SSUSB_DEV_BASE + 0x0218)
46 #define U3D_FIFO0 (SSUSB_DEV_BASE + 0x0300)
48 #define U3D_QCR0 (SSUSB_DEV_BASE + 0x0400)
49 #define U3D_QCR1 (SSUSB_DEV_BASE + 0x0404)
50 #define U3D_QCR2 (SSUSB_DEV_BASE + 0x0408)
51 #define U3D_QCR3 (SSUSB_DEV_BASE + 0x040C)
52 #define U3D_QFCR (SSUSB_DEV_BASE + 0x0428)
53 #define U3D_TXQHIAR1 (SSUSB_DEV_BASE + 0x0484)
54 #define U3D_RXQHIAR1 (SSUSB_DEV_BASE + 0x04C4)
56 #define U3D_TXQCSR1 (SSUSB_DEV_BASE + 0x0510)
57 #define U3D_TXQSAR1 (SSUSB_DEV_BASE + 0x0514)
58 #define U3D_TXQCPR1 (SSUSB_DEV_BASE + 0x0518)
60 #define U3D_RXQCSR1 (SSUSB_DEV_BASE + 0x0610)
61 #define U3D_RXQSAR1 (SSUSB_DEV_BASE + 0x0614)
62 #define U3D_RXQCPR1 (SSUSB_DEV_BASE + 0x0618)
63 #define U3D_RXQLDPR1 (SSUSB_DEV_BASE + 0x061C)
65 #define U3D_QISAR0 (SSUSB_DEV_BASE + 0x0700)
66 #define U3D_QIER0 (SSUSB_DEV_BASE + 0x0704)
67 #define U3D_QIESR0 (SSUSB_DEV_BASE + 0x0708)
68 #define U3D_QIECR0 (SSUSB_DEV_BASE + 0x070C)
69 #define U3D_QISAR1 (SSUSB_DEV_BASE + 0x0710)
70 #define U3D_QIER1 (SSUSB_DEV_BASE + 0x0714)
71 #define U3D_QIESR1 (SSUSB_DEV_BASE + 0x0718)
72 #define U3D_QIECR1 (SSUSB_DEV_BASE + 0x071C)
74 #define U3D_TQERRIR0 (SSUSB_DEV_BASE + 0x0780)
75 #define U3D_TQERRIER0 (SSUSB_DEV_BASE + 0x0784)
76 #define U3D_TQERRIESR0 (SSUSB_DEV_BASE + 0x0788)
77 #define U3D_TQERRIECR0 (SSUSB_DEV_BASE + 0x078C)
78 #define U3D_RQERRIR0 (SSUSB_DEV_BASE + 0x07C0)
79 #define U3D_RQERRIER0 (SSUSB_DEV_BASE + 0x07C4)
80 #define U3D_RQERRIESR0 (SSUSB_DEV_BASE + 0x07C8)
81 #define U3D_RQERRIECR0 (SSUSB_DEV_BASE + 0x07CC)
82 #define U3D_RQERRIR1 (SSUSB_DEV_BASE + 0x07D0)
83 #define U3D_RQERRIER1 (SSUSB_DEV_BASE + 0x07D4)
84 #define U3D_RQERRIESR1 (SSUSB_DEV_BASE + 0x07D8)
85 #define U3D_RQERRIECR1 (SSUSB_DEV_BASE + 0x07DC)
87 #define U3D_CAP_EP0FFSZ (SSUSB_DEV_BASE + 0x0C04)
88 #define U3D_CAP_EPNTXFFSZ (SSUSB_DEV_BASE + 0x0C08)
89 #define U3D_CAP_EPNRXFFSZ (SSUSB_DEV_BASE + 0x0C0C)
90 #define U3D_CAP_EPINFO (SSUSB_DEV_BASE + 0x0C10)
91 #define U3D_MISC_CTRL (SSUSB_DEV_BASE + 0x0C84)
93 /*---------------- SSUSB_DEV FIELD DEFINITION ---------------*/
96 #define EP_CTRL_INTR BIT(5)
97 #define MAC2_INTR BIT(4)
98 #define DMA_INTR BIT(3)
99 #define MAC3_INTR BIT(2)
100 #define QMU_INTR BIT(1)
101 #define BMU_INTR BIT(0)
104 #define LV1IECR_MSK GENMASK(31, 0)
107 #define EPRISR(x) (BIT(16) << (x))
108 #define SETUPENDISR BIT(16)
109 #define EPTISR(x) (BIT(0) << (x))
110 #define EP0ISR BIT(0)
113 #define EP0_SENDSTALL BIT(25)
114 #define EP0_FIFOFULL BIT(23)
115 #define EP0_SENTSTALL BIT(22)
116 #define EP0_DPHTX BIT(20)
117 #define EP0_DATAEND BIT(19)
118 #define EP0_TXPKTRDY BIT(18)
119 #define EP0_SETUPPKTRDY BIT(17)
120 #define EP0_RXPKTRDY BIT(16)
121 #define EP0_MAXPKTSZ_MSK GENMASK(9, 0)
122 #define EP0_MAXPKTSZ(x) ((x) & EP0_MAXPKTSZ_MSK)
123 #define EP0_W1C_BITS (~(EP0_RXPKTRDY | EP0_SETUPPKTRDY | EP0_SENTSTALL))
126 #define TX_DMAREQEN BIT(29)
127 #define TX_FIFOFULL BIT(25)
128 #define TX_FIFOEMPTY BIT(24)
129 #define TX_SENTSTALL BIT(22)
130 #define TX_SENDSTALL BIT(21)
131 #define TX_TXPKTRDY BIT(16)
132 #define TX_TXMAXPKTSZ_MSK GENMASK(10, 0)
133 #define TX_TXMAXPKTSZ(x) ((x) & TX_TXMAXPKTSZ_MSK)
134 #define TX_W1C_BITS (~(TX_SENTSTALL))
137 #define TX_MAX_PKT_G2(x) (((x) & 0xff) << 24)
138 #define TX_MULT_G2(x) (((x) & 0x7) << 21)
139 #define TX_MULT_OG(x) (((x) & 0x3) << 22)
140 #define TX_MAX_PKT_OG(x) (((x) & 0x3f) << 16)
141 #define TX_SLOT(x) (((x) & 0x3f) << 8)
142 #define TX_TYPE(x) (((x) & 0x3) << 4)
143 #define TX_SS_BURST(x) (((x) & 0xf) << 0)
144 #define TX_MULT(g2c, x) \
146 typeof(x) x_ = (x); \
147 (g2c) ? TX_MULT_G2(x_) : TX_MULT_OG(x_); \
149 #define TX_MAX_PKT(g2c, x) \
151 typeof(x) x_ = (x); \
152 (g2c) ? TX_MAX_PKT_G2(x_) : TX_MAX_PKT_OG(x_); \
155 /* for TX_TYPE & RX_TYPE */
156 #define TYPE_BULK (0x0)
157 #define TYPE_INT (0x1)
158 #define TYPE_ISO (0x2)
159 #define TYPE_MASK (0x3)
162 #define TX_BINTERVAL(x) (((x) & 0xff) << 24)
163 #define TX_FIFOSEGSIZE(x) (((x) & 0xf) << 16)
164 #define TX_FIFOADDR(x) (((x) & 0x1fff) << 0)
167 #define RX_DMAREQEN BIT(29)
168 #define RX_SENTSTALL BIT(22)
169 #define RX_SENDSTALL BIT(21)
170 #define RX_RXPKTRDY BIT(16)
171 #define RX_RXMAXPKTSZ_MSK GENMASK(10, 0)
172 #define RX_RXMAXPKTSZ(x) ((x) & RX_RXMAXPKTSZ_MSK)
173 #define RX_W1C_BITS (~(RX_SENTSTALL | RX_RXPKTRDY))
176 #define RX_MAX_PKT_G2(x) (((x) & 0xff) << 24)
177 #define RX_MULT_G2(x) (((x) & 0x7) << 21)
178 #define RX_MULT_OG(x) (((x) & 0x3) << 22)
179 #define RX_MAX_PKT_OG(x) (((x) & 0x3f) << 16)
180 #define RX_SLOT(x) (((x) & 0x3f) << 8)
181 #define RX_TYPE(x) (((x) & 0x3) << 4)
182 #define RX_SS_BURST(x) (((x) & 0xf) << 0)
183 #define RX_MULT(g2c, x) \
185 typeof(x) x_ = (x); \
186 (g2c) ? RX_MULT_G2(x_) : RX_MULT_OG(x_); \
188 #define RX_MAX_PKT(g2c, x) \
190 typeof(x) x_ = (x); \
191 (g2c) ? RX_MAX_PKT_G2(x_) : RX_MAX_PKT_OG(x_); \
195 #define RX_BINTERVAL(x) (((x) & 0xff) << 24)
196 #define RX_FIFOSEGSIZE(x) (((x) & 0xf) << 16)
197 #define RX_FIFOADDR(x) (((x) & 0x1fff) << 0)
200 #define QMU_RX_CS_EN(x) (BIT(16) << (x))
201 #define QMU_TX_CS_EN(x) (BIT(0) << (x))
202 #define QMU_CS16B_EN BIT(0)
205 #define QMU_TX_ZLP(x) (BIT(0) << (x))
208 #define QMU_RX_COZ(x) (BIT(16) << (x))
209 #define QMU_RX_ZLP(x) (BIT(0) << (x))
213 #define QMU_LAST_DONE_PTR_HI(x) (((x) >> 16) & 0xf)
214 #define QMU_CUR_GPD_ADDR_HI(x) (((x) >> 8) & 0xf)
215 #define QMU_START_ADDR_HI_MSK GENMASK(3, 0)
216 #define QMU_START_ADDR_HI(x) (((x) & 0xf) << 0)
220 #define QMU_Q_ACTIVE BIT(15)
221 #define QMU_Q_STOP BIT(2)
222 #define QMU_Q_RESUME BIT(1)
223 #define QMU_Q_START BIT(0)
225 /* U3D_QISAR0, U3D_QIER0, U3D_QIESR0, U3D_QIECR0 */
226 #define QMU_RX_DONE_INT(x) (BIT(16) << (x))
227 #define QMU_TX_DONE_INT(x) (BIT(0) << (x))
229 /* U3D_QISAR1, U3D_QIER1, U3D_QIESR1, U3D_QIECR1 */
230 #define RXQ_ZLPERR_INT BIT(20)
231 #define RXQ_LENERR_INT BIT(18)
232 #define RXQ_CSERR_INT BIT(17)
233 #define RXQ_EMPTY_INT BIT(16)
234 #define TXQ_LENERR_INT BIT(2)
235 #define TXQ_CSERR_INT BIT(1)
236 #define TXQ_EMPTY_INT BIT(0)
238 /* U3D_TQERRIR0, U3D_TQERRIER0, U3D_TQERRIESR0, U3D_TQERRIECR0 */
239 #define QMU_TX_LEN_ERR(x) (BIT(16) << (x))
240 #define QMU_TX_CS_ERR(x) (BIT(0) << (x))
242 /* U3D_RQERRIR0, U3D_RQERRIER0, U3D_RQERRIESR0, U3D_RQERRIECR0 */
243 #define QMU_RX_LEN_ERR(x) (BIT(16) << (x))
244 #define QMU_RX_CS_ERR(x) (BIT(0) << (x))
246 /* U3D_RQERRIR1, U3D_RQERRIER1, U3D_RQERRIESR1, U3D_RQERRIECR1 */
247 #define QMU_RX_ZLP_ERR(n) (BIT(16) << (n))
250 #define CAP_RX_EP_NUM(x) (((x) >> 8) & 0x1f)
251 #define CAP_TX_EP_NUM(x) ((x) & 0x1f)
254 #define DMA_ADDR_36BIT BIT(31)
255 #define VBUS_ON BIT(1)
256 #define VBUS_FRC_EN BIT(0)
259 /*---------------- SSUSB_EPCTL_CSR REGISTER DEFINITION ----------------*/
261 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
262 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
264 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
265 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
267 /*---------------- SSUSB_EPCTL_CSR FIELD DEFINITION ----------------*/
269 /* U3D_DEVICE_CONF */
270 #define DEV_ADDR_MSK GENMASK(30, 24)
271 #define DEV_ADDR(x) ((0x7f & (x)) << 24)
272 #define HW_USB2_3_SEL BIT(18)
273 #define SW_USB2_3_SEL_EN BIT(17)
274 #define SW_USB2_3_SEL BIT(16)
275 #define SSUSB_DEV_SPEED(x) ((x) & 0x7)
278 #define EP1_IN_RST BIT(17)
279 #define EP1_OUT_RST BIT(1)
280 #define EP_RST(is_in, epnum) (((is_in) ? BIT(16) : BIT(0)) << (epnum))
281 #define EP0_RST BIT(0)
283 /* U3D_DEV_LINK_INTR_ENABLE */
284 /* U3D_DEV_LINK_INTR */
285 #define SSUSB_DEV_SPEED_CHG_INTR BIT(0)
288 /*---------------- SSUSB_USB3_MAC_CSR REGISTER DEFINITION ----------------*/
290 #define U3D_LTSSM_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0010)
291 #define U3D_USB3_CONFIG (SSUSB_USB3_MAC_CSR_BASE + 0x001C)
293 #define U3D_LINK_STATE_MACHINE (SSUSB_USB3_MAC_CSR_BASE + 0x0134)
294 #define U3D_LTSSM_INTR_ENABLE (SSUSB_USB3_MAC_CSR_BASE + 0x013C)
295 #define U3D_LTSSM_INTR (SSUSB_USB3_MAC_CSR_BASE + 0x0140)
297 #define U3D_U3U2_SWITCH_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0170)
299 /*---------------- SSUSB_USB3_MAC_CSR FIELD DEFINITION ----------------*/
302 #define FORCE_POLLING_FAIL BIT(4)
303 #define FORCE_RXDETECT_FAIL BIT(3)
304 #define SOFT_U3_EXIT_EN BIT(2)
305 #define COMPLIANCE_EN BIT(1)
306 #define U1_GO_U2_EN BIT(0)
308 /* U3D_USB3_CONFIG */
309 #define USB3_EN BIT(0)
311 /* U3D_LINK_STATE_MACHINE */
312 #define LTSSM_STATE(x) ((x) & 0x1f)
314 /* U3D_LTSSM_INTR_ENABLE */
316 #define U3_RESUME_INTR BIT(18)
317 #define U3_LFPS_TMOUT_INTR BIT(17)
318 #define VBUS_FALL_INTR BIT(16)
319 #define VBUS_RISE_INTR BIT(15)
320 #define RXDET_SUCCESS_INTR BIT(14)
321 #define EXIT_U3_INTR BIT(13)
322 #define EXIT_U2_INTR BIT(12)
323 #define EXIT_U1_INTR BIT(11)
324 #define ENTER_U3_INTR BIT(10)
325 #define ENTER_U2_INTR BIT(9)
326 #define ENTER_U1_INTR BIT(8)
327 #define ENTER_U0_INTR BIT(7)
328 #define RECOVERY_INTR BIT(6)
329 #define WARM_RST_INTR BIT(5)
330 #define HOT_RST_INTR BIT(4)
331 #define LOOPBACK_INTR BIT(3)
332 #define COMPLIANCE_INTR BIT(2)
333 #define SS_DISABLE_INTR BIT(1)
334 #define SS_INACTIVE_INTR BIT(0)
336 /* U3D_U3U2_SWITCH_CTRL */
337 #define SOFTCON_CLR_AUTO_EN BIT(0)
339 /*---------------- SSUSB_USB3_SYS_CSR REGISTER DEFINITION ----------------*/
341 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
342 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
343 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
345 /*---------------- SSUSB_USB3_SYS_CSR FIELD DEFINITION ----------------*/
347 /* U3D_LINK_UX_INACT_TIMER */
348 #define DEV_U2_INACT_TIMEOUT_MSK GENMASK(23, 16)
349 #define DEV_U2_INACT_TIMEOUT_VALUE(x) (((x) & 0xff) << 16)
350 #define U2_INACT_TIMEOUT_MSK GENMASK(15, 8)
351 #define U1_INACT_TIMEOUT_MSK GENMASK(7, 0)
352 #define U1_INACT_TIMEOUT_VALUE(x) ((x) & 0xff)
354 /* U3D_LINK_POWER_CONTROL */
355 #define SW_U2_ACCEPT_ENABLE BIT(9)
356 #define SW_U1_ACCEPT_ENABLE BIT(8)
357 #define UX_EXIT BIT(5)
358 #define LGO_U3 BIT(4)
359 #define LGO_U2 BIT(3)
360 #define LGO_U1 BIT(2)
361 #define SW_U2_REQUEST_ENABLE BIT(1)
362 #define SW_U1_REQUEST_ENABLE BIT(0)
364 /* U3D_LINK_ERR_COUNT */
365 #define CLR_LINK_ERR_CNT BIT(16)
366 #define LINK_ERROR_COUNT GENMASK(15, 0)
368 /*---------------- SSUSB_USB2_CSR REGISTER DEFINITION ----------------*/
370 #define U3D_POWER_MANAGEMENT (SSUSB_USB2_CSR_BASE + 0x0004)
371 #define U3D_DEVICE_CONTROL (SSUSB_USB2_CSR_BASE + 0x000C)
372 #define U3D_USB2_TEST_MODE (SSUSB_USB2_CSR_BASE + 0x0014)
373 #define U3D_COMMON_USB_INTR_ENABLE (SSUSB_USB2_CSR_BASE + 0x0018)
374 #define U3D_COMMON_USB_INTR (SSUSB_USB2_CSR_BASE + 0x001C)
375 #define U3D_LINK_RESET_INFO (SSUSB_USB2_CSR_BASE + 0x0024)
376 #define U3D_USB20_FRAME_NUM (SSUSB_USB2_CSR_BASE + 0x003C)
377 #define U3D_USB20_LPM_PARAMETER (SSUSB_USB2_CSR_BASE + 0x0044)
378 #define U3D_USB20_MISC_CONTROL (SSUSB_USB2_CSR_BASE + 0x004C)
379 #define U3D_USB20_OPSTATE (SSUSB_USB2_CSR_BASE + 0x0060)
381 /*---------------- SSUSB_USB2_CSR FIELD DEFINITION ----------------*/
383 /* U3D_POWER_MANAGEMENT */
384 #define LPM_BESL_STALL BIT(14)
385 #define LPM_BESLD_STALL BIT(13)
386 #define LPM_RWP BIT(11)
387 #define LPM_HRWE BIT(10)
388 #define LPM_MODE(x) (((x) & 0x3) << 8)
389 #define ISO_UPDATE BIT(7)
390 #define SOFT_CONN BIT(6)
391 #define HS_ENABLE BIT(5)
392 #define RESUME BIT(2)
393 #define SUSPENDM_ENABLE BIT(0)
395 /* U3D_DEVICE_CONTROL */
396 #define DC_HOSTREQ BIT(1)
397 #define DC_SESSION BIT(0)
399 /* U3D_USB2_TEST_MODE */
400 #define U2U3_AUTO_SWITCH BIT(10)
401 #define LPM_FORCE_STALL BIT(8)
402 #define FIFO_ACCESS BIT(6)
403 #define FORCE_FS BIT(5)
404 #define FORCE_HS BIT(4)
405 #define TEST_PACKET_MODE BIT(3)
406 #define TEST_K_MODE BIT(2)
407 #define TEST_J_MODE BIT(1)
408 #define TEST_SE0_NAK_MODE BIT(0)
410 /* U3D_COMMON_USB_INTR_ENABLE */
411 /* U3D_COMMON_USB_INTR */
412 #define LPM_RESUME_INTR BIT(9)
413 #define LPM_INTR BIT(8)
414 #define DISCONN_INTR BIT(5)
415 #define CONN_INTR BIT(4)
416 #define SOF_INTR BIT(3)
417 #define RESET_INTR BIT(2)
418 #define RESUME_INTR BIT(1)
419 #define SUSPEND_INTR BIT(0)
421 /* U3D_LINK_RESET_INFO */
422 #define WTCHRP_MSK GENMASK(19, 16)
424 /* U3D_USB20_LPM_PARAMETER */
425 #define LPM_BESLCK_U3(x) (((x) & 0xf) << 12)
426 #define LPM_BESLCK(x) (((x) & 0xf) << 8)
427 #define LPM_BESLDCK(x) (((x) & 0xf) << 4)
428 #define LPM_BESL GENMASK(3, 0)
430 /* U3D_USB20_MISC_CONTROL */
431 #define LPM_U3_ACK_EN BIT(0)
433 /*---------------- SSUSB_SIFSLV_IPPC REGISTER DEFINITION ----------------*/
435 #define U3D_SSUSB_IP_PW_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x0000)
436 #define U3D_SSUSB_IP_PW_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x0004)
437 #define U3D_SSUSB_IP_PW_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x0008)
438 #define U3D_SSUSB_IP_PW_CTRL3 (SSUSB_SIFSLV_IPPC_BASE + 0x000C)
439 #define U3D_SSUSB_IP_PW_STS1 (SSUSB_SIFSLV_IPPC_BASE + 0x0010)
440 #define U3D_SSUSB_IP_PW_STS2 (SSUSB_SIFSLV_IPPC_BASE + 0x0014)
441 #define U3D_SSUSB_OTG_STS (SSUSB_SIFSLV_IPPC_BASE + 0x0018)
442 #define U3D_SSUSB_OTG_STS_CLR (SSUSB_SIFSLV_IPPC_BASE + 0x001C)
443 #define U3D_SSUSB_IP_XHCI_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0024)
444 #define U3D_SSUSB_IP_DEV_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0028)
445 #define U3D_SSUSB_OTG_INT_EN (SSUSB_SIFSLV_IPPC_BASE + 0x002C)
446 #define U3D_SSUSB_U3_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0030)
447 #define U3D_SSUSB_U2_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0050)
448 #define U3D_SSUSB_REF_CK_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x008C)
449 #define U3D_SSUSB_DEV_RST_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x0098)
450 #define U3D_SSUSB_HW_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A0)
451 #define U3D_SSUSB_HW_SUB_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A4)
452 #define U3D_SSUSB_IP_TRUNK_VERS (U3D_SSUSB_HW_SUB_ID)
453 #define U3D_SSUSB_PRB_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x00B0)
454 #define U3D_SSUSB_PRB_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x00B4)
455 #define U3D_SSUSB_PRB_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x00B8)
456 #define U3D_SSUSB_PRB_CTRL3 (SSUSB_SIFSLV_IPPC_BASE + 0x00BC)
457 #define U3D_SSUSB_PRB_CTRL4 (SSUSB_SIFSLV_IPPC_BASE + 0x00C0)
458 #define U3D_SSUSB_PRB_CTRL5 (SSUSB_SIFSLV_IPPC_BASE + 0x00C4)
459 #define U3D_SSUSB_IP_SPARE0 (SSUSB_SIFSLV_IPPC_BASE + 0x00C8)
461 /*---------------- SSUSB_SIFSLV_IPPC FIELD DEFINITION ----------------*/
463 /* U3D_SSUSB_IP_PW_CTRL0 */
464 #define SSUSB_IP_SW_RST BIT(0)
466 /* U3D_SSUSB_IP_PW_CTRL1 */
467 #define SSUSB_IP_HOST_PDN BIT(0)
469 /* U3D_SSUSB_IP_PW_CTRL2 */
470 #define SSUSB_IP_DEV_PDN BIT(0)
472 /* U3D_SSUSB_IP_PW_CTRL3 */
473 #define SSUSB_IP_PCIE_PDN BIT(0)
475 /* U3D_SSUSB_IP_PW_STS1 */
476 #define SSUSB_IP_SLEEP_STS BIT(30)
477 #define SSUSB_U3_MAC_RST_B_STS BIT(16)
478 #define SSUSB_XHCI_RST_B_STS BIT(11)
479 #define SSUSB_SYS125_RST_B_STS BIT(10)
480 #define SSUSB_REF_RST_B_STS BIT(8)
481 #define SSUSB_SYSPLL_STABLE BIT(0)
483 /* U3D_SSUSB_IP_PW_STS2 */
484 #define SSUSB_U2_MAC_SYS_RST_B_STS BIT(0)
486 /* U3D_SSUSB_OTG_STS */
487 #define SSUSB_VBUS_VALID BIT(9)
489 /* U3D_SSUSB_OTG_STS_CLR */
490 #define SSUSB_VBUS_INTR_CLR BIT(6)
492 /* U3D_SSUSB_IP_XHCI_CAP */
493 #define SSUSB_IP_XHCI_U2_PORT_NUM(x) (((x) >> 8) & 0xff)
494 #define SSUSB_IP_XHCI_U3_PORT_NUM(x) ((x) & 0xff)
496 /* U3D_SSUSB_IP_DEV_CAP */
497 #define SSUSB_IP_DEV_U3_PORT_NUM(x) ((x) & 0xff)
499 /* U3D_SSUSB_OTG_INT_EN */
500 #define SSUSB_VBUS_CHG_INT_A_EN BIT(7)
501 #define SSUSB_VBUS_CHG_INT_B_EN BIT(6)
503 /* U3D_SSUSB_U3_CTRL_0P */
504 #define SSUSB_U3_PORT_SSP_SPEED BIT(9)
505 #define SSUSB_U3_PORT_DUAL_MODE BIT(7)
506 #define SSUSB_U3_PORT_HOST_SEL BIT(2)
507 #define SSUSB_U3_PORT_PDN BIT(1)
508 #define SSUSB_U3_PORT_DIS BIT(0)
510 /* U3D_SSUSB_U2_CTRL_0P */
511 #define SSUSB_U2_PORT_RG_IDDIG BIT(12)
512 #define SSUSB_U2_PORT_FORCE_IDDIG BIT(11)
513 #define SSUSB_U2_PORT_VBUSVALID BIT(9)
514 #define SSUSB_U2_PORT_OTG_SEL BIT(7)
515 #define SSUSB_U2_PORT_HOST BIT(2)
516 #define SSUSB_U2_PORT_PDN BIT(1)
517 #define SSUSB_U2_PORT_DIS BIT(0)
518 #define SSUSB_U2_PORT_HOST_SEL (SSUSB_U2_PORT_VBUSVALID | SSUSB_U2_PORT_HOST)
520 /* U3D_SSUSB_DEV_RST_CTRL */
521 #define SSUSB_DEV_SW_RST BIT(0)
523 /* U3D_SSUSB_IP_TRUNK_VERS */
524 #define IP_TRUNK_VERS(x) (((x) >> 16) & 0xffff)
526 #endif /* _SSUSB_HW_REGS_H_ */
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