1 /* SPDX-License-Identifier: GPL-2.0 */
4 * xHCI host controller driver
6 * Copyright (C) 2008 Intel Corp.
9 * Some code borrowed from the Linux EHCI driver.
12 #ifndef __LINUX_XHCI_HCD_H
13 #define __LINUX_XHCI_HCD_H
15 #include <linux/usb.h>
16 #include <linux/timer.h>
17 #include <linux/kernel.h>
18 #include <linux/usb/hcd.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
21 /* Code sharing between pci-quirks and xhci hcd */
22 #include "xhci-ext-caps.h"
23 #include "pci-quirks.h"
25 /* max buffer size for trace and debug messages */
26 #define XHCI_MSG_MAX 500
28 /* xHCI PCI Configuration Registers */
29 #define XHCI_SBRN_OFFSET (0x60)
31 /* Max number of USB devices for any host controller - limit in section 6.1 */
32 #define MAX_HC_SLOTS 256
33 /* Section 5.3.3 - MaxPorts */
34 #define MAX_HC_PORTS 127
37 * xHCI register interface.
38 * This corresponds to the eXtensible Host Controller Interface (xHCI)
39 * Revision 0.95 specification
43 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
44 * @hc_capbase: length of the capabilities register and HC version number
45 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
46 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
47 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
48 * @hcc_params: HCCPARAMS - Capability Parameters
49 * @db_off: DBOFF - Doorbell array offset
50 * @run_regs_off: RTSOFF - Runtime register space offset
51 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
53 struct xhci_cap_regs {
61 __le32 hcc_params2; /* xhci 1.1 */
62 /* Reserved up to (CAPLENGTH - 0x1C) */
65 /* hc_capbase bitmasks */
66 /* bits 7:0 - how long is the Capabilities register */
67 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
69 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
71 /* HCSPARAMS1 - hcs_params1 - bitmasks */
72 /* bits 0:7, Max Device Slots */
73 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
74 #define HCS_SLOTS_MASK 0xff
75 /* bits 8:18, Max Interrupters */
76 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
77 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
78 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
80 /* HCSPARAMS2 - hcs_params2 - bitmasks */
81 /* bits 0:3, frames or uframes that SW needs to queue transactions
82 * ahead of the HW to meet periodic deadlines */
83 #define HCS_IST(p) (((p) >> 0) & 0xf)
84 /* bits 4:7, max number of Event Ring segments */
85 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
86 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
87 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
88 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
89 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
91 /* HCSPARAMS3 - hcs_params3 - bitmasks */
92 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
93 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
94 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
95 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
97 /* HCCPARAMS - hcc_params - bitmasks */
98 /* true: HC can use 64-bit address pointers */
99 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
100 /* true: HC can do bandwidth negotiation */
101 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
102 /* true: HC uses 64-byte Device Context structures
103 * FIXME 64-byte context structures aren't supported yet.
105 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
106 /* true: HC has port power switches */
107 #define HCC_PPC(p) ((p) & (1 << 3))
108 /* true: HC has port indicators */
109 #define HCS_INDICATOR(p) ((p) & (1 << 4))
110 /* true: HC has Light HC Reset Capability */
111 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
112 /* true: HC supports latency tolerance messaging */
113 #define HCC_LTC(p) ((p) & (1 << 6))
114 /* true: no secondary Stream ID Support */
115 #define HCC_NSS(p) ((p) & (1 << 7))
116 /* true: HC supports Stopped - Short Packet */
117 #define HCC_SPC(p) ((p) & (1 << 9))
118 /* true: HC has Contiguous Frame ID Capability */
119 #define HCC_CFC(p) ((p) & (1 << 11))
120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
121 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
123 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
125 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
127 /* db_off bitmask - bits 0:1 reserved */
128 #define DBOFF_MASK (~0x3)
130 /* run_regs_off bitmask - bits 0:4 reserved */
131 #define RTSOFF_MASK (~0x1f)
133 /* HCCPARAMS2 - hcc_params2 - bitmasks */
134 /* true: HC supports U3 entry Capability */
135 #define HCC2_U3C(p) ((p) & (1 << 0))
136 /* true: HC supports Configure endpoint command Max exit latency too large */
137 #define HCC2_CMC(p) ((p) & (1 << 1))
138 /* true: HC supports Force Save context Capability */
139 #define HCC2_FSC(p) ((p) & (1 << 2))
140 /* true: HC supports Compliance Transition Capability */
141 #define HCC2_CTC(p) ((p) & (1 << 3))
142 /* true: HC support Large ESIT payload Capability > 48k */
143 #define HCC2_LEC(p) ((p) & (1 << 4))
144 /* true: HC support Configuration Information Capability */
145 #define HCC2_CIC(p) ((p) & (1 << 5))
146 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
147 #define HCC2_ETC(p) ((p) & (1 << 6))
149 /* Number of registers per port */
150 #define NUM_PORT_REGS 4
158 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
159 * @command: USBCMD - xHC command register
160 * @status: USBSTS - xHC status register
161 * @page_size: This indicates the page size that the host controller
162 * supports. If bit n is set, the HC supports a page size
163 * of 2^(n+12), up to a 128MB page size.
164 * 4K is the minimum page size.
165 * @cmd_ring: CRP - 64-bit Command Ring Pointer
166 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
167 * @config_reg: CONFIG - Configure Register
168 * @port_status_base: PORTSCn - base address for Port Status and Control
169 * Each port has a Port Status and Control register,
170 * followed by a Port Power Management Status and Control
171 * register, a Port Link Info register, and a reserved
173 * @port_power_base: PORTPMSCn - base address for
174 * Port Power Management Status and Control
175 * @port_link_base: PORTLIn - base address for Port Link Info (current
176 * Link PM state and control) for USB 2.1 and USB 3.0
179 struct xhci_op_regs {
185 __le32 dev_notification;
187 /* rsvd: offset 0x20-2F */
191 /* rsvd: offset 0x3C-3FF */
192 __le32 reserved4[241];
193 /* port 1 registers, which serve as a base address for other ports */
194 __le32 port_status_base;
195 __le32 port_power_base;
196 __le32 port_link_base;
198 /* registers for ports 2-255 */
199 __le32 reserved6[NUM_PORT_REGS*254];
202 /* USBCMD - USB command - command bitmasks */
203 /* start/stop HC execution - do not write unless HC is halted*/
204 #define CMD_RUN XHCI_CMD_RUN
205 /* Reset HC - resets internal HC state machine and all registers (except
206 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
207 * The xHCI driver must reinitialize the xHC after setting this bit.
209 #define CMD_RESET (1 << 1)
210 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
211 #define CMD_EIE XHCI_CMD_EIE
212 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
213 #define CMD_HSEIE XHCI_CMD_HSEIE
214 /* bits 4:6 are reserved (and should be preserved on writes). */
215 /* light reset (port status stays unchanged) - reset completed when this is 0 */
216 #define CMD_LRESET (1 << 7)
217 /* host controller save/restore state. */
218 #define CMD_CSS (1 << 8)
219 #define CMD_CRS (1 << 9)
220 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
221 #define CMD_EWE XHCI_CMD_EWE
222 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
223 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
224 * '0' means the xHC can power it off if all ports are in the disconnect,
225 * disabled, or powered-off state.
227 #define CMD_PM_INDEX (1 << 11)
228 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
229 #define CMD_ETE (1 << 14)
230 /* bits 15:31 are reserved (and should be preserved on writes). */
232 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
233 #define XHCI_RESET_SHORT_USEC (250 * 1000)
235 /* IMAN - Interrupt Management Register */
236 #define IMAN_IE (1 << 1)
237 #define IMAN_IP (1 << 0)
239 /* USBSTS - USB status - status bitmasks */
240 /* HC not running - set to 1 when run/stop bit is cleared. */
241 #define STS_HALT XHCI_STS_HALT
242 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
243 #define STS_FATAL (1 << 2)
244 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
245 #define STS_EINT (1 << 3)
246 /* port change detect */
247 #define STS_PORT (1 << 4)
248 /* bits 5:7 reserved and zeroed */
249 /* save state status - '1' means xHC is saving state */
250 #define STS_SAVE (1 << 8)
251 /* restore state status - '1' means xHC is restoring state */
252 #define STS_RESTORE (1 << 9)
253 /* true: save or restore error */
254 #define STS_SRE (1 << 10)
255 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
256 #define STS_CNR XHCI_STS_CNR
257 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
258 #define STS_HCE (1 << 12)
259 /* bits 13:31 reserved and should be preserved */
262 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
263 * Generate a device notification event when the HC sees a transaction with a
264 * notification type that matches a bit set in this bit field.
266 #define DEV_NOTE_MASK (0xffff)
267 #define ENABLE_DEV_NOTE(x) (1 << (x))
268 /* Most of the device notification types should only be used for debug.
269 * SW does need to pay attention to function wake notifications.
271 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
273 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
274 /* bit 0 is the command ring cycle state */
275 /* stop ring operation after completion of the currently executing command */
276 #define CMD_RING_PAUSE (1 << 1)
277 /* stop ring immediately - abort the currently executing command */
278 #define CMD_RING_ABORT (1 << 2)
279 /* true: command ring is running */
280 #define CMD_RING_RUNNING (1 << 3)
281 /* bits 4:5 reserved and should be preserved */
282 /* Command Ring pointer - bit mask for the lower 32 bits. */
283 #define CMD_RING_RSVD_BITS (0x3f)
285 /* CONFIG - Configure Register - config_reg bitmasks */
286 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
287 #define MAX_DEVS(p) ((p) & 0xff)
288 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
289 #define CONFIG_U3E (1 << 8)
290 /* bit 9: Configuration Information Enable, xhci 1.1 */
291 #define CONFIG_CIE (1 << 9)
292 /* bits 10:31 - reserved and should be preserved */
294 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
295 /* true: device connected */
296 #define PORT_CONNECT (1 << 0)
297 /* true: port enabled */
298 #define PORT_PE (1 << 1)
299 /* bit 2 reserved and zeroed */
300 /* true: port has an over-current condition */
301 #define PORT_OC (1 << 3)
302 /* true: port reset signaling asserted */
303 #define PORT_RESET (1 << 4)
304 /* Port Link State - bits 5:8
305 * A read gives the current link PM state of the port,
306 * a write with Link State Write Strobe set sets the link state.
308 #define PORT_PLS_MASK (0xf << 5)
309 #define XDEV_U0 (0x0 << 5)
310 #define XDEV_U1 (0x1 << 5)
311 #define XDEV_U2 (0x2 << 5)
312 #define XDEV_U3 (0x3 << 5)
313 #define XDEV_DISABLED (0x4 << 5)
314 #define XDEV_RXDETECT (0x5 << 5)
315 #define XDEV_INACTIVE (0x6 << 5)
316 #define XDEV_POLLING (0x7 << 5)
317 #define XDEV_RECOVERY (0x8 << 5)
318 #define XDEV_HOT_RESET (0x9 << 5)
319 #define XDEV_COMP_MODE (0xa << 5)
320 #define XDEV_TEST_MODE (0xb << 5)
321 #define XDEV_RESUME (0xf << 5)
323 /* true: port has power (see HCC_PPC) */
324 #define PORT_POWER (1 << 9)
325 /* bits 10:13 indicate device speed:
326 * 0 - undefined speed - port hasn't be initialized by a reset yet
333 #define DEV_SPEED_MASK (0xf << 10)
334 #define XDEV_FS (0x1 << 10)
335 #define XDEV_LS (0x2 << 10)
336 #define XDEV_HS (0x3 << 10)
337 #define XDEV_SS (0x4 << 10)
338 #define XDEV_SSP (0x5 << 10)
339 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
340 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
341 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
342 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
343 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
344 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
345 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
346 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
348 /* Bits 20:23 in the Slot Context are the speed for the device */
349 #define SLOT_SPEED_FS (XDEV_FS << 10)
350 #define SLOT_SPEED_LS (XDEV_LS << 10)
351 #define SLOT_SPEED_HS (XDEV_HS << 10)
352 #define SLOT_SPEED_SS (XDEV_SS << 10)
353 #define SLOT_SPEED_SSP (XDEV_SSP << 10)
354 /* Port Indicator Control */
355 #define PORT_LED_OFF (0 << 14)
356 #define PORT_LED_AMBER (1 << 14)
357 #define PORT_LED_GREEN (2 << 14)
358 #define PORT_LED_MASK (3 << 14)
359 /* Port Link State Write Strobe - set this when changing link state */
360 #define PORT_LINK_STROBE (1 << 16)
361 /* true: connect status change */
362 #define PORT_CSC (1 << 17)
363 /* true: port enable change */
364 #define PORT_PEC (1 << 18)
365 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
366 * into an enabled state, and the device into the default state. A "warm" reset
367 * also resets the link, forcing the device through the link training sequence.
368 * SW can also look at the Port Reset register to see when warm reset is done.
370 #define PORT_WRC (1 << 19)
371 /* true: over-current change */
372 #define PORT_OCC (1 << 20)
373 /* true: reset change - 1 to 0 transition of PORT_RESET */
374 #define PORT_RC (1 << 21)
375 /* port link status change - set on some port link state transitions:
377 * ------------------------------------------------------------------------------
378 * - U3 to Resume Wakeup signaling from a device
379 * - Resume to Recovery to U0 USB 3.0 device resume
380 * - Resume to U0 USB 2.0 device resume
381 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
382 * - U3 to U0 Software resume of USB 2.0 device complete
383 * - U2 to U0 L1 resume of USB 2.1 device complete
384 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
385 * - U0 to disabled L1 entry error with USB 2.1 device
386 * - Any state to inactive Error on USB 3.0 port
388 #define PORT_PLC (1 << 22)
389 /* port configure error change - port failed to configure its link partner */
390 #define PORT_CEC (1 << 23)
391 #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
392 PORT_RC | PORT_PLC | PORT_CEC)
395 /* Cold Attach Status - xHC can set this bit to report device attached during
396 * Sx state. Warm port reset should be perfomed to clear this bit and move port
397 * to connected state.
399 #define PORT_CAS (1 << 24)
400 /* wake on connect (enable) */
401 #define PORT_WKCONN_E (1 << 25)
402 /* wake on disconnect (enable) */
403 #define PORT_WKDISC_E (1 << 26)
404 /* wake on over-current (enable) */
405 #define PORT_WKOC_E (1 << 27)
406 /* bits 28:29 reserved */
407 /* true: device is non-removable - for USB 3.0 roothub emulation */
408 #define PORT_DEV_REMOVE (1 << 30)
409 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
410 #define PORT_WR (1 << 31)
412 /* We mark duplicate entries with -1 */
413 #define DUPLICATE_ENTRY ((u8)(-1))
415 /* Port Power Management Status and Control - port_power_base bitmasks */
416 /* Inactivity timer value for transitions into U1, in microseconds.
417 * Timeout can be up to 127us. 0xFF means an infinite timeout.
419 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
420 #define PORT_U1_TIMEOUT_MASK 0xff
421 /* Inactivity timer value for transitions into U2 */
422 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
423 #define PORT_U2_TIMEOUT_MASK (0xff << 8)
424 /* Bits 24:31 for port testing */
426 /* USB2 Protocol PORTSPMSC */
427 #define PORT_L1S_MASK 7
428 #define PORT_L1S_SUCCESS 1
429 #define PORT_RWE (1 << 3)
430 #define PORT_HIRD(p) (((p) & 0xf) << 4)
431 #define PORT_HIRD_MASK (0xf << 4)
432 #define PORT_L1DS_MASK (0xff << 8)
433 #define PORT_L1DS(p) (((p) & 0xff) << 8)
434 #define PORT_HLE (1 << 16)
435 #define PORT_TEST_MODE_SHIFT 28
437 /* USB3 Protocol PORTLI Port Link Information */
438 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
439 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
441 /* USB2 Protocol PORTHLPMC */
442 #define PORT_HIRDM(p)((p) & 3)
443 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
444 #define PORT_BESLD(p)(((p) & 0xf) << 10)
446 /* use 512 microseconds as USB2 LPM L1 default timeout. */
447 #define XHCI_L1_TIMEOUT 512
449 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
450 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
451 * by other operating systems.
453 * XHCI 1.0 errata 8/14/12 Table 13 notes:
454 * "Software should choose xHC BESL/BESLD field values that do not violate a
455 * device's resume latency requirements,
456 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
457 * or not program values < '4' if BLC = '0' and a BESL device is attached.
459 #define XHCI_DEFAULT_BESL 4
462 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
463 * to complete link training. usually link trainig completes much faster
464 * so check status 10 times with 36ms sleep in places we need to wait for
465 * polling to complete.
467 #define XHCI_PORT_POLLING_LFPS_TIME 36
470 * struct xhci_intr_reg - Interrupt Register Set
471 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
472 * interrupts and check for pending interrupts.
473 * @irq_control: IMOD - Interrupt Moderation Register.
474 * Used to throttle interrupts.
475 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
476 * @erst_base: ERST base address.
477 * @erst_dequeue: Event ring dequeue pointer.
479 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
480 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
481 * multiple segments of the same size. The HC places events on the ring and
482 * "updates the Cycle bit in the TRBs to indicate to software the current
483 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
484 * updates the dequeue pointer.
486 struct xhci_intr_reg {
495 /* irq_pending bitmasks */
496 #define ER_IRQ_PENDING(p) ((p) & 0x1)
497 /* bits 2:31 need to be preserved */
498 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
499 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
500 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
501 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
503 /* irq_control bitmasks */
504 /* Minimum interval between interrupts (in 250ns intervals). The interval
505 * between interrupts will be longer if there are no events on the event ring.
506 * Default is 4000 (1 ms).
508 #define ER_IRQ_INTERVAL_MASK (0xffff)
509 /* Counter used to count down the time to the next interrupt - HW use only */
510 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
512 /* erst_size bitmasks */
513 /* Preserve bits 16:31 of erst_size */
514 #define ERST_SIZE_MASK (0xffff << 16)
516 /* erst_base bitmasks */
517 #define ERST_BASE_RSVDP (GENMASK_ULL(5, 0))
519 /* erst_dequeue bitmasks */
520 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
521 * where the current dequeue pointer lies. This is an optional HW hint.
523 #define ERST_DESI_MASK (0x7)
524 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
525 * a work queue (or delayed service routine)?
527 #define ERST_EHB (1 << 3)
528 #define ERST_PTR_MASK (GENMASK_ULL(63, 4))
531 * struct xhci_run_regs
533 * MFINDEX - current microframe number
535 * Section 5.5 Host Controller Runtime Registers:
536 * "Software should read and write these registers using only Dword (32 bit)
537 * or larger accesses"
539 struct xhci_run_regs {
540 __le32 microframe_index;
542 struct xhci_intr_reg ir_set[128];
546 * struct doorbell_array
548 * Bits 0 - 7: Endpoint target
550 * Bits 16 - 31: Stream ID
554 struct xhci_doorbell_array {
555 __le32 doorbell[256];
558 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
559 #define DB_VALUE_HOST 0x00000000
561 #define PLT_MASK (0x03 << 6)
562 #define PLT_SYM (0x00 << 6)
563 #define PLT_ASYM_RX (0x02 << 6)
564 #define PLT_ASYM_TX (0x03 << 6)
567 * struct xhci_container_ctx
568 * @type: Type of context. Used to calculated offsets to contained contexts.
569 * @size: Size of the context data
570 * @bytes: The raw context data given to HW
571 * @dma: dma address of the bytes
573 * Represents either a Device or Input context. Holds a pointer to the raw
574 * memory used for the context (bytes) and dma address of it (dma).
576 struct xhci_container_ctx {
578 #define XHCI_CTX_TYPE_DEVICE 0x1
579 #define XHCI_CTX_TYPE_INPUT 0x2
588 * struct xhci_slot_ctx
589 * @dev_info: Route string, device speed, hub info, and last valid endpoint
590 * @dev_info2: Max exit latency for device number, root hub port number
591 * @tt_info: tt_info is used to construct split transaction tokens
592 * @dev_state: slot state and device address
594 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
595 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
596 * reserved at the end of the slot context for HC internal use.
598 struct xhci_slot_ctx {
603 /* offset 0x10 to 0x1f reserved for HC internal use */
607 /* dev_info bitmasks */
608 /* Route String - 0:19 */
609 #define ROUTE_STRING_MASK (0xfffff)
610 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
611 #define DEV_SPEED (0xf << 20)
612 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
613 /* bit 24 reserved */
614 /* Is this LS/FS device connected through a HS hub? - bit 25 */
615 #define DEV_MTT (0x1 << 25)
616 /* Set if the device is a hub - bit 26 */
617 #define DEV_HUB (0x1 << 26)
618 /* Index of the last valid endpoint context in this device context - 27:31 */
619 #define LAST_CTX_MASK (0x1f << 27)
620 #define LAST_CTX(p) ((p) << 27)
621 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
622 #define SLOT_FLAG (1 << 0)
623 #define EP0_FLAG (1 << 1)
625 /* dev_info2 bitmasks */
626 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
627 #define MAX_EXIT (0xffff)
628 /* Root hub port number that is needed to access the USB device */
629 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
630 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
631 /* Maximum number of ports under a hub device */
632 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
633 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
635 /* tt_info bitmasks */
637 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
638 * The Slot ID of the hub that isolates the high speed signaling from
639 * this low or full-speed device. '0' if attached to root hub port.
641 #define TT_SLOT (0xff)
643 * The number of the downstream facing port of the high-speed hub
644 * '0' if the device is not low or full speed.
646 #define TT_PORT (0xff << 8)
647 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
648 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
650 /* dev_state bitmasks */
651 /* USB device address - assigned by the HC */
652 #define DEV_ADDR_MASK (0xff)
653 /* bits 8:26 reserved */
655 #define SLOT_STATE (0x1f << 27)
656 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
658 #define SLOT_STATE_DISABLED 0
659 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
660 #define SLOT_STATE_DEFAULT 1
661 #define SLOT_STATE_ADDRESSED 2
662 #define SLOT_STATE_CONFIGURED 3
666 * @ep_info: endpoint state, streams, mult, and interval information.
667 * @ep_info2: information on endpoint type, max packet size, max burst size,
668 * error count, and whether the HC will force an event for all
670 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
671 * defines one stream, this points to the endpoint transfer ring.
672 * Otherwise, it points to a stream context array, which has a
673 * ring pointer for each flow.
675 * Average TRB lengths for the endpoint ring and
676 * max payload within an Endpoint Service Interval Time (ESIT).
678 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
679 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
680 * reserved at the end of the endpoint context for HC internal use.
687 /* offset 0x14 - 0x1f reserved for HC internal use */
691 /* ep_info bitmasks */
693 * Endpoint State - bits 0:2
696 * 2 - halted due to halt condition - ok to manipulate endpoint ring
701 #define EP_STATE_MASK (0x7)
702 #define EP_STATE_DISABLED 0
703 #define EP_STATE_RUNNING 1
704 #define EP_STATE_HALTED 2
705 #define EP_STATE_STOPPED 3
706 #define EP_STATE_ERROR 4
707 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
709 /* Mult - Max number of burtst within an interval, in EP companion desc. */
710 #define EP_MULT(p) (((p) & 0x3) << 8)
711 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
712 /* bits 10:14 are Max Primary Streams */
713 /* bit 15 is Linear Stream Array */
714 /* Interval - period between requests to an endpoint - 125u increments. */
715 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
716 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
717 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
718 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
719 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
720 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
721 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
722 #define EP_HAS_LSA (1 << 15)
723 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
724 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
726 /* ep_info2 bitmasks */
728 * Force Event - generate transfer events for all TRBs for this endpoint
729 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
731 #define FORCE_EVENT (0x1)
732 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
733 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
734 #define EP_TYPE(p) ((p) << 3)
735 #define ISOC_OUT_EP 1
736 #define BULK_OUT_EP 2
743 /* bit 7 is Host Initiate Disable - for disabling stream selection */
744 #define MAX_BURST(p) (((p)&0xff) << 8)
745 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
746 #define MAX_PACKET(p) (((p)&0xffff) << 16)
747 #define MAX_PACKET_MASK (0xffff << 16)
748 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
750 /* tx_info bitmasks */
751 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
752 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
753 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
754 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
757 #define EP_CTX_CYCLE_MASK (1 << 0)
758 #define SCTX_DEQ_MASK (~0xfL)
762 * struct xhci_input_control_context
763 * Input control context; see section 6.2.5.
765 * @drop_context: set the bit of the endpoint context you want to disable
766 * @add_context: set the bit of the endpoint context you want to enable
768 struct xhci_input_control_ctx {
774 #define EP_IS_ADDED(ctrl_ctx, i) \
775 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
776 #define EP_IS_DROPPED(ctrl_ctx, i) \
777 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
779 /* Represents everything that is needed to issue a command on the command ring.
780 * It's useful to pre-allocate these for commands that cannot fail due to
781 * out-of-memory errors, like freeing streams.
783 struct xhci_command {
784 /* Input context for changing device state */
785 struct xhci_container_ctx *in_ctx;
788 /* If completion is null, no one is waiting on this command
789 * and the structure can be freed after the command completes.
791 struct completion *completion;
792 union xhci_trb *command_trb;
793 struct list_head cmd_list;
794 /* xHCI command response timeout in milliseconds */
795 unsigned int timeout_ms;
798 /* drop context bitmasks */
799 #define DROP_EP(x) (0x1 << x)
800 /* add context bitmasks */
801 #define ADD_EP(x) (0x1 << x)
803 struct xhci_stream_ctx {
804 /* 64-bit stream ring address, cycle state, and stream type */
806 /* offset 0x14 - 0x1f reserved for HC internal use */
810 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
811 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
812 /* Secondary stream array type, dequeue pointer is to a transfer ring */
814 /* Primary stream array type, dequeue pointer is to a transfer ring */
816 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
821 #define SCT_SSA_128 6
822 #define SCT_SSA_256 7
824 /* Assume no secondary streams for now */
825 struct xhci_stream_info {
826 struct xhci_ring **stream_rings;
827 /* Number of streams, including stream 0 (which drivers can't use) */
828 unsigned int num_streams;
829 /* The stream context array may be bigger than
830 * the number of streams the driver asked for
832 struct xhci_stream_ctx *stream_ctx_array;
833 unsigned int num_stream_ctxs;
834 dma_addr_t ctx_array_dma;
835 /* For mapping physical TRB addresses to segments in stream rings */
836 struct radix_tree_root trb_address_map;
837 struct xhci_command *free_streams_command;
840 #define SMALL_STREAM_ARRAY_SIZE 256
841 #define MEDIUM_STREAM_ARRAY_SIZE 1024
843 /* Some Intel xHCI host controllers need software to keep track of the bus
844 * bandwidth. Keep track of endpoint info here. Each root port is allocated
845 * the full bus bandwidth. We must also treat TTs (including each port under a
846 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
847 * (DMI) also limits the total bandwidth (across all domains) that can be used.
849 struct xhci_bw_info {
850 /* ep_interval is zero-based */
851 unsigned int ep_interval;
852 /* mult and num_packets are one-based */
854 unsigned int num_packets;
855 unsigned int max_packet_size;
856 unsigned int max_esit_payload;
860 /* "Block" sizes in bytes the hardware uses for different device speeds.
861 * The logic in this part of the hardware limits the number of bits the hardware
862 * can use, so must represent bandwidth in a less precise manner to mimic what
863 * the scheduler hardware computes.
870 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
871 * with each byte transferred. SuperSpeed devices have an initial overhead to
872 * set up bursts. These are in blocks, see above. LS overhead has already been
873 * translated into FS blocks.
875 #define DMI_OVERHEAD 8
876 #define DMI_OVERHEAD_BURST 4
877 #define SS_OVERHEAD 8
878 #define SS_OVERHEAD_BURST 32
879 #define HS_OVERHEAD 26
880 #define FS_OVERHEAD 20
881 #define LS_OVERHEAD 128
882 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
883 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
884 * of overhead associated with split transfers crossing microframe boundaries.
885 * 31 blocks is pure protocol overhead.
887 #define TT_HS_OVERHEAD (31 + 94)
888 #define TT_DMI_OVERHEAD (25 + 12)
890 /* Bandwidth limits in blocks */
891 #define FS_BW_LIMIT 1285
892 #define TT_BW_LIMIT 1320
893 #define HS_BW_LIMIT 1607
894 #define SS_BW_LIMIT_IN 3906
895 #define DMI_BW_LIMIT_IN 3906
896 #define SS_BW_LIMIT_OUT 3906
897 #define DMI_BW_LIMIT_OUT 3906
899 /* Percentage of bus bandwidth reserved for non-periodic transfers */
900 #define FS_BW_RESERVED 10
901 #define HS_BW_RESERVED 20
902 #define SS_BW_RESERVED 10
904 struct xhci_virt_ep {
905 struct xhci_virt_device *vdev; /* parent */
906 unsigned int ep_index;
907 struct xhci_ring *ring;
908 /* Related to endpoints that are configured to use stream IDs only */
909 struct xhci_stream_info *stream_info;
910 /* Temporary storage in case the configure endpoint command fails and we
911 * have to restore the device state to the previous state
913 struct xhci_ring *new_ring;
914 unsigned int err_count;
915 unsigned int ep_state;
916 #define SET_DEQ_PENDING (1 << 0)
917 #define EP_HALTED (1 << 1) /* For stall handling */
918 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
919 /* Transitioning the endpoint to using streams, don't enqueue URBs */
920 #define EP_GETTING_STREAMS (1 << 3)
921 #define EP_HAS_STREAMS (1 << 4)
922 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
923 #define EP_GETTING_NO_STREAMS (1 << 5)
924 #define EP_HARD_CLEAR_TOGGLE (1 << 6)
925 #define EP_SOFT_CLEAR_TOGGLE (1 << 7)
926 /* usb_hub_clear_tt_buffer is in progress */
927 #define EP_CLEARING_TT (1 << 8)
928 /* ---- Related to URB cancellation ---- */
929 struct list_head cancelled_td_list;
930 struct xhci_hcd *xhci;
931 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
932 * command. We'll need to update the ring's dequeue segment and dequeue
933 * pointer after the command completes.
935 struct xhci_segment *queued_deq_seg;
936 union xhci_trb *queued_deq_ptr;
938 * Sometimes the xHC can not process isochronous endpoint ring quickly
939 * enough, and it will miss some isoc tds on the ring and generate
940 * a Missed Service Error Event.
941 * Set skip flag when receive a Missed Service Error Event and
942 * process the missed tds on the endpoint ring.
945 /* Bandwidth checking storage */
946 struct xhci_bw_info bw_info;
947 struct list_head bw_endpoint_list;
948 /* Isoch Frame ID checking storage */
950 /* Use new Isoch TRB layout needed for extended TBC support */
951 bool use_extended_tbc;
954 enum xhci_overhead_type {
955 LS_OVERHEAD_TYPE = 0,
960 struct xhci_interval_bw {
961 unsigned int num_packets;
962 /* Sorted by max packet size.
963 * Head of the list is the greatest max packet size.
965 struct list_head endpoints;
966 /* How many endpoints of each speed are present. */
967 unsigned int overhead[3];
970 #define XHCI_MAX_INTERVAL 16
972 struct xhci_interval_bw_table {
973 unsigned int interval0_esit_payload;
974 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
975 /* Includes reserved bandwidth for async endpoints */
976 unsigned int bw_used;
977 unsigned int ss_bw_in;
978 unsigned int ss_bw_out;
981 #define EP_CTX_PER_DEV 31
983 struct xhci_virt_device {
985 struct usb_device *udev;
987 * Commands to the hardware are passed an "input context" that
988 * tells the hardware what to change in its data structures.
989 * The hardware will return changes in an "output context" that
990 * software must allocate for the hardware. We need to keep
991 * track of input and output contexts separately because
992 * these commands might fail and we don't trust the hardware.
994 struct xhci_container_ctx *out_ctx;
995 /* Used for addressing devices and configuration changes */
996 struct xhci_container_ctx *in_ctx;
997 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
1000 struct xhci_interval_bw_table *bw_table;
1001 struct xhci_tt_bw_info *tt_info;
1003 * flags for state tracking based on events and issued commands.
1004 * Software can not rely on states from output contexts because of
1005 * latency between events and xHC updating output context values.
1006 * See xhci 1.1 section 4.8.3 for more details
1008 unsigned long flags;
1009 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
1011 /* The current max exit latency for the enabled USB3 link states. */
1013 /* Used for the debugfs interfaces. */
1014 void *debugfs_private;
1018 * For each roothub, keep track of the bandwidth information for each periodic
1021 * If a high speed hub is attached to the roothub, each TT associated with that
1022 * hub is a separate bandwidth domain. The interval information for the
1023 * endpoints on the devices under that TT will appear in the TT structure.
1025 struct xhci_root_port_bw_info {
1026 struct list_head tts;
1027 unsigned int num_active_tts;
1028 struct xhci_interval_bw_table bw_table;
1031 struct xhci_tt_bw_info {
1032 struct list_head tt_list;
1035 struct xhci_interval_bw_table bw_table;
1041 * struct xhci_device_context_array
1042 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1044 struct xhci_device_context_array {
1045 /* 64-bit device addresses; we only write 32-bit addresses */
1046 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1047 /* private xHCD pointers */
1050 /* TODO: write function to set the 64-bit device DMA address */
1052 * TODO: change this to be dynamically sized at HC mem init time since the HC
1053 * might not be able to handle the maximum number of devices possible.
1057 struct xhci_transfer_event {
1058 /* 64-bit buffer address, or immediate data */
1060 __le32 transfer_len;
1061 /* This field is interpreted differently based on the type of TRB */
1065 /* Transfer event TRB length bit mask */
1067 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1069 /** Transfer Event bit fields **/
1070 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1072 /* Completion Code - only applicable for some types of TRBs */
1073 #define COMP_CODE_MASK (0xff << 24)
1074 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1075 #define COMP_INVALID 0
1076 #define COMP_SUCCESS 1
1077 #define COMP_DATA_BUFFER_ERROR 2
1078 #define COMP_BABBLE_DETECTED_ERROR 3
1079 #define COMP_USB_TRANSACTION_ERROR 4
1080 #define COMP_TRB_ERROR 5
1081 #define COMP_STALL_ERROR 6
1082 #define COMP_RESOURCE_ERROR 7
1083 #define COMP_BANDWIDTH_ERROR 8
1084 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1085 #define COMP_INVALID_STREAM_TYPE_ERROR 10
1086 #define COMP_SLOT_NOT_ENABLED_ERROR 11
1087 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1088 #define COMP_SHORT_PACKET 13
1089 #define COMP_RING_UNDERRUN 14
1090 #define COMP_RING_OVERRUN 15
1091 #define COMP_VF_EVENT_RING_FULL_ERROR 16
1092 #define COMP_PARAMETER_ERROR 17
1093 #define COMP_BANDWIDTH_OVERRUN_ERROR 18
1094 #define COMP_CONTEXT_STATE_ERROR 19
1095 #define COMP_NO_PING_RESPONSE_ERROR 20
1096 #define COMP_EVENT_RING_FULL_ERROR 21
1097 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1098 #define COMP_MISSED_SERVICE_ERROR 23
1099 #define COMP_COMMAND_RING_STOPPED 24
1100 #define COMP_COMMAND_ABORTED 25
1101 #define COMP_STOPPED 26
1102 #define COMP_STOPPED_LENGTH_INVALID 27
1103 #define COMP_STOPPED_SHORT_PACKET 28
1104 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1105 #define COMP_ISOCH_BUFFER_OVERRUN 31
1106 #define COMP_EVENT_LOST_ERROR 32
1107 #define COMP_UNDEFINED_ERROR 33
1108 #define COMP_INVALID_STREAM_ID_ERROR 34
1109 #define COMP_SECONDARY_BANDWIDTH_ERROR 35
1110 #define COMP_SPLIT_TRANSACTION_ERROR 36
1112 static inline const char *xhci_trb_comp_code_string(u8 status)
1119 case COMP_DATA_BUFFER_ERROR:
1120 return "Data Buffer Error";
1121 case COMP_BABBLE_DETECTED_ERROR:
1122 return "Babble Detected";
1123 case COMP_USB_TRANSACTION_ERROR:
1124 return "USB Transaction Error";
1125 case COMP_TRB_ERROR:
1127 case COMP_STALL_ERROR:
1128 return "Stall Error";
1129 case COMP_RESOURCE_ERROR:
1130 return "Resource Error";
1131 case COMP_BANDWIDTH_ERROR:
1132 return "Bandwidth Error";
1133 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1134 return "No Slots Available Error";
1135 case COMP_INVALID_STREAM_TYPE_ERROR:
1136 return "Invalid Stream Type Error";
1137 case COMP_SLOT_NOT_ENABLED_ERROR:
1138 return "Slot Not Enabled Error";
1139 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1140 return "Endpoint Not Enabled Error";
1141 case COMP_SHORT_PACKET:
1142 return "Short Packet";
1143 case COMP_RING_UNDERRUN:
1144 return "Ring Underrun";
1145 case COMP_RING_OVERRUN:
1146 return "Ring Overrun";
1147 case COMP_VF_EVENT_RING_FULL_ERROR:
1148 return "VF Event Ring Full Error";
1149 case COMP_PARAMETER_ERROR:
1150 return "Parameter Error";
1151 case COMP_BANDWIDTH_OVERRUN_ERROR:
1152 return "Bandwidth Overrun Error";
1153 case COMP_CONTEXT_STATE_ERROR:
1154 return "Context State Error";
1155 case COMP_NO_PING_RESPONSE_ERROR:
1156 return "No Ping Response Error";
1157 case COMP_EVENT_RING_FULL_ERROR:
1158 return "Event Ring Full Error";
1159 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1160 return "Incompatible Device Error";
1161 case COMP_MISSED_SERVICE_ERROR:
1162 return "Missed Service Error";
1163 case COMP_COMMAND_RING_STOPPED:
1164 return "Command Ring Stopped";
1165 case COMP_COMMAND_ABORTED:
1166 return "Command Aborted";
1169 case COMP_STOPPED_LENGTH_INVALID:
1170 return "Stopped - Length Invalid";
1171 case COMP_STOPPED_SHORT_PACKET:
1172 return "Stopped - Short Packet";
1173 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1174 return "Max Exit Latency Too Large Error";
1175 case COMP_ISOCH_BUFFER_OVERRUN:
1176 return "Isoch Buffer Overrun";
1177 case COMP_EVENT_LOST_ERROR:
1178 return "Event Lost Error";
1179 case COMP_UNDEFINED_ERROR:
1180 return "Undefined Error";
1181 case COMP_INVALID_STREAM_ID_ERROR:
1182 return "Invalid Stream ID Error";
1183 case COMP_SECONDARY_BANDWIDTH_ERROR:
1184 return "Secondary Bandwidth Error";
1185 case COMP_SPLIT_TRANSACTION_ERROR:
1186 return "Split Transaction Error";
1192 struct xhci_link_trb {
1193 /* 64-bit segment pointer*/
1199 /* control bitfields */
1200 #define LINK_TOGGLE (0x1<<1)
1202 /* Command completion event TRB */
1203 struct xhci_event_cmd {
1204 /* Pointer to command TRB, or the value passed by the event data trb */
1210 /* flags bitmasks */
1212 /* Address device - disable SetAddress */
1213 #define TRB_BSR (1<<9)
1215 /* Configure Endpoint - Deconfigure */
1216 #define TRB_DC (1<<9)
1218 /* Stop Ring - Transfer State Preserve */
1219 #define TRB_TSP (1<<9)
1221 enum xhci_ep_reset_type {
1227 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1228 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1230 /* Set Latency Tolerance Value */
1231 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1233 /* Get Port Bandwidth */
1234 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1237 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1238 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1240 enum xhci_setup_dev {
1242 SETUP_CONTEXT_ADDRESS,
1245 /* bits 16:23 are the virtual function ID */
1246 /* bits 24:31 are the slot ID */
1247 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1248 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1250 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1251 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1252 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1254 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1255 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1256 #define LAST_EP_INDEX 30
1258 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1259 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1260 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1261 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1263 /* Link TRB specific fields */
1264 #define TRB_TC (1<<1)
1266 /* Port Status Change Event TRB fields */
1267 /* Port ID - bits 31:24 */
1268 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1270 #define EVENT_DATA (1 << 2)
1272 /* Normal TRB fields */
1273 /* transfer_len bitmasks - bits 0:16 */
1274 #define TRB_LEN(p) ((p) & 0x1ffff)
1275 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1276 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1277 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1278 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1279 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1280 /* Interrupter Target - which MSI-X vector to target the completion event at */
1281 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1282 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1283 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1284 #define TRB_TBC(p) (((p) & 0x3) << 7)
1285 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1287 /* Cycle bit - indicates TRB ownership by HC or HCD */
1288 #define TRB_CYCLE (1<<0)
1290 * Force next event data TRB to be evaluated before task switch.
1291 * Used to pass OS data back after a TD completes.
1293 #define TRB_ENT (1<<1)
1294 /* Interrupt on short packet */
1295 #define TRB_ISP (1<<2)
1296 /* Set PCIe no snoop attribute */
1297 #define TRB_NO_SNOOP (1<<3)
1298 /* Chain multiple TRBs into a TD */
1299 #define TRB_CHAIN (1<<4)
1300 /* Interrupt on completion */
1301 #define TRB_IOC (1<<5)
1302 /* The buffer pointer contains immediate data */
1303 #define TRB_IDT (1<<6)
1304 /* TDs smaller than this might use IDT */
1305 #define TRB_IDT_MAX_SIZE 8
1307 /* Block Event Interrupt */
1308 #define TRB_BEI (1<<9)
1310 /* Control transfer TRB specific fields */
1311 #define TRB_DIR_IN (1<<16)
1312 #define TRB_TX_TYPE(p) ((p) << 16)
1313 #define TRB_DATA_OUT 2
1314 #define TRB_DATA_IN 3
1316 /* Isochronous TRB specific fields */
1317 #define TRB_SIA (1<<31)
1318 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1320 /* TRB cache size for xHC with TRB cache */
1321 #define TRB_CACHE_SIZE_HS 8
1322 #define TRB_CACHE_SIZE_SS 16
1324 struct xhci_generic_trb {
1329 struct xhci_link_trb link;
1330 struct xhci_transfer_event trans_event;
1331 struct xhci_event_cmd event_cmd;
1332 struct xhci_generic_trb generic;
1336 #define TRB_TYPE_BITMASK (0xfc00)
1337 #define TRB_TYPE(p) ((p) << 10)
1338 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1340 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1341 #define TRB_NORMAL 1
1342 /* setup stage for control transfers */
1344 /* data stage for control transfers */
1346 /* status stage for control transfers */
1347 #define TRB_STATUS 4
1348 /* isoc transfers */
1350 /* TRB for linking ring segments */
1352 #define TRB_EVENT_DATA 7
1353 /* Transfer Ring No-op (not for the command ring) */
1354 #define TRB_TR_NOOP 8
1356 /* Enable Slot Command */
1357 #define TRB_ENABLE_SLOT 9
1358 /* Disable Slot Command */
1359 #define TRB_DISABLE_SLOT 10
1360 /* Address Device Command */
1361 #define TRB_ADDR_DEV 11
1362 /* Configure Endpoint Command */
1363 #define TRB_CONFIG_EP 12
1364 /* Evaluate Context Command */
1365 #define TRB_EVAL_CONTEXT 13
1366 /* Reset Endpoint Command */
1367 #define TRB_RESET_EP 14
1368 /* Stop Transfer Ring Command */
1369 #define TRB_STOP_RING 15
1370 /* Set Transfer Ring Dequeue Pointer Command */
1371 #define TRB_SET_DEQ 16
1372 /* Reset Device Command */
1373 #define TRB_RESET_DEV 17
1374 /* Force Event Command (opt) */
1375 #define TRB_FORCE_EVENT 18
1376 /* Negotiate Bandwidth Command (opt) */
1377 #define TRB_NEG_BANDWIDTH 19
1378 /* Set Latency Tolerance Value Command (opt) */
1379 #define TRB_SET_LT 20
1380 /* Get port bandwidth Command */
1381 #define TRB_GET_BW 21
1382 /* Force Header Command - generate a transaction or link management packet */
1383 #define TRB_FORCE_HEADER 22
1384 /* No-op Command - not for transfer rings */
1385 #define TRB_CMD_NOOP 23
1386 /* TRB IDs 24-31 reserved */
1388 /* Transfer Event */
1389 #define TRB_TRANSFER 32
1390 /* Command Completion Event */
1391 #define TRB_COMPLETION 33
1392 /* Port Status Change Event */
1393 #define TRB_PORT_STATUS 34
1394 /* Bandwidth Request Event (opt) */
1395 #define TRB_BANDWIDTH_EVENT 35
1396 /* Doorbell Event (opt) */
1397 #define TRB_DOORBELL 36
1398 /* Host Controller Event */
1399 #define TRB_HC_EVENT 37
1400 /* Device Notification Event - device sent function wake notification */
1401 #define TRB_DEV_NOTE 38
1402 /* MFINDEX Wrap Event - microframe counter wrapped */
1403 #define TRB_MFINDEX_WRAP 39
1404 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1405 #define TRB_VENDOR_DEFINED_LOW 48
1406 /* Nec vendor-specific command completion event. */
1407 #define TRB_NEC_CMD_COMP 48
1408 /* Get NEC firmware revision. */
1409 #define TRB_NEC_GET_FW 49
1411 static inline const char *xhci_trb_type_string(u8 type)
1417 return "Setup Stage";
1419 return "Data Stage";
1421 return "Status Stage";
1426 case TRB_EVENT_DATA:
1427 return "Event Data";
1430 case TRB_ENABLE_SLOT:
1431 return "Enable Slot Command";
1432 case TRB_DISABLE_SLOT:
1433 return "Disable Slot Command";
1435 return "Address Device Command";
1437 return "Configure Endpoint Command";
1438 case TRB_EVAL_CONTEXT:
1439 return "Evaluate Context Command";
1441 return "Reset Endpoint Command";
1443 return "Stop Ring Command";
1445 return "Set TR Dequeue Pointer Command";
1447 return "Reset Device Command";
1448 case TRB_FORCE_EVENT:
1449 return "Force Event Command";
1450 case TRB_NEG_BANDWIDTH:
1451 return "Negotiate Bandwidth Command";
1453 return "Set Latency Tolerance Value Command";
1455 return "Get Port Bandwidth Command";
1456 case TRB_FORCE_HEADER:
1457 return "Force Header Command";
1459 return "No-Op Command";
1461 return "Transfer Event";
1462 case TRB_COMPLETION:
1463 return "Command Completion Event";
1464 case TRB_PORT_STATUS:
1465 return "Port Status Change Event";
1466 case TRB_BANDWIDTH_EVENT:
1467 return "Bandwidth Request Event";
1469 return "Doorbell Event";
1471 return "Host Controller Event";
1473 return "Device Notification Event";
1474 case TRB_MFINDEX_WRAP:
1475 return "MFINDEX Wrap Event";
1476 case TRB_NEC_CMD_COMP:
1477 return "NEC Command Completion Event";
1478 case TRB_NEC_GET_FW:
1479 return "NET Get Firmware Revision Command";
1485 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1486 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1487 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1488 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1489 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1490 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1492 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1493 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1496 * TRBS_PER_SEGMENT must be a multiple of 4,
1497 * since the command ring is 64-byte aligned.
1498 * It must also be greater than 16.
1500 #define TRBS_PER_SEGMENT 256
1501 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1502 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1503 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1504 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1505 /* TRB buffer pointers can't cross 64KB boundaries */
1506 #define TRB_MAX_BUFF_SHIFT 16
1507 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1508 /* How much data is left before the 64KB boundary? */
1509 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1510 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1511 #define MAX_SOFT_RETRY 3
1513 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if
1514 * XHCI_AVOID_BEI quirk is in use.
1516 #define AVOID_BEI_INTERVAL_MIN 8
1517 #define AVOID_BEI_INTERVAL_MAX 32
1519 struct xhci_segment {
1520 union xhci_trb *trbs;
1521 /* private to HCD */
1522 struct xhci_segment *next;
1525 /* Max packet sized bounce buffer for td-fragmant alignment */
1526 dma_addr_t bounce_dma;
1528 unsigned int bounce_offs;
1529 unsigned int bounce_len;
1532 enum xhci_cancelled_td_status {
1540 struct list_head td_list;
1541 struct list_head cancelled_td_list;
1543 enum xhci_cancelled_td_status cancel_status;
1545 struct xhci_segment *start_seg;
1546 union xhci_trb *first_trb;
1547 union xhci_trb *last_trb;
1548 struct xhci_segment *last_trb_seg;
1549 struct xhci_segment *bounce_seg;
1550 /* actual_length of the URB has already been set */
1551 bool urb_length_set;
1553 unsigned int num_trbs;
1557 * xHCI command default timeout value in milliseconds.
1558 * USB 3.2 spec, section 9.2.6.1
1560 #define XHCI_CMD_DEFAULT_TIMEOUT 5000
1562 /* command descriptor */
1564 struct xhci_command *command;
1565 union xhci_trb *cmd_trb;
1568 enum xhci_ring_type {
1578 static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1601 struct xhci_segment *first_seg;
1602 struct xhci_segment *last_seg;
1603 union xhci_trb *enqueue;
1604 struct xhci_segment *enq_seg;
1605 union xhci_trb *dequeue;
1606 struct xhci_segment *deq_seg;
1607 struct list_head td_list;
1609 * Write the cycle state into the TRB cycle field to give ownership of
1610 * the TRB to the host controller (if we are the producer), or to check
1611 * if we own the TRB (if we are the consumer). See section 4.9.1.
1614 unsigned int stream_id;
1615 unsigned int num_segs;
1616 unsigned int num_trbs_free; /* used only by xhci DbC */
1617 unsigned int bounce_buf_len;
1618 enum xhci_ring_type type;
1619 bool last_td_was_short;
1620 struct radix_tree_root *trb_address_map;
1623 struct xhci_erst_entry {
1624 /* 64-bit event ring segment address */
1632 struct xhci_erst_entry *entries;
1633 unsigned int num_entries;
1634 /* xhci->event_ring keeps track of segment dma addresses */
1635 dma_addr_t erst_dma_addr;
1636 /* Num entries the ERST can contain */
1637 unsigned int erst_size;
1640 struct xhci_scratchpad {
1649 struct xhci_td td[] __counted_by(num_tds);
1652 /* Reasonable limit for number of Event Ring segments (spec allows 32k) */
1653 #define ERST_MAX_SEGS 2
1654 /* Poll every 60 seconds */
1655 #define POLL_TIMEOUT 60
1656 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1657 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1658 /* XXX: Make these module parameters */
1670 struct list_head list;
1673 struct xhci_bus_state {
1674 unsigned long bus_suspended;
1675 unsigned long next_statechange;
1677 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1678 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1680 u32 suspended_ports;
1681 u32 port_remote_wakeup;
1682 /* which ports have started to resume */
1683 unsigned long resuming_ports;
1686 struct xhci_interrupter {
1687 struct xhci_ring *event_ring;
1688 struct xhci_erst erst;
1689 struct xhci_intr_reg __iomem *ir_set;
1690 unsigned int intr_num;
1692 u32 isoc_bei_interval;
1693 /* For interrupter registers save and restore over suspend/resume */
1698 u64 s3_erst_dequeue;
1701 * It can take up to 20 ms to transition from RExit to U0 on the
1702 * Intel Lynx Point LP xHCI host.
1704 #define XHCI_MAX_REXIT_TIMEOUT_MS 20
1705 struct xhci_port_cap {
1706 u32 *psi; /* array of protocol speed ID entries */
1714 __le32 __iomem *addr;
1717 struct xhci_hub *rhub;
1718 struct xhci_port_cap *port_cap;
1719 unsigned int lpm_incapable:1;
1720 unsigned long resume_timestamp;
1722 struct completion rexit_done;
1723 struct completion u3exit_done;
1727 struct xhci_port **ports;
1728 unsigned int num_ports;
1729 struct usb_hcd *hcd;
1730 /* keep track of bus suspend info */
1731 struct xhci_bus_state bus_state;
1732 /* supported prococol extended capabiliy values */
1737 /* There is one xhci_hcd structure per controller */
1739 struct usb_hcd *main_hcd;
1740 struct usb_hcd *shared_hcd;
1741 /* glue to PCI and HCD framework */
1742 struct xhci_cap_regs __iomem *cap_regs;
1743 struct xhci_op_regs __iomem *op_regs;
1744 struct xhci_run_regs __iomem *run_regs;
1745 struct xhci_doorbell_array __iomem *dba;
1747 /* Cached register copies of read-only HC data */
1756 /* packed release number */
1760 u16 max_interrupters;
1763 /* imod_interval in ns (I * 250ns) */
1766 /* 4KB min, 128MB max */
1768 /* Valid values are 12 to 20, inclusive */
1770 /* MSI-X/MSI vectors */
1772 /* optional clocks */
1774 struct clk *reg_clk;
1775 /* optional reset controller */
1776 struct reset_control *reset;
1777 /* data structures */
1778 struct xhci_device_context_array *dcbaa;
1779 struct xhci_interrupter **interrupters;
1780 struct xhci_ring *cmd_ring;
1781 unsigned int cmd_ring_state;
1782 #define CMD_RING_STATE_RUNNING (1 << 0)
1783 #define CMD_RING_STATE_ABORTED (1 << 1)
1784 #define CMD_RING_STATE_STOPPED (1 << 2)
1785 struct list_head cmd_list;
1786 unsigned int cmd_ring_reserved_trbs;
1787 struct delayed_work cmd_timer;
1788 struct completion cmd_ring_stop_completion;
1789 struct xhci_command *current_cmd;
1792 struct xhci_scratchpad *scratchpad;
1794 /* slot enabling and address device helpers */
1795 /* these are not thread safe so use mutex */
1797 /* Internal mirror of the HW's dcbaa */
1798 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1799 /* For keeping track of bandwidth domains per roothub. */
1800 struct xhci_root_port_bw_info *rh_bw;
1803 struct dma_pool *device_pool;
1804 struct dma_pool *segment_pool;
1805 struct dma_pool *small_streams_pool;
1806 struct dma_pool *medium_streams_pool;
1808 /* Host controller watchdog timer structures */
1809 unsigned int xhc_state;
1810 unsigned long run_graceperiod;
1812 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1814 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1815 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1816 * that sees this status (other than the timer that set it) should stop touching
1817 * hardware immediately. Interrupt handlers should return immediately when
1818 * they see this status (any time they drop and re-acquire xhci->lock).
1819 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1820 * putting the TD on the canceled list, etc.
1822 * There are no reports of xHCI host controllers that display this issue.
1824 #define XHCI_STATE_DYING (1 << 0)
1825 #define XHCI_STATE_HALTED (1 << 1)
1826 #define XHCI_STATE_REMOVING (1 << 2)
1827 unsigned long long quirks;
1828 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1829 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
1830 #define XHCI_NEC_HOST BIT_ULL(2)
1831 #define XHCI_AMD_PLL_FIX BIT_ULL(3)
1832 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1834 * Certain Intel host controllers have a limit to the number of endpoint
1835 * contexts they can handle. Ideally, they would signal that they can't handle
1836 * anymore endpoint contexts by returning a Resource Error for the Configure
1837 * Endpoint command, but they don't. Instead they expect software to keep track
1838 * of the number of active endpoints for them, across configure endpoint
1839 * commands, reset device commands, disable slot commands, and address device
1842 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1843 #define XHCI_BROKEN_MSI BIT_ULL(6)
1844 #define XHCI_RESET_ON_RESUME BIT_ULL(7)
1845 #define XHCI_SW_BW_CHECKING BIT_ULL(8)
1846 #define XHCI_AMD_0x96_HOST BIT_ULL(9)
1847 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1848 #define XHCI_LPM_SUPPORT BIT_ULL(11)
1849 #define XHCI_INTEL_HOST BIT_ULL(12)
1850 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1851 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1852 #define XHCI_AVOID_BEI BIT_ULL(15)
1853 #define XHCI_PLAT BIT_ULL(16) /* Deprecated */
1854 #define XHCI_SLOW_SUSPEND BIT_ULL(17)
1855 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1856 /* For controllers with a broken beyond repair streams implementation */
1857 #define XHCI_BROKEN_STREAMS BIT_ULL(19)
1858 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1859 #define XHCI_MTK_HOST BIT_ULL(21)
1860 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1861 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1862 #define XHCI_MISSING_CAS BIT_ULL(24)
1863 /* For controller with a broken Port Disable implementation */
1864 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1865 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1866 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1867 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1868 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1869 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
1870 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1871 #define XHCI_ZERO_64B_REGS BIT_ULL(32)
1872 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1873 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1874 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1875 #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
1876 #define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1877 #define XHCI_DISABLE_SPARSE BIT_ULL(38)
1878 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1879 #define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1880 #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41)
1881 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
1882 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
1883 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
1884 #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
1885 #define XHCI_ZHAOXIN_HOST BIT_ULL(46)
1887 unsigned int num_active_eps;
1888 unsigned int limit_active_eps;
1889 struct xhci_port *hw_ports;
1890 struct xhci_hub usb2_rhub;
1891 struct xhci_hub usb3_rhub;
1892 /* support xHCI 1.0 spec USB2 hardware LPM */
1893 unsigned hw_lpm_support:1;
1894 /* Broken Suspend flag for SNPS Suspend resume issue */
1895 unsigned broken_suspend:1;
1896 /* Indicates that omitting hcd is supported if root hub has no ports */
1897 unsigned allow_single_roothub:1;
1898 /* cached usb2 extened protocol capabilites */
1900 unsigned int num_ext_caps;
1901 /* cached extended protocol port capabilities */
1902 struct xhci_port_cap *port_caps;
1903 unsigned int num_port_caps;
1904 /* Compliance Mode Recovery Data */
1905 struct timer_list comp_mode_recovery_timer;
1908 /* Compliance Mode Timer Triggered every 2 seconds */
1909 #define COMP_MODE_RCVRY_MSECS 2000
1911 struct dentry *debugfs_root;
1912 struct dentry *debugfs_slots;
1913 struct list_head regset_list;
1916 /* platform-specific data -- must come last */
1917 unsigned long priv[] __aligned(sizeof(s64));
1920 /* Platform specific overrides to generic XHCI hc_driver ops */
1921 struct xhci_driver_overrides {
1922 size_t extra_priv_size;
1923 int (*reset)(struct usb_hcd *hcd);
1924 int (*start)(struct usb_hcd *hcd);
1925 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1926 struct usb_host_endpoint *ep);
1927 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1928 struct usb_host_endpoint *ep);
1929 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1930 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1931 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev,
1932 struct usb_tt *tt, gfp_t mem_flags);
1933 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1934 u16 wIndex, char *buf, u16 wLength);
1937 #define XHCI_CFC_DELAY 10
1939 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1940 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1942 struct usb_hcd *primary_hcd;
1944 if (usb_hcd_is_primary_hcd(hcd))
1947 primary_hcd = hcd->primary_hcd;
1949 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1952 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1954 return xhci->main_hcd;
1957 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci)
1959 if (xhci->shared_hcd)
1960 return xhci->shared_hcd;
1962 if (!xhci->usb2_rhub.num_ports)
1963 return xhci->main_hcd;
1968 static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd)
1970 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1972 return hcd == xhci_get_usb3_hcd(xhci);
1975 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci)
1977 return xhci->allow_single_roothub &&
1978 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);
1981 #define xhci_dbg(xhci, fmt, args...) \
1982 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1983 #define xhci_err(xhci, fmt, args...) \
1984 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1985 #define xhci_warn(xhci, fmt, args...) \
1986 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1987 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1988 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1989 #define xhci_info(xhci, fmt, args...) \
1990 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1993 * Registers should always be accessed with double word or quad word accesses.
1995 * Some xHCI implementations may support 64-bit address pointers. Registers
1996 * with 64-bit address pointers should be written to with dword accesses by
1997 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1998 * xHCI implementations that do not support 64-bit address pointers will ignore
1999 * the high dword, and write order is irrelevant.
2001 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
2002 __le64 __iomem *regs)
2004 return lo_hi_readq(regs);
2006 static inline void xhci_write_64(struct xhci_hcd *xhci,
2007 const u64 val, __le64 __iomem *regs)
2009 lo_hi_writeq(val, regs);
2012 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
2014 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
2017 /* xHCI debugging */
2018 char *xhci_get_slot_state(struct xhci_hcd *xhci,
2019 struct xhci_container_ctx *ctx);
2020 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
2021 const char *fmt, ...);
2023 /* xHCI memory management */
2024 void xhci_mem_cleanup(struct xhci_hcd *xhci);
2025 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
2026 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
2027 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
2028 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
2029 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
2030 struct usb_device *udev);
2031 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
2032 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
2033 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
2034 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2035 struct xhci_virt_device *virt_dev,
2036 int old_active_eps);
2037 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
2038 void xhci_update_bw_info(struct xhci_hcd *xhci,
2039 struct xhci_container_ctx *in_ctx,
2040 struct xhci_input_control_ctx *ctrl_ctx,
2041 struct xhci_virt_device *virt_dev);
2042 void xhci_endpoint_copy(struct xhci_hcd *xhci,
2043 struct xhci_container_ctx *in_ctx,
2044 struct xhci_container_ctx *out_ctx,
2045 unsigned int ep_index);
2046 void xhci_slot_copy(struct xhci_hcd *xhci,
2047 struct xhci_container_ctx *in_ctx,
2048 struct xhci_container_ctx *out_ctx);
2049 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
2050 struct usb_device *udev, struct usb_host_endpoint *ep,
2052 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
2053 unsigned int num_segs, unsigned int cycle_state,
2054 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
2055 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
2056 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
2057 unsigned int num_trbs, gfp_t flags);
2058 void xhci_initialize_ring_info(struct xhci_ring *ring,
2059 unsigned int cycle_state);
2060 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
2061 struct xhci_virt_device *virt_dev,
2062 unsigned int ep_index);
2063 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2064 unsigned int num_stream_ctxs,
2065 unsigned int num_streams,
2066 unsigned int max_packet, gfp_t flags);
2067 void xhci_free_stream_info(struct xhci_hcd *xhci,
2068 struct xhci_stream_info *stream_info);
2069 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2070 struct xhci_ep_ctx *ep_ctx,
2071 struct xhci_stream_info *stream_info);
2072 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2073 struct xhci_virt_ep *ep);
2074 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2075 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2076 struct xhci_ring *xhci_dma_to_transfer_ring(
2077 struct xhci_virt_ep *ep,
2079 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2080 bool allocate_completion, gfp_t mem_flags);
2081 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2082 bool allocate_completion, gfp_t mem_flags);
2083 void xhci_urb_free_priv(struct urb_priv *urb_priv);
2084 void xhci_free_command(struct xhci_hcd *xhci,
2085 struct xhci_command *command);
2086 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2087 int type, gfp_t flags);
2088 void xhci_free_container_ctx(struct xhci_hcd *xhci,
2089 struct xhci_container_ctx *ctx);
2090 struct xhci_interrupter *
2091 xhci_create_secondary_interrupter(struct usb_hcd *hcd, int num_seg);
2092 void xhci_remove_secondary_interrupter(struct usb_hcd
2093 *hcd, struct xhci_interrupter *ir);
2095 /* xHCI host controller glue */
2096 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2097 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
2098 int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr,
2099 u32 mask, u32 done, int usec, unsigned int exit_state);
2100 void xhci_quiesce(struct xhci_hcd *xhci);
2101 int xhci_halt(struct xhci_hcd *xhci);
2102 int xhci_start(struct xhci_hcd *xhci);
2103 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
2104 int xhci_run(struct usb_hcd *hcd);
2105 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2106 void xhci_shutdown(struct usb_hcd *hcd);
2107 void xhci_stop(struct usb_hcd *hcd);
2108 void xhci_init_driver(struct hc_driver *drv,
2109 const struct xhci_driver_overrides *over);
2110 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2111 struct usb_host_endpoint *ep);
2112 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2113 struct usb_host_endpoint *ep);
2114 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2115 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2116 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
2117 struct usb_tt *tt, gfp_t mem_flags);
2118 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2119 int xhci_ext_cap_init(struct xhci_hcd *xhci);
2121 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2122 int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg);
2124 irqreturn_t xhci_irq(struct usb_hcd *hcd);
2125 irqreturn_t xhci_msi_irq(int irq, void *hcd);
2126 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2127 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2128 struct xhci_virt_device *virt_dev,
2129 struct usb_device *hdev,
2130 struct usb_tt *tt, gfp_t mem_flags);
2132 /* xHCI ring, segment, TRB, and TD functions */
2133 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2134 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2135 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2136 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2137 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2138 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2139 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2140 u32 trb_type, u32 slot_id);
2141 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2142 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2143 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2144 u32 field1, u32 field2, u32 field3, u32 field4);
2145 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2146 int slot_id, unsigned int ep_index, int suspend);
2147 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2148 int slot_id, unsigned int ep_index);
2149 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2150 int slot_id, unsigned int ep_index);
2151 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2152 int slot_id, unsigned int ep_index);
2153 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2154 struct urb *urb, int slot_id, unsigned int ep_index);
2155 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2156 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2157 bool command_must_succeed);
2158 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2159 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2160 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2161 int slot_id, unsigned int ep_index,
2162 enum xhci_ep_reset_type reset_type);
2163 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2165 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
2166 unsigned int ep_index, unsigned int stream_id,
2167 struct xhci_td *td);
2168 void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2169 void xhci_handle_command_timeout(struct work_struct *work);
2171 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2172 unsigned int ep_index, unsigned int stream_id);
2173 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
2174 unsigned int slot_id,
2175 unsigned int ep_index);
2176 void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2177 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2178 unsigned int count_trbs(u64 addr, u64 len);
2180 /* xHCI roothub code */
2181 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2183 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2185 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2186 char *buf, u16 wLength);
2187 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2188 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2189 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2191 void xhci_hc_died(struct xhci_hcd *xhci);
2194 int xhci_bus_suspend(struct usb_hcd *hcd);
2195 int xhci_bus_resume(struct usb_hcd *hcd);
2196 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2198 #define xhci_bus_suspend NULL
2199 #define xhci_bus_resume NULL
2200 #define xhci_get_resuming_ports NULL
2201 #endif /* CONFIG_PM */
2203 u32 xhci_port_state_to_neutral(u32 state);
2204 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2206 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2209 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2210 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2211 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2213 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2214 unsigned int slot_id, unsigned int ep_index,
2215 unsigned int stream_id);
2217 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2220 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2221 xhci_get_endpoint_index(&urb->ep->desc),
2226 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
2227 * them anyways as we where unable to find a device that matches the
2230 static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2232 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2233 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2234 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2235 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
2242 static inline char *xhci_slot_state_string(u32 state)
2245 case SLOT_STATE_ENABLED:
2246 return "enabled/disabled";
2247 case SLOT_STATE_DEFAULT:
2249 case SLOT_STATE_ADDRESSED:
2251 case SLOT_STATE_CONFIGURED:
2252 return "configured";
2258 static inline const char *xhci_decode_trb(char *str, size_t size,
2259 u32 field0, u32 field1, u32 field2, u32 field3)
2261 int type = TRB_FIELD_TO_TYPE(field3);
2266 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2267 field1, field0, GET_INTR_TARGET(field2),
2268 xhci_trb_type_string(type),
2269 field3 & TRB_IOC ? 'I' : 'i',
2270 field3 & TRB_CHAIN ? 'C' : 'c',
2271 field3 & TRB_TC ? 'T' : 't',
2272 field3 & TRB_CYCLE ? 'C' : 'c');
2275 case TRB_COMPLETION:
2276 case TRB_PORT_STATUS:
2277 case TRB_BANDWIDTH_EVENT:
2281 case TRB_MFINDEX_WRAP:
2283 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2285 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2286 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2287 /* Macro decrements 1, maybe it shouldn't?!? */
2288 TRB_TO_EP_INDEX(field3) + 1,
2289 xhci_trb_type_string(type),
2290 field3 & EVENT_DATA ? 'E' : 'e',
2291 field3 & TRB_CYCLE ? 'C' : 'c');
2296 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2298 (field0 & 0xff00) >> 8,
2299 (field0 & 0xff000000) >> 24,
2300 (field0 & 0xff0000) >> 16,
2301 (field1 & 0xff00) >> 8,
2303 (field1 & 0xff000000) >> 16 |
2304 (field1 & 0xff0000) >> 16,
2305 TRB_LEN(field2), GET_TD_SIZE(field2),
2306 GET_INTR_TARGET(field2),
2307 xhci_trb_type_string(type),
2308 field3 & TRB_IDT ? 'I' : 'i',
2309 field3 & TRB_IOC ? 'I' : 'i',
2310 field3 & TRB_CYCLE ? 'C' : 'c');
2314 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2315 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2316 GET_INTR_TARGET(field2),
2317 xhci_trb_type_string(type),
2318 field3 & TRB_IDT ? 'I' : 'i',
2319 field3 & TRB_IOC ? 'I' : 'i',
2320 field3 & TRB_CHAIN ? 'C' : 'c',
2321 field3 & TRB_NO_SNOOP ? 'S' : 's',
2322 field3 & TRB_ISP ? 'I' : 'i',
2323 field3 & TRB_ENT ? 'E' : 'e',
2324 field3 & TRB_CYCLE ? 'C' : 'c');
2328 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2329 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2330 GET_INTR_TARGET(field2),
2331 xhci_trb_type_string(type),
2332 field3 & TRB_IOC ? 'I' : 'i',
2333 field3 & TRB_CHAIN ? 'C' : 'c',
2334 field3 & TRB_ENT ? 'E' : 'e',
2335 field3 & TRB_CYCLE ? 'C' : 'c');
2339 case TRB_EVENT_DATA:
2342 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2343 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2344 GET_INTR_TARGET(field2),
2345 xhci_trb_type_string(type),
2346 field3 & TRB_BEI ? 'B' : 'b',
2347 field3 & TRB_IDT ? 'I' : 'i',
2348 field3 & TRB_IOC ? 'I' : 'i',
2349 field3 & TRB_CHAIN ? 'C' : 'c',
2350 field3 & TRB_NO_SNOOP ? 'S' : 's',
2351 field3 & TRB_ISP ? 'I' : 'i',
2352 field3 & TRB_ENT ? 'E' : 'e',
2353 field3 & TRB_CYCLE ? 'C' : 'c');
2357 case TRB_ENABLE_SLOT:
2360 xhci_trb_type_string(type),
2361 field3 & TRB_CYCLE ? 'C' : 'c');
2363 case TRB_DISABLE_SLOT:
2364 case TRB_NEG_BANDWIDTH:
2366 "%s: slot %d flags %c",
2367 xhci_trb_type_string(type),
2368 TRB_TO_SLOT_ID(field3),
2369 field3 & TRB_CYCLE ? 'C' : 'c');
2373 "%s: ctx %08x%08x slot %d flags %c:%c",
2374 xhci_trb_type_string(type),
2376 TRB_TO_SLOT_ID(field3),
2377 field3 & TRB_BSR ? 'B' : 'b',
2378 field3 & TRB_CYCLE ? 'C' : 'c');
2382 "%s: ctx %08x%08x slot %d flags %c:%c",
2383 xhci_trb_type_string(type),
2385 TRB_TO_SLOT_ID(field3),
2386 field3 & TRB_DC ? 'D' : 'd',
2387 field3 & TRB_CYCLE ? 'C' : 'c');
2389 case TRB_EVAL_CONTEXT:
2391 "%s: ctx %08x%08x slot %d flags %c",
2392 xhci_trb_type_string(type),
2394 TRB_TO_SLOT_ID(field3),
2395 field3 & TRB_CYCLE ? 'C' : 'c');
2399 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2400 xhci_trb_type_string(type),
2402 TRB_TO_SLOT_ID(field3),
2403 /* Macro decrements 1, maybe it shouldn't?!? */
2404 TRB_TO_EP_INDEX(field3) + 1,
2405 field3 & TRB_TSP ? 'T' : 't',
2406 field3 & TRB_CYCLE ? 'C' : 'c');
2410 "%s: slot %d sp %d ep %d flags %c",
2411 xhci_trb_type_string(type),
2412 TRB_TO_SLOT_ID(field3),
2413 TRB_TO_SUSPEND_PORT(field3),
2414 /* Macro decrements 1, maybe it shouldn't?!? */
2415 TRB_TO_EP_INDEX(field3) + 1,
2416 field3 & TRB_CYCLE ? 'C' : 'c');
2420 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2421 xhci_trb_type_string(type),
2423 TRB_TO_STREAM_ID(field2),
2424 TRB_TO_SLOT_ID(field3),
2425 /* Macro decrements 1, maybe it shouldn't?!? */
2426 TRB_TO_EP_INDEX(field3) + 1,
2427 field3 & TRB_CYCLE ? 'C' : 'c');
2431 "%s: slot %d flags %c",
2432 xhci_trb_type_string(type),
2433 TRB_TO_SLOT_ID(field3),
2434 field3 & TRB_CYCLE ? 'C' : 'c');
2436 case TRB_FORCE_EVENT:
2438 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2439 xhci_trb_type_string(type),
2441 TRB_TO_VF_INTR_TARGET(field2),
2442 TRB_TO_VF_ID(field3),
2443 field3 & TRB_CYCLE ? 'C' : 'c');
2447 "%s: belt %d flags %c",
2448 xhci_trb_type_string(type),
2449 TRB_TO_BELT(field3),
2450 field3 & TRB_CYCLE ? 'C' : 'c');
2454 "%s: ctx %08x%08x slot %d speed %d flags %c",
2455 xhci_trb_type_string(type),
2457 TRB_TO_SLOT_ID(field3),
2458 TRB_TO_DEV_SPEED(field3),
2459 field3 & TRB_CYCLE ? 'C' : 'c');
2461 case TRB_FORCE_HEADER:
2463 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2464 xhci_trb_type_string(type),
2465 field2, field1, field0 & 0xffffffe0,
2466 TRB_TO_PACKET_TYPE(field0),
2467 TRB_TO_ROOTHUB_PORT(field3),
2468 field3 & TRB_CYCLE ? 'C' : 'c');
2472 "type '%s' -> raw %08x %08x %08x %08x",
2473 xhci_trb_type_string(type),
2474 field0, field1, field2, field3);
2480 static inline const char *xhci_decode_ctrl_ctx(char *str,
2481 unsigned long drop, unsigned long add)
2489 ret = sprintf(str, "Drop:");
2490 for_each_set_bit(bit, &drop, 32)
2491 ret += sprintf(str + ret, " %d%s",
2493 bit % 2 ? "in":"out");
2494 ret += sprintf(str + ret, ", ");
2498 ret += sprintf(str + ret, "Add:%s%s",
2499 (add & SLOT_FLAG) ? " slot":"",
2500 (add & EP0_FLAG) ? " ep0":"");
2501 add &= ~(SLOT_FLAG | EP0_FLAG);
2502 for_each_set_bit(bit, &add, 32)
2503 ret += sprintf(str + ret, " %d%s",
2505 bit % 2 ? "in":"out");
2510 static inline const char *xhci_decode_slot_context(char *str,
2511 u32 info, u32 info2, u32 tt_info, u32 state)
2518 speed = info & DEV_SPEED;
2519 hub = info & DEV_HUB;
2520 mtt = info & DEV_MTT;
2522 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2523 info & ROUTE_STRING_MASK,
2538 case SLOT_SPEED_SSP:
2539 s = "super-speed plus";
2542 s = "UNKNOWN speed";
2544 mtt ? " multi-TT" : "",
2546 (info & LAST_CTX_MASK) >> 27,
2548 DEVINFO_TO_ROOT_HUB_PORT(info2),
2549 DEVINFO_TO_MAX_PORTS(info2));
2551 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2552 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2553 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2554 state & DEV_ADDR_MASK,
2555 xhci_slot_state_string(GET_SLOT_STATE(state)));
2561 static inline const char *xhci_portsc_link_state_string(u32 portsc)
2563 switch (portsc & PORT_PLS_MASK) {
2582 case XDEV_HOT_RESET:
2584 case XDEV_COMP_MODE:
2585 return "Compliance mode";
2586 case XDEV_TEST_MODE:
2596 static inline const char *xhci_decode_portsc(char *str, u32 portsc)
2600 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2601 portsc & PORT_POWER ? "Powered" : "Powered-off",
2602 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2603 portsc & PORT_PE ? "Enabled" : "Disabled",
2604 xhci_portsc_link_state_string(portsc),
2605 DEV_PORT_SPEED(portsc));
2607 if (portsc & PORT_OC)
2608 ret += sprintf(str + ret, "OverCurrent ");
2609 if (portsc & PORT_RESET)
2610 ret += sprintf(str + ret, "In-Reset ");
2612 ret += sprintf(str + ret, "Change: ");
2613 if (portsc & PORT_CSC)
2614 ret += sprintf(str + ret, "CSC ");
2615 if (portsc & PORT_PEC)
2616 ret += sprintf(str + ret, "PEC ");
2617 if (portsc & PORT_WRC)
2618 ret += sprintf(str + ret, "WRC ");
2619 if (portsc & PORT_OCC)
2620 ret += sprintf(str + ret, "OCC ");
2621 if (portsc & PORT_RC)
2622 ret += sprintf(str + ret, "PRC ");
2623 if (portsc & PORT_PLC)
2624 ret += sprintf(str + ret, "PLC ");
2625 if (portsc & PORT_CEC)
2626 ret += sprintf(str + ret, "CEC ");
2627 if (portsc & PORT_CAS)
2628 ret += sprintf(str + ret, "CAS ");
2630 ret += sprintf(str + ret, "Wake: ");
2631 if (portsc & PORT_WKCONN_E)
2632 ret += sprintf(str + ret, "WCE ");
2633 if (portsc & PORT_WKDISC_E)
2634 ret += sprintf(str + ret, "WDE ");
2635 if (portsc & PORT_WKOC_E)
2636 ret += sprintf(str + ret, "WOE ");
2641 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
2645 ret = sprintf(str, " 0x%08x", usbsts);
2647 if (usbsts == ~(u32)0)
2650 if (usbsts & STS_HALT)
2651 ret += sprintf(str + ret, " HCHalted");
2652 if (usbsts & STS_FATAL)
2653 ret += sprintf(str + ret, " HSE");
2654 if (usbsts & STS_EINT)
2655 ret += sprintf(str + ret, " EINT");
2656 if (usbsts & STS_PORT)
2657 ret += sprintf(str + ret, " PCD");
2658 if (usbsts & STS_SAVE)
2659 ret += sprintf(str + ret, " SSS");
2660 if (usbsts & STS_RESTORE)
2661 ret += sprintf(str + ret, " RSS");
2662 if (usbsts & STS_SRE)
2663 ret += sprintf(str + ret, " SRE");
2664 if (usbsts & STS_CNR)
2665 ret += sprintf(str + ret, " CNR");
2666 if (usbsts & STS_HCE)
2667 ret += sprintf(str + ret, " HCE");
2672 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
2678 ep = (doorbell & 0xff);
2679 stream = doorbell >> 16;
2682 sprintf(str, "Command Ring %d", doorbell);
2685 ret = sprintf(str, "Slot %d ", slot);
2686 if (ep > 0 && ep < 32)
2687 ret = sprintf(str + ret, "ep%d%s",
2689 ep % 2 ? "in" : "out");
2690 else if (ep == 0 || ep < 248)
2691 ret = sprintf(str + ret, "Reserved %d", ep);
2693 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2695 ret = sprintf(str + ret, " Stream %d", stream);
2700 static inline const char *xhci_ep_state_string(u8 state)
2703 case EP_STATE_DISABLED:
2705 case EP_STATE_RUNNING:
2707 case EP_STATE_HALTED:
2709 case EP_STATE_STOPPED:
2711 case EP_STATE_ERROR:
2718 static inline const char *xhci_ep_type_string(u8 type)
2740 static inline const char *xhci_decode_ep_context(char *str, u32 info,
2741 u32 info2, u64 deq, u32 tx_info)
2760 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2761 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2763 ep_state = info & EP_STATE_MASK;
2764 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2765 interval = CTX_TO_EP_INTERVAL(info);
2766 mult = CTX_TO_EP_MULT(info) + 1;
2767 lsa = !!(info & EP_HAS_LSA);
2769 cerr = (info2 & (3 << 1)) >> 1;
2770 ep_type = CTX_TO_EP_TYPE(info2);
2771 hid = !!(info2 & (1 << 7));
2772 burst = CTX_TO_MAX_BURST(info2);
2773 maxp = MAX_PACKET_DECODED(info2);
2775 avg = EP_AVG_TRB_LENGTH(tx_info);
2777 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2778 xhci_ep_state_string(ep_state), mult,
2779 max_pstr, lsa ? "LSA " : "");
2781 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2782 (1 << interval) * 125, esit, cerr);
2784 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2785 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2788 ret += sprintf(str + ret, "avg trb len %d", avg);
2793 #endif /* __LINUX_XHCI_HCD_H */