3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software Foundation,
21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #ifndef __LINUX_XHCI_HCD_H
25 #define __LINUX_XHCI_HCD_H
27 #include <linux/usb.h>
28 #include <linux/timer.h>
29 #include <linux/kernel.h>
30 #include <linux/usb/hcd.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
33 /* Code sharing between pci-quirks and xhci hcd */
34 #include "xhci-ext-caps.h"
35 #include "pci-quirks.h"
37 /* xHCI PCI Configuration Registers */
38 #define XHCI_SBRN_OFFSET (0x60)
40 /* Max number of USB devices for any host controller - limit in section 6.1 */
41 #define MAX_HC_SLOTS 256
42 /* Section 5.3.3 - MaxPorts */
43 #define MAX_HC_PORTS 127
46 * xHCI register interface.
47 * This corresponds to the eXtensible Host Controller Interface (xHCI)
48 * Revision 0.95 specification
52 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
53 * @hc_capbase: length of the capabilities register and HC version number
54 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
55 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
56 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
57 * @hcc_params: HCCPARAMS - Capability Parameters
58 * @db_off: DBOFF - Doorbell array offset
59 * @run_regs_off: RTSOFF - Runtime register space offset
60 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
62 struct xhci_cap_regs {
70 __le32 hcc_params2; /* xhci 1.1 */
71 /* Reserved up to (CAPLENGTH - 0x1C) */
74 /* hc_capbase bitmasks */
75 /* bits 7:0 - how long is the Capabilities register */
76 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
78 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
80 /* HCSPARAMS1 - hcs_params1 - bitmasks */
81 /* bits 0:7, Max Device Slots */
82 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
83 #define HCS_SLOTS_MASK 0xff
84 /* bits 8:18, Max Interrupters */
85 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
86 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
87 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
89 /* HCSPARAMS2 - hcs_params2 - bitmasks */
90 /* bits 0:3, frames or uframes that SW needs to queue transactions
91 * ahead of the HW to meet periodic deadlines */
92 #define HCS_IST(p) (((p) >> 0) & 0xf)
93 /* bits 4:7, max number of Event Ring segments */
94 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
95 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
96 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
97 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
98 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
100 /* HCSPARAMS3 - hcs_params3 - bitmasks */
101 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
102 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
103 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
104 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
106 /* HCCPARAMS - hcc_params - bitmasks */
107 /* true: HC can use 64-bit address pointers */
108 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
109 /* true: HC can do bandwidth negotiation */
110 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
111 /* true: HC uses 64-byte Device Context structures
112 * FIXME 64-byte context structures aren't supported yet.
114 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
115 /* true: HC has port power switches */
116 #define HCC_PPC(p) ((p) & (1 << 3))
117 /* true: HC has port indicators */
118 #define HCS_INDICATOR(p) ((p) & (1 << 4))
119 /* true: HC has Light HC Reset Capability */
120 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
121 /* true: HC supports latency tolerance messaging */
122 #define HCC_LTC(p) ((p) & (1 << 6))
123 /* true: no secondary Stream ID Support */
124 #define HCC_NSS(p) ((p) & (1 << 7))
125 /* true: HC supports Stopped - Short Packet */
126 #define HCC_SPC(p) ((p) & (1 << 9))
127 /* true: HC has Contiguous Frame ID Capability */
128 #define HCC_CFC(p) ((p) & (1 << 11))
129 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
130 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
131 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
132 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
134 /* db_off bitmask - bits 0:1 reserved */
135 #define DBOFF_MASK (~0x3)
137 /* run_regs_off bitmask - bits 0:4 reserved */
138 #define RTSOFF_MASK (~0x1f)
140 /* HCCPARAMS2 - hcc_params2 - bitmasks */
141 /* true: HC supports U3 entry Capability */
142 #define HCC2_U3C(p) ((p) & (1 << 0))
143 /* true: HC supports Configure endpoint command Max exit latency too large */
144 #define HCC2_CMC(p) ((p) & (1 << 1))
145 /* true: HC supports Force Save context Capability */
146 #define HCC2_FSC(p) ((p) & (1 << 2))
147 /* true: HC supports Compliance Transition Capability */
148 #define HCC2_CTC(p) ((p) & (1 << 3))
149 /* true: HC support Large ESIT payload Capability > 48k */
150 #define HCC2_LEC(p) ((p) & (1 << 4))
151 /* true: HC support Configuration Information Capability */
152 #define HCC2_CIC(p) ((p) & (1 << 5))
153 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
154 #define HCC2_ETC(p) ((p) & (1 << 6))
156 /* Number of registers per port */
157 #define NUM_PORT_REGS 4
165 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
166 * @command: USBCMD - xHC command register
167 * @status: USBSTS - xHC status register
168 * @page_size: This indicates the page size that the host controller
169 * supports. If bit n is set, the HC supports a page size
170 * of 2^(n+12), up to a 128MB page size.
171 * 4K is the minimum page size.
172 * @cmd_ring: CRP - 64-bit Command Ring Pointer
173 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
174 * @config_reg: CONFIG - Configure Register
175 * @port_status_base: PORTSCn - base address for Port Status and Control
176 * Each port has a Port Status and Control register,
177 * followed by a Port Power Management Status and Control
178 * register, a Port Link Info register, and a reserved
180 * @port_power_base: PORTPMSCn - base address for
181 * Port Power Management Status and Control
182 * @port_link_base: PORTLIn - base address for Port Link Info (current
183 * Link PM state and control) for USB 2.1 and USB 3.0
186 struct xhci_op_regs {
192 __le32 dev_notification;
194 /* rsvd: offset 0x20-2F */
198 /* rsvd: offset 0x3C-3FF */
199 __le32 reserved4[241];
200 /* port 1 registers, which serve as a base address for other ports */
201 __le32 port_status_base;
202 __le32 port_power_base;
203 __le32 port_link_base;
205 /* registers for ports 2-255 */
206 __le32 reserved6[NUM_PORT_REGS*254];
209 /* USBCMD - USB command - command bitmasks */
210 /* start/stop HC execution - do not write unless HC is halted*/
211 #define CMD_RUN XHCI_CMD_RUN
212 /* Reset HC - resets internal HC state machine and all registers (except
213 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
214 * The xHCI driver must reinitialize the xHC after setting this bit.
216 #define CMD_RESET (1 << 1)
217 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
218 #define CMD_EIE XHCI_CMD_EIE
219 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
220 #define CMD_HSEIE XHCI_CMD_HSEIE
221 /* bits 4:6 are reserved (and should be preserved on writes). */
222 /* light reset (port status stays unchanged) - reset completed when this is 0 */
223 #define CMD_LRESET (1 << 7)
224 /* host controller save/restore state. */
225 #define CMD_CSS (1 << 8)
226 #define CMD_CRS (1 << 9)
227 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
228 #define CMD_EWE XHCI_CMD_EWE
229 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
230 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
231 * '0' means the xHC can power it off if all ports are in the disconnect,
232 * disabled, or powered-off state.
234 #define CMD_PM_INDEX (1 << 11)
235 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
236 #define CMD_ETE (1 << 14)
237 /* bits 15:31 are reserved (and should be preserved on writes). */
239 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
240 #define XHCI_RESET_SHORT_USEC (250 * 1000)
242 /* IMAN - Interrupt Management Register */
243 #define IMAN_IE (1 << 1)
244 #define IMAN_IP (1 << 0)
246 /* USBSTS - USB status - status bitmasks */
247 /* HC not running - set to 1 when run/stop bit is cleared. */
248 #define STS_HALT XHCI_STS_HALT
249 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
250 #define STS_FATAL (1 << 2)
251 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
252 #define STS_EINT (1 << 3)
253 /* port change detect */
254 #define STS_PORT (1 << 4)
255 /* bits 5:7 reserved and zeroed */
256 /* save state status - '1' means xHC is saving state */
257 #define STS_SAVE (1 << 8)
258 /* restore state status - '1' means xHC is restoring state */
259 #define STS_RESTORE (1 << 9)
260 /* true: save or restore error */
261 #define STS_SRE (1 << 10)
262 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
263 #define STS_CNR XHCI_STS_CNR
264 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
265 #define STS_HCE (1 << 12)
266 /* bits 13:31 reserved and should be preserved */
269 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
270 * Generate a device notification event when the HC sees a transaction with a
271 * notification type that matches a bit set in this bit field.
273 #define DEV_NOTE_MASK (0xffff)
274 #define ENABLE_DEV_NOTE(x) (1 << (x))
275 /* Most of the device notification types should only be used for debug.
276 * SW does need to pay attention to function wake notifications.
278 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
280 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
281 /* bit 0 is the command ring cycle state */
282 /* stop ring operation after completion of the currently executing command */
283 #define CMD_RING_PAUSE (1 << 1)
284 /* stop ring immediately - abort the currently executing command */
285 #define CMD_RING_ABORT (1 << 2)
286 /* true: command ring is running */
287 #define CMD_RING_RUNNING (1 << 3)
288 /* bits 4:5 reserved and should be preserved */
289 /* Command Ring pointer - bit mask for the lower 32 bits. */
290 #define CMD_RING_RSVD_BITS (0x3f)
292 /* CONFIG - Configure Register - config_reg bitmasks */
293 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
294 #define MAX_DEVS(p) ((p) & 0xff)
295 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
296 #define CONFIG_U3E (1 << 8)
297 /* bit 9: Configuration Information Enable, xhci 1.1 */
298 #define CONFIG_CIE (1 << 9)
299 /* bits 10:31 - reserved and should be preserved */
301 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
302 /* true: device connected */
303 #define PORT_CONNECT (1 << 0)
304 /* true: port enabled */
305 #define PORT_PE (1 << 1)
306 /* bit 2 reserved and zeroed */
307 /* true: port has an over-current condition */
308 #define PORT_OC (1 << 3)
309 /* true: port reset signaling asserted */
310 #define PORT_RESET (1 << 4)
311 /* Port Link State - bits 5:8
312 * A read gives the current link PM state of the port,
313 * a write with Link State Write Strobe set sets the link state.
315 #define PORT_PLS_MASK (0xf << 5)
316 #define XDEV_U0 (0x0 << 5)
317 #define XDEV_U1 (0x1 << 5)
318 #define XDEV_U2 (0x2 << 5)
319 #define XDEV_U3 (0x3 << 5)
320 #define XDEV_DISABLED (0x4 << 5)
321 #define XDEV_RXDETECT (0x5 << 5)
322 #define XDEV_INACTIVE (0x6 << 5)
323 #define XDEV_POLLING (0x7 << 5)
324 #define XDEV_RECOVERY (0x8 << 5)
325 #define XDEV_HOT_RESET (0x9 << 5)
326 #define XDEV_COMP_MODE (0xa << 5)
327 #define XDEV_TEST_MODE (0xb << 5)
328 #define XDEV_RESUME (0xf << 5)
330 /* true: port has power (see HCC_PPC) */
331 #define PORT_POWER (1 << 9)
332 /* bits 10:13 indicate device speed:
333 * 0 - undefined speed - port hasn't be initialized by a reset yet
340 #define DEV_SPEED_MASK (0xf << 10)
341 #define XDEV_FS (0x1 << 10)
342 #define XDEV_LS (0x2 << 10)
343 #define XDEV_HS (0x3 << 10)
344 #define XDEV_SS (0x4 << 10)
345 #define XDEV_SSP (0x5 << 10)
346 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
347 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
348 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
349 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
350 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
351 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
352 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
353 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
355 /* Bits 20:23 in the Slot Context are the speed for the device */
356 #define SLOT_SPEED_FS (XDEV_FS << 10)
357 #define SLOT_SPEED_LS (XDEV_LS << 10)
358 #define SLOT_SPEED_HS (XDEV_HS << 10)
359 #define SLOT_SPEED_SS (XDEV_SS << 10)
360 #define SLOT_SPEED_SSP (XDEV_SSP << 10)
361 /* Port Indicator Control */
362 #define PORT_LED_OFF (0 << 14)
363 #define PORT_LED_AMBER (1 << 14)
364 #define PORT_LED_GREEN (2 << 14)
365 #define PORT_LED_MASK (3 << 14)
366 /* Port Link State Write Strobe - set this when changing link state */
367 #define PORT_LINK_STROBE (1 << 16)
368 /* true: connect status change */
369 #define PORT_CSC (1 << 17)
370 /* true: port enable change */
371 #define PORT_PEC (1 << 18)
372 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
373 * into an enabled state, and the device into the default state. A "warm" reset
374 * also resets the link, forcing the device through the link training sequence.
375 * SW can also look at the Port Reset register to see when warm reset is done.
377 #define PORT_WRC (1 << 19)
378 /* true: over-current change */
379 #define PORT_OCC (1 << 20)
380 /* true: reset change - 1 to 0 transition of PORT_RESET */
381 #define PORT_RC (1 << 21)
382 /* port link status change - set on some port link state transitions:
384 * ------------------------------------------------------------------------------
385 * - U3 to Resume Wakeup signaling from a device
386 * - Resume to Recovery to U0 USB 3.0 device resume
387 * - Resume to U0 USB 2.0 device resume
388 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
389 * - U3 to U0 Software resume of USB 2.0 device complete
390 * - U2 to U0 L1 resume of USB 2.1 device complete
391 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
392 * - U0 to disabled L1 entry error with USB 2.1 device
393 * - Any state to inactive Error on USB 3.0 port
395 #define PORT_PLC (1 << 22)
396 /* port configure error change - port failed to configure its link partner */
397 #define PORT_CEC (1 << 23)
398 #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
399 PORT_RC | PORT_PLC | PORT_CEC)
402 /* Cold Attach Status - xHC can set this bit to report device attached during
403 * Sx state. Warm port reset should be perfomed to clear this bit and move port
404 * to connected state.
406 #define PORT_CAS (1 << 24)
407 /* wake on connect (enable) */
408 #define PORT_WKCONN_E (1 << 25)
409 /* wake on disconnect (enable) */
410 #define PORT_WKDISC_E (1 << 26)
411 /* wake on over-current (enable) */
412 #define PORT_WKOC_E (1 << 27)
413 /* bits 28:29 reserved */
414 /* true: device is non-removable - for USB 3.0 roothub emulation */
415 #define PORT_DEV_REMOVE (1 << 30)
416 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
417 #define PORT_WR (1 << 31)
419 /* We mark duplicate entries with -1 */
420 #define DUPLICATE_ENTRY ((u8)(-1))
422 /* Port Power Management Status and Control - port_power_base bitmasks */
423 /* Inactivity timer value for transitions into U1, in microseconds.
424 * Timeout can be up to 127us. 0xFF means an infinite timeout.
426 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
427 #define PORT_U1_TIMEOUT_MASK 0xff
428 /* Inactivity timer value for transitions into U2 */
429 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
430 #define PORT_U2_TIMEOUT_MASK (0xff << 8)
431 /* Bits 24:31 for port testing */
433 /* USB2 Protocol PORTSPMSC */
434 #define PORT_L1S_MASK 7
435 #define PORT_L1S_SUCCESS 1
436 #define PORT_RWE (1 << 3)
437 #define PORT_HIRD(p) (((p) & 0xf) << 4)
438 #define PORT_HIRD_MASK (0xf << 4)
439 #define PORT_L1DS_MASK (0xff << 8)
440 #define PORT_L1DS(p) (((p) & 0xff) << 8)
441 #define PORT_HLE (1 << 16)
442 #define PORT_TEST_MODE_SHIFT 28
444 /* USB3 Protocol PORTLI Port Link Information */
445 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
446 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
448 /* USB2 Protocol PORTHLPMC */
449 #define PORT_HIRDM(p)((p) & 3)
450 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
451 #define PORT_BESLD(p)(((p) & 0xf) << 10)
453 /* use 512 microseconds as USB2 LPM L1 default timeout. */
454 #define XHCI_L1_TIMEOUT 512
456 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
457 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
458 * by other operating systems.
460 * XHCI 1.0 errata 8/14/12 Table 13 notes:
461 * "Software should choose xHC BESL/BESLD field values that do not violate a
462 * device's resume latency requirements,
463 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
464 * or not program values < '4' if BLC = '0' and a BESL device is attached.
466 #define XHCI_DEFAULT_BESL 4
469 * struct xhci_intr_reg - Interrupt Register Set
470 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
471 * interrupts and check for pending interrupts.
472 * @irq_control: IMOD - Interrupt Moderation Register.
473 * Used to throttle interrupts.
474 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
475 * @erst_base: ERST base address.
476 * @erst_dequeue: Event ring dequeue pointer.
478 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
479 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
480 * multiple segments of the same size. The HC places events on the ring and
481 * "updates the Cycle bit in the TRBs to indicate to software the current
482 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
483 * updates the dequeue pointer.
485 struct xhci_intr_reg {
494 /* irq_pending bitmasks */
495 #define ER_IRQ_PENDING(p) ((p) & 0x1)
496 /* bits 2:31 need to be preserved */
497 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
498 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
499 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
500 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
502 /* irq_control bitmasks */
503 /* Minimum interval between interrupts (in 250ns intervals). The interval
504 * between interrupts will be longer if there are no events on the event ring.
505 * Default is 4000 (1 ms).
507 #define ER_IRQ_INTERVAL_MASK (0xffff)
508 /* Counter used to count down the time to the next interrupt - HW use only */
509 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
511 /* erst_size bitmasks */
512 /* Preserve bits 16:31 of erst_size */
513 #define ERST_SIZE_MASK (0xffff << 16)
515 /* erst_dequeue bitmasks */
516 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
517 * where the current dequeue pointer lies. This is an optional HW hint.
519 #define ERST_DESI_MASK (0x7)
520 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
521 * a work queue (or delayed service routine)?
523 #define ERST_EHB (1 << 3)
524 #define ERST_PTR_MASK (0xf)
527 * struct xhci_run_regs
529 * MFINDEX - current microframe number
531 * Section 5.5 Host Controller Runtime Registers:
532 * "Software should read and write these registers using only Dword (32 bit)
533 * or larger accesses"
535 struct xhci_run_regs {
536 __le32 microframe_index;
538 struct xhci_intr_reg ir_set[128];
542 * struct doorbell_array
544 * Bits 0 - 7: Endpoint target
546 * Bits 16 - 31: Stream ID
550 struct xhci_doorbell_array {
551 __le32 doorbell[256];
554 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
555 #define DB_VALUE_HOST 0x00000000
558 * struct xhci_protocol_caps
559 * @revision: major revision, minor revision, capability ID,
560 * and next capability pointer.
561 * @name_string: Four ASCII characters to say which spec this xHC
562 * follows, typically "USB ".
563 * @port_info: Port offset, count, and protocol-defined information.
565 struct xhci_protocol_caps {
571 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
572 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
573 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
574 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
575 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
577 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
578 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
579 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
580 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
581 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
582 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
584 #define PLT_MASK (0x03 << 6)
585 #define PLT_SYM (0x00 << 6)
586 #define PLT_ASYM_RX (0x02 << 6)
587 #define PLT_ASYM_TX (0x03 << 6)
590 * struct xhci_container_ctx
591 * @type: Type of context. Used to calculated offsets to contained contexts.
592 * @size: Size of the context data
593 * @bytes: The raw context data given to HW
594 * @dma: dma address of the bytes
596 * Represents either a Device or Input context. Holds a pointer to the raw
597 * memory used for the context (bytes) and dma address of it (dma).
599 struct xhci_container_ctx {
601 #define XHCI_CTX_TYPE_DEVICE 0x1
602 #define XHCI_CTX_TYPE_INPUT 0x2
611 * struct xhci_slot_ctx
612 * @dev_info: Route string, device speed, hub info, and last valid endpoint
613 * @dev_info2: Max exit latency for device number, root hub port number
614 * @tt_info: tt_info is used to construct split transaction tokens
615 * @dev_state: slot state and device address
617 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
618 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
619 * reserved at the end of the slot context for HC internal use.
621 struct xhci_slot_ctx {
626 /* offset 0x10 to 0x1f reserved for HC internal use */
630 /* dev_info bitmasks */
631 /* Route String - 0:19 */
632 #define ROUTE_STRING_MASK (0xfffff)
633 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
634 #define DEV_SPEED (0xf << 20)
635 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
636 /* bit 24 reserved */
637 /* Is this LS/FS device connected through a HS hub? - bit 25 */
638 #define DEV_MTT (0x1 << 25)
639 /* Set if the device is a hub - bit 26 */
640 #define DEV_HUB (0x1 << 26)
641 /* Index of the last valid endpoint context in this device context - 27:31 */
642 #define LAST_CTX_MASK (0x1f << 27)
643 #define LAST_CTX(p) ((p) << 27)
644 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
645 #define SLOT_FLAG (1 << 0)
646 #define EP0_FLAG (1 << 1)
648 /* dev_info2 bitmasks */
649 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
650 #define MAX_EXIT (0xffff)
651 /* Root hub port number that is needed to access the USB device */
652 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
653 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
654 /* Maximum number of ports under a hub device */
655 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
656 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
658 /* tt_info bitmasks */
660 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
661 * The Slot ID of the hub that isolates the high speed signaling from
662 * this low or full-speed device. '0' if attached to root hub port.
664 #define TT_SLOT (0xff)
666 * The number of the downstream facing port of the high-speed hub
667 * '0' if the device is not low or full speed.
669 #define TT_PORT (0xff << 8)
670 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
671 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
673 /* dev_state bitmasks */
674 /* USB device address - assigned by the HC */
675 #define DEV_ADDR_MASK (0xff)
676 /* bits 8:26 reserved */
678 #define SLOT_STATE (0x1f << 27)
679 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
681 #define SLOT_STATE_DISABLED 0
682 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
683 #define SLOT_STATE_DEFAULT 1
684 #define SLOT_STATE_ADDRESSED 2
685 #define SLOT_STATE_CONFIGURED 3
689 * @ep_info: endpoint state, streams, mult, and interval information.
690 * @ep_info2: information on endpoint type, max packet size, max burst size,
691 * error count, and whether the HC will force an event for all
693 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
694 * defines one stream, this points to the endpoint transfer ring.
695 * Otherwise, it points to a stream context array, which has a
696 * ring pointer for each flow.
698 * Average TRB lengths for the endpoint ring and
699 * max payload within an Endpoint Service Interval Time (ESIT).
701 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
702 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
703 * reserved at the end of the endpoint context for HC internal use.
710 /* offset 0x14 - 0x1f reserved for HC internal use */
714 /* ep_info bitmasks */
716 * Endpoint State - bits 0:2
719 * 2 - halted due to halt condition - ok to manipulate endpoint ring
724 #define EP_STATE_MASK (0x7)
725 #define EP_STATE_DISABLED 0
726 #define EP_STATE_RUNNING 1
727 #define EP_STATE_HALTED 2
728 #define EP_STATE_STOPPED 3
729 #define EP_STATE_ERROR 4
730 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
732 /* Mult - Max number of burtst within an interval, in EP companion desc. */
733 #define EP_MULT(p) (((p) & 0x3) << 8)
734 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
735 /* bits 10:14 are Max Primary Streams */
736 /* bit 15 is Linear Stream Array */
737 /* Interval - period between requests to an endpoint - 125u increments. */
738 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
739 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
740 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
741 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
742 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
743 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
744 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
745 #define EP_HAS_LSA (1 << 15)
746 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
747 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
749 /* ep_info2 bitmasks */
751 * Force Event - generate transfer events for all TRBs for this endpoint
752 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
754 #define FORCE_EVENT (0x1)
755 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
756 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
757 #define EP_TYPE(p) ((p) << 3)
758 #define ISOC_OUT_EP 1
759 #define BULK_OUT_EP 2
766 /* bit 7 is Host Initiate Disable - for disabling stream selection */
767 #define MAX_BURST(p) (((p)&0xff) << 8)
768 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
769 #define MAX_PACKET(p) (((p)&0xffff) << 16)
770 #define MAX_PACKET_MASK (0xffff << 16)
771 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
773 /* tx_info bitmasks */
774 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
775 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
776 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
777 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
780 #define EP_CTX_CYCLE_MASK (1 << 0)
781 #define SCTX_DEQ_MASK (~0xfL)
785 * struct xhci_input_control_context
786 * Input control context; see section 6.2.5.
788 * @drop_context: set the bit of the endpoint context you want to disable
789 * @add_context: set the bit of the endpoint context you want to enable
791 struct xhci_input_control_ctx {
797 #define EP_IS_ADDED(ctrl_ctx, i) \
798 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
799 #define EP_IS_DROPPED(ctrl_ctx, i) \
800 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
802 /* Represents everything that is needed to issue a command on the command ring.
803 * It's useful to pre-allocate these for commands that cannot fail due to
804 * out-of-memory errors, like freeing streams.
806 struct xhci_command {
807 /* Input context for changing device state */
808 struct xhci_container_ctx *in_ctx;
811 /* If completion is null, no one is waiting on this command
812 * and the structure can be freed after the command completes.
814 struct completion *completion;
815 union xhci_trb *command_trb;
816 struct list_head cmd_list;
819 /* drop context bitmasks */
820 #define DROP_EP(x) (0x1 << x)
821 /* add context bitmasks */
822 #define ADD_EP(x) (0x1 << x)
824 struct xhci_stream_ctx {
825 /* 64-bit stream ring address, cycle state, and stream type */
827 /* offset 0x14 - 0x1f reserved for HC internal use */
831 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
832 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
833 /* Secondary stream array type, dequeue pointer is to a transfer ring */
835 /* Primary stream array type, dequeue pointer is to a transfer ring */
837 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
842 #define SCT_SSA_128 6
843 #define SCT_SSA_256 7
845 /* Assume no secondary streams for now */
846 struct xhci_stream_info {
847 struct xhci_ring **stream_rings;
848 /* Number of streams, including stream 0 (which drivers can't use) */
849 unsigned int num_streams;
850 /* The stream context array may be bigger than
851 * the number of streams the driver asked for
853 struct xhci_stream_ctx *stream_ctx_array;
854 unsigned int num_stream_ctxs;
855 dma_addr_t ctx_array_dma;
856 /* For mapping physical TRB addresses to segments in stream rings */
857 struct radix_tree_root trb_address_map;
858 struct xhci_command *free_streams_command;
861 #define SMALL_STREAM_ARRAY_SIZE 256
862 #define MEDIUM_STREAM_ARRAY_SIZE 1024
864 /* Some Intel xHCI host controllers need software to keep track of the bus
865 * bandwidth. Keep track of endpoint info here. Each root port is allocated
866 * the full bus bandwidth. We must also treat TTs (including each port under a
867 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
868 * (DMI) also limits the total bandwidth (across all domains) that can be used.
870 struct xhci_bw_info {
871 /* ep_interval is zero-based */
872 unsigned int ep_interval;
873 /* mult and num_packets are one-based */
875 unsigned int num_packets;
876 unsigned int max_packet_size;
877 unsigned int max_esit_payload;
881 /* "Block" sizes in bytes the hardware uses for different device speeds.
882 * The logic in this part of the hardware limits the number of bits the hardware
883 * can use, so must represent bandwidth in a less precise manner to mimic what
884 * the scheduler hardware computes.
891 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
892 * with each byte transferred. SuperSpeed devices have an initial overhead to
893 * set up bursts. These are in blocks, see above. LS overhead has already been
894 * translated into FS blocks.
896 #define DMI_OVERHEAD 8
897 #define DMI_OVERHEAD_BURST 4
898 #define SS_OVERHEAD 8
899 #define SS_OVERHEAD_BURST 32
900 #define HS_OVERHEAD 26
901 #define FS_OVERHEAD 20
902 #define LS_OVERHEAD 128
903 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
904 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
905 * of overhead associated with split transfers crossing microframe boundaries.
906 * 31 blocks is pure protocol overhead.
908 #define TT_HS_OVERHEAD (31 + 94)
909 #define TT_DMI_OVERHEAD (25 + 12)
911 /* Bandwidth limits in blocks */
912 #define FS_BW_LIMIT 1285
913 #define TT_BW_LIMIT 1320
914 #define HS_BW_LIMIT 1607
915 #define SS_BW_LIMIT_IN 3906
916 #define DMI_BW_LIMIT_IN 3906
917 #define SS_BW_LIMIT_OUT 3906
918 #define DMI_BW_LIMIT_OUT 3906
920 /* Percentage of bus bandwidth reserved for non-periodic transfers */
921 #define FS_BW_RESERVED 10
922 #define HS_BW_RESERVED 20
923 #define SS_BW_RESERVED 10
925 struct xhci_virt_ep {
926 struct xhci_ring *ring;
927 /* Related to endpoints that are configured to use stream IDs only */
928 struct xhci_stream_info *stream_info;
929 /* Temporary storage in case the configure endpoint command fails and we
930 * have to restore the device state to the previous state
932 struct xhci_ring *new_ring;
933 unsigned int ep_state;
934 #define SET_DEQ_PENDING (1 << 0)
935 #define EP_HALTED (1 << 1) /* For stall handling */
936 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
937 /* Transitioning the endpoint to using streams, don't enqueue URBs */
938 #define EP_GETTING_STREAMS (1 << 3)
939 #define EP_HAS_STREAMS (1 << 4)
940 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
941 #define EP_GETTING_NO_STREAMS (1 << 5)
942 /* ---- Related to URB cancellation ---- */
943 struct list_head cancelled_td_list;
944 /* Watchdog timer for stop endpoint command to cancel URBs */
945 struct timer_list stop_cmd_timer;
946 struct xhci_hcd *xhci;
947 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
948 * command. We'll need to update the ring's dequeue segment and dequeue
949 * pointer after the command completes.
951 struct xhci_segment *queued_deq_seg;
952 union xhci_trb *queued_deq_ptr;
954 * Sometimes the xHC can not process isochronous endpoint ring quickly
955 * enough, and it will miss some isoc tds on the ring and generate
956 * a Missed Service Error Event.
957 * Set skip flag when receive a Missed Service Error Event and
958 * process the missed tds on the endpoint ring.
961 /* Bandwidth checking storage */
962 struct xhci_bw_info bw_info;
963 struct list_head bw_endpoint_list;
964 /* Isoch Frame ID checking storage */
966 /* Use new Isoch TRB layout needed for extended TBC support */
967 bool use_extended_tbc;
970 enum xhci_overhead_type {
971 LS_OVERHEAD_TYPE = 0,
976 struct xhci_interval_bw {
977 unsigned int num_packets;
978 /* Sorted by max packet size.
979 * Head of the list is the greatest max packet size.
981 struct list_head endpoints;
982 /* How many endpoints of each speed are present. */
983 unsigned int overhead[3];
986 #define XHCI_MAX_INTERVAL 16
988 struct xhci_interval_bw_table {
989 unsigned int interval0_esit_payload;
990 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
991 /* Includes reserved bandwidth for async endpoints */
992 unsigned int bw_used;
993 unsigned int ss_bw_in;
994 unsigned int ss_bw_out;
997 #define EP_CTX_PER_DEV 31
999 struct xhci_virt_device {
1000 struct usb_device *udev;
1002 * Commands to the hardware are passed an "input context" that
1003 * tells the hardware what to change in its data structures.
1004 * The hardware will return changes in an "output context" that
1005 * software must allocate for the hardware. We need to keep
1006 * track of input and output contexts separately because
1007 * these commands might fail and we don't trust the hardware.
1009 struct xhci_container_ctx *out_ctx;
1010 /* Used for addressing devices and configuration changes */
1011 struct xhci_container_ctx *in_ctx;
1012 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
1015 struct xhci_interval_bw_table *bw_table;
1016 struct xhci_tt_bw_info *tt_info;
1017 /* The current max exit latency for the enabled USB3 link states. */
1022 * For each roothub, keep track of the bandwidth information for each periodic
1025 * If a high speed hub is attached to the roothub, each TT associated with that
1026 * hub is a separate bandwidth domain. The interval information for the
1027 * endpoints on the devices under that TT will appear in the TT structure.
1029 struct xhci_root_port_bw_info {
1030 struct list_head tts;
1031 unsigned int num_active_tts;
1032 struct xhci_interval_bw_table bw_table;
1035 struct xhci_tt_bw_info {
1036 struct list_head tt_list;
1039 struct xhci_interval_bw_table bw_table;
1045 * struct xhci_device_context_array
1046 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1048 struct xhci_device_context_array {
1049 /* 64-bit device addresses; we only write 32-bit addresses */
1050 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1051 /* private xHCD pointers */
1054 /* TODO: write function to set the 64-bit device DMA address */
1056 * TODO: change this to be dynamically sized at HC mem init time since the HC
1057 * might not be able to handle the maximum number of devices possible.
1061 struct xhci_transfer_event {
1062 /* 64-bit buffer address, or immediate data */
1064 __le32 transfer_len;
1065 /* This field is interpreted differently based on the type of TRB */
1069 /* Transfer event TRB length bit mask */
1071 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1073 /** Transfer Event bit fields **/
1074 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1076 /* Completion Code - only applicable for some types of TRBs */
1077 #define COMP_CODE_MASK (0xff << 24)
1078 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1079 #define COMP_INVALID 0
1080 #define COMP_SUCCESS 1
1081 #define COMP_DATA_BUFFER_ERROR 2
1082 #define COMP_BABBLE_DETECTED_ERROR 3
1083 #define COMP_USB_TRANSACTION_ERROR 4
1084 #define COMP_TRB_ERROR 5
1085 #define COMP_STALL_ERROR 6
1086 #define COMP_RESOURCE_ERROR 7
1087 #define COMP_BANDWIDTH_ERROR 8
1088 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1089 #define COMP_INVALID_STREAM_TYPE_ERROR 10
1090 #define COMP_SLOT_NOT_ENABLED_ERROR 11
1091 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1092 #define COMP_SHORT_PACKET 13
1093 #define COMP_RING_UNDERRUN 14
1094 #define COMP_RING_OVERRUN 15
1095 #define COMP_VF_EVENT_RING_FULL_ERROR 16
1096 #define COMP_PARAMETER_ERROR 17
1097 #define COMP_BANDWIDTH_OVERRUN_ERROR 18
1098 #define COMP_CONTEXT_STATE_ERROR 19
1099 #define COMP_NO_PING_RESPONSE_ERROR 20
1100 #define COMP_EVENT_RING_FULL_ERROR 21
1101 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1102 #define COMP_MISSED_SERVICE_ERROR 23
1103 #define COMP_COMMAND_RING_STOPPED 24
1104 #define COMP_COMMAND_ABORTED 25
1105 #define COMP_STOPPED 26
1106 #define COMP_STOPPED_LENGTH_INVALID 27
1107 #define COMP_STOPPED_SHORT_PACKET 28
1108 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1109 #define COMP_ISOCH_BUFFER_OVERRUN 31
1110 #define COMP_EVENT_LOST_ERROR 32
1111 #define COMP_UNDEFINED_ERROR 33
1112 #define COMP_INVALID_STREAM_ID_ERROR 34
1113 #define COMP_SECONDARY_BANDWIDTH_ERROR 35
1114 #define COMP_SPLIT_TRANSACTION_ERROR 36
1116 static inline const char *xhci_trb_comp_code_string(u8 status)
1123 case COMP_DATA_BUFFER_ERROR:
1124 return "Data Buffer Error";
1125 case COMP_BABBLE_DETECTED_ERROR:
1126 return "Babble Detected";
1127 case COMP_USB_TRANSACTION_ERROR:
1128 return "USB Transaction Error";
1129 case COMP_TRB_ERROR:
1131 case COMP_STALL_ERROR:
1132 return "Stall Error";
1133 case COMP_RESOURCE_ERROR:
1134 return "Resource Error";
1135 case COMP_BANDWIDTH_ERROR:
1136 return "Bandwidth Error";
1137 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1138 return "No Slots Available Error";
1139 case COMP_INVALID_STREAM_TYPE_ERROR:
1140 return "Invalid Stream Type Error";
1141 case COMP_SLOT_NOT_ENABLED_ERROR:
1142 return "Slot Not Enabled Error";
1143 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1144 return "Endpoint Not Enabled Error";
1145 case COMP_SHORT_PACKET:
1146 return "Short Packet";
1147 case COMP_RING_UNDERRUN:
1148 return "Ring Underrun";
1149 case COMP_RING_OVERRUN:
1150 return "Ring Overrun";
1151 case COMP_VF_EVENT_RING_FULL_ERROR:
1152 return "VF Event Ring Full Error";
1153 case COMP_PARAMETER_ERROR:
1154 return "Parameter Error";
1155 case COMP_BANDWIDTH_OVERRUN_ERROR:
1156 return "Bandwidth Overrun Error";
1157 case COMP_CONTEXT_STATE_ERROR:
1158 return "Context State Error";
1159 case COMP_NO_PING_RESPONSE_ERROR:
1160 return "No Ping Response Error";
1161 case COMP_EVENT_RING_FULL_ERROR:
1162 return "Event Ring Full Error";
1163 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1164 return "Incompatible Device Error";
1165 case COMP_MISSED_SERVICE_ERROR:
1166 return "Missed Service Error";
1167 case COMP_COMMAND_RING_STOPPED:
1168 return "Command Ring Stopped";
1169 case COMP_COMMAND_ABORTED:
1170 return "Command Aborted";
1173 case COMP_STOPPED_LENGTH_INVALID:
1174 return "Stopped - Length Invalid";
1175 case COMP_STOPPED_SHORT_PACKET:
1176 return "Stopped - Short Packet";
1177 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1178 return "Max Exit Latency Too Large Error";
1179 case COMP_ISOCH_BUFFER_OVERRUN:
1180 return "Isoch Buffer Overrun";
1181 case COMP_EVENT_LOST_ERROR:
1182 return "Event Lost Error";
1183 case COMP_UNDEFINED_ERROR:
1184 return "Undefined Error";
1185 case COMP_INVALID_STREAM_ID_ERROR:
1186 return "Invalid Stream ID Error";
1187 case COMP_SECONDARY_BANDWIDTH_ERROR:
1188 return "Secondary Bandwidth Error";
1189 case COMP_SPLIT_TRANSACTION_ERROR:
1190 return "Split Transaction Error";
1196 struct xhci_link_trb {
1197 /* 64-bit segment pointer*/
1203 /* control bitfields */
1204 #define LINK_TOGGLE (0x1<<1)
1206 /* Command completion event TRB */
1207 struct xhci_event_cmd {
1208 /* Pointer to command TRB, or the value passed by the event data trb */
1214 /* flags bitmasks */
1216 /* Address device - disable SetAddress */
1217 #define TRB_BSR (1<<9)
1219 /* Configure Endpoint - Deconfigure */
1220 #define TRB_DC (1<<9)
1222 /* Stop Ring - Transfer State Preserve */
1223 #define TRB_TSP (1<<9)
1225 enum xhci_ep_reset_type {
1231 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1232 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1234 /* Set Latency Tolerance Value */
1235 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1237 /* Get Port Bandwidth */
1238 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1241 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1242 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1244 enum xhci_setup_dev {
1246 SETUP_CONTEXT_ADDRESS,
1249 /* bits 16:23 are the virtual function ID */
1250 /* bits 24:31 are the slot ID */
1251 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1252 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1254 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1255 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1256 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1258 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1259 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1260 #define LAST_EP_INDEX 30
1262 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1263 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1264 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1265 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1267 /* Link TRB specific fields */
1268 #define TRB_TC (1<<1)
1270 /* Port Status Change Event TRB fields */
1271 /* Port ID - bits 31:24 */
1272 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1274 #define EVENT_DATA (1 << 2)
1276 /* Normal TRB fields */
1277 /* transfer_len bitmasks - bits 0:16 */
1278 #define TRB_LEN(p) ((p) & 0x1ffff)
1279 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1280 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1281 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1282 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1283 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1284 /* Interrupter Target - which MSI-X vector to target the completion event at */
1285 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1286 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1287 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1288 #define TRB_TBC(p) (((p) & 0x3) << 7)
1289 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1291 /* Cycle bit - indicates TRB ownership by HC or HCD */
1292 #define TRB_CYCLE (1<<0)
1294 * Force next event data TRB to be evaluated before task switch.
1295 * Used to pass OS data back after a TD completes.
1297 #define TRB_ENT (1<<1)
1298 /* Interrupt on short packet */
1299 #define TRB_ISP (1<<2)
1300 /* Set PCIe no snoop attribute */
1301 #define TRB_NO_SNOOP (1<<3)
1302 /* Chain multiple TRBs into a TD */
1303 #define TRB_CHAIN (1<<4)
1304 /* Interrupt on completion */
1305 #define TRB_IOC (1<<5)
1306 /* The buffer pointer contains immediate data */
1307 #define TRB_IDT (1<<6)
1309 /* Block Event Interrupt */
1310 #define TRB_BEI (1<<9)
1312 /* Control transfer TRB specific fields */
1313 #define TRB_DIR_IN (1<<16)
1314 #define TRB_TX_TYPE(p) ((p) << 16)
1315 #define TRB_DATA_OUT 2
1316 #define TRB_DATA_IN 3
1318 /* Isochronous TRB specific fields */
1319 #define TRB_SIA (1<<31)
1320 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1322 struct xhci_generic_trb {
1327 struct xhci_link_trb link;
1328 struct xhci_transfer_event trans_event;
1329 struct xhci_event_cmd event_cmd;
1330 struct xhci_generic_trb generic;
1334 #define TRB_TYPE_BITMASK (0xfc00)
1335 #define TRB_TYPE(p) ((p) << 10)
1336 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1338 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1339 #define TRB_NORMAL 1
1340 /* setup stage for control transfers */
1342 /* data stage for control transfers */
1344 /* status stage for control transfers */
1345 #define TRB_STATUS 4
1346 /* isoc transfers */
1348 /* TRB for linking ring segments */
1350 #define TRB_EVENT_DATA 7
1351 /* Transfer Ring No-op (not for the command ring) */
1352 #define TRB_TR_NOOP 8
1354 /* Enable Slot Command */
1355 #define TRB_ENABLE_SLOT 9
1356 /* Disable Slot Command */
1357 #define TRB_DISABLE_SLOT 10
1358 /* Address Device Command */
1359 #define TRB_ADDR_DEV 11
1360 /* Configure Endpoint Command */
1361 #define TRB_CONFIG_EP 12
1362 /* Evaluate Context Command */
1363 #define TRB_EVAL_CONTEXT 13
1364 /* Reset Endpoint Command */
1365 #define TRB_RESET_EP 14
1366 /* Stop Transfer Ring Command */
1367 #define TRB_STOP_RING 15
1368 /* Set Transfer Ring Dequeue Pointer Command */
1369 #define TRB_SET_DEQ 16
1370 /* Reset Device Command */
1371 #define TRB_RESET_DEV 17
1372 /* Force Event Command (opt) */
1373 #define TRB_FORCE_EVENT 18
1374 /* Negotiate Bandwidth Command (opt) */
1375 #define TRB_NEG_BANDWIDTH 19
1376 /* Set Latency Tolerance Value Command (opt) */
1377 #define TRB_SET_LT 20
1378 /* Get port bandwidth Command */
1379 #define TRB_GET_BW 21
1380 /* Force Header Command - generate a transaction or link management packet */
1381 #define TRB_FORCE_HEADER 22
1382 /* No-op Command - not for transfer rings */
1383 #define TRB_CMD_NOOP 23
1384 /* TRB IDs 24-31 reserved */
1386 /* Transfer Event */
1387 #define TRB_TRANSFER 32
1388 /* Command Completion Event */
1389 #define TRB_COMPLETION 33
1390 /* Port Status Change Event */
1391 #define TRB_PORT_STATUS 34
1392 /* Bandwidth Request Event (opt) */
1393 #define TRB_BANDWIDTH_EVENT 35
1394 /* Doorbell Event (opt) */
1395 #define TRB_DOORBELL 36
1396 /* Host Controller Event */
1397 #define TRB_HC_EVENT 37
1398 /* Device Notification Event - device sent function wake notification */
1399 #define TRB_DEV_NOTE 38
1400 /* MFINDEX Wrap Event - microframe counter wrapped */
1401 #define TRB_MFINDEX_WRAP 39
1402 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1404 /* Nec vendor-specific command completion event. */
1405 #define TRB_NEC_CMD_COMP 48
1406 /* Get NEC firmware revision. */
1407 #define TRB_NEC_GET_FW 49
1409 static inline const char *xhci_trb_type_string(u8 type)
1415 return "Setup Stage";
1417 return "Data Stage";
1419 return "Status Stage";
1424 case TRB_EVENT_DATA:
1425 return "Event Data";
1428 case TRB_ENABLE_SLOT:
1429 return "Enable Slot Command";
1430 case TRB_DISABLE_SLOT:
1431 return "Disable Slot Command";
1433 return "Address Device Command";
1435 return "Configure Endpoint Command";
1436 case TRB_EVAL_CONTEXT:
1437 return "Evaluate Context Command";
1439 return "Reset Endpoint Command";
1441 return "Stop Ring Command";
1443 return "Set TR Dequeue Pointer Command";
1445 return "Reset Device Command";
1446 case TRB_FORCE_EVENT:
1447 return "Force Event Command";
1448 case TRB_NEG_BANDWIDTH:
1449 return "Negotiate Bandwidth Command";
1451 return "Set Latency Tolerance Value Command";
1453 return "Get Port Bandwidth Command";
1454 case TRB_FORCE_HEADER:
1455 return "Force Header Command";
1457 return "No-Op Command";
1459 return "Transfer Event";
1460 case TRB_COMPLETION:
1461 return "Command Completion Event";
1462 case TRB_PORT_STATUS:
1463 return "Port Status Change Event";
1464 case TRB_BANDWIDTH_EVENT:
1465 return "Bandwidth Request Event";
1467 return "Doorbell Event";
1469 return "Host Controller Event";
1471 return "Device Notification Event";
1472 case TRB_MFINDEX_WRAP:
1473 return "MFINDEX Wrap Event";
1474 case TRB_NEC_CMD_COMP:
1475 return "NEC Command Completion Event";
1476 case TRB_NEC_GET_FW:
1477 return "NET Get Firmware Revision Command";
1483 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1484 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1485 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1486 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1487 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1488 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1490 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1491 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1494 * TRBS_PER_SEGMENT must be a multiple of 4,
1495 * since the command ring is 64-byte aligned.
1496 * It must also be greater than 16.
1498 #define TRBS_PER_SEGMENT 256
1499 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1500 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1501 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1502 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1503 /* TRB buffer pointers can't cross 64KB boundaries */
1504 #define TRB_MAX_BUFF_SHIFT 16
1505 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1506 /* How much data is left before the 64KB boundary? */
1507 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1508 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1510 struct xhci_segment {
1511 union xhci_trb *trbs;
1512 /* private to HCD */
1513 struct xhci_segment *next;
1515 /* Max packet sized bounce buffer for td-fragmant alignment */
1516 dma_addr_t bounce_dma;
1518 unsigned int bounce_offs;
1519 unsigned int bounce_len;
1523 struct list_head td_list;
1524 struct list_head cancelled_td_list;
1526 struct xhci_segment *start_seg;
1527 union xhci_trb *first_trb;
1528 union xhci_trb *last_trb;
1529 struct xhci_segment *bounce_seg;
1530 /* actual_length of the URB has already been set */
1531 bool urb_length_set;
1534 /* xHCI command default timeout value */
1535 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1537 /* command descriptor */
1539 struct xhci_command *command;
1540 union xhci_trb *cmd_trb;
1543 struct xhci_dequeue_state {
1544 struct xhci_segment *new_deq_seg;
1545 union xhci_trb *new_deq_ptr;
1546 int new_cycle_state;
1547 unsigned int stream_id;
1550 enum xhci_ring_type {
1560 static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1583 struct xhci_segment *first_seg;
1584 struct xhci_segment *last_seg;
1585 union xhci_trb *enqueue;
1586 struct xhci_segment *enq_seg;
1587 union xhci_trb *dequeue;
1588 struct xhci_segment *deq_seg;
1589 struct list_head td_list;
1591 * Write the cycle state into the TRB cycle field to give ownership of
1592 * the TRB to the host controller (if we are the producer), or to check
1593 * if we own the TRB (if we are the consumer). See section 4.9.1.
1596 unsigned int stream_id;
1597 unsigned int num_segs;
1598 unsigned int num_trbs_free;
1599 unsigned int num_trbs_free_temp;
1600 unsigned int bounce_buf_len;
1601 enum xhci_ring_type type;
1602 bool last_td_was_short;
1603 struct radix_tree_root *trb_address_map;
1606 struct xhci_erst_entry {
1607 /* 64-bit event ring segment address */
1615 struct xhci_erst_entry *entries;
1616 unsigned int num_entries;
1617 /* xhci->event_ring keeps track of segment dma addresses */
1618 dma_addr_t erst_dma_addr;
1619 /* Num entries the ERST can contain */
1620 unsigned int erst_size;
1623 struct xhci_scratchpad {
1632 struct xhci_td td[0];
1636 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1637 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1638 * meaning 64 ring segments.
1639 * Initial allocated size of the ERST, in number of entries */
1640 #define ERST_NUM_SEGS 1
1641 /* Initial allocated size of the ERST, in number of entries */
1642 #define ERST_SIZE 64
1643 /* Initial number of event segment rings allocated */
1644 #define ERST_ENTRIES 1
1645 /* Poll every 60 seconds */
1646 #define POLL_TIMEOUT 60
1647 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1648 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1649 /* XXX: Make these module parameters */
1666 struct list_head list;
1669 struct xhci_bus_state {
1670 unsigned long bus_suspended;
1671 unsigned long next_statechange;
1673 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1674 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1676 u32 suspended_ports;
1677 u32 port_remote_wakeup;
1678 unsigned long resume_done[USB_MAXCHILDREN];
1679 /* which ports have started to resume */
1680 unsigned long resuming_ports;
1681 /* Which ports are waiting on RExit to U0 transition. */
1682 unsigned long rexit_ports;
1683 struct completion rexit_done[USB_MAXCHILDREN];
1688 * It can take up to 20 ms to transition from RExit to U0 on the
1689 * Intel Lynx Point LP xHCI host.
1691 #define XHCI_MAX_REXIT_TIMEOUT_MS 20
1693 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1695 if (hcd->speed >= HCD_USB3)
1704 u32 *psi; /* array of protocol speed ID entries */
1709 /* There is one xhci_hcd structure per controller */
1711 struct usb_hcd *main_hcd;
1712 struct usb_hcd *shared_hcd;
1713 /* glue to PCI and HCD framework */
1714 struct xhci_cap_regs __iomem *cap_regs;
1715 struct xhci_op_regs __iomem *op_regs;
1716 struct xhci_run_regs __iomem *run_regs;
1717 struct xhci_doorbell_array __iomem *dba;
1718 /* Our HCD's current interrupter register set */
1719 struct xhci_intr_reg __iomem *ir_set;
1721 /* Cached register copies of read-only HC data */
1730 /* packed release number */
1734 u8 max_interrupters;
1738 /* 4KB min, 128MB max */
1740 /* Valid values are 12 to 20, inclusive */
1744 /* optional clock */
1746 /* data structures */
1747 struct xhci_device_context_array *dcbaa;
1748 struct xhci_ring *cmd_ring;
1749 unsigned int cmd_ring_state;
1750 #define CMD_RING_STATE_RUNNING (1 << 0)
1751 #define CMD_RING_STATE_ABORTED (1 << 1)
1752 #define CMD_RING_STATE_STOPPED (1 << 2)
1753 struct list_head cmd_list;
1754 unsigned int cmd_ring_reserved_trbs;
1755 struct delayed_work cmd_timer;
1756 struct completion cmd_ring_stop_completion;
1757 struct xhci_command *current_cmd;
1758 struct xhci_ring *event_ring;
1759 struct xhci_erst erst;
1761 struct xhci_scratchpad *scratchpad;
1762 /* Store LPM test failed devices' information */
1763 struct list_head lpm_failed_devs;
1765 /* slot enabling and address device helpers */
1766 /* these are not thread safe so use mutex */
1768 /* For USB 3.0 LPM enable/disable. */
1769 struct xhci_command *lpm_command;
1770 /* Internal mirror of the HW's dcbaa */
1771 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1772 /* For keeping track of bandwidth domains per roothub. */
1773 struct xhci_root_port_bw_info *rh_bw;
1776 struct dma_pool *device_pool;
1777 struct dma_pool *segment_pool;
1778 struct dma_pool *small_streams_pool;
1779 struct dma_pool *medium_streams_pool;
1781 /* Host controller watchdog timer structures */
1782 unsigned int xhc_state;
1786 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1788 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1789 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1790 * that sees this status (other than the timer that set it) should stop touching
1791 * hardware immediately. Interrupt handlers should return immediately when
1792 * they see this status (any time they drop and re-acquire xhci->lock).
1793 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1794 * putting the TD on the canceled list, etc.
1796 * There are no reports of xHCI host controllers that display this issue.
1798 #define XHCI_STATE_DYING (1 << 0)
1799 #define XHCI_STATE_HALTED (1 << 1)
1800 #define XHCI_STATE_REMOVING (1 << 2)
1801 unsigned long long quirks;
1802 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1803 #define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1804 #define XHCI_NEC_HOST BIT_ULL(2)
1805 #define XHCI_AMD_PLL_FIX BIT_ULL(3)
1806 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1808 * Certain Intel host controllers have a limit to the number of endpoint
1809 * contexts they can handle. Ideally, they would signal that they can't handle
1810 * anymore endpoint contexts by returning a Resource Error for the Configure
1811 * Endpoint command, but they don't. Instead they expect software to keep track
1812 * of the number of active endpoints for them, across configure endpoint
1813 * commands, reset device commands, disable slot commands, and address device
1816 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1817 #define XHCI_BROKEN_MSI BIT_ULL(6)
1818 #define XHCI_RESET_ON_RESUME BIT_ULL(7)
1819 #define XHCI_SW_BW_CHECKING BIT_ULL(8)
1820 #define XHCI_AMD_0x96_HOST BIT_ULL(9)
1821 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1822 #define XHCI_LPM_SUPPORT BIT_ULL(11)
1823 #define XHCI_INTEL_HOST BIT_ULL(12)
1824 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1825 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1826 #define XHCI_AVOID_BEI BIT_ULL(15)
1827 #define XHCI_PLAT BIT_ULL(16)
1828 #define XHCI_SLOW_SUSPEND BIT_ULL(17)
1829 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1830 /* For controllers with a broken beyond repair streams implementation */
1831 #define XHCI_BROKEN_STREAMS BIT_ULL(19)
1832 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1833 #define XHCI_MTK_HOST BIT_ULL(21)
1834 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1835 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1836 #define XHCI_MISSING_CAS BIT_ULL(24)
1837 /* For controller with a broken Port Disable implementation */
1838 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1839 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1840 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1841 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1842 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1843 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
1844 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1845 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1846 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1848 unsigned int num_active_eps;
1849 unsigned int limit_active_eps;
1850 /* There are two roothubs to keep track of bus suspend info for */
1851 struct xhci_bus_state bus_state[2];
1852 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1854 /* Array of pointers to USB 3.0 PORTSC registers */
1855 __le32 __iomem **usb3_ports;
1856 unsigned int num_usb3_ports;
1857 /* Array of pointers to USB 2.0 PORTSC registers */
1858 __le32 __iomem **usb2_ports;
1859 struct xhci_hub usb2_rhub;
1860 struct xhci_hub usb3_rhub;
1861 unsigned int num_usb2_ports;
1862 /* support xHCI 0.96 spec USB2 software LPM */
1863 unsigned sw_lpm_support:1;
1864 /* support xHCI 1.0 spec USB2 hardware LPM */
1865 unsigned hw_lpm_support:1;
1866 /* Broken Suspend flag for SNPS Suspend resume issue */
1867 unsigned broken_suspend:1;
1868 /* cached usb2 extened protocol capabilites */
1870 unsigned int num_ext_caps;
1871 /* Compliance Mode Recovery Data */
1872 struct timer_list comp_mode_recovery_timer;
1875 /* Compliance Mode Timer Triggered every 2 seconds */
1876 #define COMP_MODE_RCVRY_MSECS 2000
1878 /* platform-specific data -- must come last */
1879 unsigned long priv[0] __aligned(sizeof(s64));
1882 /* Platform specific overrides to generic XHCI hc_driver ops */
1883 struct xhci_driver_overrides {
1884 size_t extra_priv_size;
1885 int (*reset)(struct usb_hcd *hcd);
1886 int (*start)(struct usb_hcd *hcd);
1889 #define XHCI_CFC_DELAY 10
1891 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1892 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1894 struct usb_hcd *primary_hcd;
1896 if (usb_hcd_is_primary_hcd(hcd))
1899 primary_hcd = hcd->primary_hcd;
1901 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1904 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1906 return xhci->main_hcd;
1909 #define xhci_dbg(xhci, fmt, args...) \
1910 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1911 #define xhci_err(xhci, fmt, args...) \
1912 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1913 #define xhci_warn(xhci, fmt, args...) \
1914 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1915 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1916 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1917 #define xhci_info(xhci, fmt, args...) \
1918 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1921 * Registers should always be accessed with double word or quad word accesses.
1923 * Some xHCI implementations may support 64-bit address pointers. Registers
1924 * with 64-bit address pointers should be written to with dword accesses by
1925 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1926 * xHCI implementations that do not support 64-bit address pointers will ignore
1927 * the high dword, and write order is irrelevant.
1929 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1930 __le64 __iomem *regs)
1932 return lo_hi_readq(regs);
1934 static inline void xhci_write_64(struct xhci_hcd *xhci,
1935 const u64 val, __le64 __iomem *regs)
1937 lo_hi_writeq(val, regs);
1940 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1942 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1945 /* xHCI debugging */
1946 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1947 void xhci_print_registers(struct xhci_hcd *xhci);
1948 void xhci_dbg_regs(struct xhci_hcd *xhci);
1949 void xhci_print_run_regs(struct xhci_hcd *xhci);
1950 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1951 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1952 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1953 struct xhci_container_ctx *ctx);
1954 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1955 const char *fmt, ...);
1957 /* xHCI memory management */
1958 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1959 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1960 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1961 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1962 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1963 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1964 struct usb_device *udev);
1965 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1966 unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1967 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1968 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1969 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1970 struct xhci_virt_device *virt_dev,
1971 int old_active_eps);
1972 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1973 void xhci_update_bw_info(struct xhci_hcd *xhci,
1974 struct xhci_container_ctx *in_ctx,
1975 struct xhci_input_control_ctx *ctrl_ctx,
1976 struct xhci_virt_device *virt_dev);
1977 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1978 struct xhci_container_ctx *in_ctx,
1979 struct xhci_container_ctx *out_ctx,
1980 unsigned int ep_index);
1981 void xhci_slot_copy(struct xhci_hcd *xhci,
1982 struct xhci_container_ctx *in_ctx,
1983 struct xhci_container_ctx *out_ctx);
1984 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1985 struct usb_device *udev, struct usb_host_endpoint *ep,
1987 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1988 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1989 unsigned int num_trbs, gfp_t flags);
1990 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
1991 struct xhci_virt_device *virt_dev,
1992 unsigned int ep_index);
1993 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1994 unsigned int num_stream_ctxs,
1995 unsigned int num_streams,
1996 unsigned int max_packet, gfp_t flags);
1997 void xhci_free_stream_info(struct xhci_hcd *xhci,
1998 struct xhci_stream_info *stream_info);
1999 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2000 struct xhci_ep_ctx *ep_ctx,
2001 struct xhci_stream_info *stream_info);
2002 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2003 struct xhci_virt_ep *ep);
2004 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2005 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2006 struct xhci_ring *xhci_dma_to_transfer_ring(
2007 struct xhci_virt_ep *ep,
2009 struct xhci_ring *xhci_stream_id_to_ring(
2010 struct xhci_virt_device *dev,
2011 unsigned int ep_index,
2012 unsigned int stream_id);
2013 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2014 bool allocate_in_ctx, bool allocate_completion,
2016 void xhci_urb_free_priv(struct urb_priv *urb_priv);
2017 void xhci_free_command(struct xhci_hcd *xhci,
2018 struct xhci_command *command);
2020 /* xHCI host controller glue */
2021 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2022 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
2023 void xhci_quiesce(struct xhci_hcd *xhci);
2024 int xhci_halt(struct xhci_hcd *xhci);
2025 int xhci_start(struct xhci_hcd *xhci);
2026 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
2027 int xhci_run(struct usb_hcd *hcd);
2028 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2029 void xhci_shutdown(struct usb_hcd *hcd);
2030 void xhci_init_driver(struct hc_driver *drv,
2031 const struct xhci_driver_overrides *over);
2032 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2034 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2035 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
2037 irqreturn_t xhci_irq(struct usb_hcd *hcd);
2038 irqreturn_t xhci_msi_irq(int irq, void *hcd);
2039 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2040 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2041 struct xhci_virt_device *virt_dev,
2042 struct usb_device *hdev,
2043 struct usb_tt *tt, gfp_t mem_flags);
2045 /* xHCI ring, segment, TRB, and TD functions */
2046 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2047 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2048 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2049 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2050 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2051 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2052 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2053 u32 trb_type, u32 slot_id);
2054 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2055 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2056 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2057 u32 field1, u32 field2, u32 field3, u32 field4);
2058 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2059 int slot_id, unsigned int ep_index, int suspend);
2060 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2061 int slot_id, unsigned int ep_index);
2062 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2063 int slot_id, unsigned int ep_index);
2064 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2065 int slot_id, unsigned int ep_index);
2066 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2067 struct urb *urb, int slot_id, unsigned int ep_index);
2068 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2069 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2070 bool command_must_succeed);
2071 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2072 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2073 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2074 int slot_id, unsigned int ep_index,
2075 enum xhci_ep_reset_type reset_type);
2076 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2078 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
2079 unsigned int slot_id, unsigned int ep_index,
2080 unsigned int stream_id, struct xhci_td *cur_td,
2081 struct xhci_dequeue_state *state);
2082 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
2083 unsigned int slot_id, unsigned int ep_index,
2084 struct xhci_dequeue_state *deq_state);
2085 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
2086 unsigned int stream_id, struct xhci_td *td);
2087 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
2088 void xhci_handle_command_timeout(struct work_struct *work);
2090 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2091 unsigned int ep_index, unsigned int stream_id);
2092 void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2094 /* xHCI roothub code */
2095 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
2096 int port_id, u32 link_state);
2097 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
2098 int port_id, u32 port_bit);
2099 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2100 char *buf, u16 wLength);
2101 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2102 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2103 void xhci_hc_died(struct xhci_hcd *xhci);
2106 int xhci_bus_suspend(struct usb_hcd *hcd);
2107 int xhci_bus_resume(struct usb_hcd *hcd);
2109 #define xhci_bus_suspend NULL
2110 #define xhci_bus_resume NULL
2111 #endif /* CONFIG_PM */
2113 u32 xhci_port_state_to_neutral(u32 state);
2114 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2116 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2119 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2120 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2121 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2123 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2124 unsigned int slot_id, unsigned int ep_index,
2125 unsigned int stream_id);
2126 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2129 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2130 xhci_get_endpoint_index(&urb->ep->desc),
2134 static inline char *xhci_slot_state_string(u32 state)
2137 case SLOT_STATE_ENABLED:
2138 return "enabled/disabled";
2139 case SLOT_STATE_DEFAULT:
2141 case SLOT_STATE_ADDRESSED:
2143 case SLOT_STATE_CONFIGURED:
2144 return "configured";
2150 static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2,
2153 static char str[256];
2154 int type = TRB_FIELD_TO_TYPE(field3);
2159 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2160 field1, field0, GET_INTR_TARGET(field2),
2161 xhci_trb_type_string(type),
2162 field3 & TRB_IOC ? 'I' : 'i',
2163 field3 & TRB_CHAIN ? 'C' : 'c',
2164 field3 & TRB_TC ? 'T' : 't',
2165 field3 & TRB_CYCLE ? 'C' : 'c');
2168 case TRB_COMPLETION:
2169 case TRB_PORT_STATUS:
2170 case TRB_BANDWIDTH_EVENT:
2174 case TRB_MFINDEX_WRAP:
2176 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2178 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2179 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2180 /* Macro decrements 1, maybe it shouldn't?!? */
2181 TRB_TO_EP_INDEX(field3) + 1,
2182 xhci_trb_type_string(type),
2183 field3 & EVENT_DATA ? 'E' : 'e',
2184 field3 & TRB_CYCLE ? 'C' : 'c');
2188 sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2190 (field0 & 0xff00) >> 8,
2191 (field0 & 0xff000000) >> 24,
2192 (field0 & 0xff0000) >> 16,
2193 (field1 & 0xff00) >> 8,
2195 (field1 & 0xff000000) >> 16 |
2196 (field1 & 0xff0000) >> 16,
2197 TRB_LEN(field2), GET_TD_SIZE(field2),
2198 GET_INTR_TARGET(field2),
2199 xhci_trb_type_string(type),
2200 field3 & TRB_IDT ? 'I' : 'i',
2201 field3 & TRB_IOC ? 'I' : 'i',
2202 field3 & TRB_CYCLE ? 'C' : 'c');
2205 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2206 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2207 GET_INTR_TARGET(field2),
2208 xhci_trb_type_string(type),
2209 field3 & TRB_IDT ? 'I' : 'i',
2210 field3 & TRB_IOC ? 'I' : 'i',
2211 field3 & TRB_CHAIN ? 'C' : 'c',
2212 field3 & TRB_NO_SNOOP ? 'S' : 's',
2213 field3 & TRB_ISP ? 'I' : 'i',
2214 field3 & TRB_ENT ? 'E' : 'e',
2215 field3 & TRB_CYCLE ? 'C' : 'c');
2218 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2219 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2220 GET_INTR_TARGET(field2),
2221 xhci_trb_type_string(type),
2222 field3 & TRB_IOC ? 'I' : 'i',
2223 field3 & TRB_CHAIN ? 'C' : 'c',
2224 field3 & TRB_ENT ? 'E' : 'e',
2225 field3 & TRB_CYCLE ? 'C' : 'c');
2229 case TRB_EVENT_DATA:
2232 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2233 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2234 GET_INTR_TARGET(field2),
2235 xhci_trb_type_string(type),
2236 field3 & TRB_BEI ? 'B' : 'b',
2237 field3 & TRB_IDT ? 'I' : 'i',
2238 field3 & TRB_IOC ? 'I' : 'i',
2239 field3 & TRB_CHAIN ? 'C' : 'c',
2240 field3 & TRB_NO_SNOOP ? 'S' : 's',
2241 field3 & TRB_ISP ? 'I' : 'i',
2242 field3 & TRB_ENT ? 'E' : 'e',
2243 field3 & TRB_CYCLE ? 'C' : 'c');
2247 case TRB_ENABLE_SLOT:
2250 xhci_trb_type_string(type),
2251 field3 & TRB_CYCLE ? 'C' : 'c');
2253 case TRB_DISABLE_SLOT:
2254 case TRB_NEG_BANDWIDTH:
2256 "%s: slot %d flags %c",
2257 xhci_trb_type_string(type),
2258 TRB_TO_SLOT_ID(field3),
2259 field3 & TRB_CYCLE ? 'C' : 'c');
2263 "%s: ctx %08x%08x slot %d flags %c:%c",
2264 xhci_trb_type_string(type),
2266 TRB_TO_SLOT_ID(field3),
2267 field3 & TRB_BSR ? 'B' : 'b',
2268 field3 & TRB_CYCLE ? 'C' : 'c');
2272 "%s: ctx %08x%08x slot %d flags %c:%c",
2273 xhci_trb_type_string(type),
2275 TRB_TO_SLOT_ID(field3),
2276 field3 & TRB_DC ? 'D' : 'd',
2277 field3 & TRB_CYCLE ? 'C' : 'c');
2279 case TRB_EVAL_CONTEXT:
2281 "%s: ctx %08x%08x slot %d flags %c",
2282 xhci_trb_type_string(type),
2284 TRB_TO_SLOT_ID(field3),
2285 field3 & TRB_CYCLE ? 'C' : 'c');
2289 "%s: ctx %08x%08x slot %d ep %d flags %c",
2290 xhci_trb_type_string(type),
2292 TRB_TO_SLOT_ID(field3),
2293 /* Macro decrements 1, maybe it shouldn't?!? */
2294 TRB_TO_EP_INDEX(field3) + 1,
2295 field3 & TRB_CYCLE ? 'C' : 'c');
2299 "%s: slot %d sp %d ep %d flags %c",
2300 xhci_trb_type_string(type),
2301 TRB_TO_SLOT_ID(field3),
2302 TRB_TO_SUSPEND_PORT(field3),
2303 /* Macro decrements 1, maybe it shouldn't?!? */
2304 TRB_TO_EP_INDEX(field3) + 1,
2305 field3 & TRB_CYCLE ? 'C' : 'c');
2309 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2310 xhci_trb_type_string(type),
2312 TRB_TO_STREAM_ID(field2),
2313 TRB_TO_SLOT_ID(field3),
2314 /* Macro decrements 1, maybe it shouldn't?!? */
2315 TRB_TO_EP_INDEX(field3) + 1,
2316 field3 & TRB_CYCLE ? 'C' : 'c');
2320 "%s: slot %d flags %c",
2321 xhci_trb_type_string(type),
2322 TRB_TO_SLOT_ID(field3),
2323 field3 & TRB_CYCLE ? 'C' : 'c');
2325 case TRB_FORCE_EVENT:
2327 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2328 xhci_trb_type_string(type),
2330 TRB_TO_VF_INTR_TARGET(field2),
2331 TRB_TO_VF_ID(field3),
2332 field3 & TRB_CYCLE ? 'C' : 'c');
2336 "%s: belt %d flags %c",
2337 xhci_trb_type_string(type),
2338 TRB_TO_BELT(field3),
2339 field3 & TRB_CYCLE ? 'C' : 'c');
2343 "%s: ctx %08x%08x slot %d speed %d flags %c",
2344 xhci_trb_type_string(type),
2346 TRB_TO_SLOT_ID(field3),
2347 TRB_TO_DEV_SPEED(field3),
2348 field3 & TRB_CYCLE ? 'C' : 'c');
2350 case TRB_FORCE_HEADER:
2352 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2353 xhci_trb_type_string(type),
2354 field2, field1, field0 & 0xffffffe0,
2355 TRB_TO_PACKET_TYPE(field0),
2356 TRB_TO_ROOTHUB_PORT(field3),
2357 field3 & TRB_CYCLE ? 'C' : 'c');
2361 "type '%s' -> raw %08x %08x %08x %08x",
2362 xhci_trb_type_string(type),
2363 field0, field1, field2, field3);
2369 static inline const char *xhci_decode_slot_context(u32 info, u32 info2,
2370 u32 tt_info, u32 state)
2372 static char str[1024];
2378 speed = info & DEV_SPEED;
2379 hub = info & DEV_HUB;
2380 mtt = info & DEV_MTT;
2382 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2383 info & ROUTE_STRING_MASK,
2398 case SLOT_SPEED_SSP:
2399 s = "super-speed plus";
2402 s = "UNKNOWN speed";
2404 mtt ? " multi-TT" : "",
2406 (info & LAST_CTX_MASK) >> 27,
2408 DEVINFO_TO_ROOT_HUB_PORT(info2),
2409 DEVINFO_TO_MAX_PORTS(info2));
2411 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2412 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2413 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2414 state & DEV_ADDR_MASK,
2415 xhci_slot_state_string(GET_SLOT_STATE(state)));
2421 static inline const char *xhci_portsc_link_state_string(u32 portsc)
2423 switch (portsc & PORT_PLS_MASK) {
2442 case XDEV_HOT_RESET:
2444 case XDEV_COMP_MODE:
2445 return "Compliance mode";
2446 case XDEV_TEST_MODE:
2456 static inline const char *xhci_decode_portsc(u32 portsc)
2458 static char str[256];
2461 ret = sprintf(str, "%s %s %s Link:%s ",
2462 portsc & PORT_POWER ? "Powered" : "Powered-off",
2463 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2464 portsc & PORT_PE ? "Enabled" : "Disabled",
2465 xhci_portsc_link_state_string(portsc));
2467 if (portsc & PORT_OC)
2468 ret += sprintf(str + ret, "OverCurrent ");
2469 if (portsc & PORT_RESET)
2470 ret += sprintf(str + ret, "In-Reset ");
2472 ret += sprintf(str + ret, "Change: ");
2473 if (portsc & PORT_CSC)
2474 ret += sprintf(str + ret, "CSC ");
2475 if (portsc & PORT_PEC)
2476 ret += sprintf(str + ret, "PEC ");
2477 if (portsc & PORT_WRC)
2478 ret += sprintf(str + ret, "WRC ");
2479 if (portsc & PORT_OCC)
2480 ret += sprintf(str + ret, "OCC ");
2481 if (portsc & PORT_RC)
2482 ret += sprintf(str + ret, "PRC ");
2483 if (portsc & PORT_PLC)
2484 ret += sprintf(str + ret, "PLC ");
2485 if (portsc & PORT_CEC)
2486 ret += sprintf(str + ret, "CEC ");
2487 if (portsc & PORT_CAS)
2488 ret += sprintf(str + ret, "CAS ");
2490 ret += sprintf(str + ret, "Wake: ");
2491 if (portsc & PORT_WKCONN_E)
2492 ret += sprintf(str + ret, "WCE ");
2493 if (portsc & PORT_WKDISC_E)
2494 ret += sprintf(str + ret, "WDE ");
2495 if (portsc & PORT_WKOC_E)
2496 ret += sprintf(str + ret, "WOE ");
2501 static inline const char *xhci_ep_state_string(u8 state)
2504 case EP_STATE_DISABLED:
2506 case EP_STATE_RUNNING:
2508 case EP_STATE_HALTED:
2510 case EP_STATE_STOPPED:
2512 case EP_STATE_ERROR:
2519 static inline const char *xhci_ep_type_string(u8 type)
2541 static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq,
2544 static char str[1024];
2562 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2563 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2565 ep_state = info & EP_STATE_MASK;
2566 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2567 interval = CTX_TO_EP_INTERVAL(info);
2568 mult = CTX_TO_EP_MULT(info) + 1;
2569 lsa = !!(info & EP_HAS_LSA);
2571 cerr = (info2 & (3 << 1)) >> 1;
2572 ep_type = CTX_TO_EP_TYPE(info2);
2573 hid = !!(info2 & (1 << 7));
2574 burst = CTX_TO_MAX_BURST(info2);
2575 maxp = MAX_PACKET_DECODED(info2);
2577 avg = EP_AVG_TRB_LENGTH(tx_info);
2579 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2580 xhci_ep_state_string(ep_state), mult,
2581 max_pstr, lsa ? "LSA " : "");
2583 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2584 (1 << interval) * 125, esit, cerr);
2586 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2587 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2590 ret += sprintf(str + ret, "avg trb len %d", avg);
2595 #endif /* __LINUX_XHCI_HCD_H */