3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software Foundation,
21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #ifndef __LINUX_XHCI_HCD_H
25 #define __LINUX_XHCI_HCD_H
27 #include <linux/usb.h>
28 #include <linux/timer.h>
29 #include <linux/kernel.h>
30 #include <linux/usb/hcd.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
33 /* Code sharing between pci-quirks and xhci hcd */
34 #include "xhci-ext-caps.h"
35 #include "pci-quirks.h"
37 /* xHCI PCI Configuration Registers */
38 #define XHCI_SBRN_OFFSET (0x60)
40 /* Max number of USB devices for any host controller - limit in section 6.1 */
41 #define MAX_HC_SLOTS 256
42 /* Section 5.3.3 - MaxPorts */
43 #define MAX_HC_PORTS 127
46 * xHCI register interface.
47 * This corresponds to the eXtensible Host Controller Interface (xHCI)
48 * Revision 0.95 specification
52 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
53 * @hc_capbase: length of the capabilities register and HC version number
54 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
55 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
56 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
57 * @hcc_params: HCCPARAMS - Capability Parameters
58 * @db_off: DBOFF - Doorbell array offset
59 * @run_regs_off: RTSOFF - Runtime register space offset
60 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
62 struct xhci_cap_regs {
70 __le32 hcc_params2; /* xhci 1.1 */
71 /* Reserved up to (CAPLENGTH - 0x1C) */
74 /* hc_capbase bitmasks */
75 /* bits 7:0 - how long is the Capabilities register */
76 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
78 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
80 /* HCSPARAMS1 - hcs_params1 - bitmasks */
81 /* bits 0:7, Max Device Slots */
82 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
83 #define HCS_SLOTS_MASK 0xff
84 /* bits 8:18, Max Interrupters */
85 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
86 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
87 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
89 /* HCSPARAMS2 - hcs_params2 - bitmasks */
90 /* bits 0:3, frames or uframes that SW needs to queue transactions
91 * ahead of the HW to meet periodic deadlines */
92 #define HCS_IST(p) (((p) >> 0) & 0xf)
93 /* bits 4:7, max number of Event Ring segments */
94 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
95 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
96 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
97 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
98 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
100 /* HCSPARAMS3 - hcs_params3 - bitmasks */
101 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
102 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
103 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
104 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
106 /* HCCPARAMS - hcc_params - bitmasks */
107 /* true: HC can use 64-bit address pointers */
108 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
109 /* true: HC can do bandwidth negotiation */
110 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
111 /* true: HC uses 64-byte Device Context structures
112 * FIXME 64-byte context structures aren't supported yet.
114 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
115 /* true: HC has port power switches */
116 #define HCC_PPC(p) ((p) & (1 << 3))
117 /* true: HC has port indicators */
118 #define HCS_INDICATOR(p) ((p) & (1 << 4))
119 /* true: HC has Light HC Reset Capability */
120 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
121 /* true: HC supports latency tolerance messaging */
122 #define HCC_LTC(p) ((p) & (1 << 6))
123 /* true: no secondary Stream ID Support */
124 #define HCC_NSS(p) ((p) & (1 << 7))
125 /* true: HC supports Stopped - Short Packet */
126 #define HCC_SPC(p) ((p) & (1 << 9))
127 /* true: HC has Contiguous Frame ID Capability */
128 #define HCC_CFC(p) ((p) & (1 << 11))
129 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
130 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
131 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
132 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
134 /* db_off bitmask - bits 0:1 reserved */
135 #define DBOFF_MASK (~0x3)
137 /* run_regs_off bitmask - bits 0:4 reserved */
138 #define RTSOFF_MASK (~0x1f)
140 /* HCCPARAMS2 - hcc_params2 - bitmasks */
141 /* true: HC supports U3 entry Capability */
142 #define HCC2_U3C(p) ((p) & (1 << 0))
143 /* true: HC supports Configure endpoint command Max exit latency too large */
144 #define HCC2_CMC(p) ((p) & (1 << 1))
145 /* true: HC supports Force Save context Capability */
146 #define HCC2_FSC(p) ((p) & (1 << 2))
147 /* true: HC supports Compliance Transition Capability */
148 #define HCC2_CTC(p) ((p) & (1 << 3))
149 /* true: HC support Large ESIT payload Capability > 48k */
150 #define HCC2_LEC(p) ((p) & (1 << 4))
151 /* true: HC support Configuration Information Capability */
152 #define HCC2_CIC(p) ((p) & (1 << 5))
153 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
154 #define HCC2_ETC(p) ((p) & (1 << 6))
156 /* Number of registers per port */
157 #define NUM_PORT_REGS 4
165 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
166 * @command: USBCMD - xHC command register
167 * @status: USBSTS - xHC status register
168 * @page_size: This indicates the page size that the host controller
169 * supports. If bit n is set, the HC supports a page size
170 * of 2^(n+12), up to a 128MB page size.
171 * 4K is the minimum page size.
172 * @cmd_ring: CRP - 64-bit Command Ring Pointer
173 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
174 * @config_reg: CONFIG - Configure Register
175 * @port_status_base: PORTSCn - base address for Port Status and Control
176 * Each port has a Port Status and Control register,
177 * followed by a Port Power Management Status and Control
178 * register, a Port Link Info register, and a reserved
180 * @port_power_base: PORTPMSCn - base address for
181 * Port Power Management Status and Control
182 * @port_link_base: PORTLIn - base address for Port Link Info (current
183 * Link PM state and control) for USB 2.1 and USB 3.0
186 struct xhci_op_regs {
192 __le32 dev_notification;
194 /* rsvd: offset 0x20-2F */
198 /* rsvd: offset 0x3C-3FF */
199 __le32 reserved4[241];
200 /* port 1 registers, which serve as a base address for other ports */
201 __le32 port_status_base;
202 __le32 port_power_base;
203 __le32 port_link_base;
205 /* registers for ports 2-255 */
206 __le32 reserved6[NUM_PORT_REGS*254];
209 /* USBCMD - USB command - command bitmasks */
210 /* start/stop HC execution - do not write unless HC is halted*/
211 #define CMD_RUN XHCI_CMD_RUN
212 /* Reset HC - resets internal HC state machine and all registers (except
213 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
214 * The xHCI driver must reinitialize the xHC after setting this bit.
216 #define CMD_RESET (1 << 1)
217 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
218 #define CMD_EIE XHCI_CMD_EIE
219 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
220 #define CMD_HSEIE XHCI_CMD_HSEIE
221 /* bits 4:6 are reserved (and should be preserved on writes). */
222 /* light reset (port status stays unchanged) - reset completed when this is 0 */
223 #define CMD_LRESET (1 << 7)
224 /* host controller save/restore state. */
225 #define CMD_CSS (1 << 8)
226 #define CMD_CRS (1 << 9)
227 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
228 #define CMD_EWE XHCI_CMD_EWE
229 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
230 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
231 * '0' means the xHC can power it off if all ports are in the disconnect,
232 * disabled, or powered-off state.
234 #define CMD_PM_INDEX (1 << 11)
235 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
236 #define CMD_ETE (1 << 14)
237 /* bits 15:31 are reserved (and should be preserved on writes). */
239 /* IMAN - Interrupt Management Register */
240 #define IMAN_IE (1 << 1)
241 #define IMAN_IP (1 << 0)
243 /* USBSTS - USB status - status bitmasks */
244 /* HC not running - set to 1 when run/stop bit is cleared. */
245 #define STS_HALT XHCI_STS_HALT
246 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
247 #define STS_FATAL (1 << 2)
248 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
249 #define STS_EINT (1 << 3)
250 /* port change detect */
251 #define STS_PORT (1 << 4)
252 /* bits 5:7 reserved and zeroed */
253 /* save state status - '1' means xHC is saving state */
254 #define STS_SAVE (1 << 8)
255 /* restore state status - '1' means xHC is restoring state */
256 #define STS_RESTORE (1 << 9)
257 /* true: save or restore error */
258 #define STS_SRE (1 << 10)
259 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
260 #define STS_CNR XHCI_STS_CNR
261 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
262 #define STS_HCE (1 << 12)
263 /* bits 13:31 reserved and should be preserved */
266 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
267 * Generate a device notification event when the HC sees a transaction with a
268 * notification type that matches a bit set in this bit field.
270 #define DEV_NOTE_MASK (0xffff)
271 #define ENABLE_DEV_NOTE(x) (1 << (x))
272 /* Most of the device notification types should only be used for debug.
273 * SW does need to pay attention to function wake notifications.
275 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
277 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
278 /* bit 0 is the command ring cycle state */
279 /* stop ring operation after completion of the currently executing command */
280 #define CMD_RING_PAUSE (1 << 1)
281 /* stop ring immediately - abort the currently executing command */
282 #define CMD_RING_ABORT (1 << 2)
283 /* true: command ring is running */
284 #define CMD_RING_RUNNING (1 << 3)
285 /* bits 4:5 reserved and should be preserved */
286 /* Command Ring pointer - bit mask for the lower 32 bits. */
287 #define CMD_RING_RSVD_BITS (0x3f)
289 /* CONFIG - Configure Register - config_reg bitmasks */
290 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
291 #define MAX_DEVS(p) ((p) & 0xff)
292 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
293 #define CONFIG_U3E (1 << 8)
294 /* bit 9: Configuration Information Enable, xhci 1.1 */
295 #define CONFIG_CIE (1 << 9)
296 /* bits 10:31 - reserved and should be preserved */
298 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
299 /* true: device connected */
300 #define PORT_CONNECT (1 << 0)
301 /* true: port enabled */
302 #define PORT_PE (1 << 1)
303 /* bit 2 reserved and zeroed */
304 /* true: port has an over-current condition */
305 #define PORT_OC (1 << 3)
306 /* true: port reset signaling asserted */
307 #define PORT_RESET (1 << 4)
308 /* Port Link State - bits 5:8
309 * A read gives the current link PM state of the port,
310 * a write with Link State Write Strobe set sets the link state.
312 #define PORT_PLS_MASK (0xf << 5)
313 #define XDEV_U0 (0x0 << 5)
314 #define XDEV_U1 (0x1 << 5)
315 #define XDEV_U2 (0x2 << 5)
316 #define XDEV_U3 (0x3 << 5)
317 #define XDEV_DISABLED (0x4 << 5)
318 #define XDEV_RXDETECT (0x5 << 5)
319 #define XDEV_INACTIVE (0x6 << 5)
320 #define XDEV_POLLING (0x7 << 5)
321 #define XDEV_RECOVERY (0x8 << 5)
322 #define XDEV_HOT_RESET (0x9 << 5)
323 #define XDEV_COMP_MODE (0xa << 5)
324 #define XDEV_TEST_MODE (0xb << 5)
325 #define XDEV_RESUME (0xf << 5)
327 /* true: port has power (see HCC_PPC) */
328 #define PORT_POWER (1 << 9)
329 /* bits 10:13 indicate device speed:
330 * 0 - undefined speed - port hasn't be initialized by a reset yet
337 #define DEV_SPEED_MASK (0xf << 10)
338 #define XDEV_FS (0x1 << 10)
339 #define XDEV_LS (0x2 << 10)
340 #define XDEV_HS (0x3 << 10)
341 #define XDEV_SS (0x4 << 10)
342 #define XDEV_SSP (0x5 << 10)
343 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
344 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
345 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
346 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
347 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
348 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
349 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
350 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
352 /* Bits 20:23 in the Slot Context are the speed for the device */
353 #define SLOT_SPEED_FS (XDEV_FS << 10)
354 #define SLOT_SPEED_LS (XDEV_LS << 10)
355 #define SLOT_SPEED_HS (XDEV_HS << 10)
356 #define SLOT_SPEED_SS (XDEV_SS << 10)
357 #define SLOT_SPEED_SSP (XDEV_SSP << 10)
358 /* Port Indicator Control */
359 #define PORT_LED_OFF (0 << 14)
360 #define PORT_LED_AMBER (1 << 14)
361 #define PORT_LED_GREEN (2 << 14)
362 #define PORT_LED_MASK (3 << 14)
363 /* Port Link State Write Strobe - set this when changing link state */
364 #define PORT_LINK_STROBE (1 << 16)
365 /* true: connect status change */
366 #define PORT_CSC (1 << 17)
367 /* true: port enable change */
368 #define PORT_PEC (1 << 18)
369 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
370 * into an enabled state, and the device into the default state. A "warm" reset
371 * also resets the link, forcing the device through the link training sequence.
372 * SW can also look at the Port Reset register to see when warm reset is done.
374 #define PORT_WRC (1 << 19)
375 /* true: over-current change */
376 #define PORT_OCC (1 << 20)
377 /* true: reset change - 1 to 0 transition of PORT_RESET */
378 #define PORT_RC (1 << 21)
379 /* port link status change - set on some port link state transitions:
381 * ------------------------------------------------------------------------------
382 * - U3 to Resume Wakeup signaling from a device
383 * - Resume to Recovery to U0 USB 3.0 device resume
384 * - Resume to U0 USB 2.0 device resume
385 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
386 * - U3 to U0 Software resume of USB 2.0 device complete
387 * - U2 to U0 L1 resume of USB 2.1 device complete
388 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
389 * - U0 to disabled L1 entry error with USB 2.1 device
390 * - Any state to inactive Error on USB 3.0 port
392 #define PORT_PLC (1 << 22)
393 /* port configure error change - port failed to configure its link partner */
394 #define PORT_CEC (1 << 23)
395 #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
396 PORT_RC | PORT_PLC | PORT_CEC)
399 /* Cold Attach Status - xHC can set this bit to report device attached during
400 * Sx state. Warm port reset should be perfomed to clear this bit and move port
401 * to connected state.
403 #define PORT_CAS (1 << 24)
404 /* wake on connect (enable) */
405 #define PORT_WKCONN_E (1 << 25)
406 /* wake on disconnect (enable) */
407 #define PORT_WKDISC_E (1 << 26)
408 /* wake on over-current (enable) */
409 #define PORT_WKOC_E (1 << 27)
410 /* bits 28:29 reserved */
411 /* true: device is non-removable - for USB 3.0 roothub emulation */
412 #define PORT_DEV_REMOVE (1 << 30)
413 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
414 #define PORT_WR (1 << 31)
416 /* We mark duplicate entries with -1 */
417 #define DUPLICATE_ENTRY ((u8)(-1))
419 /* Port Power Management Status and Control - port_power_base bitmasks */
420 /* Inactivity timer value for transitions into U1, in microseconds.
421 * Timeout can be up to 127us. 0xFF means an infinite timeout.
423 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
424 #define PORT_U1_TIMEOUT_MASK 0xff
425 /* Inactivity timer value for transitions into U2 */
426 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
427 #define PORT_U2_TIMEOUT_MASK (0xff << 8)
428 /* Bits 24:31 for port testing */
430 /* USB2 Protocol PORTSPMSC */
431 #define PORT_L1S_MASK 7
432 #define PORT_L1S_SUCCESS 1
433 #define PORT_RWE (1 << 3)
434 #define PORT_HIRD(p) (((p) & 0xf) << 4)
435 #define PORT_HIRD_MASK (0xf << 4)
436 #define PORT_L1DS_MASK (0xff << 8)
437 #define PORT_L1DS(p) (((p) & 0xff) << 8)
438 #define PORT_HLE (1 << 16)
439 #define PORT_TEST_MODE_SHIFT 28
441 /* USB3 Protocol PORTLI Port Link Information */
442 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
443 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
445 /* USB2 Protocol PORTHLPMC */
446 #define PORT_HIRDM(p)((p) & 3)
447 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
448 #define PORT_BESLD(p)(((p) & 0xf) << 10)
450 /* use 512 microseconds as USB2 LPM L1 default timeout. */
451 #define XHCI_L1_TIMEOUT 512
453 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
454 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
455 * by other operating systems.
457 * XHCI 1.0 errata 8/14/12 Table 13 notes:
458 * "Software should choose xHC BESL/BESLD field values that do not violate a
459 * device's resume latency requirements,
460 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
461 * or not program values < '4' if BLC = '0' and a BESL device is attached.
463 #define XHCI_DEFAULT_BESL 4
466 * struct xhci_intr_reg - Interrupt Register Set
467 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
468 * interrupts and check for pending interrupts.
469 * @irq_control: IMOD - Interrupt Moderation Register.
470 * Used to throttle interrupts.
471 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
472 * @erst_base: ERST base address.
473 * @erst_dequeue: Event ring dequeue pointer.
475 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
476 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
477 * multiple segments of the same size. The HC places events on the ring and
478 * "updates the Cycle bit in the TRBs to indicate to software the current
479 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
480 * updates the dequeue pointer.
482 struct xhci_intr_reg {
491 /* irq_pending bitmasks */
492 #define ER_IRQ_PENDING(p) ((p) & 0x1)
493 /* bits 2:31 need to be preserved */
494 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
495 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
496 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
497 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
499 /* irq_control bitmasks */
500 /* Minimum interval between interrupts (in 250ns intervals). The interval
501 * between interrupts will be longer if there are no events on the event ring.
502 * Default is 4000 (1 ms).
504 #define ER_IRQ_INTERVAL_MASK (0xffff)
505 /* Counter used to count down the time to the next interrupt - HW use only */
506 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
508 /* erst_size bitmasks */
509 /* Preserve bits 16:31 of erst_size */
510 #define ERST_SIZE_MASK (0xffff << 16)
512 /* erst_dequeue bitmasks */
513 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
514 * where the current dequeue pointer lies. This is an optional HW hint.
516 #define ERST_DESI_MASK (0x7)
517 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
518 * a work queue (or delayed service routine)?
520 #define ERST_EHB (1 << 3)
521 #define ERST_PTR_MASK (0xf)
524 * struct xhci_run_regs
526 * MFINDEX - current microframe number
528 * Section 5.5 Host Controller Runtime Registers:
529 * "Software should read and write these registers using only Dword (32 bit)
530 * or larger accesses"
532 struct xhci_run_regs {
533 __le32 microframe_index;
535 struct xhci_intr_reg ir_set[128];
539 * struct doorbell_array
541 * Bits 0 - 7: Endpoint target
543 * Bits 16 - 31: Stream ID
547 struct xhci_doorbell_array {
548 __le32 doorbell[256];
551 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
552 #define DB_VALUE_HOST 0x00000000
555 * struct xhci_protocol_caps
556 * @revision: major revision, minor revision, capability ID,
557 * and next capability pointer.
558 * @name_string: Four ASCII characters to say which spec this xHC
559 * follows, typically "USB ".
560 * @port_info: Port offset, count, and protocol-defined information.
562 struct xhci_protocol_caps {
568 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
569 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
570 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
571 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
572 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
574 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
575 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
576 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
577 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
578 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
579 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
581 #define PLT_MASK (0x03 << 6)
582 #define PLT_SYM (0x00 << 6)
583 #define PLT_ASYM_RX (0x02 << 6)
584 #define PLT_ASYM_TX (0x03 << 6)
587 * struct xhci_container_ctx
588 * @type: Type of context. Used to calculated offsets to contained contexts.
589 * @size: Size of the context data
590 * @bytes: The raw context data given to HW
591 * @dma: dma address of the bytes
593 * Represents either a Device or Input context. Holds a pointer to the raw
594 * memory used for the context (bytes) and dma address of it (dma).
596 struct xhci_container_ctx {
598 #define XHCI_CTX_TYPE_DEVICE 0x1
599 #define XHCI_CTX_TYPE_INPUT 0x2
608 * struct xhci_slot_ctx
609 * @dev_info: Route string, device speed, hub info, and last valid endpoint
610 * @dev_info2: Max exit latency for device number, root hub port number
611 * @tt_info: tt_info is used to construct split transaction tokens
612 * @dev_state: slot state and device address
614 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
615 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
616 * reserved at the end of the slot context for HC internal use.
618 struct xhci_slot_ctx {
623 /* offset 0x10 to 0x1f reserved for HC internal use */
627 /* dev_info bitmasks */
628 /* Route String - 0:19 */
629 #define ROUTE_STRING_MASK (0xfffff)
630 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
631 #define DEV_SPEED (0xf << 20)
632 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
633 /* bit 24 reserved */
634 /* Is this LS/FS device connected through a HS hub? - bit 25 */
635 #define DEV_MTT (0x1 << 25)
636 /* Set if the device is a hub - bit 26 */
637 #define DEV_HUB (0x1 << 26)
638 /* Index of the last valid endpoint context in this device context - 27:31 */
639 #define LAST_CTX_MASK (0x1f << 27)
640 #define LAST_CTX(p) ((p) << 27)
641 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
642 #define SLOT_FLAG (1 << 0)
643 #define EP0_FLAG (1 << 1)
645 /* dev_info2 bitmasks */
646 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
647 #define MAX_EXIT (0xffff)
648 /* Root hub port number that is needed to access the USB device */
649 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
650 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
651 /* Maximum number of ports under a hub device */
652 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
653 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
655 /* tt_info bitmasks */
657 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
658 * The Slot ID of the hub that isolates the high speed signaling from
659 * this low or full-speed device. '0' if attached to root hub port.
661 #define TT_SLOT (0xff)
663 * The number of the downstream facing port of the high-speed hub
664 * '0' if the device is not low or full speed.
666 #define TT_PORT (0xff << 8)
667 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
668 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
670 /* dev_state bitmasks */
671 /* USB device address - assigned by the HC */
672 #define DEV_ADDR_MASK (0xff)
673 /* bits 8:26 reserved */
675 #define SLOT_STATE (0x1f << 27)
676 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
678 #define SLOT_STATE_DISABLED 0
679 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
680 #define SLOT_STATE_DEFAULT 1
681 #define SLOT_STATE_ADDRESSED 2
682 #define SLOT_STATE_CONFIGURED 3
686 * @ep_info: endpoint state, streams, mult, and interval information.
687 * @ep_info2: information on endpoint type, max packet size, max burst size,
688 * error count, and whether the HC will force an event for all
690 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
691 * defines one stream, this points to the endpoint transfer ring.
692 * Otherwise, it points to a stream context array, which has a
693 * ring pointer for each flow.
695 * Average TRB lengths for the endpoint ring and
696 * max payload within an Endpoint Service Interval Time (ESIT).
698 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
699 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
700 * reserved at the end of the endpoint context for HC internal use.
707 /* offset 0x14 - 0x1f reserved for HC internal use */
711 /* ep_info bitmasks */
713 * Endpoint State - bits 0:2
716 * 2 - halted due to halt condition - ok to manipulate endpoint ring
721 #define EP_STATE_MASK (0x7)
722 #define EP_STATE_DISABLED 0
723 #define EP_STATE_RUNNING 1
724 #define EP_STATE_HALTED 2
725 #define EP_STATE_STOPPED 3
726 #define EP_STATE_ERROR 4
727 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
729 /* Mult - Max number of burtst within an interval, in EP companion desc. */
730 #define EP_MULT(p) (((p) & 0x3) << 8)
731 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
732 /* bits 10:14 are Max Primary Streams */
733 /* bit 15 is Linear Stream Array */
734 /* Interval - period between requests to an endpoint - 125u increments. */
735 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
736 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
737 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
738 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
739 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
740 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
741 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
742 #define EP_HAS_LSA (1 << 15)
743 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
744 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
746 /* ep_info2 bitmasks */
748 * Force Event - generate transfer events for all TRBs for this endpoint
749 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
751 #define FORCE_EVENT (0x1)
752 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
753 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
754 #define EP_TYPE(p) ((p) << 3)
755 #define ISOC_OUT_EP 1
756 #define BULK_OUT_EP 2
763 /* bit 7 is Host Initiate Disable - for disabling stream selection */
764 #define MAX_BURST(p) (((p)&0xff) << 8)
765 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
766 #define MAX_PACKET(p) (((p)&0xffff) << 16)
767 #define MAX_PACKET_MASK (0xffff << 16)
768 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
770 /* tx_info bitmasks */
771 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
772 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
773 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
774 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
777 #define EP_CTX_CYCLE_MASK (1 << 0)
778 #define SCTX_DEQ_MASK (~0xfL)
782 * struct xhci_input_control_context
783 * Input control context; see section 6.2.5.
785 * @drop_context: set the bit of the endpoint context you want to disable
786 * @add_context: set the bit of the endpoint context you want to enable
788 struct xhci_input_control_ctx {
794 #define EP_IS_ADDED(ctrl_ctx, i) \
795 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
796 #define EP_IS_DROPPED(ctrl_ctx, i) \
797 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
799 /* Represents everything that is needed to issue a command on the command ring.
800 * It's useful to pre-allocate these for commands that cannot fail due to
801 * out-of-memory errors, like freeing streams.
803 struct xhci_command {
804 /* Input context for changing device state */
805 struct xhci_container_ctx *in_ctx;
808 /* If completion is null, no one is waiting on this command
809 * and the structure can be freed after the command completes.
811 struct completion *completion;
812 union xhci_trb *command_trb;
813 struct list_head cmd_list;
816 /* drop context bitmasks */
817 #define DROP_EP(x) (0x1 << x)
818 /* add context bitmasks */
819 #define ADD_EP(x) (0x1 << x)
821 struct xhci_stream_ctx {
822 /* 64-bit stream ring address, cycle state, and stream type */
824 /* offset 0x14 - 0x1f reserved for HC internal use */
828 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
829 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
830 /* Secondary stream array type, dequeue pointer is to a transfer ring */
832 /* Primary stream array type, dequeue pointer is to a transfer ring */
834 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
839 #define SCT_SSA_128 6
840 #define SCT_SSA_256 7
842 /* Assume no secondary streams for now */
843 struct xhci_stream_info {
844 struct xhci_ring **stream_rings;
845 /* Number of streams, including stream 0 (which drivers can't use) */
846 unsigned int num_streams;
847 /* The stream context array may be bigger than
848 * the number of streams the driver asked for
850 struct xhci_stream_ctx *stream_ctx_array;
851 unsigned int num_stream_ctxs;
852 dma_addr_t ctx_array_dma;
853 /* For mapping physical TRB addresses to segments in stream rings */
854 struct radix_tree_root trb_address_map;
855 struct xhci_command *free_streams_command;
858 #define SMALL_STREAM_ARRAY_SIZE 256
859 #define MEDIUM_STREAM_ARRAY_SIZE 1024
861 /* Some Intel xHCI host controllers need software to keep track of the bus
862 * bandwidth. Keep track of endpoint info here. Each root port is allocated
863 * the full bus bandwidth. We must also treat TTs (including each port under a
864 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
865 * (DMI) also limits the total bandwidth (across all domains) that can be used.
867 struct xhci_bw_info {
868 /* ep_interval is zero-based */
869 unsigned int ep_interval;
870 /* mult and num_packets are one-based */
872 unsigned int num_packets;
873 unsigned int max_packet_size;
874 unsigned int max_esit_payload;
878 /* "Block" sizes in bytes the hardware uses for different device speeds.
879 * The logic in this part of the hardware limits the number of bits the hardware
880 * can use, so must represent bandwidth in a less precise manner to mimic what
881 * the scheduler hardware computes.
888 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
889 * with each byte transferred. SuperSpeed devices have an initial overhead to
890 * set up bursts. These are in blocks, see above. LS overhead has already been
891 * translated into FS blocks.
893 #define DMI_OVERHEAD 8
894 #define DMI_OVERHEAD_BURST 4
895 #define SS_OVERHEAD 8
896 #define SS_OVERHEAD_BURST 32
897 #define HS_OVERHEAD 26
898 #define FS_OVERHEAD 20
899 #define LS_OVERHEAD 128
900 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
901 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
902 * of overhead associated with split transfers crossing microframe boundaries.
903 * 31 blocks is pure protocol overhead.
905 #define TT_HS_OVERHEAD (31 + 94)
906 #define TT_DMI_OVERHEAD (25 + 12)
908 /* Bandwidth limits in blocks */
909 #define FS_BW_LIMIT 1285
910 #define TT_BW_LIMIT 1320
911 #define HS_BW_LIMIT 1607
912 #define SS_BW_LIMIT_IN 3906
913 #define DMI_BW_LIMIT_IN 3906
914 #define SS_BW_LIMIT_OUT 3906
915 #define DMI_BW_LIMIT_OUT 3906
917 /* Percentage of bus bandwidth reserved for non-periodic transfers */
918 #define FS_BW_RESERVED 10
919 #define HS_BW_RESERVED 20
920 #define SS_BW_RESERVED 10
922 struct xhci_virt_ep {
923 struct xhci_ring *ring;
924 /* Related to endpoints that are configured to use stream IDs only */
925 struct xhci_stream_info *stream_info;
926 /* Temporary storage in case the configure endpoint command fails and we
927 * have to restore the device state to the previous state
929 struct xhci_ring *new_ring;
930 unsigned int ep_state;
931 #define SET_DEQ_PENDING (1 << 0)
932 #define EP_HALTED (1 << 1) /* For stall handling */
933 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
934 /* Transitioning the endpoint to using streams, don't enqueue URBs */
935 #define EP_GETTING_STREAMS (1 << 3)
936 #define EP_HAS_STREAMS (1 << 4)
937 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
938 #define EP_GETTING_NO_STREAMS (1 << 5)
939 /* ---- Related to URB cancellation ---- */
940 struct list_head cancelled_td_list;
941 /* Watchdog timer for stop endpoint command to cancel URBs */
942 struct timer_list stop_cmd_timer;
943 struct xhci_hcd *xhci;
944 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
945 * command. We'll need to update the ring's dequeue segment and dequeue
946 * pointer after the command completes.
948 struct xhci_segment *queued_deq_seg;
949 union xhci_trb *queued_deq_ptr;
951 * Sometimes the xHC can not process isochronous endpoint ring quickly
952 * enough, and it will miss some isoc tds on the ring and generate
953 * a Missed Service Error Event.
954 * Set skip flag when receive a Missed Service Error Event and
955 * process the missed tds on the endpoint ring.
958 /* Bandwidth checking storage */
959 struct xhci_bw_info bw_info;
960 struct list_head bw_endpoint_list;
961 /* Isoch Frame ID checking storage */
963 /* Use new Isoch TRB layout needed for extended TBC support */
964 bool use_extended_tbc;
967 enum xhci_overhead_type {
968 LS_OVERHEAD_TYPE = 0,
973 struct xhci_interval_bw {
974 unsigned int num_packets;
975 /* Sorted by max packet size.
976 * Head of the list is the greatest max packet size.
978 struct list_head endpoints;
979 /* How many endpoints of each speed are present. */
980 unsigned int overhead[3];
983 #define XHCI_MAX_INTERVAL 16
985 struct xhci_interval_bw_table {
986 unsigned int interval0_esit_payload;
987 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
988 /* Includes reserved bandwidth for async endpoints */
989 unsigned int bw_used;
990 unsigned int ss_bw_in;
991 unsigned int ss_bw_out;
994 #define EP_CTX_PER_DEV 31
996 struct xhci_virt_device {
997 struct usb_device *udev;
999 * Commands to the hardware are passed an "input context" that
1000 * tells the hardware what to change in its data structures.
1001 * The hardware will return changes in an "output context" that
1002 * software must allocate for the hardware. We need to keep
1003 * track of input and output contexts separately because
1004 * these commands might fail and we don't trust the hardware.
1006 struct xhci_container_ctx *out_ctx;
1007 /* Used for addressing devices and configuration changes */
1008 struct xhci_container_ctx *in_ctx;
1009 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
1012 struct xhci_interval_bw_table *bw_table;
1013 struct xhci_tt_bw_info *tt_info;
1014 /* The current max exit latency for the enabled USB3 link states. */
1019 * For each roothub, keep track of the bandwidth information for each periodic
1022 * If a high speed hub is attached to the roothub, each TT associated with that
1023 * hub is a separate bandwidth domain. The interval information for the
1024 * endpoints on the devices under that TT will appear in the TT structure.
1026 struct xhci_root_port_bw_info {
1027 struct list_head tts;
1028 unsigned int num_active_tts;
1029 struct xhci_interval_bw_table bw_table;
1032 struct xhci_tt_bw_info {
1033 struct list_head tt_list;
1036 struct xhci_interval_bw_table bw_table;
1042 * struct xhci_device_context_array
1043 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1045 struct xhci_device_context_array {
1046 /* 64-bit device addresses; we only write 32-bit addresses */
1047 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1048 /* private xHCD pointers */
1051 /* TODO: write function to set the 64-bit device DMA address */
1053 * TODO: change this to be dynamically sized at HC mem init time since the HC
1054 * might not be able to handle the maximum number of devices possible.
1058 struct xhci_transfer_event {
1059 /* 64-bit buffer address, or immediate data */
1061 __le32 transfer_len;
1062 /* This field is interpreted differently based on the type of TRB */
1066 /* Transfer event TRB length bit mask */
1068 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1070 /** Transfer Event bit fields **/
1071 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1073 /* Completion Code - only applicable for some types of TRBs */
1074 #define COMP_CODE_MASK (0xff << 24)
1075 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1076 #define COMP_INVALID 0
1077 #define COMP_SUCCESS 1
1078 #define COMP_DATA_BUFFER_ERROR 2
1079 #define COMP_BABBLE_DETECTED_ERROR 3
1080 #define COMP_USB_TRANSACTION_ERROR 4
1081 #define COMP_TRB_ERROR 5
1082 #define COMP_STALL_ERROR 6
1083 #define COMP_RESOURCE_ERROR 7
1084 #define COMP_BANDWIDTH_ERROR 8
1085 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1086 #define COMP_INVALID_STREAM_TYPE_ERROR 10
1087 #define COMP_SLOT_NOT_ENABLED_ERROR 11
1088 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1089 #define COMP_SHORT_PACKET 13
1090 #define COMP_RING_UNDERRUN 14
1091 #define COMP_RING_OVERRUN 15
1092 #define COMP_VF_EVENT_RING_FULL_ERROR 16
1093 #define COMP_PARAMETER_ERROR 17
1094 #define COMP_BANDWIDTH_OVERRUN_ERROR 18
1095 #define COMP_CONTEXT_STATE_ERROR 19
1096 #define COMP_NO_PING_RESPONSE_ERROR 20
1097 #define COMP_EVENT_RING_FULL_ERROR 21
1098 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1099 #define COMP_MISSED_SERVICE_ERROR 23
1100 #define COMP_COMMAND_RING_STOPPED 24
1101 #define COMP_COMMAND_ABORTED 25
1102 #define COMP_STOPPED 26
1103 #define COMP_STOPPED_LENGTH_INVALID 27
1104 #define COMP_STOPPED_SHORT_PACKET 28
1105 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1106 #define COMP_ISOCH_BUFFER_OVERRUN 31
1107 #define COMP_EVENT_LOST_ERROR 32
1108 #define COMP_UNDEFINED_ERROR 33
1109 #define COMP_INVALID_STREAM_ID_ERROR 34
1110 #define COMP_SECONDARY_BANDWIDTH_ERROR 35
1111 #define COMP_SPLIT_TRANSACTION_ERROR 36
1113 static inline const char *xhci_trb_comp_code_string(u8 status)
1120 case COMP_DATA_BUFFER_ERROR:
1121 return "Data Buffer Error";
1122 case COMP_BABBLE_DETECTED_ERROR:
1123 return "Babble Detected";
1124 case COMP_USB_TRANSACTION_ERROR:
1125 return "USB Transaction Error";
1126 case COMP_TRB_ERROR:
1128 case COMP_STALL_ERROR:
1129 return "Stall Error";
1130 case COMP_RESOURCE_ERROR:
1131 return "Resource Error";
1132 case COMP_BANDWIDTH_ERROR:
1133 return "Bandwidth Error";
1134 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1135 return "No Slots Available Error";
1136 case COMP_INVALID_STREAM_TYPE_ERROR:
1137 return "Invalid Stream Type Error";
1138 case COMP_SLOT_NOT_ENABLED_ERROR:
1139 return "Slot Not Enabled Error";
1140 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1141 return "Endpoint Not Enabled Error";
1142 case COMP_SHORT_PACKET:
1143 return "Short Packet";
1144 case COMP_RING_UNDERRUN:
1145 return "Ring Underrun";
1146 case COMP_RING_OVERRUN:
1147 return "Ring Overrun";
1148 case COMP_VF_EVENT_RING_FULL_ERROR:
1149 return "VF Event Ring Full Error";
1150 case COMP_PARAMETER_ERROR:
1151 return "Parameter Error";
1152 case COMP_BANDWIDTH_OVERRUN_ERROR:
1153 return "Bandwidth Overrun Error";
1154 case COMP_CONTEXT_STATE_ERROR:
1155 return "Context State Error";
1156 case COMP_NO_PING_RESPONSE_ERROR:
1157 return "No Ping Response Error";
1158 case COMP_EVENT_RING_FULL_ERROR:
1159 return "Event Ring Full Error";
1160 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1161 return "Incompatible Device Error";
1162 case COMP_MISSED_SERVICE_ERROR:
1163 return "Missed Service Error";
1164 case COMP_COMMAND_RING_STOPPED:
1165 return "Command Ring Stopped";
1166 case COMP_COMMAND_ABORTED:
1167 return "Command Aborted";
1170 case COMP_STOPPED_LENGTH_INVALID:
1171 return "Stopped - Length Invalid";
1172 case COMP_STOPPED_SHORT_PACKET:
1173 return "Stopped - Short Packet";
1174 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1175 return "Max Exit Latency Too Large Error";
1176 case COMP_ISOCH_BUFFER_OVERRUN:
1177 return "Isoch Buffer Overrun";
1178 case COMP_EVENT_LOST_ERROR:
1179 return "Event Lost Error";
1180 case COMP_UNDEFINED_ERROR:
1181 return "Undefined Error";
1182 case COMP_INVALID_STREAM_ID_ERROR:
1183 return "Invalid Stream ID Error";
1184 case COMP_SECONDARY_BANDWIDTH_ERROR:
1185 return "Secondary Bandwidth Error";
1186 case COMP_SPLIT_TRANSACTION_ERROR:
1187 return "Split Transaction Error";
1193 struct xhci_link_trb {
1194 /* 64-bit segment pointer*/
1200 /* control bitfields */
1201 #define LINK_TOGGLE (0x1<<1)
1203 /* Command completion event TRB */
1204 struct xhci_event_cmd {
1205 /* Pointer to command TRB, or the value passed by the event data trb */
1211 /* flags bitmasks */
1213 /* Address device - disable SetAddress */
1214 #define TRB_BSR (1<<9)
1216 /* Configure Endpoint - Deconfigure */
1217 #define TRB_DC (1<<9)
1219 /* Stop Ring - Transfer State Preserve */
1220 #define TRB_TSP (1<<9)
1222 enum xhci_ep_reset_type {
1228 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1229 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1231 /* Set Latency Tolerance Value */
1232 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1234 /* Get Port Bandwidth */
1235 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1238 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1239 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1241 enum xhci_setup_dev {
1243 SETUP_CONTEXT_ADDRESS,
1246 /* bits 16:23 are the virtual function ID */
1247 /* bits 24:31 are the slot ID */
1248 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1249 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1251 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1252 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1253 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1255 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1256 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1257 #define LAST_EP_INDEX 30
1259 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1260 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1261 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1262 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1264 /* Link TRB specific fields */
1265 #define TRB_TC (1<<1)
1267 /* Port Status Change Event TRB fields */
1268 /* Port ID - bits 31:24 */
1269 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1271 #define EVENT_DATA (1 << 2)
1273 /* Normal TRB fields */
1274 /* transfer_len bitmasks - bits 0:16 */
1275 #define TRB_LEN(p) ((p) & 0x1ffff)
1276 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1277 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1278 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1279 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1280 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1281 /* Interrupter Target - which MSI-X vector to target the completion event at */
1282 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1283 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1284 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1285 #define TRB_TBC(p) (((p) & 0x3) << 7)
1286 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1288 /* Cycle bit - indicates TRB ownership by HC or HCD */
1289 #define TRB_CYCLE (1<<0)
1291 * Force next event data TRB to be evaluated before task switch.
1292 * Used to pass OS data back after a TD completes.
1294 #define TRB_ENT (1<<1)
1295 /* Interrupt on short packet */
1296 #define TRB_ISP (1<<2)
1297 /* Set PCIe no snoop attribute */
1298 #define TRB_NO_SNOOP (1<<3)
1299 /* Chain multiple TRBs into a TD */
1300 #define TRB_CHAIN (1<<4)
1301 /* Interrupt on completion */
1302 #define TRB_IOC (1<<5)
1303 /* The buffer pointer contains immediate data */
1304 #define TRB_IDT (1<<6)
1306 /* Block Event Interrupt */
1307 #define TRB_BEI (1<<9)
1309 /* Control transfer TRB specific fields */
1310 #define TRB_DIR_IN (1<<16)
1311 #define TRB_TX_TYPE(p) ((p) << 16)
1312 #define TRB_DATA_OUT 2
1313 #define TRB_DATA_IN 3
1315 /* Isochronous TRB specific fields */
1316 #define TRB_SIA (1<<31)
1317 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1319 struct xhci_generic_trb {
1324 struct xhci_link_trb link;
1325 struct xhci_transfer_event trans_event;
1326 struct xhci_event_cmd event_cmd;
1327 struct xhci_generic_trb generic;
1331 #define TRB_TYPE_BITMASK (0xfc00)
1332 #define TRB_TYPE(p) ((p) << 10)
1333 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1335 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1336 #define TRB_NORMAL 1
1337 /* setup stage for control transfers */
1339 /* data stage for control transfers */
1341 /* status stage for control transfers */
1342 #define TRB_STATUS 4
1343 /* isoc transfers */
1345 /* TRB for linking ring segments */
1347 #define TRB_EVENT_DATA 7
1348 /* Transfer Ring No-op (not for the command ring) */
1349 #define TRB_TR_NOOP 8
1351 /* Enable Slot Command */
1352 #define TRB_ENABLE_SLOT 9
1353 /* Disable Slot Command */
1354 #define TRB_DISABLE_SLOT 10
1355 /* Address Device Command */
1356 #define TRB_ADDR_DEV 11
1357 /* Configure Endpoint Command */
1358 #define TRB_CONFIG_EP 12
1359 /* Evaluate Context Command */
1360 #define TRB_EVAL_CONTEXT 13
1361 /* Reset Endpoint Command */
1362 #define TRB_RESET_EP 14
1363 /* Stop Transfer Ring Command */
1364 #define TRB_STOP_RING 15
1365 /* Set Transfer Ring Dequeue Pointer Command */
1366 #define TRB_SET_DEQ 16
1367 /* Reset Device Command */
1368 #define TRB_RESET_DEV 17
1369 /* Force Event Command (opt) */
1370 #define TRB_FORCE_EVENT 18
1371 /* Negotiate Bandwidth Command (opt) */
1372 #define TRB_NEG_BANDWIDTH 19
1373 /* Set Latency Tolerance Value Command (opt) */
1374 #define TRB_SET_LT 20
1375 /* Get port bandwidth Command */
1376 #define TRB_GET_BW 21
1377 /* Force Header Command - generate a transaction or link management packet */
1378 #define TRB_FORCE_HEADER 22
1379 /* No-op Command - not for transfer rings */
1380 #define TRB_CMD_NOOP 23
1381 /* TRB IDs 24-31 reserved */
1383 /* Transfer Event */
1384 #define TRB_TRANSFER 32
1385 /* Command Completion Event */
1386 #define TRB_COMPLETION 33
1387 /* Port Status Change Event */
1388 #define TRB_PORT_STATUS 34
1389 /* Bandwidth Request Event (opt) */
1390 #define TRB_BANDWIDTH_EVENT 35
1391 /* Doorbell Event (opt) */
1392 #define TRB_DOORBELL 36
1393 /* Host Controller Event */
1394 #define TRB_HC_EVENT 37
1395 /* Device Notification Event - device sent function wake notification */
1396 #define TRB_DEV_NOTE 38
1397 /* MFINDEX Wrap Event - microframe counter wrapped */
1398 #define TRB_MFINDEX_WRAP 39
1399 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1401 /* Nec vendor-specific command completion event. */
1402 #define TRB_NEC_CMD_COMP 48
1403 /* Get NEC firmware revision. */
1404 #define TRB_NEC_GET_FW 49
1406 static inline const char *xhci_trb_type_string(u8 type)
1412 return "Setup Stage";
1414 return "Data Stage";
1416 return "Status Stage";
1421 case TRB_EVENT_DATA:
1422 return "Event Data";
1425 case TRB_ENABLE_SLOT:
1426 return "Enable Slot Command";
1427 case TRB_DISABLE_SLOT:
1428 return "Disable Slot Command";
1430 return "Address Device Command";
1432 return "Configure Endpoint Command";
1433 case TRB_EVAL_CONTEXT:
1434 return "Evaluate Context Command";
1436 return "Reset Endpoint Command";
1438 return "Stop Ring Command";
1440 return "Set TR Dequeue Pointer Command";
1442 return "Reset Device Command";
1443 case TRB_FORCE_EVENT:
1444 return "Force Event Command";
1445 case TRB_NEG_BANDWIDTH:
1446 return "Negotiate Bandwidth Command";
1448 return "Set Latency Tolerance Value Command";
1450 return "Get Port Bandwidth Command";
1451 case TRB_FORCE_HEADER:
1452 return "Force Header Command";
1454 return "No-Op Command";
1456 return "Transfer Event";
1457 case TRB_COMPLETION:
1458 return "Command Completion Event";
1459 case TRB_PORT_STATUS:
1460 return "Port Status Change Event";
1461 case TRB_BANDWIDTH_EVENT:
1462 return "Bandwidth Request Event";
1464 return "Doorbell Event";
1466 return "Host Controller Event";
1468 return "Device Notification Event";
1469 case TRB_MFINDEX_WRAP:
1470 return "MFINDEX Wrap Event";
1471 case TRB_NEC_CMD_COMP:
1472 return "NEC Command Completion Event";
1473 case TRB_NEC_GET_FW:
1474 return "NET Get Firmware Revision Command";
1480 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1481 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1482 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1483 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1484 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1485 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1487 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1488 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1491 * TRBS_PER_SEGMENT must be a multiple of 4,
1492 * since the command ring is 64-byte aligned.
1493 * It must also be greater than 16.
1495 #define TRBS_PER_SEGMENT 256
1496 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1497 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1498 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1499 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1500 /* TRB buffer pointers can't cross 64KB boundaries */
1501 #define TRB_MAX_BUFF_SHIFT 16
1502 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1503 /* How much data is left before the 64KB boundary? */
1504 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1505 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1507 struct xhci_segment {
1508 union xhci_trb *trbs;
1509 /* private to HCD */
1510 struct xhci_segment *next;
1512 /* Max packet sized bounce buffer for td-fragmant alignment */
1513 dma_addr_t bounce_dma;
1515 unsigned int bounce_offs;
1516 unsigned int bounce_len;
1520 struct list_head td_list;
1521 struct list_head cancelled_td_list;
1523 struct xhci_segment *start_seg;
1524 union xhci_trb *first_trb;
1525 union xhci_trb *last_trb;
1526 struct xhci_segment *bounce_seg;
1527 /* actual_length of the URB has already been set */
1528 bool urb_length_set;
1531 /* xHCI command default timeout value */
1532 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1534 /* command descriptor */
1536 struct xhci_command *command;
1537 union xhci_trb *cmd_trb;
1540 struct xhci_dequeue_state {
1541 struct xhci_segment *new_deq_seg;
1542 union xhci_trb *new_deq_ptr;
1543 int new_cycle_state;
1544 unsigned int stream_id;
1547 enum xhci_ring_type {
1557 static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1580 struct xhci_segment *first_seg;
1581 struct xhci_segment *last_seg;
1582 union xhci_trb *enqueue;
1583 struct xhci_segment *enq_seg;
1584 union xhci_trb *dequeue;
1585 struct xhci_segment *deq_seg;
1586 struct list_head td_list;
1588 * Write the cycle state into the TRB cycle field to give ownership of
1589 * the TRB to the host controller (if we are the producer), or to check
1590 * if we own the TRB (if we are the consumer). See section 4.9.1.
1593 unsigned int stream_id;
1594 unsigned int num_segs;
1595 unsigned int num_trbs_free;
1596 unsigned int num_trbs_free_temp;
1597 unsigned int bounce_buf_len;
1598 enum xhci_ring_type type;
1599 bool last_td_was_short;
1600 struct radix_tree_root *trb_address_map;
1603 struct xhci_erst_entry {
1604 /* 64-bit event ring segment address */
1612 struct xhci_erst_entry *entries;
1613 unsigned int num_entries;
1614 /* xhci->event_ring keeps track of segment dma addresses */
1615 dma_addr_t erst_dma_addr;
1616 /* Num entries the ERST can contain */
1617 unsigned int erst_size;
1620 struct xhci_scratchpad {
1629 struct xhci_td td[0];
1633 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1634 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1635 * meaning 64 ring segments.
1636 * Initial allocated size of the ERST, in number of entries */
1637 #define ERST_NUM_SEGS 1
1638 /* Initial allocated size of the ERST, in number of entries */
1639 #define ERST_SIZE 64
1640 /* Initial number of event segment rings allocated */
1641 #define ERST_ENTRIES 1
1642 /* Poll every 60 seconds */
1643 #define POLL_TIMEOUT 60
1644 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1645 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1646 /* XXX: Make these module parameters */
1663 struct list_head list;
1666 struct xhci_bus_state {
1667 unsigned long bus_suspended;
1668 unsigned long next_statechange;
1670 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1671 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1673 u32 suspended_ports;
1674 u32 port_remote_wakeup;
1675 unsigned long resume_done[USB_MAXCHILDREN];
1676 /* which ports have started to resume */
1677 unsigned long resuming_ports;
1678 /* Which ports are waiting on RExit to U0 transition. */
1679 unsigned long rexit_ports;
1680 struct completion rexit_done[USB_MAXCHILDREN];
1685 * It can take up to 20 ms to transition from RExit to U0 on the
1686 * Intel Lynx Point LP xHCI host.
1688 #define XHCI_MAX_REXIT_TIMEOUT_MS 20
1690 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1692 if (hcd->speed >= HCD_USB3)
1701 u32 *psi; /* array of protocol speed ID entries */
1706 /* There is one xhci_hcd structure per controller */
1708 struct usb_hcd *main_hcd;
1709 struct usb_hcd *shared_hcd;
1710 /* glue to PCI and HCD framework */
1711 struct xhci_cap_regs __iomem *cap_regs;
1712 struct xhci_op_regs __iomem *op_regs;
1713 struct xhci_run_regs __iomem *run_regs;
1714 struct xhci_doorbell_array __iomem *dba;
1715 /* Our HCD's current interrupter register set */
1716 struct xhci_intr_reg __iomem *ir_set;
1718 /* Cached register copies of read-only HC data */
1727 /* packed release number */
1731 u8 max_interrupters;
1735 /* 4KB min, 128MB max */
1737 /* Valid values are 12 to 20, inclusive */
1741 /* optional clock */
1743 /* data structures */
1744 struct xhci_device_context_array *dcbaa;
1745 struct xhci_ring *cmd_ring;
1746 unsigned int cmd_ring_state;
1747 #define CMD_RING_STATE_RUNNING (1 << 0)
1748 #define CMD_RING_STATE_ABORTED (1 << 1)
1749 #define CMD_RING_STATE_STOPPED (1 << 2)
1750 struct list_head cmd_list;
1751 unsigned int cmd_ring_reserved_trbs;
1752 struct delayed_work cmd_timer;
1753 struct completion cmd_ring_stop_completion;
1754 struct xhci_command *current_cmd;
1755 struct xhci_ring *event_ring;
1756 struct xhci_erst erst;
1758 struct xhci_scratchpad *scratchpad;
1759 /* Store LPM test failed devices' information */
1760 struct list_head lpm_failed_devs;
1762 /* slot enabling and address device helpers */
1763 /* these are not thread safe so use mutex */
1765 /* For USB 3.0 LPM enable/disable. */
1766 struct xhci_command *lpm_command;
1767 /* Internal mirror of the HW's dcbaa */
1768 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1769 /* For keeping track of bandwidth domains per roothub. */
1770 struct xhci_root_port_bw_info *rh_bw;
1773 struct dma_pool *device_pool;
1774 struct dma_pool *segment_pool;
1775 struct dma_pool *small_streams_pool;
1776 struct dma_pool *medium_streams_pool;
1778 /* Host controller watchdog timer structures */
1779 unsigned int xhc_state;
1783 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1785 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1786 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1787 * that sees this status (other than the timer that set it) should stop touching
1788 * hardware immediately. Interrupt handlers should return immediately when
1789 * they see this status (any time they drop and re-acquire xhci->lock).
1790 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1791 * putting the TD on the canceled list, etc.
1793 * There are no reports of xHCI host controllers that display this issue.
1795 #define XHCI_STATE_DYING (1 << 0)
1796 #define XHCI_STATE_HALTED (1 << 1)
1797 #define XHCI_STATE_REMOVING (1 << 2)
1798 unsigned long long quirks;
1799 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1800 #define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1801 #define XHCI_NEC_HOST BIT_ULL(2)
1802 #define XHCI_AMD_PLL_FIX BIT_ULL(3)
1803 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1805 * Certain Intel host controllers have a limit to the number of endpoint
1806 * contexts they can handle. Ideally, they would signal that they can't handle
1807 * anymore endpoint contexts by returning a Resource Error for the Configure
1808 * Endpoint command, but they don't. Instead they expect software to keep track
1809 * of the number of active endpoints for them, across configure endpoint
1810 * commands, reset device commands, disable slot commands, and address device
1813 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1814 #define XHCI_BROKEN_MSI BIT_ULL(6)
1815 #define XHCI_RESET_ON_RESUME BIT_ULL(7)
1816 #define XHCI_SW_BW_CHECKING BIT_ULL(8)
1817 #define XHCI_AMD_0x96_HOST BIT_ULL(9)
1818 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1819 #define XHCI_LPM_SUPPORT BIT_ULL(11)
1820 #define XHCI_INTEL_HOST BIT_ULL(12)
1821 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1822 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1823 #define XHCI_AVOID_BEI BIT_ULL(15)
1824 #define XHCI_PLAT BIT_ULL(16)
1825 #define XHCI_SLOW_SUSPEND BIT_ULL(17)
1826 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1827 /* For controllers with a broken beyond repair streams implementation */
1828 #define XHCI_BROKEN_STREAMS BIT_ULL(19)
1829 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1830 #define XHCI_MTK_HOST BIT_ULL(21)
1831 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1832 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1833 #define XHCI_MISSING_CAS BIT_ULL(24)
1834 /* For controller with a broken Port Disable implementation */
1835 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1836 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1837 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1838 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1839 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1840 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
1841 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1842 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1843 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1845 unsigned int num_active_eps;
1846 unsigned int limit_active_eps;
1847 /* There are two roothubs to keep track of bus suspend info for */
1848 struct xhci_bus_state bus_state[2];
1849 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1851 /* Array of pointers to USB 3.0 PORTSC registers */
1852 __le32 __iomem **usb3_ports;
1853 unsigned int num_usb3_ports;
1854 /* Array of pointers to USB 2.0 PORTSC registers */
1855 __le32 __iomem **usb2_ports;
1856 struct xhci_hub usb2_rhub;
1857 struct xhci_hub usb3_rhub;
1858 unsigned int num_usb2_ports;
1859 /* support xHCI 0.96 spec USB2 software LPM */
1860 unsigned sw_lpm_support:1;
1861 /* support xHCI 1.0 spec USB2 hardware LPM */
1862 unsigned hw_lpm_support:1;
1863 /* Broken Suspend flag for SNPS Suspend resume issue */
1864 unsigned broken_suspend:1;
1865 /* cached usb2 extened protocol capabilites */
1867 unsigned int num_ext_caps;
1868 /* Compliance Mode Recovery Data */
1869 struct timer_list comp_mode_recovery_timer;
1872 /* Compliance Mode Timer Triggered every 2 seconds */
1873 #define COMP_MODE_RCVRY_MSECS 2000
1875 /* platform-specific data -- must come last */
1876 unsigned long priv[0] __aligned(sizeof(s64));
1879 /* Platform specific overrides to generic XHCI hc_driver ops */
1880 struct xhci_driver_overrides {
1881 size_t extra_priv_size;
1882 int (*reset)(struct usb_hcd *hcd);
1883 int (*start)(struct usb_hcd *hcd);
1886 #define XHCI_CFC_DELAY 10
1888 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1889 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1891 struct usb_hcd *primary_hcd;
1893 if (usb_hcd_is_primary_hcd(hcd))
1896 primary_hcd = hcd->primary_hcd;
1898 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1901 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1903 return xhci->main_hcd;
1906 #define xhci_dbg(xhci, fmt, args...) \
1907 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1908 #define xhci_err(xhci, fmt, args...) \
1909 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1910 #define xhci_warn(xhci, fmt, args...) \
1911 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1912 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1913 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1914 #define xhci_info(xhci, fmt, args...) \
1915 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1918 * Registers should always be accessed with double word or quad word accesses.
1920 * Some xHCI implementations may support 64-bit address pointers. Registers
1921 * with 64-bit address pointers should be written to with dword accesses by
1922 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1923 * xHCI implementations that do not support 64-bit address pointers will ignore
1924 * the high dword, and write order is irrelevant.
1926 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1927 __le64 __iomem *regs)
1929 return lo_hi_readq(regs);
1931 static inline void xhci_write_64(struct xhci_hcd *xhci,
1932 const u64 val, __le64 __iomem *regs)
1934 lo_hi_writeq(val, regs);
1937 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1939 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1942 /* xHCI debugging */
1943 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1944 void xhci_print_registers(struct xhci_hcd *xhci);
1945 void xhci_dbg_regs(struct xhci_hcd *xhci);
1946 void xhci_print_run_regs(struct xhci_hcd *xhci);
1947 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1948 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1949 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1950 struct xhci_container_ctx *ctx);
1951 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1952 const char *fmt, ...);
1954 /* xHCI memory management */
1955 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1956 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1957 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1958 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1959 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1960 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1961 struct usb_device *udev);
1962 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1963 unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1964 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1965 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1966 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1967 struct xhci_virt_device *virt_dev,
1968 int old_active_eps);
1969 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1970 void xhci_update_bw_info(struct xhci_hcd *xhci,
1971 struct xhci_container_ctx *in_ctx,
1972 struct xhci_input_control_ctx *ctrl_ctx,
1973 struct xhci_virt_device *virt_dev);
1974 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1975 struct xhci_container_ctx *in_ctx,
1976 struct xhci_container_ctx *out_ctx,
1977 unsigned int ep_index);
1978 void xhci_slot_copy(struct xhci_hcd *xhci,
1979 struct xhci_container_ctx *in_ctx,
1980 struct xhci_container_ctx *out_ctx);
1981 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1982 struct usb_device *udev, struct usb_host_endpoint *ep,
1984 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1985 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1986 unsigned int num_trbs, gfp_t flags);
1987 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
1988 struct xhci_virt_device *virt_dev,
1989 unsigned int ep_index);
1990 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1991 unsigned int num_stream_ctxs,
1992 unsigned int num_streams,
1993 unsigned int max_packet, gfp_t flags);
1994 void xhci_free_stream_info(struct xhci_hcd *xhci,
1995 struct xhci_stream_info *stream_info);
1996 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1997 struct xhci_ep_ctx *ep_ctx,
1998 struct xhci_stream_info *stream_info);
1999 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2000 struct xhci_virt_ep *ep);
2001 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2002 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2003 struct xhci_ring *xhci_dma_to_transfer_ring(
2004 struct xhci_virt_ep *ep,
2006 struct xhci_ring *xhci_stream_id_to_ring(
2007 struct xhci_virt_device *dev,
2008 unsigned int ep_index,
2009 unsigned int stream_id);
2010 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2011 bool allocate_in_ctx, bool allocate_completion,
2013 void xhci_urb_free_priv(struct urb_priv *urb_priv);
2014 void xhci_free_command(struct xhci_hcd *xhci,
2015 struct xhci_command *command);
2017 /* xHCI host controller glue */
2018 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2019 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec);
2020 void xhci_quiesce(struct xhci_hcd *xhci);
2021 int xhci_halt(struct xhci_hcd *xhci);
2022 int xhci_start(struct xhci_hcd *xhci);
2023 int xhci_reset(struct xhci_hcd *xhci);
2024 int xhci_run(struct usb_hcd *hcd);
2025 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2026 void xhci_shutdown(struct usb_hcd *hcd);
2027 void xhci_init_driver(struct hc_driver *drv,
2028 const struct xhci_driver_overrides *over);
2029 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2031 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2032 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
2034 irqreturn_t xhci_irq(struct usb_hcd *hcd);
2035 irqreturn_t xhci_msi_irq(int irq, void *hcd);
2036 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2037 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2038 struct xhci_virt_device *virt_dev,
2039 struct usb_device *hdev,
2040 struct usb_tt *tt, gfp_t mem_flags);
2042 /* xHCI ring, segment, TRB, and TD functions */
2043 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2044 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2045 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2046 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2047 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2048 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2049 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2050 u32 trb_type, u32 slot_id);
2051 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2052 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2053 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2054 u32 field1, u32 field2, u32 field3, u32 field4);
2055 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2056 int slot_id, unsigned int ep_index, int suspend);
2057 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2058 int slot_id, unsigned int ep_index);
2059 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2060 int slot_id, unsigned int ep_index);
2061 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2062 int slot_id, unsigned int ep_index);
2063 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2064 struct urb *urb, int slot_id, unsigned int ep_index);
2065 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2066 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2067 bool command_must_succeed);
2068 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2069 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2070 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2071 int slot_id, unsigned int ep_index,
2072 enum xhci_ep_reset_type reset_type);
2073 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2075 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
2076 unsigned int slot_id, unsigned int ep_index,
2077 unsigned int stream_id, struct xhci_td *cur_td,
2078 struct xhci_dequeue_state *state);
2079 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
2080 unsigned int slot_id, unsigned int ep_index,
2081 struct xhci_dequeue_state *deq_state);
2082 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
2083 unsigned int stream_id, struct xhci_td *td);
2084 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
2085 void xhci_handle_command_timeout(struct work_struct *work);
2087 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2088 unsigned int ep_index, unsigned int stream_id);
2089 void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2091 /* xHCI roothub code */
2092 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
2093 int port_id, u32 link_state);
2094 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
2095 int port_id, u32 port_bit);
2096 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2097 char *buf, u16 wLength);
2098 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2099 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2100 void xhci_hc_died(struct xhci_hcd *xhci);
2103 int xhci_bus_suspend(struct usb_hcd *hcd);
2104 int xhci_bus_resume(struct usb_hcd *hcd);
2106 #define xhci_bus_suspend NULL
2107 #define xhci_bus_resume NULL
2108 #endif /* CONFIG_PM */
2110 u32 xhci_port_state_to_neutral(u32 state);
2111 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2113 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2116 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2117 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2118 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2120 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2121 unsigned int slot_id, unsigned int ep_index,
2122 unsigned int stream_id);
2123 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2126 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2127 xhci_get_endpoint_index(&urb->ep->desc),
2131 static inline char *xhci_slot_state_string(u32 state)
2134 case SLOT_STATE_ENABLED:
2135 return "enabled/disabled";
2136 case SLOT_STATE_DEFAULT:
2138 case SLOT_STATE_ADDRESSED:
2140 case SLOT_STATE_CONFIGURED:
2141 return "configured";
2147 static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2,
2150 static char str[256];
2151 int type = TRB_FIELD_TO_TYPE(field3);
2156 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2157 field1, field0, GET_INTR_TARGET(field2),
2158 xhci_trb_type_string(type),
2159 field3 & TRB_IOC ? 'I' : 'i',
2160 field3 & TRB_CHAIN ? 'C' : 'c',
2161 field3 & TRB_TC ? 'T' : 't',
2162 field3 & TRB_CYCLE ? 'C' : 'c');
2165 case TRB_COMPLETION:
2166 case TRB_PORT_STATUS:
2167 case TRB_BANDWIDTH_EVENT:
2171 case TRB_MFINDEX_WRAP:
2173 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2175 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2176 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2177 /* Macro decrements 1, maybe it shouldn't?!? */
2178 TRB_TO_EP_INDEX(field3) + 1,
2179 xhci_trb_type_string(type),
2180 field3 & EVENT_DATA ? 'E' : 'e',
2181 field3 & TRB_CYCLE ? 'C' : 'c');
2185 sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2187 (field0 & 0xff00) >> 8,
2188 (field0 & 0xff000000) >> 24,
2189 (field0 & 0xff0000) >> 16,
2190 (field1 & 0xff00) >> 8,
2192 (field1 & 0xff000000) >> 16 |
2193 (field1 & 0xff0000) >> 16,
2194 TRB_LEN(field2), GET_TD_SIZE(field2),
2195 GET_INTR_TARGET(field2),
2196 xhci_trb_type_string(type),
2197 field3 & TRB_IDT ? 'I' : 'i',
2198 field3 & TRB_IOC ? 'I' : 'i',
2199 field3 & TRB_CYCLE ? 'C' : 'c');
2202 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2203 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2204 GET_INTR_TARGET(field2),
2205 xhci_trb_type_string(type),
2206 field3 & TRB_IDT ? 'I' : 'i',
2207 field3 & TRB_IOC ? 'I' : 'i',
2208 field3 & TRB_CHAIN ? 'C' : 'c',
2209 field3 & TRB_NO_SNOOP ? 'S' : 's',
2210 field3 & TRB_ISP ? 'I' : 'i',
2211 field3 & TRB_ENT ? 'E' : 'e',
2212 field3 & TRB_CYCLE ? 'C' : 'c');
2215 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2216 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2217 GET_INTR_TARGET(field2),
2218 xhci_trb_type_string(type),
2219 field3 & TRB_IOC ? 'I' : 'i',
2220 field3 & TRB_CHAIN ? 'C' : 'c',
2221 field3 & TRB_ENT ? 'E' : 'e',
2222 field3 & TRB_CYCLE ? 'C' : 'c');
2226 case TRB_EVENT_DATA:
2229 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2230 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2231 GET_INTR_TARGET(field2),
2232 xhci_trb_type_string(type),
2233 field3 & TRB_BEI ? 'B' : 'b',
2234 field3 & TRB_IDT ? 'I' : 'i',
2235 field3 & TRB_IOC ? 'I' : 'i',
2236 field3 & TRB_CHAIN ? 'C' : 'c',
2237 field3 & TRB_NO_SNOOP ? 'S' : 's',
2238 field3 & TRB_ISP ? 'I' : 'i',
2239 field3 & TRB_ENT ? 'E' : 'e',
2240 field3 & TRB_CYCLE ? 'C' : 'c');
2244 case TRB_ENABLE_SLOT:
2247 xhci_trb_type_string(type),
2248 field3 & TRB_CYCLE ? 'C' : 'c');
2250 case TRB_DISABLE_SLOT:
2251 case TRB_NEG_BANDWIDTH:
2253 "%s: slot %d flags %c",
2254 xhci_trb_type_string(type),
2255 TRB_TO_SLOT_ID(field3),
2256 field3 & TRB_CYCLE ? 'C' : 'c');
2260 "%s: ctx %08x%08x slot %d flags %c:%c",
2261 xhci_trb_type_string(type),
2263 TRB_TO_SLOT_ID(field3),
2264 field3 & TRB_BSR ? 'B' : 'b',
2265 field3 & TRB_CYCLE ? 'C' : 'c');
2269 "%s: ctx %08x%08x slot %d flags %c:%c",
2270 xhci_trb_type_string(type),
2272 TRB_TO_SLOT_ID(field3),
2273 field3 & TRB_DC ? 'D' : 'd',
2274 field3 & TRB_CYCLE ? 'C' : 'c');
2276 case TRB_EVAL_CONTEXT:
2278 "%s: ctx %08x%08x slot %d flags %c",
2279 xhci_trb_type_string(type),
2281 TRB_TO_SLOT_ID(field3),
2282 field3 & TRB_CYCLE ? 'C' : 'c');
2286 "%s: ctx %08x%08x slot %d ep %d flags %c",
2287 xhci_trb_type_string(type),
2289 TRB_TO_SLOT_ID(field3),
2290 /* Macro decrements 1, maybe it shouldn't?!? */
2291 TRB_TO_EP_INDEX(field3) + 1,
2292 field3 & TRB_CYCLE ? 'C' : 'c');
2296 "%s: slot %d sp %d ep %d flags %c",
2297 xhci_trb_type_string(type),
2298 TRB_TO_SLOT_ID(field3),
2299 TRB_TO_SUSPEND_PORT(field3),
2300 /* Macro decrements 1, maybe it shouldn't?!? */
2301 TRB_TO_EP_INDEX(field3) + 1,
2302 field3 & TRB_CYCLE ? 'C' : 'c');
2306 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2307 xhci_trb_type_string(type),
2309 TRB_TO_STREAM_ID(field2),
2310 TRB_TO_SLOT_ID(field3),
2311 /* Macro decrements 1, maybe it shouldn't?!? */
2312 TRB_TO_EP_INDEX(field3) + 1,
2313 field3 & TRB_CYCLE ? 'C' : 'c');
2317 "%s: slot %d flags %c",
2318 xhci_trb_type_string(type),
2319 TRB_TO_SLOT_ID(field3),
2320 field3 & TRB_CYCLE ? 'C' : 'c');
2322 case TRB_FORCE_EVENT:
2324 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2325 xhci_trb_type_string(type),
2327 TRB_TO_VF_INTR_TARGET(field2),
2328 TRB_TO_VF_ID(field3),
2329 field3 & TRB_CYCLE ? 'C' : 'c');
2333 "%s: belt %d flags %c",
2334 xhci_trb_type_string(type),
2335 TRB_TO_BELT(field3),
2336 field3 & TRB_CYCLE ? 'C' : 'c');
2340 "%s: ctx %08x%08x slot %d speed %d flags %c",
2341 xhci_trb_type_string(type),
2343 TRB_TO_SLOT_ID(field3),
2344 TRB_TO_DEV_SPEED(field3),
2345 field3 & TRB_CYCLE ? 'C' : 'c');
2347 case TRB_FORCE_HEADER:
2349 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2350 xhci_trb_type_string(type),
2351 field2, field1, field0 & 0xffffffe0,
2352 TRB_TO_PACKET_TYPE(field0),
2353 TRB_TO_ROOTHUB_PORT(field3),
2354 field3 & TRB_CYCLE ? 'C' : 'c');
2358 "type '%s' -> raw %08x %08x %08x %08x",
2359 xhci_trb_type_string(type),
2360 field0, field1, field2, field3);
2366 static inline const char *xhci_decode_slot_context(u32 info, u32 info2,
2367 u32 tt_info, u32 state)
2369 static char str[1024];
2375 speed = info & DEV_SPEED;
2376 hub = info & DEV_HUB;
2377 mtt = info & DEV_MTT;
2379 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2380 info & ROUTE_STRING_MASK,
2395 case SLOT_SPEED_SSP:
2396 s = "super-speed plus";
2399 s = "UNKNOWN speed";
2401 mtt ? " multi-TT" : "",
2403 (info & LAST_CTX_MASK) >> 27,
2405 DEVINFO_TO_ROOT_HUB_PORT(info2),
2406 DEVINFO_TO_MAX_PORTS(info2));
2408 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2409 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2410 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2411 state & DEV_ADDR_MASK,
2412 xhci_slot_state_string(GET_SLOT_STATE(state)));
2418 static inline const char *xhci_portsc_link_state_string(u32 portsc)
2420 switch (portsc & PORT_PLS_MASK) {
2439 case XDEV_HOT_RESET:
2441 case XDEV_COMP_MODE:
2442 return "Compliance mode";
2443 case XDEV_TEST_MODE:
2453 static inline const char *xhci_decode_portsc(u32 portsc)
2455 static char str[256];
2458 ret = sprintf(str, "%s %s %s Link:%s ",
2459 portsc & PORT_POWER ? "Powered" : "Powered-off",
2460 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2461 portsc & PORT_PE ? "Enabled" : "Disabled",
2462 xhci_portsc_link_state_string(portsc));
2464 if (portsc & PORT_OC)
2465 ret += sprintf(str + ret, "OverCurrent ");
2466 if (portsc & PORT_RESET)
2467 ret += sprintf(str + ret, "In-Reset ");
2469 ret += sprintf(str + ret, "Change: ");
2470 if (portsc & PORT_CSC)
2471 ret += sprintf(str + ret, "CSC ");
2472 if (portsc & PORT_PEC)
2473 ret += sprintf(str + ret, "PEC ");
2474 if (portsc & PORT_WRC)
2475 ret += sprintf(str + ret, "WRC ");
2476 if (portsc & PORT_OCC)
2477 ret += sprintf(str + ret, "OCC ");
2478 if (portsc & PORT_RC)
2479 ret += sprintf(str + ret, "PRC ");
2480 if (portsc & PORT_PLC)
2481 ret += sprintf(str + ret, "PLC ");
2482 if (portsc & PORT_CEC)
2483 ret += sprintf(str + ret, "CEC ");
2484 if (portsc & PORT_CAS)
2485 ret += sprintf(str + ret, "CAS ");
2487 ret += sprintf(str + ret, "Wake: ");
2488 if (portsc & PORT_WKCONN_E)
2489 ret += sprintf(str + ret, "WCE ");
2490 if (portsc & PORT_WKDISC_E)
2491 ret += sprintf(str + ret, "WDE ");
2492 if (portsc & PORT_WKOC_E)
2493 ret += sprintf(str + ret, "WOE ");
2498 static inline const char *xhci_ep_state_string(u8 state)
2501 case EP_STATE_DISABLED:
2503 case EP_STATE_RUNNING:
2505 case EP_STATE_HALTED:
2507 case EP_STATE_STOPPED:
2509 case EP_STATE_ERROR:
2516 static inline const char *xhci_ep_type_string(u8 type)
2538 static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq,
2541 static char str[1024];
2559 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2560 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2562 ep_state = info & EP_STATE_MASK;
2563 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2564 interval = CTX_TO_EP_INTERVAL(info);
2565 mult = CTX_TO_EP_MULT(info) + 1;
2566 lsa = !!(info & EP_HAS_LSA);
2568 cerr = (info2 & (3 << 1)) >> 1;
2569 ep_type = CTX_TO_EP_TYPE(info2);
2570 hid = !!(info2 & (1 << 7));
2571 burst = CTX_TO_MAX_BURST(info2);
2572 maxp = MAX_PACKET_DECODED(info2);
2574 avg = EP_AVG_TRB_LENGTH(tx_info);
2576 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2577 xhci_ep_state_string(ep_state), mult,
2578 max_pstr, lsa ? "LSA " : "");
2580 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2581 (1 << interval) * 125, esit, cerr);
2583 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2584 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2587 ret += sprintf(str + ret, "avg trb len %d", avg);
2592 #endif /* __LINUX_XHCI_HCD_H */