2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/iopoll.h>
25 #include <linux/irq.h>
26 #include <linux/log2.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/slab.h>
30 #include <linux/dmi.h>
31 #include <linux/dma-mapping.h>
34 #include "xhci-trace.h"
37 #define DRIVER_AUTHOR "Sarah Sharp"
38 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
40 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
42 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
43 static int link_quirk;
44 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
45 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
47 static unsigned int quirks;
48 module_param(quirks, uint, S_IRUGO);
49 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
52 * xhci_handshake - spin reading hc until handshake completes or fails
53 * @ptr: address of hc register to be read
54 * @mask: bits to look at in result of read
55 * @done: value of those bits when handshake succeeds
56 * @usec: timeout in microseconds
58 * Returns negative errno, or zero on success
60 * Success happens when the "mask" bits have the specified value (hardware
61 * handshake done). There are two failure modes: "usec" have passed (major
62 * hardware flakeout), or the register reads as all-ones (hardware removed).
64 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
69 ret = readl_poll_timeout_atomic(ptr, result,
70 (result & mask) == done ||
73 if (result == U32_MAX) /* card removed */
80 * Disable interrupts and begin the xHCI halting process.
82 void xhci_quiesce(struct xhci_hcd *xhci)
89 halted = readl(&xhci->op_regs->status) & STS_HALT;
93 cmd = readl(&xhci->op_regs->command);
95 writel(cmd, &xhci->op_regs->command);
99 * Force HC into halt state.
101 * Disable any IRQs and clear the run/stop bit.
102 * HC will complete any current and actively pipelined transactions, and
103 * should halt within 16 ms of the run/stop bit being cleared.
104 * Read HC Halted bit in the status register to see when the HC is finished.
106 int xhci_halt(struct xhci_hcd *xhci)
109 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
112 ret = xhci_handshake(&xhci->op_regs->status,
113 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
115 xhci->xhc_state |= XHCI_STATE_HALTED;
116 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
118 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
124 * Set the run bit and wait for the host to be running.
126 static int xhci_start(struct xhci_hcd *xhci)
131 temp = readl(&xhci->op_regs->command);
133 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
135 writel(temp, &xhci->op_regs->command);
138 * Wait for the HCHalted Status bit to be 0 to indicate the host is
141 ret = xhci_handshake(&xhci->op_regs->status,
142 STS_HALT, 0, XHCI_MAX_HALT_USEC);
143 if (ret == -ETIMEDOUT)
144 xhci_err(xhci, "Host took too long to start, "
145 "waited %u microseconds.\n",
148 /* clear state flags. Including dying, halted or removing */
157 * This resets pipelines, timers, counters, state machines, etc.
158 * Transactions will be terminated immediately, and operational registers
159 * will be set to their defaults.
161 int xhci_reset(struct xhci_hcd *xhci)
167 state = readl(&xhci->op_regs->status);
168 if ((state & STS_HALT) == 0) {
169 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
173 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
174 command = readl(&xhci->op_regs->command);
175 command |= CMD_RESET;
176 writel(command, &xhci->op_regs->command);
178 /* Existing Intel xHCI controllers require a delay of 1 mS,
179 * after setting the CMD_RESET bit, and before accessing any
180 * HC registers. This allows the HC to complete the
181 * reset operation and be ready for HC register access.
182 * Without this delay, the subsequent HC register access,
183 * may result in a system hang very rarely.
185 if (xhci->quirks & XHCI_INTEL_HOST)
188 ret = xhci_handshake(&xhci->op_regs->command,
189 CMD_RESET, 0, 10 * 1000 * 1000);
193 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
194 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
196 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
197 "Wait for controller to be ready for doorbell rings");
199 * xHCI cannot write to any doorbells or operational registers other
200 * than status until the "Controller Not Ready" flag is cleared.
202 ret = xhci_handshake(&xhci->op_regs->status,
203 STS_CNR, 0, 10 * 1000 * 1000);
205 for (i = 0; i < 2; ++i) {
206 xhci->bus_state[i].port_c_suspend = 0;
207 xhci->bus_state[i].suspended_ports = 0;
208 xhci->bus_state[i].resuming_ports = 0;
215 static int xhci_free_msi(struct xhci_hcd *xhci)
219 if (!xhci->msix_entries)
222 for (i = 0; i < xhci->msix_count; i++)
223 if (xhci->msix_entries[i].vector)
224 free_irq(xhci->msix_entries[i].vector,
232 static int xhci_setup_msi(struct xhci_hcd *xhci)
235 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
237 ret = pci_enable_msi(pdev);
239 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
240 "failed to allocate MSI entry");
244 ret = request_irq(pdev->irq, xhci_msi_irq,
245 0, "xhci_hcd", xhci_to_hcd(xhci));
247 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
248 "disable MSI interrupt");
249 pci_disable_msi(pdev);
257 * free all IRQs request
259 static void xhci_free_irq(struct xhci_hcd *xhci)
261 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
264 /* return if using legacy interrupt */
265 if (xhci_to_hcd(xhci)->irq > 0)
268 ret = xhci_free_msi(xhci);
272 free_irq(pdev->irq, xhci_to_hcd(xhci));
280 static int xhci_setup_msix(struct xhci_hcd *xhci)
283 struct usb_hcd *hcd = xhci_to_hcd(xhci);
284 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
287 * calculate number of msi-x vectors supported.
288 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
289 * with max number of interrupters based on the xhci HCSPARAMS1.
290 * - num_online_cpus: maximum msi-x vectors per CPUs core.
291 * Add additional 1 vector to ensure always available interrupt.
293 xhci->msix_count = min(num_online_cpus() + 1,
294 HCS_MAX_INTRS(xhci->hcs_params1));
297 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
299 if (!xhci->msix_entries)
302 for (i = 0; i < xhci->msix_count; i++) {
303 xhci->msix_entries[i].entry = i;
304 xhci->msix_entries[i].vector = 0;
307 ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count);
309 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
310 "Failed to enable MSI-X");
314 for (i = 0; i < xhci->msix_count; i++) {
315 ret = request_irq(xhci->msix_entries[i].vector,
317 0, "xhci_hcd", xhci_to_hcd(xhci));
322 hcd->msix_enabled = 1;
326 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
328 pci_disable_msix(pdev);
330 kfree(xhci->msix_entries);
331 xhci->msix_entries = NULL;
335 /* Free any IRQs and disable MSI-X */
336 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
338 struct usb_hcd *hcd = xhci_to_hcd(xhci);
339 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
341 if (xhci->quirks & XHCI_PLAT)
346 if (xhci->msix_entries) {
347 pci_disable_msix(pdev);
348 kfree(xhci->msix_entries);
349 xhci->msix_entries = NULL;
351 pci_disable_msi(pdev);
354 hcd->msix_enabled = 0;
358 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
362 if (xhci->msix_entries) {
363 for (i = 0; i < xhci->msix_count; i++)
364 synchronize_irq(xhci->msix_entries[i].vector);
368 static int xhci_try_enable_msi(struct usb_hcd *hcd)
370 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
371 struct pci_dev *pdev;
374 /* The xhci platform device has set up IRQs through usb_add_hcd. */
375 if (xhci->quirks & XHCI_PLAT)
378 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
380 * Some Fresco Logic host controllers advertise MSI, but fail to
381 * generate interrupts. Don't even try to enable MSI.
383 if (xhci->quirks & XHCI_BROKEN_MSI)
386 /* unregister the legacy interrupt */
388 free_irq(hcd->irq, hcd);
391 ret = xhci_setup_msix(xhci);
393 /* fall back to msi*/
394 ret = xhci_setup_msi(xhci);
397 /* hcd->irq is 0, we have MSI */
401 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
406 if (!strlen(hcd->irq_descr))
407 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
408 hcd->driver->description, hcd->self.busnum);
410 /* fall back to legacy interrupt*/
411 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
412 hcd->irq_descr, hcd);
414 xhci_err(xhci, "request interrupt %d failed\n",
418 hcd->irq = pdev->irq;
424 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
429 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
433 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
439 static void compliance_mode_recovery(unsigned long arg)
441 struct xhci_hcd *xhci;
446 xhci = (struct xhci_hcd *)arg;
448 for (i = 0; i < xhci->num_usb3_ports; i++) {
449 temp = readl(xhci->usb3_ports[i]);
450 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
452 * Compliance Mode Detected. Letting USB Core
453 * handle the Warm Reset
455 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
456 "Compliance mode detected->port %d",
458 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
459 "Attempting compliance mode recovery");
460 hcd = xhci->shared_hcd;
462 if (hcd->state == HC_STATE_SUSPENDED)
463 usb_hcd_resume_root_hub(hcd);
465 usb_hcd_poll_rh_status(hcd);
469 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
470 mod_timer(&xhci->comp_mode_recovery_timer,
471 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
475 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
476 * that causes ports behind that hardware to enter compliance mode sometimes.
477 * The quirk creates a timer that polls every 2 seconds the link state of
478 * each host controller's port and recovers it by issuing a Warm reset
479 * if Compliance mode is detected, otherwise the port will become "dead" (no
480 * device connections or disconnections will be detected anymore). Becasue no
481 * status event is generated when entering compliance mode (per xhci spec),
482 * this quirk is needed on systems that have the failing hardware installed.
484 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
486 xhci->port_status_u0 = 0;
487 setup_timer(&xhci->comp_mode_recovery_timer,
488 compliance_mode_recovery, (unsigned long)xhci);
489 xhci->comp_mode_recovery_timer.expires = jiffies +
490 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
492 add_timer(&xhci->comp_mode_recovery_timer);
493 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
494 "Compliance mode recovery timer initialized");
498 * This function identifies the systems that have installed the SN65LVPE502CP
499 * USB3.0 re-driver and that need the Compliance Mode Quirk.
501 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
503 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
505 const char *dmi_product_name, *dmi_sys_vendor;
507 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
508 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
509 if (!dmi_product_name || !dmi_sys_vendor)
512 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
515 if (strstr(dmi_product_name, "Z420") ||
516 strstr(dmi_product_name, "Z620") ||
517 strstr(dmi_product_name, "Z820") ||
518 strstr(dmi_product_name, "Z1 Workstation"))
524 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
526 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
531 * Initialize memory for HCD and xHC (one-time init).
533 * Program the PAGESIZE register, initialize the device context array, create
534 * device contexts (?), set up a command ring segment (or two?), create event
535 * ring (one for now).
537 int xhci_init(struct usb_hcd *hcd)
539 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
542 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
543 spin_lock_init(&xhci->lock);
544 if (xhci->hci_version == 0x95 && link_quirk) {
545 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
546 "QUIRK: Not clearing Link TRB chain bits.");
547 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
549 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
550 "xHCI doesn't need link TRB QUIRK");
552 retval = xhci_mem_init(xhci, GFP_KERNEL);
553 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
555 /* Initializing Compliance Mode Recovery Data If Needed */
556 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
557 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
558 compliance_mode_recovery_timer_init(xhci);
564 /*-------------------------------------------------------------------------*/
567 static int xhci_run_finished(struct xhci_hcd *xhci)
569 if (xhci_start(xhci)) {
573 xhci->shared_hcd->state = HC_STATE_RUNNING;
574 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
576 if (xhci->quirks & XHCI_NEC_HOST)
577 xhci_ring_cmd_db(xhci);
579 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
580 "Finished xhci_run for USB3 roothub");
585 * Start the HC after it was halted.
587 * This function is called by the USB core when the HC driver is added.
588 * Its opposite is xhci_stop().
590 * xhci_init() must be called once before this function can be called.
591 * Reset the HC, enable device slot contexts, program DCBAAP, and
592 * set command ring pointer and event ring pointer.
594 * Setup MSI-X vectors and enable interrupts.
596 int xhci_run(struct usb_hcd *hcd)
601 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
603 /* Start the xHCI host controller running only after the USB 2.0 roothub
607 hcd->uses_new_polling = 1;
608 if (!usb_hcd_is_primary_hcd(hcd))
609 return xhci_run_finished(xhci);
611 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
613 ret = xhci_try_enable_msi(hcd);
617 xhci_dbg(xhci, "Command ring memory map follows:\n");
618 xhci_debug_ring(xhci, xhci->cmd_ring);
619 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
620 xhci_dbg_cmd_ptrs(xhci);
622 xhci_dbg(xhci, "ERST memory map follows:\n");
623 xhci_dbg_erst(xhci, &xhci->erst);
624 xhci_dbg(xhci, "Event ring:\n");
625 xhci_debug_ring(xhci, xhci->event_ring);
626 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
627 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
628 temp_64 &= ~ERST_PTR_MASK;
629 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
630 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
632 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
633 "// Set the interrupt modulation register");
634 temp = readl(&xhci->ir_set->irq_control);
635 temp &= ~ER_IRQ_INTERVAL_MASK;
637 * the increment interval is 8 times as much as that defined
638 * in xHCI spec on MTK's controller
640 temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
641 writel(temp, &xhci->ir_set->irq_control);
643 /* Set the HCD state before we enable the irqs */
644 temp = readl(&xhci->op_regs->command);
646 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
647 "// Enable interrupts, cmd = 0x%x.", temp);
648 writel(temp, &xhci->op_regs->command);
650 temp = readl(&xhci->ir_set->irq_pending);
651 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
652 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
653 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
654 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
655 xhci_print_ir_set(xhci, 0);
657 if (xhci->quirks & XHCI_NEC_HOST) {
658 struct xhci_command *command;
659 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
662 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
663 TRB_TYPE(TRB_NEC_GET_FW));
665 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
666 "Finished xhci_run for USB2 roothub");
669 EXPORT_SYMBOL_GPL(xhci_run);
674 * This function is called by the USB core when the HC driver is removed.
675 * Its opposite is xhci_run().
677 * Disable device contexts, disable IRQs, and quiesce the HC.
678 * Reset the HC, finish any completed transactions, and cleanup memory.
680 void xhci_stop(struct usb_hcd *hcd)
683 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
685 mutex_lock(&xhci->mutex);
687 if (!(xhci->xhc_state & XHCI_STATE_HALTED)) {
688 spin_lock_irq(&xhci->lock);
690 xhci->xhc_state |= XHCI_STATE_HALTED;
691 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
695 spin_unlock_irq(&xhci->lock);
698 if (!usb_hcd_is_primary_hcd(hcd)) {
699 mutex_unlock(&xhci->mutex);
703 xhci_cleanup_msix(xhci);
705 /* Deleting Compliance Mode Recovery Timer */
706 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
707 (!(xhci_all_ports_seen_u0(xhci)))) {
708 del_timer_sync(&xhci->comp_mode_recovery_timer);
709 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
710 "%s: compliance mode recovery timer deleted",
714 if (xhci->quirks & XHCI_AMD_PLL_FIX)
717 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
718 "// Disabling event ring interrupts");
719 temp = readl(&xhci->op_regs->status);
720 writel(temp & ~STS_EINT, &xhci->op_regs->status);
721 temp = readl(&xhci->ir_set->irq_pending);
722 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
723 xhci_print_ir_set(xhci, 0);
725 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
726 xhci_mem_cleanup(xhci);
727 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
728 "xhci_stop completed - status = %x",
729 readl(&xhci->op_regs->status));
730 mutex_unlock(&xhci->mutex);
734 * Shutdown HC (not bus-specific)
736 * This is called when the machine is rebooting or halting. We assume that the
737 * machine will be powered off, and the HC's internal state will be reset.
738 * Don't bother to free memory.
740 * This will only ever be called with the main usb_hcd (the USB3 roothub).
742 void xhci_shutdown(struct usb_hcd *hcd)
744 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
746 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
747 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
749 /* Don't poll the roothubs after shutdown. */
750 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
751 __func__, hcd->self.busnum);
752 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
753 del_timer_sync(&hcd->rh_timer);
755 if (xhci->shared_hcd) {
756 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
757 del_timer_sync(&xhci->shared_hcd->rh_timer);
760 spin_lock_irq(&xhci->lock);
762 /* Workaround for spurious wakeups at shutdown with HSW */
763 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
765 spin_unlock_irq(&xhci->lock);
767 xhci_cleanup_msix(xhci);
769 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
770 "xhci_shutdown completed - status = %x",
771 readl(&xhci->op_regs->status));
773 EXPORT_SYMBOL_GPL(xhci_shutdown);
776 static void xhci_save_registers(struct xhci_hcd *xhci)
778 xhci->s3.command = readl(&xhci->op_regs->command);
779 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
780 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
781 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
782 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
783 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
784 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
785 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
786 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
789 static void xhci_restore_registers(struct xhci_hcd *xhci)
791 writel(xhci->s3.command, &xhci->op_regs->command);
792 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
793 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
794 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
795 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
796 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
797 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
798 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
799 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
802 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
806 /* step 2: initialize command ring buffer */
807 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
808 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
809 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
810 xhci->cmd_ring->dequeue) &
811 (u64) ~CMD_RING_RSVD_BITS) |
812 xhci->cmd_ring->cycle_state;
813 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
814 "// Setting command ring address to 0x%llx",
815 (long unsigned long) val_64);
816 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
820 * The whole command ring must be cleared to zero when we suspend the host.
822 * The host doesn't save the command ring pointer in the suspend well, so we
823 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
824 * aligned, because of the reserved bits in the command ring dequeue pointer
825 * register. Therefore, we can't just set the dequeue pointer back in the
826 * middle of the ring (TRBs are 16-byte aligned).
828 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
830 struct xhci_ring *ring;
831 struct xhci_segment *seg;
833 ring = xhci->cmd_ring;
837 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
838 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
839 cpu_to_le32(~TRB_CYCLE);
841 } while (seg != ring->deq_seg);
843 /* Reset the software enqueue and dequeue pointers */
844 ring->deq_seg = ring->first_seg;
845 ring->dequeue = ring->first_seg->trbs;
846 ring->enq_seg = ring->deq_seg;
847 ring->enqueue = ring->dequeue;
849 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
851 * Ring is now zeroed, so the HW should look for change of ownership
852 * when the cycle bit is set to 1.
854 ring->cycle_state = 1;
857 * Reset the hardware dequeue pointer.
858 * Yes, this will need to be re-written after resume, but we're paranoid
859 * and want to make sure the hardware doesn't access bogus memory
860 * because, say, the BIOS or an SMI started the host without changing
861 * the command ring pointers.
863 xhci_set_cmd_ring_deq(xhci);
866 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
869 __le32 __iomem **port_array;
873 spin_lock_irqsave(&xhci->lock, flags);
875 /* disble usb3 ports Wake bits*/
876 port_index = xhci->num_usb3_ports;
877 port_array = xhci->usb3_ports;
878 while (port_index--) {
879 t1 = readl(port_array[port_index]);
880 t1 = xhci_port_state_to_neutral(t1);
881 t2 = t1 & ~PORT_WAKE_BITS;
883 writel(t2, port_array[port_index]);
886 /* disble usb2 ports Wake bits*/
887 port_index = xhci->num_usb2_ports;
888 port_array = xhci->usb2_ports;
889 while (port_index--) {
890 t1 = readl(port_array[port_index]);
891 t1 = xhci_port_state_to_neutral(t1);
892 t2 = t1 & ~PORT_WAKE_BITS;
894 writel(t2, port_array[port_index]);
897 spin_unlock_irqrestore(&xhci->lock, flags);
900 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
902 __le32 __iomem **port_array;
907 status = readl(&xhci->op_regs->status);
908 if (status & STS_EINT)
911 * Checking STS_EINT is not enough as there is a lag between a change
912 * bit being set and the Port Status Change Event that it generated
913 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
916 port_index = xhci->num_usb2_ports;
917 port_array = xhci->usb2_ports;
918 while (port_index--) {
919 portsc = readl(port_array[port_index]);
920 if (portsc & PORT_CHANGE_MASK ||
921 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
924 port_index = xhci->num_usb3_ports;
925 port_array = xhci->usb3_ports;
926 while (port_index--) {
927 portsc = readl(port_array[port_index]);
928 if (portsc & PORT_CHANGE_MASK ||
929 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
936 * Stop HC (not bus-specific)
938 * This is called when the machine transition into S3/S4 mode.
941 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
944 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
945 struct usb_hcd *hcd = xhci_to_hcd(xhci);
951 if (hcd->state != HC_STATE_SUSPENDED ||
952 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
955 /* Clear root port wake on bits if wakeup not allowed. */
957 xhci_disable_port_wake_on_bits(xhci);
959 /* Don't poll the roothubs on bus suspend. */
960 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
961 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
962 del_timer_sync(&hcd->rh_timer);
963 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
964 del_timer_sync(&xhci->shared_hcd->rh_timer);
966 spin_lock_irq(&xhci->lock);
967 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
968 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
969 /* step 1: stop endpoint */
970 /* skipped assuming that port suspend has done */
972 /* step 2: clear Run/Stop bit */
973 command = readl(&xhci->op_regs->command);
975 writel(command, &xhci->op_regs->command);
977 /* Some chips from Fresco Logic need an extraordinary delay */
978 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
980 if (xhci_handshake(&xhci->op_regs->status,
981 STS_HALT, STS_HALT, delay)) {
982 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
983 spin_unlock_irq(&xhci->lock);
986 xhci_clear_command_ring(xhci);
988 /* step 3: save registers */
989 xhci_save_registers(xhci);
991 /* step 4: set CSS flag */
992 command = readl(&xhci->op_regs->command);
994 writel(command, &xhci->op_regs->command);
995 if (xhci_handshake(&xhci->op_regs->status,
996 STS_SAVE, 0, 20 * 1000)) {
997 xhci_warn(xhci, "WARN: xHC save state timeout\n");
998 spin_unlock_irq(&xhci->lock);
1001 spin_unlock_irq(&xhci->lock);
1004 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1005 * is about to be suspended.
1007 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1008 (!(xhci_all_ports_seen_u0(xhci)))) {
1009 del_timer_sync(&xhci->comp_mode_recovery_timer);
1010 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1011 "%s: compliance mode recovery timer deleted",
1015 /* step 5: remove core well power */
1016 /* synchronize irq when using MSI-X */
1017 xhci_msix_sync_irqs(xhci);
1021 EXPORT_SYMBOL_GPL(xhci_suspend);
1024 * start xHC (not bus-specific)
1026 * This is called when the machine transition from S3/S4 mode.
1029 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1031 u32 command, temp = 0;
1032 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1033 struct usb_hcd *secondary_hcd;
1035 bool comp_timer_running = false;
1036 bool pending_portevent = false;
1041 /* Wait a bit if either of the roothubs need to settle from the
1042 * transition into bus suspend.
1044 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1045 time_before(jiffies,
1046 xhci->bus_state[1].next_statechange))
1049 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1050 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1052 spin_lock_irq(&xhci->lock);
1053 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1058 * Some controllers might lose power during suspend, so wait
1059 * for controller not ready bit to clear, just as in xHC init.
1061 retval = xhci_handshake(&xhci->op_regs->status,
1062 STS_CNR, 0, 10 * 1000 * 1000);
1064 xhci_warn(xhci, "Controller not ready at resume %d\n",
1066 spin_unlock_irq(&xhci->lock);
1069 /* step 1: restore register */
1070 xhci_restore_registers(xhci);
1071 /* step 2: initialize command ring buffer */
1072 xhci_set_cmd_ring_deq(xhci);
1073 /* step 3: restore state and start state*/
1074 /* step 3: set CRS flag */
1075 command = readl(&xhci->op_regs->command);
1077 writel(command, &xhci->op_regs->command);
1079 * Some controllers take up to 55+ ms to complete the controller
1080 * restore so setting the timeout to 100ms. Xhci specification
1081 * doesn't mention any timeout value.
1083 if (xhci_handshake(&xhci->op_regs->status,
1084 STS_RESTORE, 0, 100 * 1000)) {
1085 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1086 spin_unlock_irq(&xhci->lock);
1089 temp = readl(&xhci->op_regs->status);
1092 /* If restore operation fails, re-initialize the HC during resume */
1093 if ((temp & STS_SRE) || hibernated) {
1095 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1096 !(xhci_all_ports_seen_u0(xhci))) {
1097 del_timer_sync(&xhci->comp_mode_recovery_timer);
1098 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1099 "Compliance Mode Recovery Timer deleted!");
1102 /* Let the USB core know _both_ roothubs lost power. */
1103 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1104 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1106 xhci_dbg(xhci, "Stop HCD\n");
1109 spin_unlock_irq(&xhci->lock);
1110 xhci_cleanup_msix(xhci);
1112 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1113 temp = readl(&xhci->op_regs->status);
1114 writel(temp & ~STS_EINT, &xhci->op_regs->status);
1115 temp = readl(&xhci->ir_set->irq_pending);
1116 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1117 xhci_print_ir_set(xhci, 0);
1119 xhci_dbg(xhci, "cleaning up memory\n");
1120 xhci_mem_cleanup(xhci);
1121 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1122 readl(&xhci->op_regs->status));
1124 /* USB core calls the PCI reinit and start functions twice:
1125 * first with the primary HCD, and then with the secondary HCD.
1126 * If we don't do the same, the host will never be started.
1128 if (!usb_hcd_is_primary_hcd(hcd))
1129 secondary_hcd = hcd;
1131 secondary_hcd = xhci->shared_hcd;
1133 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1134 retval = xhci_init(hcd->primary_hcd);
1137 comp_timer_running = true;
1139 xhci_dbg(xhci, "Start the primary HCD\n");
1140 retval = xhci_run(hcd->primary_hcd);
1142 xhci_dbg(xhci, "Start the secondary HCD\n");
1143 retval = xhci_run(secondary_hcd);
1145 hcd->state = HC_STATE_SUSPENDED;
1146 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1150 /* step 4: set Run/Stop bit */
1151 command = readl(&xhci->op_regs->command);
1153 writel(command, &xhci->op_regs->command);
1154 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1157 /* step 5: walk topology and initialize portsc,
1158 * portpmsc and portli
1160 /* this is done in bus_resume */
1162 /* step 6: restart each of the previously
1163 * Running endpoints by ringing their doorbells
1166 spin_unlock_irq(&xhci->lock);
1171 * Resume roothubs only if there are pending events.
1172 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1173 * the first wake signalling failed, give it that chance.
1175 pending_portevent = xhci_pending_portevent(xhci);
1176 if (!pending_portevent) {
1178 pending_portevent = xhci_pending_portevent(xhci);
1181 if (pending_portevent) {
1182 usb_hcd_resume_root_hub(xhci->shared_hcd);
1183 usb_hcd_resume_root_hub(hcd);
1187 * If system is subject to the Quirk, Compliance Mode Timer needs to
1188 * be re-initialized Always after a system resume. Ports are subject
1189 * to suffer the Compliance Mode issue again. It doesn't matter if
1190 * ports have entered previously to U0 before system's suspension.
1192 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1193 compliance_mode_recovery_timer_init(xhci);
1195 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1196 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1198 /* Re-enable port polling. */
1199 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1200 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1201 usb_hcd_poll_rh_status(xhci->shared_hcd);
1202 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1203 usb_hcd_poll_rh_status(hcd);
1207 EXPORT_SYMBOL_GPL(xhci_resume);
1208 #endif /* CONFIG_PM */
1210 /*-------------------------------------------------------------------------*/
1213 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1214 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1215 * value to right shift 1 for the bitmask.
1217 * Index = (epnum * 2) + direction - 1,
1218 * where direction = 0 for OUT, 1 for IN.
1219 * For control endpoints, the IN index is used (OUT index is unused), so
1220 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1222 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1225 if (usb_endpoint_xfer_control(desc))
1226 index = (unsigned int) (usb_endpoint_num(desc)*2);
1228 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1229 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1233 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1234 * address from the XHCI endpoint index.
1236 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1238 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1239 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1240 return direction | number;
1243 /* Find the flag for this endpoint (for use in the control context). Use the
1244 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1247 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1249 return 1 << (xhci_get_endpoint_index(desc) + 1);
1252 /* Find the flag for this endpoint (for use in the control context). Use the
1253 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1256 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1258 return 1 << (ep_index + 1);
1261 /* Compute the last valid endpoint context index. Basically, this is the
1262 * endpoint index plus one. For slot contexts with more than valid endpoint,
1263 * we find the most significant bit set in the added contexts flags.
1264 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1265 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1267 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1269 return fls(added_ctxs) - 1;
1272 /* Returns 1 if the arguments are OK;
1273 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1275 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1276 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1278 struct xhci_hcd *xhci;
1279 struct xhci_virt_device *virt_dev;
1281 if (!hcd || (check_ep && !ep) || !udev) {
1282 pr_debug("xHCI %s called with invalid args\n", func);
1285 if (!udev->parent) {
1286 pr_debug("xHCI %s called for root hub\n", func);
1290 xhci = hcd_to_xhci(hcd);
1291 if (check_virt_dev) {
1292 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1293 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1298 virt_dev = xhci->devs[udev->slot_id];
1299 if (virt_dev->udev != udev) {
1300 xhci_dbg(xhci, "xHCI %s called with udev and "
1301 "virt_dev does not match\n", func);
1306 if (xhci->xhc_state & XHCI_STATE_HALTED)
1312 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1313 struct usb_device *udev, struct xhci_command *command,
1314 bool ctx_change, bool must_succeed);
1317 * Full speed devices may have a max packet size greater than 8 bytes, but the
1318 * USB core doesn't know that until it reads the first 8 bytes of the
1319 * descriptor. If the usb_device's max packet size changes after that point,
1320 * we need to issue an evaluate context command and wait on it.
1322 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1323 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1325 struct xhci_container_ctx *out_ctx;
1326 struct xhci_input_control_ctx *ctrl_ctx;
1327 struct xhci_ep_ctx *ep_ctx;
1328 struct xhci_command *command;
1329 int max_packet_size;
1330 int hw_max_packet_size;
1333 out_ctx = xhci->devs[slot_id]->out_ctx;
1334 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1335 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1336 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1337 if (hw_max_packet_size != max_packet_size) {
1338 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1339 "Max Packet Size for ep 0 changed.");
1340 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1341 "Max packet size in usb_device = %d",
1343 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1344 "Max packet size in xHCI HW = %d",
1345 hw_max_packet_size);
1346 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1347 "Issuing evaluate context command.");
1349 /* Set up the input context flags for the command */
1350 /* FIXME: This won't work if a non-default control endpoint
1351 * changes max packet sizes.
1354 command = xhci_alloc_command(xhci, false, true, mem_flags);
1358 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1359 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1361 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1364 goto command_cleanup;
1366 /* Set up the modified control endpoint 0 */
1367 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1368 xhci->devs[slot_id]->out_ctx, ep_index);
1370 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1371 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1372 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1373 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1375 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1376 ctrl_ctx->drop_flags = 0;
1378 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1379 xhci_dbg_ctx(xhci, command->in_ctx, ep_index);
1380 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1381 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1383 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1386 /* Clean up the input context for later use by bandwidth
1389 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1391 kfree(command->completion);
1398 * non-error returns are a promise to giveback() the urb later
1399 * we drop ownership so next owner (or urb unlink) can get it
1401 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1403 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1404 struct xhci_td *buffer;
1405 unsigned long flags;
1407 unsigned int slot_id, ep_index;
1408 struct urb_priv *urb_priv;
1413 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1414 true, true, __func__);
1416 return ret ? ret : -EINVAL;
1418 slot_id = urb->dev->slot_id;
1419 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1421 if (!HCD_HW_ACCESSIBLE(hcd)) {
1422 if (!in_interrupt())
1423 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1428 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1429 size = urb->number_of_packets;
1430 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1431 urb->transfer_buffer_length > 0 &&
1432 urb->transfer_flags & URB_ZERO_PACKET &&
1433 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1438 urb_priv = kzalloc(sizeof(struct urb_priv) +
1439 size * sizeof(struct xhci_td *), mem_flags);
1443 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1449 for (i = 0; i < size; i++) {
1450 urb_priv->td[i] = buffer;
1454 urb_priv->length = size;
1455 urb_priv->td_cnt = 0;
1456 urb->hcpriv = urb_priv;
1458 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1459 /* Check to see if the max packet size for the default control
1460 * endpoint changed during FS device enumeration
1462 if (urb->dev->speed == USB_SPEED_FULL) {
1463 ret = xhci_check_maxpacket(xhci, slot_id,
1464 ep_index, urb, mem_flags);
1466 xhci_urb_free_priv(urb_priv);
1472 /* We have a spinlock and interrupts disabled, so we must pass
1473 * atomic context to this function, which may allocate memory.
1475 spin_lock_irqsave(&xhci->lock, flags);
1476 if (xhci->xhc_state & XHCI_STATE_DYING)
1478 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1482 spin_unlock_irqrestore(&xhci->lock, flags);
1483 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1484 spin_lock_irqsave(&xhci->lock, flags);
1485 if (xhci->xhc_state & XHCI_STATE_DYING)
1487 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1488 EP_GETTING_STREAMS) {
1489 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1490 "is transitioning to using streams.\n");
1492 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1493 EP_GETTING_NO_STREAMS) {
1494 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1495 "is transitioning to "
1496 "not having streams.\n");
1499 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1504 spin_unlock_irqrestore(&xhci->lock, flags);
1505 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1506 spin_lock_irqsave(&xhci->lock, flags);
1507 if (xhci->xhc_state & XHCI_STATE_DYING)
1509 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1513 spin_unlock_irqrestore(&xhci->lock, flags);
1515 spin_lock_irqsave(&xhci->lock, flags);
1516 if (xhci->xhc_state & XHCI_STATE_DYING)
1518 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1522 spin_unlock_irqrestore(&xhci->lock, flags);
1527 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1528 "non-responsive xHCI host.\n",
1529 urb->ep->desc.bEndpointAddress, urb);
1532 xhci_urb_free_priv(urb_priv);
1534 spin_unlock_irqrestore(&xhci->lock, flags);
1539 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1540 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1541 * should pick up where it left off in the TD, unless a Set Transfer Ring
1542 * Dequeue Pointer is issued.
1544 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1545 * the ring. Since the ring is a contiguous structure, they can't be physically
1546 * removed. Instead, there are two options:
1548 * 1) If the HC is in the middle of processing the URB to be canceled, we
1549 * simply move the ring's dequeue pointer past those TRBs using the Set
1550 * Transfer Ring Dequeue Pointer command. This will be the common case,
1551 * when drivers timeout on the last submitted URB and attempt to cancel.
1553 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1554 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1555 * HC will need to invalidate the any TRBs it has cached after the stop
1556 * endpoint command, as noted in the xHCI 0.95 errata.
1558 * 3) The TD may have completed by the time the Stop Endpoint Command
1559 * completes, so software needs to handle that case too.
1561 * This function should protect against the TD enqueueing code ringing the
1562 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1563 * It also needs to account for multiple cancellations on happening at the same
1564 * time for the same endpoint.
1566 * Note that this function can be called in any context, or so says
1567 * usb_hcd_unlink_urb()
1569 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1571 unsigned long flags;
1574 struct xhci_hcd *xhci;
1575 struct urb_priv *urb_priv;
1577 unsigned int ep_index;
1578 struct xhci_ring *ep_ring;
1579 struct xhci_virt_ep *ep;
1580 struct xhci_command *command;
1582 xhci = hcd_to_xhci(hcd);
1583 spin_lock_irqsave(&xhci->lock, flags);
1584 /* Make sure the URB hasn't completed or been unlinked already */
1585 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1586 if (ret || !urb->hcpriv)
1588 temp = readl(&xhci->op_regs->status);
1589 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1590 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1591 "HW died, freeing TD.");
1592 urb_priv = urb->hcpriv;
1593 for (i = urb_priv->td_cnt;
1594 i < urb_priv->length && xhci->devs[urb->dev->slot_id];
1596 td = urb_priv->td[i];
1597 if (!list_empty(&td->td_list))
1598 list_del_init(&td->td_list);
1599 if (!list_empty(&td->cancelled_td_list))
1600 list_del_init(&td->cancelled_td_list);
1603 usb_hcd_unlink_urb_from_ep(hcd, urb);
1604 spin_unlock_irqrestore(&xhci->lock, flags);
1605 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1606 xhci_urb_free_priv(urb_priv);
1610 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1611 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1612 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1618 urb_priv = urb->hcpriv;
1619 i = urb_priv->td_cnt;
1620 if (i < urb_priv->length)
1621 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1622 "Cancel URB %p, dev %s, ep 0x%x, "
1623 "starting at offset 0x%llx",
1624 urb, urb->dev->devpath,
1625 urb->ep->desc.bEndpointAddress,
1626 (unsigned long long) xhci_trb_virt_to_dma(
1627 urb_priv->td[i]->start_seg,
1628 urb_priv->td[i]->first_trb));
1630 for (; i < urb_priv->length; i++) {
1631 td = urb_priv->td[i];
1632 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1635 /* Queue a stop endpoint command, but only if this is
1636 * the first cancellation to be handled.
1638 if (!(ep->ep_state & EP_HALT_PENDING)) {
1639 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1644 ep->ep_state |= EP_HALT_PENDING;
1645 ep->stop_cmds_pending++;
1646 ep->stop_cmd_timer.expires = jiffies +
1647 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1648 add_timer(&ep->stop_cmd_timer);
1649 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1651 xhci_ring_cmd_db(xhci);
1654 spin_unlock_irqrestore(&xhci->lock, flags);
1658 /* Drop an endpoint from a new bandwidth configuration for this device.
1659 * Only one call to this function is allowed per endpoint before
1660 * check_bandwidth() or reset_bandwidth() must be called.
1661 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1662 * add the endpoint to the schedule with possibly new parameters denoted by a
1663 * different endpoint descriptor in usb_host_endpoint.
1664 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1667 * The USB core will not allow URBs to be queued to an endpoint that is being
1668 * disabled, so there's no need for mutual exclusion to protect
1669 * the xhci->devs[slot_id] structure.
1671 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1672 struct usb_host_endpoint *ep)
1674 struct xhci_hcd *xhci;
1675 struct xhci_container_ctx *in_ctx, *out_ctx;
1676 struct xhci_input_control_ctx *ctrl_ctx;
1677 unsigned int ep_index;
1678 struct xhci_ep_ctx *ep_ctx;
1680 u32 new_add_flags, new_drop_flags;
1683 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1686 xhci = hcd_to_xhci(hcd);
1687 if (xhci->xhc_state & XHCI_STATE_DYING)
1690 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1691 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1692 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1693 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1694 __func__, drop_flag);
1698 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1699 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1700 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1702 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1707 ep_index = xhci_get_endpoint_index(&ep->desc);
1708 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1709 /* If the HC already knows the endpoint is disabled,
1710 * or the HCD has noted it is disabled, ignore this request
1712 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1713 cpu_to_le32(EP_STATE_DISABLED)) ||
1714 le32_to_cpu(ctrl_ctx->drop_flags) &
1715 xhci_get_endpoint_flag(&ep->desc)) {
1716 /* Do not warn when called after a usb_device_reset */
1717 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1718 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1723 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1724 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1726 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1727 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1729 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1731 if (xhci->quirks & XHCI_MTK_HOST)
1732 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1734 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1735 (unsigned int) ep->desc.bEndpointAddress,
1737 (unsigned int) new_drop_flags,
1738 (unsigned int) new_add_flags);
1742 /* Add an endpoint to a new possible bandwidth configuration for this device.
1743 * Only one call to this function is allowed per endpoint before
1744 * check_bandwidth() or reset_bandwidth() must be called.
1745 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1746 * add the endpoint to the schedule with possibly new parameters denoted by a
1747 * different endpoint descriptor in usb_host_endpoint.
1748 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1751 * The USB core will not allow URBs to be queued to an endpoint until the
1752 * configuration or alt setting is installed in the device, so there's no need
1753 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1755 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1756 struct usb_host_endpoint *ep)
1758 struct xhci_hcd *xhci;
1759 struct xhci_container_ctx *in_ctx;
1760 unsigned int ep_index;
1761 struct xhci_input_control_ctx *ctrl_ctx;
1763 u32 new_add_flags, new_drop_flags;
1764 struct xhci_virt_device *virt_dev;
1767 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1769 /* So we won't queue a reset ep command for a root hub */
1773 xhci = hcd_to_xhci(hcd);
1774 if (xhci->xhc_state & XHCI_STATE_DYING)
1777 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1778 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1779 /* FIXME when we have to issue an evaluate endpoint command to
1780 * deal with ep0 max packet size changing once we get the
1783 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1784 __func__, added_ctxs);
1788 virt_dev = xhci->devs[udev->slot_id];
1789 in_ctx = virt_dev->in_ctx;
1790 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1792 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1797 ep_index = xhci_get_endpoint_index(&ep->desc);
1798 /* If this endpoint is already in use, and the upper layers are trying
1799 * to add it again without dropping it, reject the addition.
1801 if (virt_dev->eps[ep_index].ring &&
1802 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1803 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1804 "without dropping it.\n",
1805 (unsigned int) ep->desc.bEndpointAddress);
1809 /* If the HCD has already noted the endpoint is enabled,
1810 * ignore this request.
1812 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1813 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1819 * Configuration and alternate setting changes must be done in
1820 * process context, not interrupt context (or so documenation
1821 * for usb_set_interface() and usb_set_configuration() claim).
1823 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1824 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1825 __func__, ep->desc.bEndpointAddress);
1829 if (xhci->quirks & XHCI_MTK_HOST) {
1830 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1832 xhci_free_or_cache_endpoint_ring(xhci,
1833 virt_dev, ep_index);
1838 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1839 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1841 /* If xhci_endpoint_disable() was called for this endpoint, but the
1842 * xHC hasn't been notified yet through the check_bandwidth() call,
1843 * this re-adds a new state for the endpoint from the new endpoint
1844 * descriptors. We must drop and re-add this endpoint, so we leave the
1847 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1849 /* Store the usb_device pointer for later use */
1852 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1853 (unsigned int) ep->desc.bEndpointAddress,
1855 (unsigned int) new_drop_flags,
1856 (unsigned int) new_add_flags);
1860 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1862 struct xhci_input_control_ctx *ctrl_ctx;
1863 struct xhci_ep_ctx *ep_ctx;
1864 struct xhci_slot_ctx *slot_ctx;
1867 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1869 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1874 /* When a device's add flag and drop flag are zero, any subsequent
1875 * configure endpoint command will leave that endpoint's state
1876 * untouched. Make sure we don't leave any old state in the input
1877 * endpoint contexts.
1879 ctrl_ctx->drop_flags = 0;
1880 ctrl_ctx->add_flags = 0;
1881 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1882 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1883 /* Endpoint 0 is always valid */
1884 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1885 for (i = 1; i < 31; ++i) {
1886 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1887 ep_ctx->ep_info = 0;
1888 ep_ctx->ep_info2 = 0;
1890 ep_ctx->tx_info = 0;
1894 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1895 struct usb_device *udev, u32 *cmd_status)
1899 switch (*cmd_status) {
1900 case COMP_CMD_ABORT:
1902 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1906 dev_warn(&udev->dev,
1907 "Not enough host controller resources for new device state.\n");
1909 /* FIXME: can we allocate more resources for the HC? */
1912 case COMP_2ND_BW_ERR:
1913 dev_warn(&udev->dev,
1914 "Not enough bandwidth for new device state.\n");
1916 /* FIXME: can we go back to the old state? */
1919 /* the HCD set up something wrong */
1920 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1922 "and endpoint is not disabled.\n");
1926 dev_warn(&udev->dev,
1927 "ERROR: Incompatible device for endpoint configure command.\n");
1931 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1932 "Successful Endpoint Configure command");
1936 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1944 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1945 struct usb_device *udev, u32 *cmd_status)
1948 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1950 switch (*cmd_status) {
1951 case COMP_CMD_ABORT:
1953 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1957 dev_warn(&udev->dev,
1958 "WARN: xHCI driver setup invalid evaluate context command.\n");
1962 dev_warn(&udev->dev,
1963 "WARN: slot not enabled for evaluate context command.\n");
1966 case COMP_CTX_STATE:
1967 dev_warn(&udev->dev,
1968 "WARN: invalid context state for evaluate context command.\n");
1969 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1973 dev_warn(&udev->dev,
1974 "ERROR: Incompatible device for evaluate context command.\n");
1978 /* Max Exit Latency too large error */
1979 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1983 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1984 "Successful evaluate context command");
1988 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1996 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1997 struct xhci_input_control_ctx *ctrl_ctx)
1999 u32 valid_add_flags;
2000 u32 valid_drop_flags;
2002 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2003 * (bit 1). The default control endpoint is added during the Address
2004 * Device command and is never removed until the slot is disabled.
2006 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2007 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2009 /* Use hweight32 to count the number of ones in the add flags, or
2010 * number of endpoints added. Don't count endpoints that are changed
2011 * (both added and dropped).
2013 return hweight32(valid_add_flags) -
2014 hweight32(valid_add_flags & valid_drop_flags);
2017 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2018 struct xhci_input_control_ctx *ctrl_ctx)
2020 u32 valid_add_flags;
2021 u32 valid_drop_flags;
2023 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2024 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2026 return hweight32(valid_drop_flags) -
2027 hweight32(valid_add_flags & valid_drop_flags);
2031 * We need to reserve the new number of endpoints before the configure endpoint
2032 * command completes. We can't subtract the dropped endpoints from the number
2033 * of active endpoints until the command completes because we can oversubscribe
2034 * the host in this case:
2036 * - the first configure endpoint command drops more endpoints than it adds
2037 * - a second configure endpoint command that adds more endpoints is queued
2038 * - the first configure endpoint command fails, so the config is unchanged
2039 * - the second command may succeed, even though there isn't enough resources
2041 * Must be called with xhci->lock held.
2043 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2044 struct xhci_input_control_ctx *ctrl_ctx)
2048 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2049 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2050 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2051 "Not enough ep ctxs: "
2052 "%u active, need to add %u, limit is %u.",
2053 xhci->num_active_eps, added_eps,
2054 xhci->limit_active_eps);
2057 xhci->num_active_eps += added_eps;
2058 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2059 "Adding %u ep ctxs, %u now active.", added_eps,
2060 xhci->num_active_eps);
2065 * The configure endpoint was failed by the xHC for some other reason, so we
2066 * need to revert the resources that failed configuration would have used.
2068 * Must be called with xhci->lock held.
2070 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2071 struct xhci_input_control_ctx *ctrl_ctx)
2075 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2076 xhci->num_active_eps -= num_failed_eps;
2077 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2078 "Removing %u failed ep ctxs, %u now active.",
2080 xhci->num_active_eps);
2084 * Now that the command has completed, clean up the active endpoint count by
2085 * subtracting out the endpoints that were dropped (but not changed).
2087 * Must be called with xhci->lock held.
2089 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2090 struct xhci_input_control_ctx *ctrl_ctx)
2092 u32 num_dropped_eps;
2094 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2095 xhci->num_active_eps -= num_dropped_eps;
2096 if (num_dropped_eps)
2097 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2098 "Removing %u dropped ep ctxs, %u now active.",
2100 xhci->num_active_eps);
2103 static unsigned int xhci_get_block_size(struct usb_device *udev)
2105 switch (udev->speed) {
2107 case USB_SPEED_FULL:
2109 case USB_SPEED_HIGH:
2111 case USB_SPEED_SUPER:
2112 case USB_SPEED_SUPER_PLUS:
2114 case USB_SPEED_UNKNOWN:
2115 case USB_SPEED_WIRELESS:
2117 /* Should never happen */
2123 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2125 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2127 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2132 /* If we are changing a LS/FS device under a HS hub,
2133 * make sure (if we are activating a new TT) that the HS bus has enough
2134 * bandwidth for this new TT.
2136 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2137 struct xhci_virt_device *virt_dev,
2140 struct xhci_interval_bw_table *bw_table;
2141 struct xhci_tt_bw_info *tt_info;
2143 /* Find the bandwidth table for the root port this TT is attached to. */
2144 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2145 tt_info = virt_dev->tt_info;
2146 /* If this TT already had active endpoints, the bandwidth for this TT
2147 * has already been added. Removing all periodic endpoints (and thus
2148 * making the TT enactive) will only decrease the bandwidth used.
2152 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2153 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2157 /* Not sure why we would have no new active endpoints...
2159 * Maybe because of an Evaluate Context change for a hub update or a
2160 * control endpoint 0 max packet size change?
2161 * FIXME: skip the bandwidth calculation in that case.
2166 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2167 struct xhci_virt_device *virt_dev)
2169 unsigned int bw_reserved;
2171 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2172 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2175 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2176 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2183 * This algorithm is a very conservative estimate of the worst-case scheduling
2184 * scenario for any one interval. The hardware dynamically schedules the
2185 * packets, so we can't tell which microframe could be the limiting factor in
2186 * the bandwidth scheduling. This only takes into account periodic endpoints.
2188 * Obviously, we can't solve an NP complete problem to find the minimum worst
2189 * case scenario. Instead, we come up with an estimate that is no less than
2190 * the worst case bandwidth used for any one microframe, but may be an
2193 * We walk the requirements for each endpoint by interval, starting with the
2194 * smallest interval, and place packets in the schedule where there is only one
2195 * possible way to schedule packets for that interval. In order to simplify
2196 * this algorithm, we record the largest max packet size for each interval, and
2197 * assume all packets will be that size.
2199 * For interval 0, we obviously must schedule all packets for each interval.
2200 * The bandwidth for interval 0 is just the amount of data to be transmitted
2201 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2202 * the number of packets).
2204 * For interval 1, we have two possible microframes to schedule those packets
2205 * in. For this algorithm, if we can schedule the same number of packets for
2206 * each possible scheduling opportunity (each microframe), we will do so. The
2207 * remaining number of packets will be saved to be transmitted in the gaps in
2208 * the next interval's scheduling sequence.
2210 * As we move those remaining packets to be scheduled with interval 2 packets,
2211 * we have to double the number of remaining packets to transmit. This is
2212 * because the intervals are actually powers of 2, and we would be transmitting
2213 * the previous interval's packets twice in this interval. We also have to be
2214 * sure that when we look at the largest max packet size for this interval, we
2215 * also look at the largest max packet size for the remaining packets and take
2216 * the greater of the two.
2218 * The algorithm continues to evenly distribute packets in each scheduling
2219 * opportunity, and push the remaining packets out, until we get to the last
2220 * interval. Then those packets and their associated overhead are just added
2221 * to the bandwidth used.
2223 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2224 struct xhci_virt_device *virt_dev,
2227 unsigned int bw_reserved;
2228 unsigned int max_bandwidth;
2229 unsigned int bw_used;
2230 unsigned int block_size;
2231 struct xhci_interval_bw_table *bw_table;
2232 unsigned int packet_size = 0;
2233 unsigned int overhead = 0;
2234 unsigned int packets_transmitted = 0;
2235 unsigned int packets_remaining = 0;
2238 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2239 return xhci_check_ss_bw(xhci, virt_dev);
2241 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2242 max_bandwidth = HS_BW_LIMIT;
2243 /* Convert percent of bus BW reserved to blocks reserved */
2244 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2246 max_bandwidth = FS_BW_LIMIT;
2247 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2250 bw_table = virt_dev->bw_table;
2251 /* We need to translate the max packet size and max ESIT payloads into
2252 * the units the hardware uses.
2254 block_size = xhci_get_block_size(virt_dev->udev);
2256 /* If we are manipulating a LS/FS device under a HS hub, double check
2257 * that the HS bus has enough bandwidth if we are activing a new TT.
2259 if (virt_dev->tt_info) {
2260 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2261 "Recalculating BW for rootport %u",
2262 virt_dev->real_port);
2263 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2264 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2265 "newly activated TT.\n");
2268 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2269 "Recalculating BW for TT slot %u port %u",
2270 virt_dev->tt_info->slot_id,
2271 virt_dev->tt_info->ttport);
2273 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2274 "Recalculating BW for rootport %u",
2275 virt_dev->real_port);
2278 /* Add in how much bandwidth will be used for interval zero, or the
2279 * rounded max ESIT payload + number of packets * largest overhead.
2281 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2282 bw_table->interval_bw[0].num_packets *
2283 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2285 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2286 unsigned int bw_added;
2287 unsigned int largest_mps;
2288 unsigned int interval_overhead;
2291 * How many packets could we transmit in this interval?
2292 * If packets didn't fit in the previous interval, we will need
2293 * to transmit that many packets twice within this interval.
2295 packets_remaining = 2 * packets_remaining +
2296 bw_table->interval_bw[i].num_packets;
2298 /* Find the largest max packet size of this or the previous
2301 if (list_empty(&bw_table->interval_bw[i].endpoints))
2304 struct xhci_virt_ep *virt_ep;
2305 struct list_head *ep_entry;
2307 ep_entry = bw_table->interval_bw[i].endpoints.next;
2308 virt_ep = list_entry(ep_entry,
2309 struct xhci_virt_ep, bw_endpoint_list);
2310 /* Convert to blocks, rounding up */
2311 largest_mps = DIV_ROUND_UP(
2312 virt_ep->bw_info.max_packet_size,
2315 if (largest_mps > packet_size)
2316 packet_size = largest_mps;
2318 /* Use the larger overhead of this or the previous interval. */
2319 interval_overhead = xhci_get_largest_overhead(
2320 &bw_table->interval_bw[i]);
2321 if (interval_overhead > overhead)
2322 overhead = interval_overhead;
2324 /* How many packets can we evenly distribute across
2325 * (1 << (i + 1)) possible scheduling opportunities?
2327 packets_transmitted = packets_remaining >> (i + 1);
2329 /* Add in the bandwidth used for those scheduled packets */
2330 bw_added = packets_transmitted * (overhead + packet_size);
2332 /* How many packets do we have remaining to transmit? */
2333 packets_remaining = packets_remaining % (1 << (i + 1));
2335 /* What largest max packet size should those packets have? */
2336 /* If we've transmitted all packets, don't carry over the
2337 * largest packet size.
2339 if (packets_remaining == 0) {
2342 } else if (packets_transmitted > 0) {
2343 /* Otherwise if we do have remaining packets, and we've
2344 * scheduled some packets in this interval, take the
2345 * largest max packet size from endpoints with this
2348 packet_size = largest_mps;
2349 overhead = interval_overhead;
2351 /* Otherwise carry over packet_size and overhead from the last
2352 * time we had a remainder.
2354 bw_used += bw_added;
2355 if (bw_used > max_bandwidth) {
2356 xhci_warn(xhci, "Not enough bandwidth. "
2357 "Proposed: %u, Max: %u\n",
2358 bw_used, max_bandwidth);
2363 * Ok, we know we have some packets left over after even-handedly
2364 * scheduling interval 15. We don't know which microframes they will
2365 * fit into, so we over-schedule and say they will be scheduled every
2368 if (packets_remaining > 0)
2369 bw_used += overhead + packet_size;
2371 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2372 unsigned int port_index = virt_dev->real_port - 1;
2374 /* OK, we're manipulating a HS device attached to a
2375 * root port bandwidth domain. Include the number of active TTs
2376 * in the bandwidth used.
2378 bw_used += TT_HS_OVERHEAD *
2379 xhci->rh_bw[port_index].num_active_tts;
2382 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2383 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2384 "Available: %u " "percent",
2385 bw_used, max_bandwidth, bw_reserved,
2386 (max_bandwidth - bw_used - bw_reserved) * 100 /
2389 bw_used += bw_reserved;
2390 if (bw_used > max_bandwidth) {
2391 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2392 bw_used, max_bandwidth);
2396 bw_table->bw_used = bw_used;
2400 static bool xhci_is_async_ep(unsigned int ep_type)
2402 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2403 ep_type != ISOC_IN_EP &&
2404 ep_type != INT_IN_EP);
2407 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2409 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2412 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2414 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2416 if (ep_bw->ep_interval == 0)
2417 return SS_OVERHEAD_BURST +
2418 (ep_bw->mult * ep_bw->num_packets *
2419 (SS_OVERHEAD + mps));
2420 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2421 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2422 1 << ep_bw->ep_interval);
2426 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2427 struct xhci_bw_info *ep_bw,
2428 struct xhci_interval_bw_table *bw_table,
2429 struct usb_device *udev,
2430 struct xhci_virt_ep *virt_ep,
2431 struct xhci_tt_bw_info *tt_info)
2433 struct xhci_interval_bw *interval_bw;
2434 int normalized_interval;
2436 if (xhci_is_async_ep(ep_bw->type))
2439 if (udev->speed >= USB_SPEED_SUPER) {
2440 if (xhci_is_sync_in_ep(ep_bw->type))
2441 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2442 xhci_get_ss_bw_consumed(ep_bw);
2444 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2445 xhci_get_ss_bw_consumed(ep_bw);
2449 /* SuperSpeed endpoints never get added to intervals in the table, so
2450 * this check is only valid for HS/FS/LS devices.
2452 if (list_empty(&virt_ep->bw_endpoint_list))
2454 /* For LS/FS devices, we need to translate the interval expressed in
2455 * microframes to frames.
2457 if (udev->speed == USB_SPEED_HIGH)
2458 normalized_interval = ep_bw->ep_interval;
2460 normalized_interval = ep_bw->ep_interval - 3;
2462 if (normalized_interval == 0)
2463 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2464 interval_bw = &bw_table->interval_bw[normalized_interval];
2465 interval_bw->num_packets -= ep_bw->num_packets;
2466 switch (udev->speed) {
2468 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2470 case USB_SPEED_FULL:
2471 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2473 case USB_SPEED_HIGH:
2474 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2476 case USB_SPEED_SUPER:
2477 case USB_SPEED_SUPER_PLUS:
2478 case USB_SPEED_UNKNOWN:
2479 case USB_SPEED_WIRELESS:
2480 /* Should never happen because only LS/FS/HS endpoints will get
2481 * added to the endpoint list.
2486 tt_info->active_eps -= 1;
2487 list_del_init(&virt_ep->bw_endpoint_list);
2490 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2491 struct xhci_bw_info *ep_bw,
2492 struct xhci_interval_bw_table *bw_table,
2493 struct usb_device *udev,
2494 struct xhci_virt_ep *virt_ep,
2495 struct xhci_tt_bw_info *tt_info)
2497 struct xhci_interval_bw *interval_bw;
2498 struct xhci_virt_ep *smaller_ep;
2499 int normalized_interval;
2501 if (xhci_is_async_ep(ep_bw->type))
2504 if (udev->speed == USB_SPEED_SUPER) {
2505 if (xhci_is_sync_in_ep(ep_bw->type))
2506 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2507 xhci_get_ss_bw_consumed(ep_bw);
2509 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2510 xhci_get_ss_bw_consumed(ep_bw);
2514 /* For LS/FS devices, we need to translate the interval expressed in
2515 * microframes to frames.
2517 if (udev->speed == USB_SPEED_HIGH)
2518 normalized_interval = ep_bw->ep_interval;
2520 normalized_interval = ep_bw->ep_interval - 3;
2522 if (normalized_interval == 0)
2523 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2524 interval_bw = &bw_table->interval_bw[normalized_interval];
2525 interval_bw->num_packets += ep_bw->num_packets;
2526 switch (udev->speed) {
2528 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2530 case USB_SPEED_FULL:
2531 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2533 case USB_SPEED_HIGH:
2534 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2536 case USB_SPEED_SUPER:
2537 case USB_SPEED_SUPER_PLUS:
2538 case USB_SPEED_UNKNOWN:
2539 case USB_SPEED_WIRELESS:
2540 /* Should never happen because only LS/FS/HS endpoints will get
2541 * added to the endpoint list.
2547 tt_info->active_eps += 1;
2548 /* Insert the endpoint into the list, largest max packet size first. */
2549 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2551 if (ep_bw->max_packet_size >=
2552 smaller_ep->bw_info.max_packet_size) {
2553 /* Add the new ep before the smaller endpoint */
2554 list_add_tail(&virt_ep->bw_endpoint_list,
2555 &smaller_ep->bw_endpoint_list);
2559 /* Add the new endpoint at the end of the list. */
2560 list_add_tail(&virt_ep->bw_endpoint_list,
2561 &interval_bw->endpoints);
2564 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2565 struct xhci_virt_device *virt_dev,
2568 struct xhci_root_port_bw_info *rh_bw_info;
2569 if (!virt_dev->tt_info)
2572 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2573 if (old_active_eps == 0 &&
2574 virt_dev->tt_info->active_eps != 0) {
2575 rh_bw_info->num_active_tts += 1;
2576 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2577 } else if (old_active_eps != 0 &&
2578 virt_dev->tt_info->active_eps == 0) {
2579 rh_bw_info->num_active_tts -= 1;
2580 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2584 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2585 struct xhci_virt_device *virt_dev,
2586 struct xhci_container_ctx *in_ctx)
2588 struct xhci_bw_info ep_bw_info[31];
2590 struct xhci_input_control_ctx *ctrl_ctx;
2591 int old_active_eps = 0;
2593 if (virt_dev->tt_info)
2594 old_active_eps = virt_dev->tt_info->active_eps;
2596 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2598 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2603 for (i = 0; i < 31; i++) {
2604 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2607 /* Make a copy of the BW info in case we need to revert this */
2608 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2609 sizeof(ep_bw_info[i]));
2610 /* Drop the endpoint from the interval table if the endpoint is
2611 * being dropped or changed.
2613 if (EP_IS_DROPPED(ctrl_ctx, i))
2614 xhci_drop_ep_from_interval_table(xhci,
2615 &virt_dev->eps[i].bw_info,
2621 /* Overwrite the information stored in the endpoints' bw_info */
2622 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2623 for (i = 0; i < 31; i++) {
2624 /* Add any changed or added endpoints to the interval table */
2625 if (EP_IS_ADDED(ctrl_ctx, i))
2626 xhci_add_ep_to_interval_table(xhci,
2627 &virt_dev->eps[i].bw_info,
2634 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2635 /* Ok, this fits in the bandwidth we have.
2636 * Update the number of active TTs.
2638 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2642 /* We don't have enough bandwidth for this, revert the stored info. */
2643 for (i = 0; i < 31; i++) {
2644 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2647 /* Drop the new copies of any added or changed endpoints from
2648 * the interval table.
2650 if (EP_IS_ADDED(ctrl_ctx, i)) {
2651 xhci_drop_ep_from_interval_table(xhci,
2652 &virt_dev->eps[i].bw_info,
2658 /* Revert the endpoint back to its old information */
2659 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2660 sizeof(ep_bw_info[i]));
2661 /* Add any changed or dropped endpoints back into the table */
2662 if (EP_IS_DROPPED(ctrl_ctx, i))
2663 xhci_add_ep_to_interval_table(xhci,
2664 &virt_dev->eps[i].bw_info,
2674 /* Issue a configure endpoint command or evaluate context command
2675 * and wait for it to finish.
2677 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2678 struct usb_device *udev,
2679 struct xhci_command *command,
2680 bool ctx_change, bool must_succeed)
2683 unsigned long flags;
2684 struct xhci_input_control_ctx *ctrl_ctx;
2685 struct xhci_virt_device *virt_dev;
2690 spin_lock_irqsave(&xhci->lock, flags);
2691 virt_dev = xhci->devs[udev->slot_id];
2693 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2695 spin_unlock_irqrestore(&xhci->lock, flags);
2696 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2701 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2702 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2703 spin_unlock_irqrestore(&xhci->lock, flags);
2704 xhci_warn(xhci, "Not enough host resources, "
2705 "active endpoint contexts = %u\n",
2706 xhci->num_active_eps);
2709 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2710 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2711 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2712 xhci_free_host_resources(xhci, ctrl_ctx);
2713 spin_unlock_irqrestore(&xhci->lock, flags);
2714 xhci_warn(xhci, "Not enough bandwidth\n");
2719 ret = xhci_queue_configure_endpoint(xhci, command,
2720 command->in_ctx->dma,
2721 udev->slot_id, must_succeed);
2723 ret = xhci_queue_evaluate_context(xhci, command,
2724 command->in_ctx->dma,
2725 udev->slot_id, must_succeed);
2727 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2728 xhci_free_host_resources(xhci, ctrl_ctx);
2729 spin_unlock_irqrestore(&xhci->lock, flags);
2730 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2731 "FIXME allocate a new ring segment");
2734 xhci_ring_cmd_db(xhci);
2735 spin_unlock_irqrestore(&xhci->lock, flags);
2737 /* Wait for the configure endpoint command to complete */
2738 wait_for_completion(command->completion);
2741 ret = xhci_configure_endpoint_result(xhci, udev,
2744 ret = xhci_evaluate_context_result(xhci, udev,
2747 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2748 spin_lock_irqsave(&xhci->lock, flags);
2749 /* If the command failed, remove the reserved resources.
2750 * Otherwise, clean up the estimate to include dropped eps.
2753 xhci_free_host_resources(xhci, ctrl_ctx);
2755 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2756 spin_unlock_irqrestore(&xhci->lock, flags);
2761 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2762 struct xhci_virt_device *vdev, int i)
2764 struct xhci_virt_ep *ep = &vdev->eps[i];
2766 if (ep->ep_state & EP_HAS_STREAMS) {
2767 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2768 xhci_get_endpoint_address(i));
2769 xhci_free_stream_info(xhci, ep->stream_info);
2770 ep->stream_info = NULL;
2771 ep->ep_state &= ~EP_HAS_STREAMS;
2775 /* Called after one or more calls to xhci_add_endpoint() or
2776 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2777 * to call xhci_reset_bandwidth().
2779 * Since we are in the middle of changing either configuration or
2780 * installing a new alt setting, the USB core won't allow URBs to be
2781 * enqueued for any endpoint on the old config or interface. Nothing
2782 * else should be touching the xhci->devs[slot_id] structure, so we
2783 * don't need to take the xhci->lock for manipulating that.
2785 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2789 struct xhci_hcd *xhci;
2790 struct xhci_virt_device *virt_dev;
2791 struct xhci_input_control_ctx *ctrl_ctx;
2792 struct xhci_slot_ctx *slot_ctx;
2793 struct xhci_command *command;
2795 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2798 xhci = hcd_to_xhci(hcd);
2799 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2800 (xhci->xhc_state & XHCI_STATE_REMOVING))
2803 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2804 virt_dev = xhci->devs[udev->slot_id];
2806 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2810 command->in_ctx = virt_dev->in_ctx;
2812 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2813 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2815 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2818 goto command_cleanup;
2820 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2821 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2822 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2824 /* Don't issue the command if there's no endpoints to update. */
2825 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2826 ctrl_ctx->drop_flags == 0) {
2828 goto command_cleanup;
2830 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2831 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2832 for (i = 31; i >= 1; i--) {
2833 __le32 le32 = cpu_to_le32(BIT(i));
2835 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2836 || (ctrl_ctx->add_flags & le32) || i == 1) {
2837 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2838 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2842 xhci_dbg(xhci, "New Input Control Context:\n");
2843 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2844 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2846 ret = xhci_configure_endpoint(xhci, udev, command,
2849 /* Callee should call reset_bandwidth() */
2850 goto command_cleanup;
2852 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2853 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2854 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2856 /* Free any rings that were dropped, but not changed. */
2857 for (i = 1; i < 31; ++i) {
2858 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2859 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2860 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2861 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2864 xhci_zero_in_ctx(xhci, virt_dev);
2866 * Install any rings for completely new endpoints or changed endpoints,
2867 * and free or cache any old rings from changed endpoints.
2869 for (i = 1; i < 31; ++i) {
2870 if (!virt_dev->eps[i].new_ring)
2872 /* Only cache or free the old ring if it exists.
2873 * It may not if this is the first add of an endpoint.
2875 if (virt_dev->eps[i].ring) {
2876 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2878 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2879 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2880 virt_dev->eps[i].new_ring = NULL;
2883 kfree(command->completion);
2889 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2891 struct xhci_hcd *xhci;
2892 struct xhci_virt_device *virt_dev;
2895 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2898 xhci = hcd_to_xhci(hcd);
2900 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2901 virt_dev = xhci->devs[udev->slot_id];
2902 /* Free any rings allocated for added endpoints */
2903 for (i = 0; i < 31; ++i) {
2904 if (virt_dev->eps[i].new_ring) {
2905 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2906 virt_dev->eps[i].new_ring = NULL;
2909 xhci_zero_in_ctx(xhci, virt_dev);
2912 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2913 struct xhci_container_ctx *in_ctx,
2914 struct xhci_container_ctx *out_ctx,
2915 struct xhci_input_control_ctx *ctrl_ctx,
2916 u32 add_flags, u32 drop_flags)
2918 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2919 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2920 xhci_slot_copy(xhci, in_ctx, out_ctx);
2921 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2923 xhci_dbg(xhci, "Input Context:\n");
2924 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2927 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2928 unsigned int slot_id, unsigned int ep_index,
2929 struct xhci_dequeue_state *deq_state)
2931 struct xhci_input_control_ctx *ctrl_ctx;
2932 struct xhci_container_ctx *in_ctx;
2933 struct xhci_ep_ctx *ep_ctx;
2937 in_ctx = xhci->devs[slot_id]->in_ctx;
2938 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2940 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2945 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2946 xhci->devs[slot_id]->out_ctx, ep_index);
2947 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2948 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2949 deq_state->new_deq_ptr);
2951 xhci_warn(xhci, "WARN Cannot submit config ep after "
2952 "reset ep command\n");
2953 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2954 deq_state->new_deq_seg,
2955 deq_state->new_deq_ptr);
2958 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2960 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2961 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2962 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2963 added_ctxs, added_ctxs);
2966 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2967 unsigned int ep_index, struct xhci_td *td)
2969 struct xhci_dequeue_state deq_state;
2970 struct xhci_virt_ep *ep;
2971 struct usb_device *udev = td->urb->dev;
2973 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2974 "Cleaning up stalled endpoint ring");
2975 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2976 /* We need to move the HW's dequeue pointer past this TD,
2977 * or it will attempt to resend it on the next doorbell ring.
2979 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2980 ep_index, ep->stopped_stream, td, &deq_state);
2982 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2985 /* HW with the reset endpoint quirk will use the saved dequeue state to
2986 * issue a configure endpoint command later.
2988 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2989 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2990 "Queueing new dequeue state");
2991 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2992 ep_index, ep->stopped_stream, &deq_state);
2994 /* Better hope no one uses the input context between now and the
2995 * reset endpoint completion!
2996 * XXX: No idea how this hardware will react when stream rings
2999 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3000 "Setting up input context for "
3001 "configure endpoint command");
3002 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
3003 ep_index, &deq_state);
3007 /* Called when clearing halted device. The core should have sent the control
3008 * message to clear the device halt condition. The host side of the halt should
3009 * already be cleared with a reset endpoint command issued when the STALL tx
3010 * event was received.
3012 * Context: in_interrupt
3015 void xhci_endpoint_reset(struct usb_hcd *hcd,
3016 struct usb_host_endpoint *ep)
3018 struct xhci_hcd *xhci;
3020 xhci = hcd_to_xhci(hcd);
3023 * We might need to implement the config ep cmd in xhci 4.8.1 note:
3024 * The Reset Endpoint Command may only be issued to endpoints in the
3025 * Halted state. If software wishes reset the Data Toggle or Sequence
3026 * Number of an endpoint that isn't in the Halted state, then software
3027 * may issue a Configure Endpoint Command with the Drop and Add bits set
3028 * for the target endpoint. that is in the Stopped state.
3031 /* For now just print debug to follow the situation */
3032 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
3033 ep->desc.bEndpointAddress);
3036 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3037 struct usb_device *udev, struct usb_host_endpoint *ep,
3038 unsigned int slot_id)
3041 unsigned int ep_index;
3042 unsigned int ep_state;
3046 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3048 return ret ? ret : -EINVAL;
3049 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3050 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3051 " descriptor for ep 0x%x does not support streams\n",
3052 ep->desc.bEndpointAddress);
3056 ep_index = xhci_get_endpoint_index(&ep->desc);
3057 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3058 if (ep_state & EP_HAS_STREAMS ||
3059 ep_state & EP_GETTING_STREAMS) {
3060 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3061 "already has streams set up.\n",
3062 ep->desc.bEndpointAddress);
3063 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3064 "dynamic stream context array reallocation.\n");
3067 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3068 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3069 "endpoint 0x%x; URBs are pending.\n",
3070 ep->desc.bEndpointAddress);
3076 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3077 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3079 unsigned int max_streams;
3081 /* The stream context array size must be a power of two */
3082 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3084 * Find out how many primary stream array entries the host controller
3085 * supports. Later we may use secondary stream arrays (similar to 2nd
3086 * level page entries), but that's an optional feature for xHCI host
3087 * controllers. xHCs must support at least 4 stream IDs.
3089 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3090 if (*num_stream_ctxs > max_streams) {
3091 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3093 *num_stream_ctxs = max_streams;
3094 *num_streams = max_streams;
3098 /* Returns an error code if one of the endpoint already has streams.
3099 * This does not change any data structures, it only checks and gathers
3102 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3103 struct usb_device *udev,
3104 struct usb_host_endpoint **eps, unsigned int num_eps,
3105 unsigned int *num_streams, u32 *changed_ep_bitmask)
3107 unsigned int max_streams;
3108 unsigned int endpoint_flag;
3112 for (i = 0; i < num_eps; i++) {
3113 ret = xhci_check_streams_endpoint(xhci, udev,
3114 eps[i], udev->slot_id);
3118 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3119 if (max_streams < (*num_streams - 1)) {
3120 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3121 eps[i]->desc.bEndpointAddress,
3123 *num_streams = max_streams+1;
3126 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3127 if (*changed_ep_bitmask & endpoint_flag)
3129 *changed_ep_bitmask |= endpoint_flag;
3134 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3135 struct usb_device *udev,
3136 struct usb_host_endpoint **eps, unsigned int num_eps)
3138 u32 changed_ep_bitmask = 0;
3139 unsigned int slot_id;
3140 unsigned int ep_index;
3141 unsigned int ep_state;
3144 slot_id = udev->slot_id;
3145 if (!xhci->devs[slot_id])
3148 for (i = 0; i < num_eps; i++) {
3149 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3150 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3151 /* Are streams already being freed for the endpoint? */
3152 if (ep_state & EP_GETTING_NO_STREAMS) {
3153 xhci_warn(xhci, "WARN Can't disable streams for "
3155 "streams are being disabled already\n",
3156 eps[i]->desc.bEndpointAddress);
3159 /* Are there actually any streams to free? */
3160 if (!(ep_state & EP_HAS_STREAMS) &&
3161 !(ep_state & EP_GETTING_STREAMS)) {
3162 xhci_warn(xhci, "WARN Can't disable streams for "
3164 "streams are already disabled!\n",
3165 eps[i]->desc.bEndpointAddress);
3166 xhci_warn(xhci, "WARN xhci_free_streams() called "
3167 "with non-streams endpoint\n");
3170 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3172 return changed_ep_bitmask;
3176 * The USB device drivers use this function (through the HCD interface in USB
3177 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3178 * coordinate mass storage command queueing across multiple endpoints (basically
3179 * a stream ID == a task ID).
3181 * Setting up streams involves allocating the same size stream context array
3182 * for each endpoint and issuing a configure endpoint command for all endpoints.
3184 * Don't allow the call to succeed if one endpoint only supports one stream
3185 * (which means it doesn't support streams at all).
3187 * Drivers may get less stream IDs than they asked for, if the host controller
3188 * hardware or endpoints claim they can't support the number of requested
3191 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3192 struct usb_host_endpoint **eps, unsigned int num_eps,
3193 unsigned int num_streams, gfp_t mem_flags)
3196 struct xhci_hcd *xhci;
3197 struct xhci_virt_device *vdev;
3198 struct xhci_command *config_cmd;
3199 struct xhci_input_control_ctx *ctrl_ctx;
3200 unsigned int ep_index;
3201 unsigned int num_stream_ctxs;
3202 unsigned int max_packet;
3203 unsigned long flags;
3204 u32 changed_ep_bitmask = 0;
3209 /* Add one to the number of streams requested to account for
3210 * stream 0 that is reserved for xHCI usage.
3213 xhci = hcd_to_xhci(hcd);
3214 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3217 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3218 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3219 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3220 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3224 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3226 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3229 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3231 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3233 xhci_free_command(xhci, config_cmd);
3237 /* Check to make sure all endpoints are not already configured for
3238 * streams. While we're at it, find the maximum number of streams that
3239 * all the endpoints will support and check for duplicate endpoints.
3241 spin_lock_irqsave(&xhci->lock, flags);
3242 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3243 num_eps, &num_streams, &changed_ep_bitmask);
3245 xhci_free_command(xhci, config_cmd);
3246 spin_unlock_irqrestore(&xhci->lock, flags);
3249 if (num_streams <= 1) {
3250 xhci_warn(xhci, "WARN: endpoints can't handle "
3251 "more than one stream.\n");
3252 xhci_free_command(xhci, config_cmd);
3253 spin_unlock_irqrestore(&xhci->lock, flags);
3256 vdev = xhci->devs[udev->slot_id];
3257 /* Mark each endpoint as being in transition, so
3258 * xhci_urb_enqueue() will reject all URBs.
3260 for (i = 0; i < num_eps; i++) {
3261 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3262 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3264 spin_unlock_irqrestore(&xhci->lock, flags);
3266 /* Setup internal data structures and allocate HW data structures for
3267 * streams (but don't install the HW structures in the input context
3268 * until we're sure all memory allocation succeeded).
3270 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3271 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3272 num_stream_ctxs, num_streams);
3274 for (i = 0; i < num_eps; i++) {
3275 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3276 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&eps[i]->desc));
3277 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3280 max_packet, mem_flags);
3281 if (!vdev->eps[ep_index].stream_info)
3283 /* Set maxPstreams in endpoint context and update deq ptr to
3284 * point to stream context array. FIXME
3288 /* Set up the input context for a configure endpoint command. */
3289 for (i = 0; i < num_eps; i++) {
3290 struct xhci_ep_ctx *ep_ctx;
3292 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3293 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3295 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3296 vdev->out_ctx, ep_index);
3297 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3298 vdev->eps[ep_index].stream_info);
3300 /* Tell the HW to drop its old copy of the endpoint context info
3301 * and add the updated copy from the input context.
3303 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3304 vdev->out_ctx, ctrl_ctx,
3305 changed_ep_bitmask, changed_ep_bitmask);
3307 /* Issue and wait for the configure endpoint command */
3308 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3311 /* xHC rejected the configure endpoint command for some reason, so we
3312 * leave the old ring intact and free our internal streams data
3318 spin_lock_irqsave(&xhci->lock, flags);
3319 for (i = 0; i < num_eps; i++) {
3320 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3321 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3322 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3323 udev->slot_id, ep_index);
3324 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3326 xhci_free_command(xhci, config_cmd);
3327 spin_unlock_irqrestore(&xhci->lock, flags);
3329 /* Subtract 1 for stream 0, which drivers can't use */
3330 return num_streams - 1;
3333 /* If it didn't work, free the streams! */
3334 for (i = 0; i < num_eps; i++) {
3335 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3336 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3337 vdev->eps[ep_index].stream_info = NULL;
3338 /* FIXME Unset maxPstreams in endpoint context and
3339 * update deq ptr to point to normal string ring.
3341 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3342 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3343 xhci_endpoint_zero(xhci, vdev, eps[i]);
3345 xhci_free_command(xhci, config_cmd);
3349 /* Transition the endpoint from using streams to being a "normal" endpoint
3352 * Modify the endpoint context state, submit a configure endpoint command,
3353 * and free all endpoint rings for streams if that completes successfully.
3355 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3356 struct usb_host_endpoint **eps, unsigned int num_eps,
3360 struct xhci_hcd *xhci;
3361 struct xhci_virt_device *vdev;
3362 struct xhci_command *command;
3363 struct xhci_input_control_ctx *ctrl_ctx;
3364 unsigned int ep_index;
3365 unsigned long flags;
3366 u32 changed_ep_bitmask;
3368 xhci = hcd_to_xhci(hcd);
3369 vdev = xhci->devs[udev->slot_id];
3371 /* Set up a configure endpoint command to remove the streams rings */
3372 spin_lock_irqsave(&xhci->lock, flags);
3373 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3374 udev, eps, num_eps);
3375 if (changed_ep_bitmask == 0) {
3376 spin_unlock_irqrestore(&xhci->lock, flags);
3380 /* Use the xhci_command structure from the first endpoint. We may have
3381 * allocated too many, but the driver may call xhci_free_streams() for
3382 * each endpoint it grouped into one call to xhci_alloc_streams().
3384 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3385 command = vdev->eps[ep_index].stream_info->free_streams_command;
3386 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3388 spin_unlock_irqrestore(&xhci->lock, flags);
3389 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3394 for (i = 0; i < num_eps; i++) {
3395 struct xhci_ep_ctx *ep_ctx;
3397 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3398 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3399 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3400 EP_GETTING_NO_STREAMS;
3402 xhci_endpoint_copy(xhci, command->in_ctx,
3403 vdev->out_ctx, ep_index);
3404 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3405 &vdev->eps[ep_index]);
3407 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3408 vdev->out_ctx, ctrl_ctx,
3409 changed_ep_bitmask, changed_ep_bitmask);
3410 spin_unlock_irqrestore(&xhci->lock, flags);
3412 /* Issue and wait for the configure endpoint command,
3413 * which must succeed.
3415 ret = xhci_configure_endpoint(xhci, udev, command,
3418 /* xHC rejected the configure endpoint command for some reason, so we
3419 * leave the streams rings intact.
3424 spin_lock_irqsave(&xhci->lock, flags);
3425 for (i = 0; i < num_eps; i++) {
3426 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3427 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3428 vdev->eps[ep_index].stream_info = NULL;
3429 /* FIXME Unset maxPstreams in endpoint context and
3430 * update deq ptr to point to normal string ring.
3432 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3433 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3435 spin_unlock_irqrestore(&xhci->lock, flags);
3441 * Deletes endpoint resources for endpoints that were active before a Reset
3442 * Device command, or a Disable Slot command. The Reset Device command leaves
3443 * the control endpoint intact, whereas the Disable Slot command deletes it.
3445 * Must be called with xhci->lock held.
3447 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3448 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3451 unsigned int num_dropped_eps = 0;
3452 unsigned int drop_flags = 0;
3454 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3455 if (virt_dev->eps[i].ring) {
3456 drop_flags |= 1 << i;
3460 xhci->num_active_eps -= num_dropped_eps;
3461 if (num_dropped_eps)
3462 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3463 "Dropped %u ep ctxs, flags = 0x%x, "
3465 num_dropped_eps, drop_flags,
3466 xhci->num_active_eps);
3470 * This submits a Reset Device Command, which will set the device state to 0,
3471 * set the device address to 0, and disable all the endpoints except the default
3472 * control endpoint. The USB core should come back and call
3473 * xhci_address_device(), and then re-set up the configuration. If this is
3474 * called because of a usb_reset_and_verify_device(), then the old alternate
3475 * settings will be re-installed through the normal bandwidth allocation
3478 * Wait for the Reset Device command to finish. Remove all structures
3479 * associated with the endpoints that were disabled. Clear the input device
3480 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3482 * If the virt_dev to be reset does not exist or does not match the udev,
3483 * it means the device is lost, possibly due to the xHC restore error and
3484 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3485 * re-allocate the device.
3487 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3490 unsigned long flags;
3491 struct xhci_hcd *xhci;
3492 unsigned int slot_id;
3493 struct xhci_virt_device *virt_dev;
3494 struct xhci_command *reset_device_cmd;
3495 int last_freed_endpoint;
3496 struct xhci_slot_ctx *slot_ctx;
3497 int old_active_eps = 0;
3499 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3502 xhci = hcd_to_xhci(hcd);
3503 slot_id = udev->slot_id;
3504 virt_dev = xhci->devs[slot_id];
3506 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3507 "not exist. Re-allocate the device\n", slot_id);
3508 ret = xhci_alloc_dev(hcd, udev);
3515 if (virt_dev->tt_info)
3516 old_active_eps = virt_dev->tt_info->active_eps;
3518 if (virt_dev->udev != udev) {
3519 /* If the virt_dev and the udev does not match, this virt_dev
3520 * may belong to another udev.
3521 * Re-allocate the device.
3523 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3524 "not match the udev. Re-allocate the device\n",
3526 ret = xhci_alloc_dev(hcd, udev);
3533 /* If device is not setup, there is no point in resetting it */
3534 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3535 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3536 SLOT_STATE_DISABLED)
3539 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3540 /* Allocate the command structure that holds the struct completion.
3541 * Assume we're in process context, since the normal device reset
3542 * process has to wait for the device anyway. Storage devices are
3543 * reset as part of error handling, so use GFP_NOIO instead of
3546 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3547 if (!reset_device_cmd) {
3548 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3552 /* Attempt to submit the Reset Device command to the command ring */
3553 spin_lock_irqsave(&xhci->lock, flags);
3555 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3557 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3558 spin_unlock_irqrestore(&xhci->lock, flags);
3559 goto command_cleanup;
3561 xhci_ring_cmd_db(xhci);
3562 spin_unlock_irqrestore(&xhci->lock, flags);
3564 /* Wait for the Reset Device command to finish */
3565 wait_for_completion(reset_device_cmd->completion);
3567 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3568 * unless we tried to reset a slot ID that wasn't enabled,
3569 * or the device wasn't in the addressed or configured state.
3571 ret = reset_device_cmd->status;
3573 case COMP_CMD_ABORT:
3575 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3577 goto command_cleanup;
3578 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3579 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3580 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3582 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3583 xhci_dbg(xhci, "Not freeing device rings.\n");
3584 /* Don't treat this as an error. May change my mind later. */
3586 goto command_cleanup;
3588 xhci_dbg(xhci, "Successful reset device command.\n");
3591 if (xhci_is_vendor_info_code(xhci, ret))
3593 xhci_warn(xhci, "Unknown completion code %u for "
3594 "reset device command.\n", ret);
3596 goto command_cleanup;
3599 /* Free up host controller endpoint resources */
3600 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3601 spin_lock_irqsave(&xhci->lock, flags);
3602 /* Don't delete the default control endpoint resources */
3603 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3604 spin_unlock_irqrestore(&xhci->lock, flags);
3607 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3608 last_freed_endpoint = 1;
3609 for (i = 1; i < 31; ++i) {
3610 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3612 if (ep->ep_state & EP_HAS_STREAMS) {
3613 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3614 xhci_get_endpoint_address(i));
3615 xhci_free_stream_info(xhci, ep->stream_info);
3616 ep->stream_info = NULL;
3617 ep->ep_state &= ~EP_HAS_STREAMS;
3621 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3622 last_freed_endpoint = i;
3624 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3625 xhci_drop_ep_from_interval_table(xhci,
3626 &virt_dev->eps[i].bw_info,
3631 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3633 /* If necessary, update the number of active TTs on this root port */
3634 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3636 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3637 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3641 xhci_free_command(xhci, reset_device_cmd);
3646 * At this point, the struct usb_device is about to go away, the device has
3647 * disconnected, and all traffic has been stopped and the endpoints have been
3648 * disabled. Free any HC data structures associated with that device.
3650 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3652 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3653 struct xhci_virt_device *virt_dev;
3654 unsigned long flags;
3657 struct xhci_command *command;
3659 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3663 #ifndef CONFIG_USB_DEFAULT_PERSIST
3665 * We called pm_runtime_get_noresume when the device was attached.
3666 * Decrement the counter here to allow controller to runtime suspend
3667 * if no devices remain.
3669 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3670 pm_runtime_put_noidle(hcd->self.controller);
3673 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3674 /* If the host is halted due to driver unload, we still need to free the
3677 if (ret <= 0 && ret != -ENODEV) {
3682 virt_dev = xhci->devs[udev->slot_id];
3684 /* Stop any wayward timer functions (which may grab the lock) */
3685 for (i = 0; i < 31; ++i) {
3686 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3687 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3690 spin_lock_irqsave(&xhci->lock, flags);
3692 virt_dev->udev = NULL;
3694 /* Don't disable the slot if the host controller is dead. */
3695 state = readl(&xhci->op_regs->status);
3696 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3697 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3698 xhci_free_virt_device(xhci, udev->slot_id);
3699 spin_unlock_irqrestore(&xhci->lock, flags);
3704 if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3706 spin_unlock_irqrestore(&xhci->lock, flags);
3707 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3710 xhci_ring_cmd_db(xhci);
3711 spin_unlock_irqrestore(&xhci->lock, flags);
3714 * Event command completion handler will free any data structures
3715 * associated with the slot. XXX Can free sleep?
3720 * Checks if we have enough host controller resources for the default control
3723 * Must be called with xhci->lock held.
3725 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3727 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3728 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3729 "Not enough ep ctxs: "
3730 "%u active, need to add 1, limit is %u.",
3731 xhci->num_active_eps, xhci->limit_active_eps);
3734 xhci->num_active_eps += 1;
3735 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3736 "Adding 1 ep ctx, %u now active.",
3737 xhci->num_active_eps);
3743 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3744 * timed out, or allocating memory failed. Returns 1 on success.
3746 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3748 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3749 unsigned long flags;
3751 struct xhci_command *command;
3753 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3757 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3758 mutex_lock(&xhci->mutex);
3759 spin_lock_irqsave(&xhci->lock, flags);
3760 command->completion = &xhci->addr_dev;
3761 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3763 spin_unlock_irqrestore(&xhci->lock, flags);
3764 mutex_unlock(&xhci->mutex);
3765 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3769 xhci_ring_cmd_db(xhci);
3770 spin_unlock_irqrestore(&xhci->lock, flags);
3772 wait_for_completion(command->completion);
3773 slot_id = xhci->slot_id;
3774 mutex_unlock(&xhci->mutex);
3776 if (!slot_id || command->status != COMP_SUCCESS) {
3777 xhci_err(xhci, "Error while assigning device slot ID\n");
3778 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3780 readl(&xhci->cap_regs->hcs_params1)));
3785 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3786 spin_lock_irqsave(&xhci->lock, flags);
3787 ret = xhci_reserve_host_control_ep_resources(xhci);
3789 spin_unlock_irqrestore(&xhci->lock, flags);
3790 xhci_warn(xhci, "Not enough host resources, "
3791 "active endpoint contexts = %u\n",
3792 xhci->num_active_eps);
3795 spin_unlock_irqrestore(&xhci->lock, flags);
3797 /* Use GFP_NOIO, since this function can be called from
3798 * xhci_discover_or_reset_device(), which may be called as part of
3799 * mass storage driver error handling.
3801 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3802 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3805 udev->slot_id = slot_id;
3807 #ifndef CONFIG_USB_DEFAULT_PERSIST
3809 * If resetting upon resume, we can't put the controller into runtime
3810 * suspend if there is a device attached.
3812 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3813 pm_runtime_get_noresume(hcd->self.controller);
3818 /* Is this a LS or FS device under a HS hub? */
3819 /* Hub or peripherial? */
3823 /* Disable slot, if we can do it without mem alloc */
3824 spin_lock_irqsave(&xhci->lock, flags);
3825 command->completion = NULL;
3826 command->status = 0;
3827 if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3829 xhci_ring_cmd_db(xhci);
3830 spin_unlock_irqrestore(&xhci->lock, flags);
3835 * Issue an Address Device command and optionally send a corresponding
3836 * SetAddress request to the device.
3838 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3839 enum xhci_setup_dev setup)
3841 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3842 unsigned long flags;
3843 struct xhci_virt_device *virt_dev;
3845 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3846 struct xhci_slot_ctx *slot_ctx;
3847 struct xhci_input_control_ctx *ctrl_ctx;
3849 struct xhci_command *command = NULL;
3851 mutex_lock(&xhci->mutex);
3853 if (xhci->xhc_state) { /* dying, removing or halted */
3858 if (!udev->slot_id) {
3859 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3860 "Bad Slot ID %d", udev->slot_id);
3865 virt_dev = xhci->devs[udev->slot_id];
3867 if (WARN_ON(!virt_dev)) {
3869 * In plug/unplug torture test with an NEC controller,
3870 * a zero-dereference was observed once due to virt_dev = 0.
3871 * Print useful debug rather than crash if it is observed again!
3873 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3879 if (setup == SETUP_CONTEXT_ONLY) {
3880 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3881 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3882 SLOT_STATE_DEFAULT) {
3883 xhci_dbg(xhci, "Slot already in default state\n");
3888 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3894 command->in_ctx = virt_dev->in_ctx;
3895 command->completion = &xhci->addr_dev;
3897 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3898 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3900 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3906 * If this is the first Set Address since device plug-in or
3907 * virt_device realloaction after a resume with an xHCI power loss,
3908 * then set up the slot context.
3910 if (!slot_ctx->dev_info)
3911 xhci_setup_addressable_virt_dev(xhci, udev);
3912 /* Otherwise, update the control endpoint ring enqueue pointer. */
3914 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3915 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3916 ctrl_ctx->drop_flags = 0;
3918 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3919 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3920 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3921 le32_to_cpu(slot_ctx->dev_info) >> 27);
3923 spin_lock_irqsave(&xhci->lock, flags);
3924 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3925 udev->slot_id, setup);
3927 spin_unlock_irqrestore(&xhci->lock, flags);
3928 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3929 "FIXME: allocate a command ring segment");
3932 xhci_ring_cmd_db(xhci);
3933 spin_unlock_irqrestore(&xhci->lock, flags);
3935 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3936 wait_for_completion(command->completion);
3938 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3939 * the SetAddress() "recovery interval" required by USB and aborting the
3940 * command on a timeout.
3942 switch (command->status) {
3943 case COMP_CMD_ABORT:
3945 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3948 case COMP_CTX_STATE:
3950 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3951 act, udev->slot_id);
3955 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3959 dev_warn(&udev->dev,
3960 "ERROR: Incompatible device for setup %s command\n", act);
3964 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3965 "Successful setup %s command", act);
3969 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3970 act, command->status);
3971 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3972 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3973 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3979 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3980 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3981 "Op regs DCBAA ptr = %#016llx", temp_64);
3982 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3983 "Slot ID %d dcbaa entry @%p = %#016llx",
3985 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3986 (unsigned long long)
3987 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3988 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3989 "Output Context DMA address = %#08llx",
3990 (unsigned long long)virt_dev->out_ctx->dma);
3991 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3992 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3993 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3994 le32_to_cpu(slot_ctx->dev_info) >> 27);
3995 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3996 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3998 * USB core uses address 1 for the roothubs, so we add one to the
3999 * address given back to us by the HC.
4001 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4002 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4003 le32_to_cpu(slot_ctx->dev_info) >> 27);
4004 /* Zero the input context control for later use */
4005 ctrl_ctx->add_flags = 0;
4006 ctrl_ctx->drop_flags = 0;
4008 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4009 "Internal device address = %d",
4010 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4012 mutex_unlock(&xhci->mutex);
4017 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4019 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4022 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4024 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4028 * Transfer the port index into real index in the HW port status
4029 * registers. Caculate offset between the port's PORTSC register
4030 * and port status base. Divide the number of per port register
4031 * to get the real index. The raw port number bases 1.
4033 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4035 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4036 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
4037 __le32 __iomem *addr;
4040 if (hcd->speed < HCD_USB3)
4041 addr = xhci->usb2_ports[port1 - 1];
4043 addr = xhci->usb3_ports[port1 - 1];
4045 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
4050 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4051 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4053 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4054 struct usb_device *udev, u16 max_exit_latency)
4056 struct xhci_virt_device *virt_dev;
4057 struct xhci_command *command;
4058 struct xhci_input_control_ctx *ctrl_ctx;
4059 struct xhci_slot_ctx *slot_ctx;
4060 unsigned long flags;
4063 spin_lock_irqsave(&xhci->lock, flags);
4065 virt_dev = xhci->devs[udev->slot_id];
4068 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4069 * xHC was re-initialized. Exit latency will be set later after
4070 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4073 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4074 spin_unlock_irqrestore(&xhci->lock, flags);
4078 /* Attempt to issue an Evaluate Context command to change the MEL. */
4079 command = xhci->lpm_command;
4080 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4082 spin_unlock_irqrestore(&xhci->lock, flags);
4083 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4088 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4089 spin_unlock_irqrestore(&xhci->lock, flags);
4091 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4092 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4093 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4094 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4095 slot_ctx->dev_state = 0;
4097 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4098 "Set up evaluate context for LPM MEL change.");
4099 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4100 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4102 /* Issue and wait for the evaluate context command. */
4103 ret = xhci_configure_endpoint(xhci, udev, command,
4105 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4106 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4109 spin_lock_irqsave(&xhci->lock, flags);
4110 virt_dev->current_mel = max_exit_latency;
4111 spin_unlock_irqrestore(&xhci->lock, flags);
4118 /* BESL to HIRD Encoding array for USB2 LPM */
4119 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4120 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4122 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4123 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4124 struct usb_device *udev)
4126 int u2del, besl, besl_host;
4127 int besl_device = 0;
4130 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4131 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4133 if (field & USB_BESL_SUPPORT) {
4134 for (besl_host = 0; besl_host < 16; besl_host++) {
4135 if (xhci_besl_encoding[besl_host] >= u2del)
4138 /* Use baseline BESL value as default */
4139 if (field & USB_BESL_BASELINE_VALID)
4140 besl_device = USB_GET_BESL_BASELINE(field);
4141 else if (field & USB_BESL_DEEP_VALID)
4142 besl_device = USB_GET_BESL_DEEP(field);
4147 besl_host = (u2del - 51) / 75 + 1;
4150 besl = besl_host + besl_device;
4157 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4158 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4165 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4167 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4168 l1 = udev->l1_params.timeout / 256;
4170 /* device has preferred BESLD */
4171 if (field & USB_BESL_DEEP_VALID) {
4172 besld = USB_GET_BESL_DEEP(field);
4176 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4179 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4180 struct usb_device *udev, int enable)
4182 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4183 __le32 __iomem **port_array;
4184 __le32 __iomem *pm_addr, *hlpm_addr;
4185 u32 pm_val, hlpm_val, field;
4186 unsigned int port_num;
4187 unsigned long flags;
4188 int hird, exit_latency;
4191 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4195 if (!udev->parent || udev->parent->parent ||
4196 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4199 if (udev->usb2_hw_lpm_capable != 1)
4202 spin_lock_irqsave(&xhci->lock, flags);
4204 port_array = xhci->usb2_ports;
4205 port_num = udev->portnum - 1;
4206 pm_addr = port_array[port_num] + PORTPMSC;
4207 pm_val = readl(pm_addr);
4208 hlpm_addr = port_array[port_num] + PORTHLPMC;
4210 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4211 enable ? "enable" : "disable", port_num + 1);
4214 /* Host supports BESL timeout instead of HIRD */
4215 if (udev->usb2_hw_lpm_besl_capable) {
4216 /* if device doesn't have a preferred BESL value use a
4217 * default one which works with mixed HIRD and BESL
4218 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4220 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4221 if ((field & USB_BESL_SUPPORT) &&
4222 (field & USB_BESL_BASELINE_VALID))
4223 hird = USB_GET_BESL_BASELINE(field);
4225 hird = udev->l1_params.besl;
4227 exit_latency = xhci_besl_encoding[hird];
4228 spin_unlock_irqrestore(&xhci->lock, flags);
4230 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4231 * input context for link powermanagement evaluate
4232 * context commands. It is protected by hcd->bandwidth
4233 * mutex and is shared by all devices. We need to set
4234 * the max ext latency in USB 2 BESL LPM as well, so
4235 * use the same mutex and xhci_change_max_exit_latency()
4237 mutex_lock(hcd->bandwidth_mutex);
4238 ret = xhci_change_max_exit_latency(xhci, udev,
4240 mutex_unlock(hcd->bandwidth_mutex);
4244 spin_lock_irqsave(&xhci->lock, flags);
4246 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4247 writel(hlpm_val, hlpm_addr);
4251 hird = xhci_calculate_hird_besl(xhci, udev);
4254 pm_val &= ~PORT_HIRD_MASK;
4255 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4256 writel(pm_val, pm_addr);
4257 pm_val = readl(pm_addr);
4259 writel(pm_val, pm_addr);
4263 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4264 writel(pm_val, pm_addr);
4267 if (udev->usb2_hw_lpm_besl_capable) {
4268 spin_unlock_irqrestore(&xhci->lock, flags);
4269 mutex_lock(hcd->bandwidth_mutex);
4270 xhci_change_max_exit_latency(xhci, udev, 0);
4271 mutex_unlock(hcd->bandwidth_mutex);
4272 readl_poll_timeout(port_array[port_num], pm_val,
4273 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4279 spin_unlock_irqrestore(&xhci->lock, flags);
4283 /* check if a usb2 port supports a given extened capability protocol
4284 * only USB2 ports extended protocol capability values are cached.
4285 * Return 1 if capability is supported
4287 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4288 unsigned capability)
4290 u32 port_offset, port_count;
4293 for (i = 0; i < xhci->num_ext_caps; i++) {
4294 if (xhci->ext_caps[i] & capability) {
4295 /* port offsets starts at 1 */
4296 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4297 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4298 if (port >= port_offset &&
4299 port < port_offset + port_count)
4306 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4308 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4309 int portnum = udev->portnum - 1;
4311 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4315 /* we only support lpm for non-hub device connected to root hub yet */
4316 if (!udev->parent || udev->parent->parent ||
4317 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4320 if (xhci->hw_lpm_support == 1 &&
4321 xhci_check_usb2_port_capability(
4322 xhci, portnum, XHCI_HLC)) {
4323 udev->usb2_hw_lpm_capable = 1;
4324 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4325 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4326 if (xhci_check_usb2_port_capability(xhci, portnum,
4328 udev->usb2_hw_lpm_besl_capable = 1;
4334 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4336 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4337 static unsigned long long xhci_service_interval_to_ns(
4338 struct usb_endpoint_descriptor *desc)
4340 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4343 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4344 enum usb3_link_state state)
4346 unsigned long long sel;
4347 unsigned long long pel;
4348 unsigned int max_sel_pel;
4353 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4354 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4355 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4356 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4360 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4361 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4362 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4366 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4368 return USB3_LPM_DISABLED;
4371 if (sel <= max_sel_pel && pel <= max_sel_pel)
4372 return USB3_LPM_DEVICE_INITIATED;
4374 if (sel > max_sel_pel)
4375 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4376 "due to long SEL %llu ms\n",
4379 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4380 "due to long PEL %llu ms\n",
4382 return USB3_LPM_DISABLED;
4385 /* The U1 timeout should be the maximum of the following values:
4386 * - For control endpoints, U1 system exit latency (SEL) * 3
4387 * - For bulk endpoints, U1 SEL * 5
4388 * - For interrupt endpoints:
4389 * - Notification EPs, U1 SEL * 3
4390 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4391 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4393 static unsigned long long xhci_calculate_intel_u1_timeout(
4394 struct usb_device *udev,
4395 struct usb_endpoint_descriptor *desc)
4397 unsigned long long timeout_ns;
4401 ep_type = usb_endpoint_type(desc);
4403 case USB_ENDPOINT_XFER_CONTROL:
4404 timeout_ns = udev->u1_params.sel * 3;
4406 case USB_ENDPOINT_XFER_BULK:
4407 timeout_ns = udev->u1_params.sel * 5;
4409 case USB_ENDPOINT_XFER_INT:
4410 intr_type = usb_endpoint_interrupt_type(desc);
4411 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4412 timeout_ns = udev->u1_params.sel * 3;
4415 /* Otherwise the calculation is the same as isoc eps */
4416 case USB_ENDPOINT_XFER_ISOC:
4417 timeout_ns = xhci_service_interval_to_ns(desc);
4418 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4419 if (timeout_ns < udev->u1_params.sel * 2)
4420 timeout_ns = udev->u1_params.sel * 2;
4429 /* Returns the hub-encoded U1 timeout value. */
4430 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4431 struct usb_device *udev,
4432 struct usb_endpoint_descriptor *desc)
4434 unsigned long long timeout_ns;
4436 /* Prevent U1 if service interval is shorter than U1 exit latency */
4437 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4438 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4439 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4440 return USB3_LPM_DISABLED;
4444 if (xhci->quirks & XHCI_INTEL_HOST)
4445 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4447 timeout_ns = udev->u1_params.sel;
4449 /* The U1 timeout is encoded in 1us intervals.
4450 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4452 if (timeout_ns == USB3_LPM_DISABLED)
4455 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4457 /* If the necessary timeout value is bigger than what we can set in the
4458 * USB 3.0 hub, we have to disable hub-initiated U1.
4460 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4462 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4463 "due to long timeout %llu ms\n", timeout_ns);
4464 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4467 /* The U2 timeout should be the maximum of:
4468 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4469 * - largest bInterval of any active periodic endpoint (to avoid going
4470 * into lower power link states between intervals).
4471 * - the U2 Exit Latency of the device
4473 static unsigned long long xhci_calculate_intel_u2_timeout(
4474 struct usb_device *udev,
4475 struct usb_endpoint_descriptor *desc)
4477 unsigned long long timeout_ns;
4478 unsigned long long u2_del_ns;
4480 timeout_ns = 10 * 1000 * 1000;
4482 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4483 (xhci_service_interval_to_ns(desc) > timeout_ns))
4484 timeout_ns = xhci_service_interval_to_ns(desc);
4486 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4487 if (u2_del_ns > timeout_ns)
4488 timeout_ns = u2_del_ns;
4493 /* Returns the hub-encoded U2 timeout value. */
4494 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4495 struct usb_device *udev,
4496 struct usb_endpoint_descriptor *desc)
4498 unsigned long long timeout_ns;
4500 /* Prevent U2 if service interval is shorter than U2 exit latency */
4501 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4502 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4503 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4504 return USB3_LPM_DISABLED;
4508 if (xhci->quirks & XHCI_INTEL_HOST)
4509 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4511 timeout_ns = udev->u2_params.sel;
4513 /* The U2 timeout is encoded in 256us intervals */
4514 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4515 /* If the necessary timeout value is bigger than what we can set in the
4516 * USB 3.0 hub, we have to disable hub-initiated U2.
4518 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4520 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4521 "due to long timeout %llu ms\n", timeout_ns);
4522 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4525 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4526 struct usb_device *udev,
4527 struct usb_endpoint_descriptor *desc,
4528 enum usb3_link_state state,
4531 if (state == USB3_LPM_U1)
4532 return xhci_calculate_u1_timeout(xhci, udev, desc);
4533 else if (state == USB3_LPM_U2)
4534 return xhci_calculate_u2_timeout(xhci, udev, desc);
4536 return USB3_LPM_DISABLED;
4539 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4540 struct usb_device *udev,
4541 struct usb_endpoint_descriptor *desc,
4542 enum usb3_link_state state,
4547 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4548 desc, state, timeout);
4550 /* If we found we can't enable hub-initiated LPM, and
4551 * the U1 or U2 exit latency was too high to allow
4552 * device-initiated LPM as well, then we will disable LPM
4553 * for this device, so stop searching any further.
4555 if (alt_timeout == USB3_LPM_DISABLED) {
4556 *timeout = alt_timeout;
4559 if (alt_timeout > *timeout)
4560 *timeout = alt_timeout;
4564 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4565 struct usb_device *udev,
4566 struct usb_host_interface *alt,
4567 enum usb3_link_state state,
4572 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4573 if (xhci_update_timeout_for_endpoint(xhci, udev,
4574 &alt->endpoint[j].desc, state, timeout))
4581 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4582 enum usb3_link_state state)
4584 struct usb_device *parent;
4585 unsigned int num_hubs;
4587 if (state == USB3_LPM_U2)
4590 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4591 for (parent = udev->parent, num_hubs = 0; parent->parent;
4592 parent = parent->parent)
4598 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4599 " below second-tier hub.\n");
4600 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4601 "to decrease power consumption.\n");
4605 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4606 struct usb_device *udev,
4607 enum usb3_link_state state)
4609 if (xhci->quirks & XHCI_INTEL_HOST)
4610 return xhci_check_intel_tier_policy(udev, state);
4615 /* Returns the U1 or U2 timeout that should be enabled.
4616 * If the tier check or timeout setting functions return with a non-zero exit
4617 * code, that means the timeout value has been finalized and we shouldn't look
4618 * at any more endpoints.
4620 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4621 struct usb_device *udev, enum usb3_link_state state)
4623 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4624 struct usb_host_config *config;
4627 u16 timeout = USB3_LPM_DISABLED;
4629 if (state == USB3_LPM_U1)
4631 else if (state == USB3_LPM_U2)
4634 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4639 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4642 /* Gather some information about the currently installed configuration
4643 * and alternate interface settings.
4645 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4649 config = udev->actconfig;
4653 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4654 struct usb_driver *driver;
4655 struct usb_interface *intf = config->interface[i];
4660 /* Check if any currently bound drivers want hub-initiated LPM
4663 if (intf->dev.driver) {
4664 driver = to_usb_driver(intf->dev.driver);
4665 if (driver && driver->disable_hub_initiated_lpm) {
4666 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4667 state_name, driver->name);
4668 timeout = xhci_get_timeout_no_hub_lpm(udev,
4670 if (timeout == USB3_LPM_DISABLED)
4675 /* Not sure how this could happen... */
4676 if (!intf->cur_altsetting)
4679 if (xhci_update_timeout_for_interface(xhci, udev,
4680 intf->cur_altsetting,
4687 static int calculate_max_exit_latency(struct usb_device *udev,
4688 enum usb3_link_state state_changed,
4689 u16 hub_encoded_timeout)
4691 unsigned long long u1_mel_us = 0;
4692 unsigned long long u2_mel_us = 0;
4693 unsigned long long mel_us = 0;
4699 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4700 hub_encoded_timeout == USB3_LPM_DISABLED);
4701 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4702 hub_encoded_timeout == USB3_LPM_DISABLED);
4704 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4705 hub_encoded_timeout != USB3_LPM_DISABLED);
4706 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4707 hub_encoded_timeout != USB3_LPM_DISABLED);
4709 /* If U1 was already enabled and we're not disabling it,
4710 * or we're going to enable U1, account for the U1 max exit latency.
4712 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4714 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4715 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4717 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4719 if (u1_mel_us > u2_mel_us)
4723 /* xHCI host controller max exit latency field is only 16 bits wide. */
4724 if (mel_us > MAX_EXIT) {
4725 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4726 "is too big.\n", mel_us);
4732 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4733 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4734 struct usb_device *udev, enum usb3_link_state state)
4736 struct xhci_hcd *xhci;
4737 u16 hub_encoded_timeout;
4741 xhci = hcd_to_xhci(hcd);
4742 /* The LPM timeout values are pretty host-controller specific, so don't
4743 * enable hub-initiated timeouts unless the vendor has provided
4744 * information about their timeout algorithm.
4746 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4747 !xhci->devs[udev->slot_id])
4748 return USB3_LPM_DISABLED;
4750 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4751 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4753 /* Max Exit Latency is too big, disable LPM. */
4754 hub_encoded_timeout = USB3_LPM_DISABLED;
4758 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4761 return hub_encoded_timeout;
4764 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4765 struct usb_device *udev, enum usb3_link_state state)
4767 struct xhci_hcd *xhci;
4770 xhci = hcd_to_xhci(hcd);
4771 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4772 !xhci->devs[udev->slot_id])
4775 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4776 return xhci_change_max_exit_latency(xhci, udev, mel);
4778 #else /* CONFIG_PM */
4780 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4781 struct usb_device *udev, int enable)
4786 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4791 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4792 struct usb_device *udev, enum usb3_link_state state)
4794 return USB3_LPM_DISABLED;
4797 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4798 struct usb_device *udev, enum usb3_link_state state)
4802 #endif /* CONFIG_PM */
4804 /*-------------------------------------------------------------------------*/
4806 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4807 * internal data structures for the device.
4809 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4810 struct usb_tt *tt, gfp_t mem_flags)
4812 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4813 struct xhci_virt_device *vdev;
4814 struct xhci_command *config_cmd;
4815 struct xhci_input_control_ctx *ctrl_ctx;
4816 struct xhci_slot_ctx *slot_ctx;
4817 unsigned long flags;
4818 unsigned think_time;
4821 /* Ignore root hubs */
4825 vdev = xhci->devs[hdev->slot_id];
4827 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4830 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4832 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4835 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4837 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4839 xhci_free_command(xhci, config_cmd);
4843 spin_lock_irqsave(&xhci->lock, flags);
4844 if (hdev->speed == USB_SPEED_HIGH &&
4845 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4846 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4847 xhci_free_command(xhci, config_cmd);
4848 spin_unlock_irqrestore(&xhci->lock, flags);
4852 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4853 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4854 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4855 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4857 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4858 * but it may be already set to 1 when setup an xHCI virtual
4859 * device, so clear it anyway.
4862 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4863 else if (hdev->speed == USB_SPEED_FULL)
4864 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4866 if (xhci->hci_version > 0x95) {
4867 xhci_dbg(xhci, "xHCI version %x needs hub "
4868 "TT think time and number of ports\n",
4869 (unsigned int) xhci->hci_version);
4870 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4871 /* Set TT think time - convert from ns to FS bit times.
4872 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4873 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4875 * xHCI 1.0: this field shall be 0 if the device is not a
4878 think_time = tt->think_time;
4879 if (think_time != 0)
4880 think_time = (think_time / 666) - 1;
4881 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4882 slot_ctx->tt_info |=
4883 cpu_to_le32(TT_THINK_TIME(think_time));
4885 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4886 "TT think time or number of ports\n",
4887 (unsigned int) xhci->hci_version);
4889 slot_ctx->dev_state = 0;
4890 spin_unlock_irqrestore(&xhci->lock, flags);
4892 xhci_dbg(xhci, "Set up %s for hub device.\n",
4893 (xhci->hci_version > 0x95) ?
4894 "configure endpoint" : "evaluate context");
4895 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4896 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4898 /* Issue and wait for the configure endpoint or
4899 * evaluate context command.
4901 if (xhci->hci_version > 0x95)
4902 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4905 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4908 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4909 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4911 xhci_free_command(xhci, config_cmd);
4915 int xhci_get_frame(struct usb_hcd *hcd)
4917 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4918 /* EHCI mods by the periodic size. Why? */
4919 return readl(&xhci->run_regs->microframe_index) >> 3;
4922 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4924 struct xhci_hcd *xhci;
4925 struct device *dev = hcd->self.controller;
4928 /* Accept arbitrarily long scatter-gather lists */
4929 hcd->self.sg_tablesize = ~0;
4931 /* support to build packet from discontinuous buffers */
4932 hcd->self.no_sg_constraint = 1;
4934 /* XHCI controllers don't stop the ep queue on short packets :| */
4935 hcd->self.no_stop_on_short = 1;
4937 xhci = hcd_to_xhci(hcd);
4939 if (usb_hcd_is_primary_hcd(hcd)) {
4940 xhci->main_hcd = hcd;
4941 /* Mark the first roothub as being USB 2.0.
4942 * The xHCI driver will register the USB 3.0 roothub.
4944 hcd->speed = HCD_USB2;
4945 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4947 * USB 2.0 roothub under xHCI has an integrated TT,
4948 * (rate matching hub) as opposed to having an OHCI/UHCI
4949 * companion controller.
4953 /* Some 3.1 hosts return sbrn 0x30, can't rely on sbrn alone */
4954 if (xhci->sbrn == 0x31 || xhci->usb3_rhub.min_rev >= 1) {
4955 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4956 hcd->speed = HCD_USB31;
4957 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
4959 /* xHCI private pointer was set in xhci_pci_probe for the second
4960 * registered roothub.
4965 mutex_init(&xhci->mutex);
4966 xhci->cap_regs = hcd->regs;
4967 xhci->op_regs = hcd->regs +
4968 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4969 xhci->run_regs = hcd->regs +
4970 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4971 /* Cache read-only capability registers */
4972 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4973 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4974 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4975 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4976 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4977 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4978 if (xhci->hci_version > 0x100)
4979 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4980 xhci_print_registers(xhci);
4982 xhci->quirks |= quirks;
4984 get_quirks(dev, xhci);
4986 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4987 * success event after a short transfer. This quirk will ignore such
4990 if (xhci->hci_version > 0x96)
4991 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4993 /* Make sure the HC is halted. */
4994 retval = xhci_halt(xhci);
4998 xhci_dbg(xhci, "Resetting HCD\n");
4999 /* Reset the internal HC memory state and registers. */
5000 retval = xhci_reset(xhci);
5003 xhci_dbg(xhci, "Reset complete\n");
5006 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5007 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5008 * address memory pointers actually. So, this driver clears the AC64
5009 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5010 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5012 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5013 xhci->hcc_params &= ~BIT(0);
5015 /* Set dma_mask and coherent_dma_mask to 64-bits,
5016 * if xHC supports 64-bit addressing */
5017 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5018 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5019 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5020 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5023 * This is to avoid error in cases where a 32-bit USB
5024 * controller is used on a 64-bit capable system.
5026 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5029 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5030 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5033 xhci_dbg(xhci, "Calling HCD init\n");
5034 /* Initialize HCD and host controller data structures. */
5035 retval = xhci_init(hcd);
5038 xhci_dbg(xhci, "Called HCD init\n");
5040 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
5041 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5045 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5047 static const struct hc_driver xhci_hc_driver = {
5048 .description = "xhci-hcd",
5049 .product_desc = "xHCI Host Controller",
5050 .hcd_priv_size = sizeof(struct xhci_hcd),
5053 * generic hardware linkage
5056 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
5059 * basic lifecycle operations
5061 .reset = NULL, /* set in xhci_init_driver() */
5064 .shutdown = xhci_shutdown,
5067 * managing i/o requests and associated device resources
5069 .urb_enqueue = xhci_urb_enqueue,
5070 .urb_dequeue = xhci_urb_dequeue,
5071 .alloc_dev = xhci_alloc_dev,
5072 .free_dev = xhci_free_dev,
5073 .alloc_streams = xhci_alloc_streams,
5074 .free_streams = xhci_free_streams,
5075 .add_endpoint = xhci_add_endpoint,
5076 .drop_endpoint = xhci_drop_endpoint,
5077 .endpoint_reset = xhci_endpoint_reset,
5078 .check_bandwidth = xhci_check_bandwidth,
5079 .reset_bandwidth = xhci_reset_bandwidth,
5080 .address_device = xhci_address_device,
5081 .enable_device = xhci_enable_device,
5082 .update_hub_device = xhci_update_hub_device,
5083 .reset_device = xhci_discover_or_reset_device,
5086 * scheduling support
5088 .get_frame_number = xhci_get_frame,
5093 .hub_control = xhci_hub_control,
5094 .hub_status_data = xhci_hub_status_data,
5095 .bus_suspend = xhci_bus_suspend,
5096 .bus_resume = xhci_bus_resume,
5099 * call back when device connected and addressed
5101 .update_device = xhci_update_device,
5102 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5103 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5104 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5105 .find_raw_port_number = xhci_find_raw_port_number,
5108 void xhci_init_driver(struct hc_driver *drv,
5109 const struct xhci_driver_overrides *over)
5113 /* Copy the generic table to drv then apply the overrides */
5114 *drv = xhci_hc_driver;
5117 drv->hcd_priv_size += over->extra_priv_size;
5119 drv->reset = over->reset;
5121 drv->start = over->start;
5124 EXPORT_SYMBOL_GPL(xhci_init_driver);
5126 MODULE_DESCRIPTION(DRIVER_DESC);
5127 MODULE_AUTHOR(DRIVER_AUTHOR);
5128 MODULE_LICENSE("GPL");
5130 static int __init xhci_hcd_init(void)
5133 * Check the compiler generated sizes of structures that must be laid
5134 * out in specific ways for hardware access.
5136 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5137 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5138 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5139 /* xhci_device_control has eight fields, and also
5140 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5142 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5143 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5144 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5145 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5146 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5147 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5148 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5157 * If an init function is provided, an exit function must also be provided
5158 * to allow module unload.
5160 static void __exit xhci_hcd_fini(void) { }
5162 module_init(xhci_hcd_init);
5163 module_exit(xhci_hcd_fini);