2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/iopoll.h>
25 #include <linux/irq.h>
26 #include <linux/log2.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/slab.h>
30 #include <linux/dmi.h>
31 #include <linux/dma-mapping.h>
34 #include "xhci-trace.h"
37 #define DRIVER_AUTHOR "Sarah Sharp"
38 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
40 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
42 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
43 static int link_quirk;
44 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
45 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
47 static unsigned long long quirks;
48 module_param(quirks, ullong, S_IRUGO);
49 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
51 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
53 struct xhci_segment *seg = ring->first_seg;
55 if (!td || !td->start_seg)
58 if (seg == td->start_seg)
61 } while (seg && seg != ring->first_seg);
67 * xhci_handshake - spin reading hc until handshake completes or fails
68 * @ptr: address of hc register to be read
69 * @mask: bits to look at in result of read
70 * @done: value of those bits when handshake succeeds
71 * @usec: timeout in microseconds
73 * Returns negative errno, or zero on success
75 * Success happens when the "mask" bits have the specified value (hardware
76 * handshake done). There are two failure modes: "usec" have passed (major
77 * hardware flakeout), or the register reads as all-ones (hardware removed).
79 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
84 ret = readl_poll_timeout_atomic(ptr, result,
85 (result & mask) == done ||
88 if (result == U32_MAX) /* card removed */
95 * Disable interrupts and begin the xHCI halting process.
97 void xhci_quiesce(struct xhci_hcd *xhci)
104 halted = readl(&xhci->op_regs->status) & STS_HALT;
108 cmd = readl(&xhci->op_regs->command);
110 writel(cmd, &xhci->op_regs->command);
114 * Force HC into halt state.
116 * Disable any IRQs and clear the run/stop bit.
117 * HC will complete any current and actively pipelined transactions, and
118 * should halt within 16 ms of the run/stop bit being cleared.
119 * Read HC Halted bit in the status register to see when the HC is finished.
121 int xhci_halt(struct xhci_hcd *xhci)
124 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
127 ret = xhci_handshake(&xhci->op_regs->status,
128 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
130 xhci_warn(xhci, "Host halt failed, %d\n", ret);
133 xhci->xhc_state |= XHCI_STATE_HALTED;
134 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
139 * Set the run bit and wait for the host to be running.
141 int xhci_start(struct xhci_hcd *xhci)
146 temp = readl(&xhci->op_regs->command);
148 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
150 writel(temp, &xhci->op_regs->command);
153 * Wait for the HCHalted Status bit to be 0 to indicate the host is
156 ret = xhci_handshake(&xhci->op_regs->status,
157 STS_HALT, 0, XHCI_MAX_HALT_USEC);
158 if (ret == -ETIMEDOUT)
159 xhci_err(xhci, "Host took too long to start, "
160 "waited %u microseconds.\n",
163 /* clear state flags. Including dying, halted or removing */
172 * This resets pipelines, timers, counters, state machines, etc.
173 * Transactions will be terminated immediately, and operational registers
174 * will be set to their defaults.
176 int xhci_reset(struct xhci_hcd *xhci)
182 state = readl(&xhci->op_regs->status);
184 if (state == ~(u32)0) {
185 xhci_warn(xhci, "Host not accessible, reset failed.\n");
189 if ((state & STS_HALT) == 0) {
190 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
194 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
195 command = readl(&xhci->op_regs->command);
196 command |= CMD_RESET;
197 writel(command, &xhci->op_regs->command);
199 /* Existing Intel xHCI controllers require a delay of 1 mS,
200 * after setting the CMD_RESET bit, and before accessing any
201 * HC registers. This allows the HC to complete the
202 * reset operation and be ready for HC register access.
203 * Without this delay, the subsequent HC register access,
204 * may result in a system hang very rarely.
206 if (xhci->quirks & XHCI_INTEL_HOST)
209 ret = xhci_handshake(&xhci->op_regs->command,
210 CMD_RESET, 0, 10 * 1000 * 1000);
214 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
215 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
217 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
218 "Wait for controller to be ready for doorbell rings");
220 * xHCI cannot write to any doorbells or operational registers other
221 * than status until the "Controller Not Ready" flag is cleared.
223 ret = xhci_handshake(&xhci->op_regs->status,
224 STS_CNR, 0, 10 * 1000 * 1000);
226 for (i = 0; i < 2; i++) {
227 xhci->bus_state[i].port_c_suspend = 0;
228 xhci->bus_state[i].suspended_ports = 0;
229 xhci->bus_state[i].resuming_ports = 0;
236 #ifdef CONFIG_USB_PCI
240 static int xhci_setup_msi(struct xhci_hcd *xhci)
244 * TODO:Check with MSI Soc for sysdev
246 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
248 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
250 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
251 "failed to allocate MSI entry");
255 ret = request_irq(pdev->irq, xhci_msi_irq,
256 0, "xhci_hcd", xhci_to_hcd(xhci));
258 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
259 "disable MSI interrupt");
260 pci_free_irq_vectors(pdev);
269 static int xhci_setup_msix(struct xhci_hcd *xhci)
272 struct usb_hcd *hcd = xhci_to_hcd(xhci);
273 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
276 * calculate number of msi-x vectors supported.
277 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
278 * with max number of interrupters based on the xhci HCSPARAMS1.
279 * - num_online_cpus: maximum msi-x vectors per CPUs core.
280 * Add additional 1 vector to ensure always available interrupt.
282 xhci->msix_count = min(num_online_cpus() + 1,
283 HCS_MAX_INTRS(xhci->hcs_params1));
285 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
288 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
289 "Failed to enable MSI-X");
293 for (i = 0; i < xhci->msix_count; i++) {
294 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
295 "xhci_hcd", xhci_to_hcd(xhci));
300 hcd->msix_enabled = 1;
304 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
306 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
307 pci_free_irq_vectors(pdev);
311 /* Free any IRQs and disable MSI-X */
312 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
314 struct usb_hcd *hcd = xhci_to_hcd(xhci);
315 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
317 if (xhci->quirks & XHCI_PLAT)
320 /* return if using legacy interrupt */
324 if (hcd->msix_enabled) {
327 for (i = 0; i < xhci->msix_count; i++)
328 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
330 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
333 pci_free_irq_vectors(pdev);
334 hcd->msix_enabled = 0;
337 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
339 struct usb_hcd *hcd = xhci_to_hcd(xhci);
341 if (hcd->msix_enabled) {
342 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
345 for (i = 0; i < xhci->msix_count; i++)
346 synchronize_irq(pci_irq_vector(pdev, i));
350 static int xhci_try_enable_msi(struct usb_hcd *hcd)
352 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
353 struct pci_dev *pdev;
356 /* The xhci platform device has set up IRQs through usb_add_hcd. */
357 if (xhci->quirks & XHCI_PLAT)
360 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
362 * Some Fresco Logic host controllers advertise MSI, but fail to
363 * generate interrupts. Don't even try to enable MSI.
365 if (xhci->quirks & XHCI_BROKEN_MSI)
368 /* unregister the legacy interrupt */
370 free_irq(hcd->irq, hcd);
373 ret = xhci_setup_msix(xhci);
375 /* fall back to msi*/
376 ret = xhci_setup_msi(xhci);
379 hcd->msi_enabled = 1;
384 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
389 if (!strlen(hcd->irq_descr))
390 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
391 hcd->driver->description, hcd->self.busnum);
393 /* fall back to legacy interrupt*/
394 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
395 hcd->irq_descr, hcd);
397 xhci_err(xhci, "request interrupt %d failed\n",
401 hcd->irq = pdev->irq;
407 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
412 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
416 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
422 static void compliance_mode_recovery(unsigned long arg)
424 struct xhci_hcd *xhci;
429 xhci = (struct xhci_hcd *)arg;
431 for (i = 0; i < xhci->num_usb3_ports; i++) {
432 temp = readl(xhci->usb3_ports[i]);
433 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
435 * Compliance Mode Detected. Letting USB Core
436 * handle the Warm Reset
438 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
439 "Compliance mode detected->port %d",
441 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
442 "Attempting compliance mode recovery");
443 hcd = xhci->shared_hcd;
445 if (hcd->state == HC_STATE_SUSPENDED)
446 usb_hcd_resume_root_hub(hcd);
448 usb_hcd_poll_rh_status(hcd);
452 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
453 mod_timer(&xhci->comp_mode_recovery_timer,
454 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
458 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
459 * that causes ports behind that hardware to enter compliance mode sometimes.
460 * The quirk creates a timer that polls every 2 seconds the link state of
461 * each host controller's port and recovers it by issuing a Warm reset
462 * if Compliance mode is detected, otherwise the port will become "dead" (no
463 * device connections or disconnections will be detected anymore). Becasue no
464 * status event is generated when entering compliance mode (per xhci spec),
465 * this quirk is needed on systems that have the failing hardware installed.
467 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
469 xhci->port_status_u0 = 0;
470 setup_timer(&xhci->comp_mode_recovery_timer,
471 compliance_mode_recovery, (unsigned long)xhci);
472 xhci->comp_mode_recovery_timer.expires = jiffies +
473 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
475 add_timer(&xhci->comp_mode_recovery_timer);
476 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
477 "Compliance mode recovery timer initialized");
481 * This function identifies the systems that have installed the SN65LVPE502CP
482 * USB3.0 re-driver and that need the Compliance Mode Quirk.
484 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
486 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
488 const char *dmi_product_name, *dmi_sys_vendor;
490 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
491 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
492 if (!dmi_product_name || !dmi_sys_vendor)
495 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
498 if (strstr(dmi_product_name, "Z420") ||
499 strstr(dmi_product_name, "Z620") ||
500 strstr(dmi_product_name, "Z820") ||
501 strstr(dmi_product_name, "Z1 Workstation"))
507 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
509 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
514 * Initialize memory for HCD and xHC (one-time init).
516 * Program the PAGESIZE register, initialize the device context array, create
517 * device contexts (?), set up a command ring segment (or two?), create event
518 * ring (one for now).
520 static int xhci_init(struct usb_hcd *hcd)
522 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
525 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
526 spin_lock_init(&xhci->lock);
527 if (xhci->hci_version == 0x95 && link_quirk) {
528 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
529 "QUIRK: Not clearing Link TRB chain bits.");
530 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
532 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
533 "xHCI doesn't need link TRB QUIRK");
535 retval = xhci_mem_init(xhci, GFP_KERNEL);
536 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
538 /* Initializing Compliance Mode Recovery Data If Needed */
539 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
540 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
541 compliance_mode_recovery_timer_init(xhci);
547 /*-------------------------------------------------------------------------*/
550 static int xhci_run_finished(struct xhci_hcd *xhci)
552 if (xhci_start(xhci)) {
556 xhci->shared_hcd->state = HC_STATE_RUNNING;
557 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
559 if (xhci->quirks & XHCI_NEC_HOST)
560 xhci_ring_cmd_db(xhci);
562 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
563 "Finished xhci_run for USB3 roothub");
568 * Start the HC after it was halted.
570 * This function is called by the USB core when the HC driver is added.
571 * Its opposite is xhci_stop().
573 * xhci_init() must be called once before this function can be called.
574 * Reset the HC, enable device slot contexts, program DCBAAP, and
575 * set command ring pointer and event ring pointer.
577 * Setup MSI-X vectors and enable interrupts.
579 int xhci_run(struct usb_hcd *hcd)
584 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
586 /* Start the xHCI host controller running only after the USB 2.0 roothub
590 hcd->uses_new_polling = 1;
591 if (!usb_hcd_is_primary_hcd(hcd))
592 return xhci_run_finished(xhci);
594 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
596 ret = xhci_try_enable_msi(hcd);
600 xhci_dbg_cmd_ptrs(xhci);
602 xhci_dbg(xhci, "ERST memory map follows:\n");
603 xhci_dbg_erst(xhci, &xhci->erst);
604 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
605 temp_64 &= ~ERST_PTR_MASK;
606 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
607 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
609 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
610 "// Set the interrupt modulation register");
611 temp = readl(&xhci->ir_set->irq_control);
612 temp &= ~ER_IRQ_INTERVAL_MASK;
614 * the increment interval is 8 times as much as that defined
615 * in xHCI spec on MTK's controller
617 temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
618 writel(temp, &xhci->ir_set->irq_control);
620 /* Set the HCD state before we enable the irqs */
621 temp = readl(&xhci->op_regs->command);
623 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
624 "// Enable interrupts, cmd = 0x%x.", temp);
625 writel(temp, &xhci->op_regs->command);
627 temp = readl(&xhci->ir_set->irq_pending);
628 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
629 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
630 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
631 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
632 xhci_print_ir_set(xhci, 0);
634 if (xhci->quirks & XHCI_NEC_HOST) {
635 struct xhci_command *command;
637 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
641 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
642 TRB_TYPE(TRB_NEC_GET_FW));
644 xhci_free_command(xhci, command);
646 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
647 "Finished xhci_run for USB2 roothub");
650 EXPORT_SYMBOL_GPL(xhci_run);
655 * This function is called by the USB core when the HC driver is removed.
656 * Its opposite is xhci_run().
658 * Disable device contexts, disable IRQs, and quiesce the HC.
659 * Reset the HC, finish any completed transactions, and cleanup memory.
661 static void xhci_stop(struct usb_hcd *hcd)
664 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
666 mutex_lock(&xhci->mutex);
668 /* Only halt host and free memory after both hcds are removed */
669 if (!usb_hcd_is_primary_hcd(hcd)) {
670 mutex_unlock(&xhci->mutex);
674 spin_lock_irq(&xhci->lock);
675 xhci->xhc_state |= XHCI_STATE_HALTED;
676 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
679 spin_unlock_irq(&xhci->lock);
681 xhci_cleanup_msix(xhci);
683 /* Deleting Compliance Mode Recovery Timer */
684 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
685 (!(xhci_all_ports_seen_u0(xhci)))) {
686 del_timer_sync(&xhci->comp_mode_recovery_timer);
687 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
688 "%s: compliance mode recovery timer deleted",
692 if (xhci->quirks & XHCI_AMD_PLL_FIX)
695 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
696 "// Disabling event ring interrupts");
697 temp = readl(&xhci->op_regs->status);
698 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
699 temp = readl(&xhci->ir_set->irq_pending);
700 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
701 xhci_print_ir_set(xhci, 0);
703 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
704 xhci_mem_cleanup(xhci);
705 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
706 "xhci_stop completed - status = %x",
707 readl(&xhci->op_regs->status));
708 mutex_unlock(&xhci->mutex);
712 * Shutdown HC (not bus-specific)
714 * This is called when the machine is rebooting or halting. We assume that the
715 * machine will be powered off, and the HC's internal state will be reset.
716 * Don't bother to free memory.
718 * This will only ever be called with the main usb_hcd (the USB3 roothub).
720 void xhci_shutdown(struct usb_hcd *hcd)
722 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
724 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
725 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
727 spin_lock_irq(&xhci->lock);
729 /* Workaround for spurious wakeups at shutdown with HSW */
730 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
732 spin_unlock_irq(&xhci->lock);
734 xhci_cleanup_msix(xhci);
736 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
737 "xhci_shutdown completed - status = %x",
738 readl(&xhci->op_regs->status));
740 EXPORT_SYMBOL_GPL(xhci_shutdown);
743 static void xhci_save_registers(struct xhci_hcd *xhci)
745 xhci->s3.command = readl(&xhci->op_regs->command);
746 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
747 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
748 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
749 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
750 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
751 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
752 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
753 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
756 static void xhci_restore_registers(struct xhci_hcd *xhci)
758 writel(xhci->s3.command, &xhci->op_regs->command);
759 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
760 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
761 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
762 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
763 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
764 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
765 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
766 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
769 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
773 /* step 2: initialize command ring buffer */
774 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
775 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
776 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
777 xhci->cmd_ring->dequeue) &
778 (u64) ~CMD_RING_RSVD_BITS) |
779 xhci->cmd_ring->cycle_state;
780 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
781 "// Setting command ring address to 0x%llx",
782 (long unsigned long) val_64);
783 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
787 * The whole command ring must be cleared to zero when we suspend the host.
789 * The host doesn't save the command ring pointer in the suspend well, so we
790 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
791 * aligned, because of the reserved bits in the command ring dequeue pointer
792 * register. Therefore, we can't just set the dequeue pointer back in the
793 * middle of the ring (TRBs are 16-byte aligned).
795 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
797 struct xhci_ring *ring;
798 struct xhci_segment *seg;
800 ring = xhci->cmd_ring;
804 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
805 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
806 cpu_to_le32(~TRB_CYCLE);
808 } while (seg != ring->deq_seg);
810 /* Reset the software enqueue and dequeue pointers */
811 ring->deq_seg = ring->first_seg;
812 ring->dequeue = ring->first_seg->trbs;
813 ring->enq_seg = ring->deq_seg;
814 ring->enqueue = ring->dequeue;
816 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
818 * Ring is now zeroed, so the HW should look for change of ownership
819 * when the cycle bit is set to 1.
821 ring->cycle_state = 1;
824 * Reset the hardware dequeue pointer.
825 * Yes, this will need to be re-written after resume, but we're paranoid
826 * and want to make sure the hardware doesn't access bogus memory
827 * because, say, the BIOS or an SMI started the host without changing
828 * the command ring pointers.
830 xhci_set_cmd_ring_deq(xhci);
833 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
836 __le32 __iomem **port_array;
840 spin_lock_irqsave(&xhci->lock, flags);
842 /* disable usb3 ports Wake bits */
843 port_index = xhci->num_usb3_ports;
844 port_array = xhci->usb3_ports;
845 while (port_index--) {
846 t1 = readl(port_array[port_index]);
847 t1 = xhci_port_state_to_neutral(t1);
848 t2 = t1 & ~PORT_WAKE_BITS;
850 writel(t2, port_array[port_index]);
853 /* disable usb2 ports Wake bits */
854 port_index = xhci->num_usb2_ports;
855 port_array = xhci->usb2_ports;
856 while (port_index--) {
857 t1 = readl(port_array[port_index]);
858 t1 = xhci_port_state_to_neutral(t1);
859 t2 = t1 & ~PORT_WAKE_BITS;
861 writel(t2, port_array[port_index]);
864 spin_unlock_irqrestore(&xhci->lock, flags);
867 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
869 __le32 __iomem **port_array;
874 status = readl(&xhci->op_regs->status);
875 if (status & STS_EINT)
878 * Checking STS_EINT is not enough as there is a lag between a change
879 * bit being set and the Port Status Change Event that it generated
880 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
883 port_index = xhci->num_usb2_ports;
884 port_array = xhci->usb2_ports;
885 while (port_index--) {
886 portsc = readl(port_array[port_index]);
887 if (portsc & PORT_CHANGE_MASK ||
888 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
891 port_index = xhci->num_usb3_ports;
892 port_array = xhci->usb3_ports;
893 while (port_index--) {
894 portsc = readl(port_array[port_index]);
895 if (portsc & PORT_CHANGE_MASK ||
896 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
903 * Stop HC (not bus-specific)
905 * This is called when the machine transition into S3/S4 mode.
908 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
911 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
912 struct usb_hcd *hcd = xhci_to_hcd(xhci);
919 if (hcd->state != HC_STATE_SUSPENDED ||
920 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
923 /* Clear root port wake on bits if wakeup not allowed. */
925 xhci_disable_port_wake_on_bits(xhci);
927 /* Don't poll the roothubs on bus suspend. */
928 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
929 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
930 del_timer_sync(&hcd->rh_timer);
931 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
932 del_timer_sync(&xhci->shared_hcd->rh_timer);
934 if (xhci->quirks & XHCI_SUSPEND_DELAY)
935 usleep_range(1000, 1500);
937 spin_lock_irq(&xhci->lock);
938 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
939 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
940 /* step 1: stop endpoint */
941 /* skipped assuming that port suspend has done */
943 /* step 2: clear Run/Stop bit */
944 command = readl(&xhci->op_regs->command);
946 writel(command, &xhci->op_regs->command);
948 /* Some chips from Fresco Logic need an extraordinary delay */
949 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
951 if (xhci_handshake(&xhci->op_regs->status,
952 STS_HALT, STS_HALT, delay)) {
953 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
954 spin_unlock_irq(&xhci->lock);
957 xhci_clear_command_ring(xhci);
959 /* step 3: save registers */
960 xhci_save_registers(xhci);
962 /* step 4: set CSS flag */
963 command = readl(&xhci->op_regs->command);
965 writel(command, &xhci->op_regs->command);
966 xhci->broken_suspend = 0;
967 if (xhci_handshake(&xhci->op_regs->status,
968 STS_SAVE, 0, 20 * 1000)) {
970 * AMD SNPS xHC 3.0 occasionally does not clear the
971 * SSS bit of USBSTS and when driver tries to poll
972 * to see if the xHC clears BIT(8) which never happens
973 * and driver assumes that controller is not responding
974 * and times out. To workaround this, its good to check
975 * if SRE and HCE bits are not set (as per xhci
976 * Section 5.4.2) and bypass the timeout.
978 res = readl(&xhci->op_regs->status);
979 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
980 (((res & STS_SRE) == 0) &&
981 ((res & STS_HCE) == 0))) {
982 xhci->broken_suspend = 1;
984 xhci_warn(xhci, "WARN: xHC save state timeout\n");
985 spin_unlock_irq(&xhci->lock);
989 spin_unlock_irq(&xhci->lock);
992 * Deleting Compliance Mode Recovery Timer because the xHCI Host
993 * is about to be suspended.
995 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
996 (!(xhci_all_ports_seen_u0(xhci)))) {
997 del_timer_sync(&xhci->comp_mode_recovery_timer);
998 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
999 "%s: compliance mode recovery timer deleted",
1003 /* step 5: remove core well power */
1004 /* synchronize irq when using MSI-X */
1005 xhci_msix_sync_irqs(xhci);
1009 EXPORT_SYMBOL_GPL(xhci_suspend);
1012 * start xHC (not bus-specific)
1014 * This is called when the machine transition from S3/S4 mode.
1017 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1019 u32 command, temp = 0;
1020 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1021 struct usb_hcd *secondary_hcd;
1023 bool comp_timer_running = false;
1024 bool pending_portevent = false;
1029 /* Wait a bit if either of the roothubs need to settle from the
1030 * transition into bus suspend.
1032 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1033 time_before(jiffies,
1034 xhci->bus_state[1].next_statechange))
1037 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1038 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1040 spin_lock_irq(&xhci->lock);
1041 if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend)
1046 * Some controllers might lose power during suspend, so wait
1047 * for controller not ready bit to clear, just as in xHC init.
1049 retval = xhci_handshake(&xhci->op_regs->status,
1050 STS_CNR, 0, 10 * 1000 * 1000);
1052 xhci_warn(xhci, "Controller not ready at resume %d\n",
1054 spin_unlock_irq(&xhci->lock);
1057 /* step 1: restore register */
1058 xhci_restore_registers(xhci);
1059 /* step 2: initialize command ring buffer */
1060 xhci_set_cmd_ring_deq(xhci);
1061 /* step 3: restore state and start state*/
1062 /* step 3: set CRS flag */
1063 command = readl(&xhci->op_regs->command);
1065 writel(command, &xhci->op_regs->command);
1067 * Some controllers take up to 55+ ms to complete the controller
1068 * restore so setting the timeout to 100ms. Xhci specification
1069 * doesn't mention any timeout value.
1071 if (xhci_handshake(&xhci->op_regs->status,
1072 STS_RESTORE, 0, 100 * 1000)) {
1073 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1074 spin_unlock_irq(&xhci->lock);
1077 temp = readl(&xhci->op_regs->status);
1080 /* If restore operation fails, re-initialize the HC during resume */
1081 if ((temp & STS_SRE) || hibernated) {
1083 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1084 !(xhci_all_ports_seen_u0(xhci))) {
1085 del_timer_sync(&xhci->comp_mode_recovery_timer);
1086 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1087 "Compliance Mode Recovery Timer deleted!");
1090 /* Let the USB core know _both_ roothubs lost power. */
1091 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1092 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1094 xhci_dbg(xhci, "Stop HCD\n");
1097 spin_unlock_irq(&xhci->lock);
1098 xhci_cleanup_msix(xhci);
1100 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1101 temp = readl(&xhci->op_regs->status);
1102 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1103 temp = readl(&xhci->ir_set->irq_pending);
1104 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1105 xhci_print_ir_set(xhci, 0);
1107 xhci_dbg(xhci, "cleaning up memory\n");
1108 xhci_mem_cleanup(xhci);
1109 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1110 readl(&xhci->op_regs->status));
1112 /* USB core calls the PCI reinit and start functions twice:
1113 * first with the primary HCD, and then with the secondary HCD.
1114 * If we don't do the same, the host will never be started.
1116 if (!usb_hcd_is_primary_hcd(hcd))
1117 secondary_hcd = hcd;
1119 secondary_hcd = xhci->shared_hcd;
1121 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1122 retval = xhci_init(hcd->primary_hcd);
1125 comp_timer_running = true;
1127 xhci_dbg(xhci, "Start the primary HCD\n");
1128 retval = xhci_run(hcd->primary_hcd);
1130 xhci_dbg(xhci, "Start the secondary HCD\n");
1131 retval = xhci_run(secondary_hcd);
1133 hcd->state = HC_STATE_SUSPENDED;
1134 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1138 /* step 4: set Run/Stop bit */
1139 command = readl(&xhci->op_regs->command);
1141 writel(command, &xhci->op_regs->command);
1142 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1145 /* step 5: walk topology and initialize portsc,
1146 * portpmsc and portli
1148 /* this is done in bus_resume */
1150 /* step 6: restart each of the previously
1151 * Running endpoints by ringing their doorbells
1154 spin_unlock_irq(&xhci->lock);
1159 * Resume roothubs only if there are pending events.
1160 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1161 * the first wake signalling failed, give it that chance.
1163 pending_portevent = xhci_pending_portevent(xhci);
1164 if (!pending_portevent) {
1166 pending_portevent = xhci_pending_portevent(xhci);
1169 if (pending_portevent) {
1170 usb_hcd_resume_root_hub(xhci->shared_hcd);
1171 usb_hcd_resume_root_hub(hcd);
1175 * If system is subject to the Quirk, Compliance Mode Timer needs to
1176 * be re-initialized Always after a system resume. Ports are subject
1177 * to suffer the Compliance Mode issue again. It doesn't matter if
1178 * ports have entered previously to U0 before system's suspension.
1180 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1181 compliance_mode_recovery_timer_init(xhci);
1183 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1184 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1186 /* Re-enable port polling. */
1187 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1188 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1189 usb_hcd_poll_rh_status(xhci->shared_hcd);
1190 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1191 usb_hcd_poll_rh_status(hcd);
1195 EXPORT_SYMBOL_GPL(xhci_resume);
1196 #endif /* CONFIG_PM */
1198 /*-------------------------------------------------------------------------*/
1201 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1202 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1203 * value to right shift 1 for the bitmask.
1205 * Index = (epnum * 2) + direction - 1,
1206 * where direction = 0 for OUT, 1 for IN.
1207 * For control endpoints, the IN index is used (OUT index is unused), so
1208 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1210 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1213 if (usb_endpoint_xfer_control(desc))
1214 index = (unsigned int) (usb_endpoint_num(desc)*2);
1216 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1217 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1221 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1222 * address from the XHCI endpoint index.
1224 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1226 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1227 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1228 return direction | number;
1231 /* Find the flag for this endpoint (for use in the control context). Use the
1232 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1235 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1237 return 1 << (xhci_get_endpoint_index(desc) + 1);
1240 /* Find the flag for this endpoint (for use in the control context). Use the
1241 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1244 static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1246 return 1 << (ep_index + 1);
1249 /* Compute the last valid endpoint context index. Basically, this is the
1250 * endpoint index plus one. For slot contexts with more than valid endpoint,
1251 * we find the most significant bit set in the added contexts flags.
1252 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1253 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1255 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1257 return fls(added_ctxs) - 1;
1260 /* Returns 1 if the arguments are OK;
1261 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1263 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1264 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1266 struct xhci_hcd *xhci;
1267 struct xhci_virt_device *virt_dev;
1269 if (!hcd || (check_ep && !ep) || !udev) {
1270 pr_debug("xHCI %s called with invalid args\n", func);
1273 if (!udev->parent) {
1274 pr_debug("xHCI %s called for root hub\n", func);
1278 xhci = hcd_to_xhci(hcd);
1279 if (check_virt_dev) {
1280 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1281 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1286 virt_dev = xhci->devs[udev->slot_id];
1287 if (virt_dev->udev != udev) {
1288 xhci_dbg(xhci, "xHCI %s called with udev and "
1289 "virt_dev does not match\n", func);
1294 if (xhci->xhc_state & XHCI_STATE_HALTED)
1300 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1301 struct usb_device *udev, struct xhci_command *command,
1302 bool ctx_change, bool must_succeed);
1305 * Full speed devices may have a max packet size greater than 8 bytes, but the
1306 * USB core doesn't know that until it reads the first 8 bytes of the
1307 * descriptor. If the usb_device's max packet size changes after that point,
1308 * we need to issue an evaluate context command and wait on it.
1310 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1311 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1313 struct xhci_container_ctx *out_ctx;
1314 struct xhci_input_control_ctx *ctrl_ctx;
1315 struct xhci_ep_ctx *ep_ctx;
1316 struct xhci_command *command;
1317 int max_packet_size;
1318 int hw_max_packet_size;
1321 out_ctx = xhci->devs[slot_id]->out_ctx;
1322 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1323 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1324 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1325 if (hw_max_packet_size != max_packet_size) {
1326 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1327 "Max Packet Size for ep 0 changed.");
1328 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1329 "Max packet size in usb_device = %d",
1331 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1332 "Max packet size in xHCI HW = %d",
1333 hw_max_packet_size);
1334 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1335 "Issuing evaluate context command.");
1337 /* Set up the input context flags for the command */
1338 /* FIXME: This won't work if a non-default control endpoint
1339 * changes max packet sizes.
1342 command = xhci_alloc_command(xhci, false, true, mem_flags);
1346 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1347 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1349 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1352 goto command_cleanup;
1354 /* Set up the modified control endpoint 0 */
1355 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1356 xhci->devs[slot_id]->out_ctx, ep_index);
1358 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1359 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1360 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1361 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1363 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1364 ctrl_ctx->drop_flags = 0;
1366 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1369 /* Clean up the input context for later use by bandwidth
1372 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1374 kfree(command->completion);
1381 * non-error returns are a promise to giveback() the urb later
1382 * we drop ownership so next owner (or urb unlink) can get it
1384 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1386 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1387 unsigned long flags;
1389 unsigned int slot_id, ep_index, ep_state;
1390 struct urb_priv *urb_priv;
1393 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1394 true, true, __func__) <= 0)
1397 slot_id = urb->dev->slot_id;
1398 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1400 if (!HCD_HW_ACCESSIBLE(hcd)) {
1401 if (!in_interrupt())
1402 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1406 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1407 num_tds = urb->number_of_packets;
1408 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1409 urb->transfer_buffer_length > 0 &&
1410 urb->transfer_flags & URB_ZERO_PACKET &&
1411 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1416 urb_priv = kzalloc(sizeof(struct urb_priv) +
1417 num_tds * sizeof(struct xhci_td), mem_flags);
1421 urb_priv->num_tds = num_tds;
1422 urb_priv->num_tds_done = 0;
1423 urb->hcpriv = urb_priv;
1425 trace_xhci_urb_enqueue(urb);
1427 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1428 /* Check to see if the max packet size for the default control
1429 * endpoint changed during FS device enumeration
1431 if (urb->dev->speed == USB_SPEED_FULL) {
1432 ret = xhci_check_maxpacket(xhci, slot_id,
1433 ep_index, urb, mem_flags);
1435 xhci_urb_free_priv(urb_priv);
1442 spin_lock_irqsave(&xhci->lock, flags);
1444 if (xhci->xhc_state & XHCI_STATE_DYING) {
1445 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1446 urb->ep->desc.bEndpointAddress, urb);
1451 switch (usb_endpoint_type(&urb->ep->desc)) {
1453 case USB_ENDPOINT_XFER_CONTROL:
1454 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1457 case USB_ENDPOINT_XFER_BULK:
1458 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1459 if (ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1460 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1465 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1470 case USB_ENDPOINT_XFER_INT:
1471 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1475 case USB_ENDPOINT_XFER_ISOC:
1476 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1482 xhci_urb_free_priv(urb_priv);
1485 spin_unlock_irqrestore(&xhci->lock, flags);
1490 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1491 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1492 * should pick up where it left off in the TD, unless a Set Transfer Ring
1493 * Dequeue Pointer is issued.
1495 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1496 * the ring. Since the ring is a contiguous structure, they can't be physically
1497 * removed. Instead, there are two options:
1499 * 1) If the HC is in the middle of processing the URB to be canceled, we
1500 * simply move the ring's dequeue pointer past those TRBs using the Set
1501 * Transfer Ring Dequeue Pointer command. This will be the common case,
1502 * when drivers timeout on the last submitted URB and attempt to cancel.
1504 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1505 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1506 * HC will need to invalidate the any TRBs it has cached after the stop
1507 * endpoint command, as noted in the xHCI 0.95 errata.
1509 * 3) The TD may have completed by the time the Stop Endpoint Command
1510 * completes, so software needs to handle that case too.
1512 * This function should protect against the TD enqueueing code ringing the
1513 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1514 * It also needs to account for multiple cancellations on happening at the same
1515 * time for the same endpoint.
1517 * Note that this function can be called in any context, or so says
1518 * usb_hcd_unlink_urb()
1520 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1522 unsigned long flags;
1525 struct xhci_hcd *xhci;
1526 struct urb_priv *urb_priv;
1528 unsigned int ep_index;
1529 struct xhci_ring *ep_ring;
1530 struct xhci_virt_ep *ep;
1531 struct xhci_command *command;
1532 struct xhci_virt_device *vdev;
1534 xhci = hcd_to_xhci(hcd);
1535 spin_lock_irqsave(&xhci->lock, flags);
1537 trace_xhci_urb_dequeue(urb);
1539 /* Make sure the URB hasn't completed or been unlinked already */
1540 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1544 /* give back URB now if we can't queue it for cancel */
1545 vdev = xhci->devs[urb->dev->slot_id];
1546 urb_priv = urb->hcpriv;
1547 if (!vdev || !urb_priv)
1550 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1551 ep = &vdev->eps[ep_index];
1552 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1553 if (!ep || !ep_ring)
1556 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1557 temp = readl(&xhci->op_regs->status);
1558 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1564 * check ring is not re-allocated since URB was enqueued. If it is, then
1565 * make sure none of the ring related pointers in this URB private data
1566 * are touched, such as td_list, otherwise we overwrite freed data
1568 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1569 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1570 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1571 td = &urb_priv->td[i];
1572 if (!list_empty(&td->cancelled_td_list))
1573 list_del_init(&td->cancelled_td_list);
1578 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1579 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1580 "HC halted, freeing TD manually.");
1581 for (i = urb_priv->num_tds_done;
1582 i < urb_priv->num_tds;
1584 td = &urb_priv->td[i];
1585 if (!list_empty(&td->td_list))
1586 list_del_init(&td->td_list);
1587 if (!list_empty(&td->cancelled_td_list))
1588 list_del_init(&td->cancelled_td_list);
1593 i = urb_priv->num_tds_done;
1594 if (i < urb_priv->num_tds)
1595 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1596 "Cancel URB %p, dev %s, ep 0x%x, "
1597 "starting at offset 0x%llx",
1598 urb, urb->dev->devpath,
1599 urb->ep->desc.bEndpointAddress,
1600 (unsigned long long) xhci_trb_virt_to_dma(
1601 urb_priv->td[i].start_seg,
1602 urb_priv->td[i].first_trb));
1604 for (; i < urb_priv->num_tds; i++) {
1605 td = &urb_priv->td[i];
1606 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1609 /* Queue a stop endpoint command, but only if this is
1610 * the first cancellation to be handled.
1612 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1613 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1618 ep->ep_state |= EP_STOP_CMD_PENDING;
1619 ep->stop_cmd_timer.expires = jiffies +
1620 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1621 add_timer(&ep->stop_cmd_timer);
1622 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1624 xhci_ring_cmd_db(xhci);
1627 spin_unlock_irqrestore(&xhci->lock, flags);
1632 xhci_urb_free_priv(urb_priv);
1633 usb_hcd_unlink_urb_from_ep(hcd, urb);
1634 spin_unlock_irqrestore(&xhci->lock, flags);
1635 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1639 /* Drop an endpoint from a new bandwidth configuration for this device.
1640 * Only one call to this function is allowed per endpoint before
1641 * check_bandwidth() or reset_bandwidth() must be called.
1642 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1643 * add the endpoint to the schedule with possibly new parameters denoted by a
1644 * different endpoint descriptor in usb_host_endpoint.
1645 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1648 * The USB core will not allow URBs to be queued to an endpoint that is being
1649 * disabled, so there's no need for mutual exclusion to protect
1650 * the xhci->devs[slot_id] structure.
1652 static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1653 struct usb_host_endpoint *ep)
1655 struct xhci_hcd *xhci;
1656 struct xhci_container_ctx *in_ctx, *out_ctx;
1657 struct xhci_input_control_ctx *ctrl_ctx;
1658 unsigned int ep_index;
1659 struct xhci_ep_ctx *ep_ctx;
1661 u32 new_add_flags, new_drop_flags;
1664 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1667 xhci = hcd_to_xhci(hcd);
1668 if (xhci->xhc_state & XHCI_STATE_DYING)
1671 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1672 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1673 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1674 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1675 __func__, drop_flag);
1679 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1680 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1681 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1683 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1688 ep_index = xhci_get_endpoint_index(&ep->desc);
1689 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1690 /* If the HC already knows the endpoint is disabled,
1691 * or the HCD has noted it is disabled, ignore this request
1693 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1694 le32_to_cpu(ctrl_ctx->drop_flags) &
1695 xhci_get_endpoint_flag(&ep->desc)) {
1696 /* Do not warn when called after a usb_device_reset */
1697 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1698 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1703 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1704 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1706 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1707 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1709 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1711 if (xhci->quirks & XHCI_MTK_HOST)
1712 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1714 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1715 (unsigned int) ep->desc.bEndpointAddress,
1717 (unsigned int) new_drop_flags,
1718 (unsigned int) new_add_flags);
1722 /* Add an endpoint to a new possible bandwidth configuration for this device.
1723 * Only one call to this function is allowed per endpoint before
1724 * check_bandwidth() or reset_bandwidth() must be called.
1725 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1726 * add the endpoint to the schedule with possibly new parameters denoted by a
1727 * different endpoint descriptor in usb_host_endpoint.
1728 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1731 * The USB core will not allow URBs to be queued to an endpoint until the
1732 * configuration or alt setting is installed in the device, so there's no need
1733 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1735 static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1736 struct usb_host_endpoint *ep)
1738 struct xhci_hcd *xhci;
1739 struct xhci_container_ctx *in_ctx;
1740 unsigned int ep_index;
1741 struct xhci_input_control_ctx *ctrl_ctx;
1743 u32 new_add_flags, new_drop_flags;
1744 struct xhci_virt_device *virt_dev;
1747 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1749 /* So we won't queue a reset ep command for a root hub */
1753 xhci = hcd_to_xhci(hcd);
1754 if (xhci->xhc_state & XHCI_STATE_DYING)
1757 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1758 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1759 /* FIXME when we have to issue an evaluate endpoint command to
1760 * deal with ep0 max packet size changing once we get the
1763 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1764 __func__, added_ctxs);
1768 virt_dev = xhci->devs[udev->slot_id];
1769 in_ctx = virt_dev->in_ctx;
1770 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1772 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1777 ep_index = xhci_get_endpoint_index(&ep->desc);
1778 /* If this endpoint is already in use, and the upper layers are trying
1779 * to add it again without dropping it, reject the addition.
1781 if (virt_dev->eps[ep_index].ring &&
1782 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1783 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1784 "without dropping it.\n",
1785 (unsigned int) ep->desc.bEndpointAddress);
1789 /* If the HCD has already noted the endpoint is enabled,
1790 * ignore this request.
1792 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1793 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1799 * Configuration and alternate setting changes must be done in
1800 * process context, not interrupt context (or so documenation
1801 * for usb_set_interface() and usb_set_configuration() claim).
1803 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1804 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1805 __func__, ep->desc.bEndpointAddress);
1809 if (xhci->quirks & XHCI_MTK_HOST) {
1810 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1812 xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring);
1813 virt_dev->eps[ep_index].new_ring = NULL;
1818 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1819 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1821 /* If xhci_endpoint_disable() was called for this endpoint, but the
1822 * xHC hasn't been notified yet through the check_bandwidth() call,
1823 * this re-adds a new state for the endpoint from the new endpoint
1824 * descriptors. We must drop and re-add this endpoint, so we leave the
1827 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1829 /* Store the usb_device pointer for later use */
1832 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1833 (unsigned int) ep->desc.bEndpointAddress,
1835 (unsigned int) new_drop_flags,
1836 (unsigned int) new_add_flags);
1840 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1842 struct xhci_input_control_ctx *ctrl_ctx;
1843 struct xhci_ep_ctx *ep_ctx;
1844 struct xhci_slot_ctx *slot_ctx;
1847 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1849 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1854 /* When a device's add flag and drop flag are zero, any subsequent
1855 * configure endpoint command will leave that endpoint's state
1856 * untouched. Make sure we don't leave any old state in the input
1857 * endpoint contexts.
1859 ctrl_ctx->drop_flags = 0;
1860 ctrl_ctx->add_flags = 0;
1861 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1862 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1863 /* Endpoint 0 is always valid */
1864 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1865 for (i = 1; i < 31; i++) {
1866 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1867 ep_ctx->ep_info = 0;
1868 ep_ctx->ep_info2 = 0;
1870 ep_ctx->tx_info = 0;
1874 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1875 struct usb_device *udev, u32 *cmd_status)
1879 switch (*cmd_status) {
1880 case COMP_COMMAND_ABORTED:
1881 case COMP_COMMAND_RING_STOPPED:
1882 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1885 case COMP_RESOURCE_ERROR:
1886 dev_warn(&udev->dev,
1887 "Not enough host controller resources for new device state.\n");
1889 /* FIXME: can we allocate more resources for the HC? */
1891 case COMP_BANDWIDTH_ERROR:
1892 case COMP_SECONDARY_BANDWIDTH_ERROR:
1893 dev_warn(&udev->dev,
1894 "Not enough bandwidth for new device state.\n");
1896 /* FIXME: can we go back to the old state? */
1898 case COMP_TRB_ERROR:
1899 /* the HCD set up something wrong */
1900 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1902 "and endpoint is not disabled.\n");
1905 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1906 dev_warn(&udev->dev,
1907 "ERROR: Incompatible device for endpoint configure command.\n");
1911 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1912 "Successful Endpoint Configure command");
1916 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1924 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1925 struct usb_device *udev, u32 *cmd_status)
1929 switch (*cmd_status) {
1930 case COMP_COMMAND_ABORTED:
1931 case COMP_COMMAND_RING_STOPPED:
1932 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1935 case COMP_PARAMETER_ERROR:
1936 dev_warn(&udev->dev,
1937 "WARN: xHCI driver setup invalid evaluate context command.\n");
1940 case COMP_SLOT_NOT_ENABLED_ERROR:
1941 dev_warn(&udev->dev,
1942 "WARN: slot not enabled for evaluate context command.\n");
1945 case COMP_CONTEXT_STATE_ERROR:
1946 dev_warn(&udev->dev,
1947 "WARN: invalid context state for evaluate context command.\n");
1950 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1951 dev_warn(&udev->dev,
1952 "ERROR: Incompatible device for evaluate context command.\n");
1955 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1956 /* Max Exit Latency too large error */
1957 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1961 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1962 "Successful evaluate context command");
1966 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1974 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1975 struct xhci_input_control_ctx *ctrl_ctx)
1977 u32 valid_add_flags;
1978 u32 valid_drop_flags;
1980 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1981 * (bit 1). The default control endpoint is added during the Address
1982 * Device command and is never removed until the slot is disabled.
1984 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1985 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1987 /* Use hweight32 to count the number of ones in the add flags, or
1988 * number of endpoints added. Don't count endpoints that are changed
1989 * (both added and dropped).
1991 return hweight32(valid_add_flags) -
1992 hweight32(valid_add_flags & valid_drop_flags);
1995 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1996 struct xhci_input_control_ctx *ctrl_ctx)
1998 u32 valid_add_flags;
1999 u32 valid_drop_flags;
2001 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2002 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2004 return hweight32(valid_drop_flags) -
2005 hweight32(valid_add_flags & valid_drop_flags);
2009 * We need to reserve the new number of endpoints before the configure endpoint
2010 * command completes. We can't subtract the dropped endpoints from the number
2011 * of active endpoints until the command completes because we can oversubscribe
2012 * the host in this case:
2014 * - the first configure endpoint command drops more endpoints than it adds
2015 * - a second configure endpoint command that adds more endpoints is queued
2016 * - the first configure endpoint command fails, so the config is unchanged
2017 * - the second command may succeed, even though there isn't enough resources
2019 * Must be called with xhci->lock held.
2021 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2022 struct xhci_input_control_ctx *ctrl_ctx)
2026 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2027 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2028 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2029 "Not enough ep ctxs: "
2030 "%u active, need to add %u, limit is %u.",
2031 xhci->num_active_eps, added_eps,
2032 xhci->limit_active_eps);
2035 xhci->num_active_eps += added_eps;
2036 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2037 "Adding %u ep ctxs, %u now active.", added_eps,
2038 xhci->num_active_eps);
2043 * The configure endpoint was failed by the xHC for some other reason, so we
2044 * need to revert the resources that failed configuration would have used.
2046 * Must be called with xhci->lock held.
2048 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2049 struct xhci_input_control_ctx *ctrl_ctx)
2053 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2054 xhci->num_active_eps -= num_failed_eps;
2055 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2056 "Removing %u failed ep ctxs, %u now active.",
2058 xhci->num_active_eps);
2062 * Now that the command has completed, clean up the active endpoint count by
2063 * subtracting out the endpoints that were dropped (but not changed).
2065 * Must be called with xhci->lock held.
2067 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2068 struct xhci_input_control_ctx *ctrl_ctx)
2070 u32 num_dropped_eps;
2072 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2073 xhci->num_active_eps -= num_dropped_eps;
2074 if (num_dropped_eps)
2075 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2076 "Removing %u dropped ep ctxs, %u now active.",
2078 xhci->num_active_eps);
2081 static unsigned int xhci_get_block_size(struct usb_device *udev)
2083 switch (udev->speed) {
2085 case USB_SPEED_FULL:
2087 case USB_SPEED_HIGH:
2089 case USB_SPEED_SUPER:
2090 case USB_SPEED_SUPER_PLUS:
2092 case USB_SPEED_UNKNOWN:
2093 case USB_SPEED_WIRELESS:
2095 /* Should never happen */
2101 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2103 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2105 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2110 /* If we are changing a LS/FS device under a HS hub,
2111 * make sure (if we are activating a new TT) that the HS bus has enough
2112 * bandwidth for this new TT.
2114 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2115 struct xhci_virt_device *virt_dev,
2118 struct xhci_interval_bw_table *bw_table;
2119 struct xhci_tt_bw_info *tt_info;
2121 /* Find the bandwidth table for the root port this TT is attached to. */
2122 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2123 tt_info = virt_dev->tt_info;
2124 /* If this TT already had active endpoints, the bandwidth for this TT
2125 * has already been added. Removing all periodic endpoints (and thus
2126 * making the TT enactive) will only decrease the bandwidth used.
2130 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2131 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2135 /* Not sure why we would have no new active endpoints...
2137 * Maybe because of an Evaluate Context change for a hub update or a
2138 * control endpoint 0 max packet size change?
2139 * FIXME: skip the bandwidth calculation in that case.
2144 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2145 struct xhci_virt_device *virt_dev)
2147 unsigned int bw_reserved;
2149 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2150 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2153 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2154 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2161 * This algorithm is a very conservative estimate of the worst-case scheduling
2162 * scenario for any one interval. The hardware dynamically schedules the
2163 * packets, so we can't tell which microframe could be the limiting factor in
2164 * the bandwidth scheduling. This only takes into account periodic endpoints.
2166 * Obviously, we can't solve an NP complete problem to find the minimum worst
2167 * case scenario. Instead, we come up with an estimate that is no less than
2168 * the worst case bandwidth used for any one microframe, but may be an
2171 * We walk the requirements for each endpoint by interval, starting with the
2172 * smallest interval, and place packets in the schedule where there is only one
2173 * possible way to schedule packets for that interval. In order to simplify
2174 * this algorithm, we record the largest max packet size for each interval, and
2175 * assume all packets will be that size.
2177 * For interval 0, we obviously must schedule all packets for each interval.
2178 * The bandwidth for interval 0 is just the amount of data to be transmitted
2179 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2180 * the number of packets).
2182 * For interval 1, we have two possible microframes to schedule those packets
2183 * in. For this algorithm, if we can schedule the same number of packets for
2184 * each possible scheduling opportunity (each microframe), we will do so. The
2185 * remaining number of packets will be saved to be transmitted in the gaps in
2186 * the next interval's scheduling sequence.
2188 * As we move those remaining packets to be scheduled with interval 2 packets,
2189 * we have to double the number of remaining packets to transmit. This is
2190 * because the intervals are actually powers of 2, and we would be transmitting
2191 * the previous interval's packets twice in this interval. We also have to be
2192 * sure that when we look at the largest max packet size for this interval, we
2193 * also look at the largest max packet size for the remaining packets and take
2194 * the greater of the two.
2196 * The algorithm continues to evenly distribute packets in each scheduling
2197 * opportunity, and push the remaining packets out, until we get to the last
2198 * interval. Then those packets and their associated overhead are just added
2199 * to the bandwidth used.
2201 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2202 struct xhci_virt_device *virt_dev,
2205 unsigned int bw_reserved;
2206 unsigned int max_bandwidth;
2207 unsigned int bw_used;
2208 unsigned int block_size;
2209 struct xhci_interval_bw_table *bw_table;
2210 unsigned int packet_size = 0;
2211 unsigned int overhead = 0;
2212 unsigned int packets_transmitted = 0;
2213 unsigned int packets_remaining = 0;
2216 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2217 return xhci_check_ss_bw(xhci, virt_dev);
2219 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2220 max_bandwidth = HS_BW_LIMIT;
2221 /* Convert percent of bus BW reserved to blocks reserved */
2222 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2224 max_bandwidth = FS_BW_LIMIT;
2225 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2228 bw_table = virt_dev->bw_table;
2229 /* We need to translate the max packet size and max ESIT payloads into
2230 * the units the hardware uses.
2232 block_size = xhci_get_block_size(virt_dev->udev);
2234 /* If we are manipulating a LS/FS device under a HS hub, double check
2235 * that the HS bus has enough bandwidth if we are activing a new TT.
2237 if (virt_dev->tt_info) {
2238 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2239 "Recalculating BW for rootport %u",
2240 virt_dev->real_port);
2241 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2242 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2243 "newly activated TT.\n");
2246 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2247 "Recalculating BW for TT slot %u port %u",
2248 virt_dev->tt_info->slot_id,
2249 virt_dev->tt_info->ttport);
2251 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2252 "Recalculating BW for rootport %u",
2253 virt_dev->real_port);
2256 /* Add in how much bandwidth will be used for interval zero, or the
2257 * rounded max ESIT payload + number of packets * largest overhead.
2259 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2260 bw_table->interval_bw[0].num_packets *
2261 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2263 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2264 unsigned int bw_added;
2265 unsigned int largest_mps;
2266 unsigned int interval_overhead;
2269 * How many packets could we transmit in this interval?
2270 * If packets didn't fit in the previous interval, we will need
2271 * to transmit that many packets twice within this interval.
2273 packets_remaining = 2 * packets_remaining +
2274 bw_table->interval_bw[i].num_packets;
2276 /* Find the largest max packet size of this or the previous
2279 if (list_empty(&bw_table->interval_bw[i].endpoints))
2282 struct xhci_virt_ep *virt_ep;
2283 struct list_head *ep_entry;
2285 ep_entry = bw_table->interval_bw[i].endpoints.next;
2286 virt_ep = list_entry(ep_entry,
2287 struct xhci_virt_ep, bw_endpoint_list);
2288 /* Convert to blocks, rounding up */
2289 largest_mps = DIV_ROUND_UP(
2290 virt_ep->bw_info.max_packet_size,
2293 if (largest_mps > packet_size)
2294 packet_size = largest_mps;
2296 /* Use the larger overhead of this or the previous interval. */
2297 interval_overhead = xhci_get_largest_overhead(
2298 &bw_table->interval_bw[i]);
2299 if (interval_overhead > overhead)
2300 overhead = interval_overhead;
2302 /* How many packets can we evenly distribute across
2303 * (1 << (i + 1)) possible scheduling opportunities?
2305 packets_transmitted = packets_remaining >> (i + 1);
2307 /* Add in the bandwidth used for those scheduled packets */
2308 bw_added = packets_transmitted * (overhead + packet_size);
2310 /* How many packets do we have remaining to transmit? */
2311 packets_remaining = packets_remaining % (1 << (i + 1));
2313 /* What largest max packet size should those packets have? */
2314 /* If we've transmitted all packets, don't carry over the
2315 * largest packet size.
2317 if (packets_remaining == 0) {
2320 } else if (packets_transmitted > 0) {
2321 /* Otherwise if we do have remaining packets, and we've
2322 * scheduled some packets in this interval, take the
2323 * largest max packet size from endpoints with this
2326 packet_size = largest_mps;
2327 overhead = interval_overhead;
2329 /* Otherwise carry over packet_size and overhead from the last
2330 * time we had a remainder.
2332 bw_used += bw_added;
2333 if (bw_used > max_bandwidth) {
2334 xhci_warn(xhci, "Not enough bandwidth. "
2335 "Proposed: %u, Max: %u\n",
2336 bw_used, max_bandwidth);
2341 * Ok, we know we have some packets left over after even-handedly
2342 * scheduling interval 15. We don't know which microframes they will
2343 * fit into, so we over-schedule and say they will be scheduled every
2346 if (packets_remaining > 0)
2347 bw_used += overhead + packet_size;
2349 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2350 unsigned int port_index = virt_dev->real_port - 1;
2352 /* OK, we're manipulating a HS device attached to a
2353 * root port bandwidth domain. Include the number of active TTs
2354 * in the bandwidth used.
2356 bw_used += TT_HS_OVERHEAD *
2357 xhci->rh_bw[port_index].num_active_tts;
2360 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2361 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2362 "Available: %u " "percent",
2363 bw_used, max_bandwidth, bw_reserved,
2364 (max_bandwidth - bw_used - bw_reserved) * 100 /
2367 bw_used += bw_reserved;
2368 if (bw_used > max_bandwidth) {
2369 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2370 bw_used, max_bandwidth);
2374 bw_table->bw_used = bw_used;
2378 static bool xhci_is_async_ep(unsigned int ep_type)
2380 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2381 ep_type != ISOC_IN_EP &&
2382 ep_type != INT_IN_EP);
2385 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2387 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2390 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2392 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2394 if (ep_bw->ep_interval == 0)
2395 return SS_OVERHEAD_BURST +
2396 (ep_bw->mult * ep_bw->num_packets *
2397 (SS_OVERHEAD + mps));
2398 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2399 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2400 1 << ep_bw->ep_interval);
2404 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2405 struct xhci_bw_info *ep_bw,
2406 struct xhci_interval_bw_table *bw_table,
2407 struct usb_device *udev,
2408 struct xhci_virt_ep *virt_ep,
2409 struct xhci_tt_bw_info *tt_info)
2411 struct xhci_interval_bw *interval_bw;
2412 int normalized_interval;
2414 if (xhci_is_async_ep(ep_bw->type))
2417 if (udev->speed >= USB_SPEED_SUPER) {
2418 if (xhci_is_sync_in_ep(ep_bw->type))
2419 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2420 xhci_get_ss_bw_consumed(ep_bw);
2422 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2423 xhci_get_ss_bw_consumed(ep_bw);
2427 /* SuperSpeed endpoints never get added to intervals in the table, so
2428 * this check is only valid for HS/FS/LS devices.
2430 if (list_empty(&virt_ep->bw_endpoint_list))
2432 /* For LS/FS devices, we need to translate the interval expressed in
2433 * microframes to frames.
2435 if (udev->speed == USB_SPEED_HIGH)
2436 normalized_interval = ep_bw->ep_interval;
2438 normalized_interval = ep_bw->ep_interval - 3;
2440 if (normalized_interval == 0)
2441 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2442 interval_bw = &bw_table->interval_bw[normalized_interval];
2443 interval_bw->num_packets -= ep_bw->num_packets;
2444 switch (udev->speed) {
2446 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2448 case USB_SPEED_FULL:
2449 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2451 case USB_SPEED_HIGH:
2452 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2454 case USB_SPEED_SUPER:
2455 case USB_SPEED_SUPER_PLUS:
2456 case USB_SPEED_UNKNOWN:
2457 case USB_SPEED_WIRELESS:
2458 /* Should never happen because only LS/FS/HS endpoints will get
2459 * added to the endpoint list.
2464 tt_info->active_eps -= 1;
2465 list_del_init(&virt_ep->bw_endpoint_list);
2468 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2469 struct xhci_bw_info *ep_bw,
2470 struct xhci_interval_bw_table *bw_table,
2471 struct usb_device *udev,
2472 struct xhci_virt_ep *virt_ep,
2473 struct xhci_tt_bw_info *tt_info)
2475 struct xhci_interval_bw *interval_bw;
2476 struct xhci_virt_ep *smaller_ep;
2477 int normalized_interval;
2479 if (xhci_is_async_ep(ep_bw->type))
2482 if (udev->speed == USB_SPEED_SUPER) {
2483 if (xhci_is_sync_in_ep(ep_bw->type))
2484 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2485 xhci_get_ss_bw_consumed(ep_bw);
2487 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2488 xhci_get_ss_bw_consumed(ep_bw);
2492 /* For LS/FS devices, we need to translate the interval expressed in
2493 * microframes to frames.
2495 if (udev->speed == USB_SPEED_HIGH)
2496 normalized_interval = ep_bw->ep_interval;
2498 normalized_interval = ep_bw->ep_interval - 3;
2500 if (normalized_interval == 0)
2501 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2502 interval_bw = &bw_table->interval_bw[normalized_interval];
2503 interval_bw->num_packets += ep_bw->num_packets;
2504 switch (udev->speed) {
2506 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2508 case USB_SPEED_FULL:
2509 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2511 case USB_SPEED_HIGH:
2512 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2514 case USB_SPEED_SUPER:
2515 case USB_SPEED_SUPER_PLUS:
2516 case USB_SPEED_UNKNOWN:
2517 case USB_SPEED_WIRELESS:
2518 /* Should never happen because only LS/FS/HS endpoints will get
2519 * added to the endpoint list.
2525 tt_info->active_eps += 1;
2526 /* Insert the endpoint into the list, largest max packet size first. */
2527 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2529 if (ep_bw->max_packet_size >=
2530 smaller_ep->bw_info.max_packet_size) {
2531 /* Add the new ep before the smaller endpoint */
2532 list_add_tail(&virt_ep->bw_endpoint_list,
2533 &smaller_ep->bw_endpoint_list);
2537 /* Add the new endpoint at the end of the list. */
2538 list_add_tail(&virt_ep->bw_endpoint_list,
2539 &interval_bw->endpoints);
2542 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2543 struct xhci_virt_device *virt_dev,
2546 struct xhci_root_port_bw_info *rh_bw_info;
2547 if (!virt_dev->tt_info)
2550 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2551 if (old_active_eps == 0 &&
2552 virt_dev->tt_info->active_eps != 0) {
2553 rh_bw_info->num_active_tts += 1;
2554 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2555 } else if (old_active_eps != 0 &&
2556 virt_dev->tt_info->active_eps == 0) {
2557 rh_bw_info->num_active_tts -= 1;
2558 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2562 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2563 struct xhci_virt_device *virt_dev,
2564 struct xhci_container_ctx *in_ctx)
2566 struct xhci_bw_info ep_bw_info[31];
2568 struct xhci_input_control_ctx *ctrl_ctx;
2569 int old_active_eps = 0;
2571 if (virt_dev->tt_info)
2572 old_active_eps = virt_dev->tt_info->active_eps;
2574 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2576 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2581 for (i = 0; i < 31; i++) {
2582 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2585 /* Make a copy of the BW info in case we need to revert this */
2586 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2587 sizeof(ep_bw_info[i]));
2588 /* Drop the endpoint from the interval table if the endpoint is
2589 * being dropped or changed.
2591 if (EP_IS_DROPPED(ctrl_ctx, i))
2592 xhci_drop_ep_from_interval_table(xhci,
2593 &virt_dev->eps[i].bw_info,
2599 /* Overwrite the information stored in the endpoints' bw_info */
2600 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2601 for (i = 0; i < 31; i++) {
2602 /* Add any changed or added endpoints to the interval table */
2603 if (EP_IS_ADDED(ctrl_ctx, i))
2604 xhci_add_ep_to_interval_table(xhci,
2605 &virt_dev->eps[i].bw_info,
2612 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2613 /* Ok, this fits in the bandwidth we have.
2614 * Update the number of active TTs.
2616 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2620 /* We don't have enough bandwidth for this, revert the stored info. */
2621 for (i = 0; i < 31; i++) {
2622 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2625 /* Drop the new copies of any added or changed endpoints from
2626 * the interval table.
2628 if (EP_IS_ADDED(ctrl_ctx, i)) {
2629 xhci_drop_ep_from_interval_table(xhci,
2630 &virt_dev->eps[i].bw_info,
2636 /* Revert the endpoint back to its old information */
2637 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2638 sizeof(ep_bw_info[i]));
2639 /* Add any changed or dropped endpoints back into the table */
2640 if (EP_IS_DROPPED(ctrl_ctx, i))
2641 xhci_add_ep_to_interval_table(xhci,
2642 &virt_dev->eps[i].bw_info,
2652 /* Issue a configure endpoint command or evaluate context command
2653 * and wait for it to finish.
2655 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2656 struct usb_device *udev,
2657 struct xhci_command *command,
2658 bool ctx_change, bool must_succeed)
2661 unsigned long flags;
2662 struct xhci_input_control_ctx *ctrl_ctx;
2663 struct xhci_virt_device *virt_dev;
2668 spin_lock_irqsave(&xhci->lock, flags);
2670 if (xhci->xhc_state & XHCI_STATE_DYING) {
2671 spin_unlock_irqrestore(&xhci->lock, flags);
2675 virt_dev = xhci->devs[udev->slot_id];
2677 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2679 spin_unlock_irqrestore(&xhci->lock, flags);
2680 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2685 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2686 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2687 spin_unlock_irqrestore(&xhci->lock, flags);
2688 xhci_warn(xhci, "Not enough host resources, "
2689 "active endpoint contexts = %u\n",
2690 xhci->num_active_eps);
2693 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2694 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2695 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2696 xhci_free_host_resources(xhci, ctrl_ctx);
2697 spin_unlock_irqrestore(&xhci->lock, flags);
2698 xhci_warn(xhci, "Not enough bandwidth\n");
2703 ret = xhci_queue_configure_endpoint(xhci, command,
2704 command->in_ctx->dma,
2705 udev->slot_id, must_succeed);
2707 ret = xhci_queue_evaluate_context(xhci, command,
2708 command->in_ctx->dma,
2709 udev->slot_id, must_succeed);
2711 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2712 xhci_free_host_resources(xhci, ctrl_ctx);
2713 spin_unlock_irqrestore(&xhci->lock, flags);
2714 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2715 "FIXME allocate a new ring segment");
2718 xhci_ring_cmd_db(xhci);
2719 spin_unlock_irqrestore(&xhci->lock, flags);
2721 /* Wait for the configure endpoint command to complete */
2722 wait_for_completion(command->completion);
2725 ret = xhci_configure_endpoint_result(xhci, udev,
2728 ret = xhci_evaluate_context_result(xhci, udev,
2731 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2732 spin_lock_irqsave(&xhci->lock, flags);
2733 /* If the command failed, remove the reserved resources.
2734 * Otherwise, clean up the estimate to include dropped eps.
2737 xhci_free_host_resources(xhci, ctrl_ctx);
2739 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2740 spin_unlock_irqrestore(&xhci->lock, flags);
2745 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2746 struct xhci_virt_device *vdev, int i)
2748 struct xhci_virt_ep *ep = &vdev->eps[i];
2750 if (ep->ep_state & EP_HAS_STREAMS) {
2751 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2752 xhci_get_endpoint_address(i));
2753 xhci_free_stream_info(xhci, ep->stream_info);
2754 ep->stream_info = NULL;
2755 ep->ep_state &= ~EP_HAS_STREAMS;
2759 /* Called after one or more calls to xhci_add_endpoint() or
2760 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2761 * to call xhci_reset_bandwidth().
2763 * Since we are in the middle of changing either configuration or
2764 * installing a new alt setting, the USB core won't allow URBs to be
2765 * enqueued for any endpoint on the old config or interface. Nothing
2766 * else should be touching the xhci->devs[slot_id] structure, so we
2767 * don't need to take the xhci->lock for manipulating that.
2769 static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2773 struct xhci_hcd *xhci;
2774 struct xhci_virt_device *virt_dev;
2775 struct xhci_input_control_ctx *ctrl_ctx;
2776 struct xhci_slot_ctx *slot_ctx;
2777 struct xhci_command *command;
2779 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2782 xhci = hcd_to_xhci(hcd);
2783 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2784 (xhci->xhc_state & XHCI_STATE_REMOVING))
2787 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2788 virt_dev = xhci->devs[udev->slot_id];
2790 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2794 command->in_ctx = virt_dev->in_ctx;
2796 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2797 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2799 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2802 goto command_cleanup;
2804 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2805 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2806 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2808 /* Don't issue the command if there's no endpoints to update. */
2809 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2810 ctrl_ctx->drop_flags == 0) {
2812 goto command_cleanup;
2814 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2815 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2816 for (i = 31; i >= 1; i--) {
2817 __le32 le32 = cpu_to_le32(BIT(i));
2819 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2820 || (ctrl_ctx->add_flags & le32) || i == 1) {
2821 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2822 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2827 ret = xhci_configure_endpoint(xhci, udev, command,
2830 /* Callee should call reset_bandwidth() */
2831 goto command_cleanup;
2833 /* Free any rings that were dropped, but not changed. */
2834 for (i = 1; i < 31; i++) {
2835 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2836 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2837 xhci_free_endpoint_ring(xhci, virt_dev, i);
2838 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2841 xhci_zero_in_ctx(xhci, virt_dev);
2843 * Install any rings for completely new endpoints or changed endpoints,
2844 * and free any old rings from changed endpoints.
2846 for (i = 1; i < 31; i++) {
2847 if (!virt_dev->eps[i].new_ring)
2849 /* Only free the old ring if it exists.
2850 * It may not if this is the first add of an endpoint.
2852 if (virt_dev->eps[i].ring) {
2853 xhci_free_endpoint_ring(xhci, virt_dev, i);
2855 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2856 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2857 virt_dev->eps[i].new_ring = NULL;
2860 kfree(command->completion);
2866 static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2868 struct xhci_hcd *xhci;
2869 struct xhci_virt_device *virt_dev;
2872 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2875 xhci = hcd_to_xhci(hcd);
2877 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2878 virt_dev = xhci->devs[udev->slot_id];
2879 /* Free any rings allocated for added endpoints */
2880 for (i = 0; i < 31; i++) {
2881 if (virt_dev->eps[i].new_ring) {
2882 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2883 virt_dev->eps[i].new_ring = NULL;
2886 xhci_zero_in_ctx(xhci, virt_dev);
2889 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2890 struct xhci_container_ctx *in_ctx,
2891 struct xhci_container_ctx *out_ctx,
2892 struct xhci_input_control_ctx *ctrl_ctx,
2893 u32 add_flags, u32 drop_flags)
2895 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2896 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2897 xhci_slot_copy(xhci, in_ctx, out_ctx);
2898 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2901 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2902 unsigned int slot_id, unsigned int ep_index,
2903 struct xhci_dequeue_state *deq_state)
2905 struct xhci_input_control_ctx *ctrl_ctx;
2906 struct xhci_container_ctx *in_ctx;
2907 struct xhci_ep_ctx *ep_ctx;
2911 in_ctx = xhci->devs[slot_id]->in_ctx;
2912 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2914 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2919 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2920 xhci->devs[slot_id]->out_ctx, ep_index);
2921 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2922 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2923 deq_state->new_deq_ptr);
2925 xhci_warn(xhci, "WARN Cannot submit config ep after "
2926 "reset ep command\n");
2927 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2928 deq_state->new_deq_seg,
2929 deq_state->new_deq_ptr);
2932 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2934 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2935 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2936 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2937 added_ctxs, added_ctxs);
2940 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
2941 unsigned int stream_id, struct xhci_td *td)
2943 struct xhci_dequeue_state deq_state;
2944 struct xhci_virt_ep *ep;
2945 struct usb_device *udev = td->urb->dev;
2947 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2948 "Cleaning up stalled endpoint ring");
2949 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2950 /* We need to move the HW's dequeue pointer past this TD,
2951 * or it will attempt to resend it on the next doorbell ring.
2953 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2954 ep_index, stream_id, td, &deq_state);
2956 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2959 /* HW with the reset endpoint quirk will use the saved dequeue state to
2960 * issue a configure endpoint command later.
2962 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2963 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2964 "Queueing new dequeue state");
2965 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2966 ep_index, &deq_state);
2968 /* Better hope no one uses the input context between now and the
2969 * reset endpoint completion!
2970 * XXX: No idea how this hardware will react when stream rings
2973 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2974 "Setting up input context for "
2975 "configure endpoint command");
2976 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2977 ep_index, &deq_state);
2981 /* Called when clearing halted device. The core should have sent the control
2982 * message to clear the device halt condition. The host side of the halt should
2983 * already be cleared with a reset endpoint command issued when the STALL tx
2984 * event was received.
2986 * Context: in_interrupt
2989 static void xhci_endpoint_reset(struct usb_hcd *hcd,
2990 struct usb_host_endpoint *ep)
2992 struct xhci_hcd *xhci;
2994 xhci = hcd_to_xhci(hcd);
2997 * We might need to implement the config ep cmd in xhci 4.8.1 note:
2998 * The Reset Endpoint Command may only be issued to endpoints in the
2999 * Halted state. If software wishes reset the Data Toggle or Sequence
3000 * Number of an endpoint that isn't in the Halted state, then software
3001 * may issue a Configure Endpoint Command with the Drop and Add bits set
3002 * for the target endpoint. that is in the Stopped state.
3005 /* For now just print debug to follow the situation */
3006 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
3007 ep->desc.bEndpointAddress);
3010 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3011 struct usb_device *udev, struct usb_host_endpoint *ep,
3012 unsigned int slot_id)
3015 unsigned int ep_index;
3016 unsigned int ep_state;
3020 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3023 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3024 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3025 " descriptor for ep 0x%x does not support streams\n",
3026 ep->desc.bEndpointAddress);
3030 ep_index = xhci_get_endpoint_index(&ep->desc);
3031 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3032 if (ep_state & EP_HAS_STREAMS ||
3033 ep_state & EP_GETTING_STREAMS) {
3034 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3035 "already has streams set up.\n",
3036 ep->desc.bEndpointAddress);
3037 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3038 "dynamic stream context array reallocation.\n");
3041 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3042 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3043 "endpoint 0x%x; URBs are pending.\n",
3044 ep->desc.bEndpointAddress);
3050 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3051 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3053 unsigned int max_streams;
3055 /* The stream context array size must be a power of two */
3056 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3058 * Find out how many primary stream array entries the host controller
3059 * supports. Later we may use secondary stream arrays (similar to 2nd
3060 * level page entries), but that's an optional feature for xHCI host
3061 * controllers. xHCs must support at least 4 stream IDs.
3063 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3064 if (*num_stream_ctxs > max_streams) {
3065 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3067 *num_stream_ctxs = max_streams;
3068 *num_streams = max_streams;
3072 /* Returns an error code if one of the endpoint already has streams.
3073 * This does not change any data structures, it only checks and gathers
3076 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3077 struct usb_device *udev,
3078 struct usb_host_endpoint **eps, unsigned int num_eps,
3079 unsigned int *num_streams, u32 *changed_ep_bitmask)
3081 unsigned int max_streams;
3082 unsigned int endpoint_flag;
3086 for (i = 0; i < num_eps; i++) {
3087 ret = xhci_check_streams_endpoint(xhci, udev,
3088 eps[i], udev->slot_id);
3092 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3093 if (max_streams < (*num_streams - 1)) {
3094 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3095 eps[i]->desc.bEndpointAddress,
3097 *num_streams = max_streams+1;
3100 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3101 if (*changed_ep_bitmask & endpoint_flag)
3103 *changed_ep_bitmask |= endpoint_flag;
3108 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3109 struct usb_device *udev,
3110 struct usb_host_endpoint **eps, unsigned int num_eps)
3112 u32 changed_ep_bitmask = 0;
3113 unsigned int slot_id;
3114 unsigned int ep_index;
3115 unsigned int ep_state;
3118 slot_id = udev->slot_id;
3119 if (!xhci->devs[slot_id])
3122 for (i = 0; i < num_eps; i++) {
3123 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3124 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3125 /* Are streams already being freed for the endpoint? */
3126 if (ep_state & EP_GETTING_NO_STREAMS) {
3127 xhci_warn(xhci, "WARN Can't disable streams for "
3129 "streams are being disabled already\n",
3130 eps[i]->desc.bEndpointAddress);
3133 /* Are there actually any streams to free? */
3134 if (!(ep_state & EP_HAS_STREAMS) &&
3135 !(ep_state & EP_GETTING_STREAMS)) {
3136 xhci_warn(xhci, "WARN Can't disable streams for "
3138 "streams are already disabled!\n",
3139 eps[i]->desc.bEndpointAddress);
3140 xhci_warn(xhci, "WARN xhci_free_streams() called "
3141 "with non-streams endpoint\n");
3144 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3146 return changed_ep_bitmask;
3150 * The USB device drivers use this function (through the HCD interface in USB
3151 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3152 * coordinate mass storage command queueing across multiple endpoints (basically
3153 * a stream ID == a task ID).
3155 * Setting up streams involves allocating the same size stream context array
3156 * for each endpoint and issuing a configure endpoint command for all endpoints.
3158 * Don't allow the call to succeed if one endpoint only supports one stream
3159 * (which means it doesn't support streams at all).
3161 * Drivers may get less stream IDs than they asked for, if the host controller
3162 * hardware or endpoints claim they can't support the number of requested
3165 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3166 struct usb_host_endpoint **eps, unsigned int num_eps,
3167 unsigned int num_streams, gfp_t mem_flags)
3170 struct xhci_hcd *xhci;
3171 struct xhci_virt_device *vdev;
3172 struct xhci_command *config_cmd;
3173 struct xhci_input_control_ctx *ctrl_ctx;
3174 unsigned int ep_index;
3175 unsigned int num_stream_ctxs;
3176 unsigned int max_packet;
3177 unsigned long flags;
3178 u32 changed_ep_bitmask = 0;
3183 /* Add one to the number of streams requested to account for
3184 * stream 0 that is reserved for xHCI usage.
3187 xhci = hcd_to_xhci(hcd);
3188 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3191 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3192 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3193 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3194 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3198 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3202 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3204 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3206 xhci_free_command(xhci, config_cmd);
3210 /* Check to make sure all endpoints are not already configured for
3211 * streams. While we're at it, find the maximum number of streams that
3212 * all the endpoints will support and check for duplicate endpoints.
3214 spin_lock_irqsave(&xhci->lock, flags);
3215 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3216 num_eps, &num_streams, &changed_ep_bitmask);
3218 xhci_free_command(xhci, config_cmd);
3219 spin_unlock_irqrestore(&xhci->lock, flags);
3222 if (num_streams <= 1) {
3223 xhci_warn(xhci, "WARN: endpoints can't handle "
3224 "more than one stream.\n");
3225 xhci_free_command(xhci, config_cmd);
3226 spin_unlock_irqrestore(&xhci->lock, flags);
3229 vdev = xhci->devs[udev->slot_id];
3230 /* Mark each endpoint as being in transition, so
3231 * xhci_urb_enqueue() will reject all URBs.
3233 for (i = 0; i < num_eps; i++) {
3234 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3235 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3237 spin_unlock_irqrestore(&xhci->lock, flags);
3239 /* Setup internal data structures and allocate HW data structures for
3240 * streams (but don't install the HW structures in the input context
3241 * until we're sure all memory allocation succeeded).
3243 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3244 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3245 num_stream_ctxs, num_streams);
3247 for (i = 0; i < num_eps; i++) {
3248 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3249 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3250 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3253 max_packet, mem_flags);
3254 if (!vdev->eps[ep_index].stream_info)
3256 /* Set maxPstreams in endpoint context and update deq ptr to
3257 * point to stream context array. FIXME
3261 /* Set up the input context for a configure endpoint command. */
3262 for (i = 0; i < num_eps; i++) {
3263 struct xhci_ep_ctx *ep_ctx;
3265 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3266 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3268 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3269 vdev->out_ctx, ep_index);
3270 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3271 vdev->eps[ep_index].stream_info);
3273 /* Tell the HW to drop its old copy of the endpoint context info
3274 * and add the updated copy from the input context.
3276 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3277 vdev->out_ctx, ctrl_ctx,
3278 changed_ep_bitmask, changed_ep_bitmask);
3280 /* Issue and wait for the configure endpoint command */
3281 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3284 /* xHC rejected the configure endpoint command for some reason, so we
3285 * leave the old ring intact and free our internal streams data
3291 spin_lock_irqsave(&xhci->lock, flags);
3292 for (i = 0; i < num_eps; i++) {
3293 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3294 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3295 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3296 udev->slot_id, ep_index);
3297 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3299 xhci_free_command(xhci, config_cmd);
3300 spin_unlock_irqrestore(&xhci->lock, flags);
3302 /* Subtract 1 for stream 0, which drivers can't use */
3303 return num_streams - 1;
3306 /* If it didn't work, free the streams! */
3307 for (i = 0; i < num_eps; i++) {
3308 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3309 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3310 vdev->eps[ep_index].stream_info = NULL;
3311 /* FIXME Unset maxPstreams in endpoint context and
3312 * update deq ptr to point to normal string ring.
3314 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3315 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3316 xhci_endpoint_zero(xhci, vdev, eps[i]);
3318 xhci_free_command(xhci, config_cmd);
3322 /* Transition the endpoint from using streams to being a "normal" endpoint
3325 * Modify the endpoint context state, submit a configure endpoint command,
3326 * and free all endpoint rings for streams if that completes successfully.
3328 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3329 struct usb_host_endpoint **eps, unsigned int num_eps,
3333 struct xhci_hcd *xhci;
3334 struct xhci_virt_device *vdev;
3335 struct xhci_command *command;
3336 struct xhci_input_control_ctx *ctrl_ctx;
3337 unsigned int ep_index;
3338 unsigned long flags;
3339 u32 changed_ep_bitmask;
3341 xhci = hcd_to_xhci(hcd);
3342 vdev = xhci->devs[udev->slot_id];
3344 /* Set up a configure endpoint command to remove the streams rings */
3345 spin_lock_irqsave(&xhci->lock, flags);
3346 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3347 udev, eps, num_eps);
3348 if (changed_ep_bitmask == 0) {
3349 spin_unlock_irqrestore(&xhci->lock, flags);
3353 /* Use the xhci_command structure from the first endpoint. We may have
3354 * allocated too many, but the driver may call xhci_free_streams() for
3355 * each endpoint it grouped into one call to xhci_alloc_streams().
3357 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3358 command = vdev->eps[ep_index].stream_info->free_streams_command;
3359 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3361 spin_unlock_irqrestore(&xhci->lock, flags);
3362 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3367 for (i = 0; i < num_eps; i++) {
3368 struct xhci_ep_ctx *ep_ctx;
3370 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3371 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3372 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3373 EP_GETTING_NO_STREAMS;
3375 xhci_endpoint_copy(xhci, command->in_ctx,
3376 vdev->out_ctx, ep_index);
3377 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3378 &vdev->eps[ep_index]);
3380 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3381 vdev->out_ctx, ctrl_ctx,
3382 changed_ep_bitmask, changed_ep_bitmask);
3383 spin_unlock_irqrestore(&xhci->lock, flags);
3385 /* Issue and wait for the configure endpoint command,
3386 * which must succeed.
3388 ret = xhci_configure_endpoint(xhci, udev, command,
3391 /* xHC rejected the configure endpoint command for some reason, so we
3392 * leave the streams rings intact.
3397 spin_lock_irqsave(&xhci->lock, flags);
3398 for (i = 0; i < num_eps; i++) {
3399 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3400 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3401 vdev->eps[ep_index].stream_info = NULL;
3402 /* FIXME Unset maxPstreams in endpoint context and
3403 * update deq ptr to point to normal string ring.
3405 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3406 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3408 spin_unlock_irqrestore(&xhci->lock, flags);
3414 * Deletes endpoint resources for endpoints that were active before a Reset
3415 * Device command, or a Disable Slot command. The Reset Device command leaves
3416 * the control endpoint intact, whereas the Disable Slot command deletes it.
3418 * Must be called with xhci->lock held.
3420 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3421 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3424 unsigned int num_dropped_eps = 0;
3425 unsigned int drop_flags = 0;
3427 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3428 if (virt_dev->eps[i].ring) {
3429 drop_flags |= 1 << i;
3433 xhci->num_active_eps -= num_dropped_eps;
3434 if (num_dropped_eps)
3435 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3436 "Dropped %u ep ctxs, flags = 0x%x, "
3438 num_dropped_eps, drop_flags,
3439 xhci->num_active_eps);
3443 * This submits a Reset Device Command, which will set the device state to 0,
3444 * set the device address to 0, and disable all the endpoints except the default
3445 * control endpoint. The USB core should come back and call
3446 * xhci_address_device(), and then re-set up the configuration. If this is
3447 * called because of a usb_reset_and_verify_device(), then the old alternate
3448 * settings will be re-installed through the normal bandwidth allocation
3451 * Wait for the Reset Device command to finish. Remove all structures
3452 * associated with the endpoints that were disabled. Clear the input device
3453 * structure? Reset the control endpoint 0 max packet size?
3455 * If the virt_dev to be reset does not exist or does not match the udev,
3456 * it means the device is lost, possibly due to the xHC restore error and
3457 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3458 * re-allocate the device.
3460 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3461 struct usb_device *udev)
3464 unsigned long flags;
3465 struct xhci_hcd *xhci;
3466 unsigned int slot_id;
3467 struct xhci_virt_device *virt_dev;
3468 struct xhci_command *reset_device_cmd;
3469 int last_freed_endpoint;
3470 struct xhci_slot_ctx *slot_ctx;
3471 int old_active_eps = 0;
3473 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3476 xhci = hcd_to_xhci(hcd);
3477 slot_id = udev->slot_id;
3478 virt_dev = xhci->devs[slot_id];
3480 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3481 "not exist. Re-allocate the device\n", slot_id);
3482 ret = xhci_alloc_dev(hcd, udev);
3489 if (virt_dev->tt_info)
3490 old_active_eps = virt_dev->tt_info->active_eps;
3492 if (virt_dev->udev != udev) {
3493 /* If the virt_dev and the udev does not match, this virt_dev
3494 * may belong to another udev.
3495 * Re-allocate the device.
3497 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3498 "not match the udev. Re-allocate the device\n",
3500 ret = xhci_alloc_dev(hcd, udev);
3507 /* If device is not setup, there is no point in resetting it */
3508 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3509 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3510 SLOT_STATE_DISABLED)
3513 trace_xhci_discover_or_reset_device(slot_ctx);
3515 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3516 /* Allocate the command structure that holds the struct completion.
3517 * Assume we're in process context, since the normal device reset
3518 * process has to wait for the device anyway. Storage devices are
3519 * reset as part of error handling, so use GFP_NOIO instead of
3522 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3523 if (!reset_device_cmd) {
3524 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3528 /* Attempt to submit the Reset Device command to the command ring */
3529 spin_lock_irqsave(&xhci->lock, flags);
3531 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3533 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3534 spin_unlock_irqrestore(&xhci->lock, flags);
3535 goto command_cleanup;
3537 xhci_ring_cmd_db(xhci);
3538 spin_unlock_irqrestore(&xhci->lock, flags);
3540 /* Wait for the Reset Device command to finish */
3541 wait_for_completion(reset_device_cmd->completion);
3543 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3544 * unless we tried to reset a slot ID that wasn't enabled,
3545 * or the device wasn't in the addressed or configured state.
3547 ret = reset_device_cmd->status;
3549 case COMP_COMMAND_ABORTED:
3550 case COMP_COMMAND_RING_STOPPED:
3551 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3553 goto command_cleanup;
3554 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3555 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3556 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3558 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3559 xhci_dbg(xhci, "Not freeing device rings.\n");
3560 /* Don't treat this as an error. May change my mind later. */
3562 goto command_cleanup;
3564 xhci_dbg(xhci, "Successful reset device command.\n");
3567 if (xhci_is_vendor_info_code(xhci, ret))
3569 xhci_warn(xhci, "Unknown completion code %u for "
3570 "reset device command.\n", ret);
3572 goto command_cleanup;
3575 /* Free up host controller endpoint resources */
3576 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3577 spin_lock_irqsave(&xhci->lock, flags);
3578 /* Don't delete the default control endpoint resources */
3579 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3580 spin_unlock_irqrestore(&xhci->lock, flags);
3583 /* Everything but endpoint 0 is disabled, so free the rings. */
3584 last_freed_endpoint = 1;
3585 for (i = 1; i < 31; i++) {
3586 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3588 if (ep->ep_state & EP_HAS_STREAMS) {
3589 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3590 xhci_get_endpoint_address(i));
3591 xhci_free_stream_info(xhci, ep->stream_info);
3592 ep->stream_info = NULL;
3593 ep->ep_state &= ~EP_HAS_STREAMS;
3597 xhci_free_endpoint_ring(xhci, virt_dev, i);
3598 last_freed_endpoint = i;
3600 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3601 xhci_drop_ep_from_interval_table(xhci,
3602 &virt_dev->eps[i].bw_info,
3607 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3609 /* If necessary, update the number of active TTs on this root port */
3610 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3614 xhci_free_command(xhci, reset_device_cmd);
3619 * At this point, the struct usb_device is about to go away, the device has
3620 * disconnected, and all traffic has been stopped and the endpoints have been
3621 * disabled. Free any HC data structures associated with that device.
3623 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3625 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3626 struct xhci_virt_device *virt_dev;
3627 struct xhci_slot_ctx *slot_ctx;
3630 #ifndef CONFIG_USB_DEFAULT_PERSIST
3632 * We called pm_runtime_get_noresume when the device was attached.
3633 * Decrement the counter here to allow controller to runtime suspend
3634 * if no devices remain.
3636 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3637 pm_runtime_put_noidle(hcd->self.controller);
3640 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3641 /* If the host is halted due to driver unload, we still need to free the
3644 if (ret <= 0 && ret != -ENODEV)
3647 virt_dev = xhci->devs[udev->slot_id];
3648 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3649 trace_xhci_free_dev(slot_ctx);
3651 /* Stop any wayward timer functions (which may grab the lock) */
3652 for (i = 0; i < 31; i++) {
3653 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3654 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3657 virt_dev->udev = NULL;
3658 xhci_disable_slot(xhci, udev->slot_id);
3660 * Event command completion handler will free any data structures
3661 * associated with the slot. XXX Can free sleep?
3665 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3667 struct xhci_command *command;
3668 unsigned long flags;
3672 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3676 spin_lock_irqsave(&xhci->lock, flags);
3677 /* Don't disable the slot if the host controller is dead. */
3678 state = readl(&xhci->op_regs->status);
3679 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3680 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3681 spin_unlock_irqrestore(&xhci->lock, flags);
3686 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3689 spin_unlock_irqrestore(&xhci->lock, flags);
3693 xhci_ring_cmd_db(xhci);
3694 spin_unlock_irqrestore(&xhci->lock, flags);
3699 * Checks if we have enough host controller resources for the default control
3702 * Must be called with xhci->lock held.
3704 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3706 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3707 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3708 "Not enough ep ctxs: "
3709 "%u active, need to add 1, limit is %u.",
3710 xhci->num_active_eps, xhci->limit_active_eps);
3713 xhci->num_active_eps += 1;
3714 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3715 "Adding 1 ep ctx, %u now active.",
3716 xhci->num_active_eps);
3722 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3723 * timed out, or allocating memory failed. Returns 1 on success.
3725 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3727 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3728 struct xhci_virt_device *vdev;
3729 struct xhci_slot_ctx *slot_ctx;
3730 unsigned long flags;
3732 struct xhci_command *command;
3734 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
3738 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3739 mutex_lock(&xhci->mutex);
3740 spin_lock_irqsave(&xhci->lock, flags);
3741 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3743 spin_unlock_irqrestore(&xhci->lock, flags);
3744 mutex_unlock(&xhci->mutex);
3745 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3746 xhci_free_command(xhci, command);
3749 xhci_ring_cmd_db(xhci);
3750 spin_unlock_irqrestore(&xhci->lock, flags);
3752 wait_for_completion(command->completion);
3753 slot_id = command->slot_id;
3754 mutex_unlock(&xhci->mutex);
3756 if (!slot_id || command->status != COMP_SUCCESS) {
3757 xhci_err(xhci, "Error while assigning device slot ID\n");
3758 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3760 readl(&xhci->cap_regs->hcs_params1)));
3761 xhci_free_command(xhci, command);
3765 xhci_free_command(xhci, command);
3767 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3768 spin_lock_irqsave(&xhci->lock, flags);
3769 ret = xhci_reserve_host_control_ep_resources(xhci);
3771 spin_unlock_irqrestore(&xhci->lock, flags);
3772 xhci_warn(xhci, "Not enough host resources, "
3773 "active endpoint contexts = %u\n",
3774 xhci->num_active_eps);
3777 spin_unlock_irqrestore(&xhci->lock, flags);
3779 /* Use GFP_NOIO, since this function can be called from
3780 * xhci_discover_or_reset_device(), which may be called as part of
3781 * mass storage driver error handling.
3783 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3784 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3787 vdev = xhci->devs[slot_id];
3788 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
3789 trace_xhci_alloc_dev(slot_ctx);
3791 udev->slot_id = slot_id;
3793 #ifndef CONFIG_USB_DEFAULT_PERSIST
3795 * If resetting upon resume, we can't put the controller into runtime
3796 * suspend if there is a device attached.
3798 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3799 pm_runtime_get_noresume(hcd->self.controller);
3802 /* Is this a LS or FS device under a HS hub? */
3803 /* Hub or peripherial? */
3807 return xhci_disable_slot(xhci, udev->slot_id);
3811 * Issue an Address Device command and optionally send a corresponding
3812 * SetAddress request to the device.
3814 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3815 enum xhci_setup_dev setup)
3817 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3818 unsigned long flags;
3819 struct xhci_virt_device *virt_dev;
3821 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3822 struct xhci_slot_ctx *slot_ctx;
3823 struct xhci_input_control_ctx *ctrl_ctx;
3825 struct xhci_command *command = NULL;
3827 mutex_lock(&xhci->mutex);
3829 if (xhci->xhc_state) { /* dying, removing or halted */
3834 if (!udev->slot_id) {
3835 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3836 "Bad Slot ID %d", udev->slot_id);
3841 virt_dev = xhci->devs[udev->slot_id];
3843 if (WARN_ON(!virt_dev)) {
3845 * In plug/unplug torture test with an NEC controller,
3846 * a zero-dereference was observed once due to virt_dev = 0.
3847 * Print useful debug rather than crash if it is observed again!
3849 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3854 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3855 trace_xhci_setup_device_slot(slot_ctx);
3857 if (setup == SETUP_CONTEXT_ONLY) {
3858 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3859 SLOT_STATE_DEFAULT) {
3860 xhci_dbg(xhci, "Slot already in default state\n");
3865 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
3871 command->in_ctx = virt_dev->in_ctx;
3873 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3874 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3876 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3882 * If this is the first Set Address since device plug-in or
3883 * virt_device realloaction after a resume with an xHCI power loss,
3884 * then set up the slot context.
3886 if (!slot_ctx->dev_info)
3887 xhci_setup_addressable_virt_dev(xhci, udev);
3888 /* Otherwise, update the control endpoint ring enqueue pointer. */
3890 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3891 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3892 ctrl_ctx->drop_flags = 0;
3894 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3895 le32_to_cpu(slot_ctx->dev_info) >> 27);
3897 spin_lock_irqsave(&xhci->lock, flags);
3898 trace_xhci_setup_device(virt_dev);
3899 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3900 udev->slot_id, setup);
3902 spin_unlock_irqrestore(&xhci->lock, flags);
3903 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3904 "FIXME: allocate a command ring segment");
3907 xhci_ring_cmd_db(xhci);
3908 spin_unlock_irqrestore(&xhci->lock, flags);
3910 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3911 wait_for_completion(command->completion);
3913 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3914 * the SetAddress() "recovery interval" required by USB and aborting the
3915 * command on a timeout.
3917 switch (command->status) {
3918 case COMP_COMMAND_ABORTED:
3919 case COMP_COMMAND_RING_STOPPED:
3920 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3923 case COMP_CONTEXT_STATE_ERROR:
3924 case COMP_SLOT_NOT_ENABLED_ERROR:
3925 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3926 act, udev->slot_id);
3929 case COMP_USB_TRANSACTION_ERROR:
3930 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3933 case COMP_INCOMPATIBLE_DEVICE_ERROR:
3934 dev_warn(&udev->dev,
3935 "ERROR: Incompatible device for setup %s command\n", act);
3939 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3940 "Successful setup %s command", act);
3944 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3945 act, command->status);
3946 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3952 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3953 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3954 "Op regs DCBAA ptr = %#016llx", temp_64);
3955 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3956 "Slot ID %d dcbaa entry @%p = %#016llx",
3958 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3959 (unsigned long long)
3960 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3961 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3962 "Output Context DMA address = %#08llx",
3963 (unsigned long long)virt_dev->out_ctx->dma);
3964 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3965 le32_to_cpu(slot_ctx->dev_info) >> 27);
3967 * USB core uses address 1 for the roothubs, so we add one to the
3968 * address given back to us by the HC.
3970 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3971 le32_to_cpu(slot_ctx->dev_info) >> 27);
3972 /* Zero the input context control for later use */
3973 ctrl_ctx->add_flags = 0;
3974 ctrl_ctx->drop_flags = 0;
3976 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3977 "Internal device address = %d",
3978 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
3980 mutex_unlock(&xhci->mutex);
3982 kfree(command->completion);
3988 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3990 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
3993 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
3995 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
3999 * Transfer the port index into real index in the HW port status
4000 * registers. Caculate offset between the port's PORTSC register
4001 * and port status base. Divide the number of per port register
4002 * to get the real index. The raw port number bases 1.
4004 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4006 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4007 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
4008 __le32 __iomem *addr;
4011 if (hcd->speed < HCD_USB3)
4012 addr = xhci->usb2_ports[port1 - 1];
4014 addr = xhci->usb3_ports[port1 - 1];
4016 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
4021 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4022 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4024 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4025 struct usb_device *udev, u16 max_exit_latency)
4027 struct xhci_virt_device *virt_dev;
4028 struct xhci_command *command;
4029 struct xhci_input_control_ctx *ctrl_ctx;
4030 struct xhci_slot_ctx *slot_ctx;
4031 unsigned long flags;
4034 spin_lock_irqsave(&xhci->lock, flags);
4036 virt_dev = xhci->devs[udev->slot_id];
4039 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4040 * xHC was re-initialized. Exit latency will be set later after
4041 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4044 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4045 spin_unlock_irqrestore(&xhci->lock, flags);
4049 /* Attempt to issue an Evaluate Context command to change the MEL. */
4050 command = xhci->lpm_command;
4051 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4053 spin_unlock_irqrestore(&xhci->lock, flags);
4054 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4059 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4060 spin_unlock_irqrestore(&xhci->lock, flags);
4062 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4063 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4064 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4065 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4066 slot_ctx->dev_state = 0;
4068 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4069 "Set up evaluate context for LPM MEL change.");
4071 /* Issue and wait for the evaluate context command. */
4072 ret = xhci_configure_endpoint(xhci, udev, command,
4076 spin_lock_irqsave(&xhci->lock, flags);
4077 virt_dev->current_mel = max_exit_latency;
4078 spin_unlock_irqrestore(&xhci->lock, flags);
4085 /* BESL to HIRD Encoding array for USB2 LPM */
4086 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4087 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4089 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4090 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4091 struct usb_device *udev)
4093 int u2del, besl, besl_host;
4094 int besl_device = 0;
4097 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4098 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4100 if (field & USB_BESL_SUPPORT) {
4101 for (besl_host = 0; besl_host < 16; besl_host++) {
4102 if (xhci_besl_encoding[besl_host] >= u2del)
4105 /* Use baseline BESL value as default */
4106 if (field & USB_BESL_BASELINE_VALID)
4107 besl_device = USB_GET_BESL_BASELINE(field);
4108 else if (field & USB_BESL_DEEP_VALID)
4109 besl_device = USB_GET_BESL_DEEP(field);
4114 besl_host = (u2del - 51) / 75 + 1;
4117 besl = besl_host + besl_device;
4124 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4125 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4132 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4134 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4135 l1 = udev->l1_params.timeout / 256;
4137 /* device has preferred BESLD */
4138 if (field & USB_BESL_DEEP_VALID) {
4139 besld = USB_GET_BESL_DEEP(field);
4143 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4146 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4147 struct usb_device *udev, int enable)
4149 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4150 __le32 __iomem **port_array;
4151 __le32 __iomem *pm_addr, *hlpm_addr;
4152 u32 pm_val, hlpm_val, field;
4153 unsigned int port_num;
4154 unsigned long flags;
4155 int hird, exit_latency;
4158 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4162 if (!udev->parent || udev->parent->parent ||
4163 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4166 if (udev->usb2_hw_lpm_capable != 1)
4169 spin_lock_irqsave(&xhci->lock, flags);
4171 port_array = xhci->usb2_ports;
4172 port_num = udev->portnum - 1;
4173 pm_addr = port_array[port_num] + PORTPMSC;
4174 pm_val = readl(pm_addr);
4175 hlpm_addr = port_array[port_num] + PORTHLPMC;
4177 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4178 enable ? "enable" : "disable", port_num + 1);
4181 /* Host supports BESL timeout instead of HIRD */
4182 if (udev->usb2_hw_lpm_besl_capable) {
4183 /* if device doesn't have a preferred BESL value use a
4184 * default one which works with mixed HIRD and BESL
4185 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4187 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4188 if ((field & USB_BESL_SUPPORT) &&
4189 (field & USB_BESL_BASELINE_VALID))
4190 hird = USB_GET_BESL_BASELINE(field);
4192 hird = udev->l1_params.besl;
4194 exit_latency = xhci_besl_encoding[hird];
4195 spin_unlock_irqrestore(&xhci->lock, flags);
4197 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4198 * input context for link powermanagement evaluate
4199 * context commands. It is protected by hcd->bandwidth
4200 * mutex and is shared by all devices. We need to set
4201 * the max ext latency in USB 2 BESL LPM as well, so
4202 * use the same mutex and xhci_change_max_exit_latency()
4204 mutex_lock(hcd->bandwidth_mutex);
4205 ret = xhci_change_max_exit_latency(xhci, udev,
4207 mutex_unlock(hcd->bandwidth_mutex);
4211 spin_lock_irqsave(&xhci->lock, flags);
4213 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4214 writel(hlpm_val, hlpm_addr);
4218 hird = xhci_calculate_hird_besl(xhci, udev);
4221 pm_val &= ~PORT_HIRD_MASK;
4222 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4223 writel(pm_val, pm_addr);
4224 pm_val = readl(pm_addr);
4226 writel(pm_val, pm_addr);
4230 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4231 writel(pm_val, pm_addr);
4234 if (udev->usb2_hw_lpm_besl_capable) {
4235 spin_unlock_irqrestore(&xhci->lock, flags);
4236 mutex_lock(hcd->bandwidth_mutex);
4237 xhci_change_max_exit_latency(xhci, udev, 0);
4238 mutex_unlock(hcd->bandwidth_mutex);
4239 readl_poll_timeout(port_array[port_num], pm_val,
4240 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4246 spin_unlock_irqrestore(&xhci->lock, flags);
4250 /* check if a usb2 port supports a given extened capability protocol
4251 * only USB2 ports extended protocol capability values are cached.
4252 * Return 1 if capability is supported
4254 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4255 unsigned capability)
4257 u32 port_offset, port_count;
4260 for (i = 0; i < xhci->num_ext_caps; i++) {
4261 if (xhci->ext_caps[i] & capability) {
4262 /* port offsets starts at 1 */
4263 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4264 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4265 if (port >= port_offset &&
4266 port < port_offset + port_count)
4273 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4275 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4276 int portnum = udev->portnum - 1;
4278 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4282 /* we only support lpm for non-hub device connected to root hub yet */
4283 if (!udev->parent || udev->parent->parent ||
4284 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4287 if (xhci->hw_lpm_support == 1 &&
4288 xhci_check_usb2_port_capability(
4289 xhci, portnum, XHCI_HLC)) {
4290 udev->usb2_hw_lpm_capable = 1;
4291 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4292 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4293 if (xhci_check_usb2_port_capability(xhci, portnum,
4295 udev->usb2_hw_lpm_besl_capable = 1;
4301 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4303 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4304 static unsigned long long xhci_service_interval_to_ns(
4305 struct usb_endpoint_descriptor *desc)
4307 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4310 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4311 enum usb3_link_state state)
4313 unsigned long long sel;
4314 unsigned long long pel;
4315 unsigned int max_sel_pel;
4320 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4321 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4322 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4323 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4327 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4328 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4329 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4333 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4335 return USB3_LPM_DISABLED;
4338 if (sel <= max_sel_pel && pel <= max_sel_pel)
4339 return USB3_LPM_DEVICE_INITIATED;
4341 if (sel > max_sel_pel)
4342 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4343 "due to long SEL %llu ms\n",
4346 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4347 "due to long PEL %llu ms\n",
4349 return USB3_LPM_DISABLED;
4352 /* The U1 timeout should be the maximum of the following values:
4353 * - For control endpoints, U1 system exit latency (SEL) * 3
4354 * - For bulk endpoints, U1 SEL * 5
4355 * - For interrupt endpoints:
4356 * - Notification EPs, U1 SEL * 3
4357 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4358 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4360 static unsigned long long xhci_calculate_intel_u1_timeout(
4361 struct usb_device *udev,
4362 struct usb_endpoint_descriptor *desc)
4364 unsigned long long timeout_ns;
4368 ep_type = usb_endpoint_type(desc);
4370 case USB_ENDPOINT_XFER_CONTROL:
4371 timeout_ns = udev->u1_params.sel * 3;
4373 case USB_ENDPOINT_XFER_BULK:
4374 timeout_ns = udev->u1_params.sel * 5;
4376 case USB_ENDPOINT_XFER_INT:
4377 intr_type = usb_endpoint_interrupt_type(desc);
4378 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4379 timeout_ns = udev->u1_params.sel * 3;
4382 /* Otherwise the calculation is the same as isoc eps */
4383 case USB_ENDPOINT_XFER_ISOC:
4384 timeout_ns = xhci_service_interval_to_ns(desc);
4385 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4386 if (timeout_ns < udev->u1_params.sel * 2)
4387 timeout_ns = udev->u1_params.sel * 2;
4396 /* Returns the hub-encoded U1 timeout value. */
4397 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4398 struct usb_device *udev,
4399 struct usb_endpoint_descriptor *desc)
4401 unsigned long long timeout_ns;
4403 /* Prevent U1 if service interval is shorter than U1 exit latency */
4404 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4405 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4406 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4407 return USB3_LPM_DISABLED;
4411 if (xhci->quirks & XHCI_INTEL_HOST)
4412 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4414 timeout_ns = udev->u1_params.sel;
4416 /* The U1 timeout is encoded in 1us intervals.
4417 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4419 if (timeout_ns == USB3_LPM_DISABLED)
4422 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4424 /* If the necessary timeout value is bigger than what we can set in the
4425 * USB 3.0 hub, we have to disable hub-initiated U1.
4427 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4429 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4430 "due to long timeout %llu ms\n", timeout_ns);
4431 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4434 /* The U2 timeout should be the maximum of:
4435 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4436 * - largest bInterval of any active periodic endpoint (to avoid going
4437 * into lower power link states between intervals).
4438 * - the U2 Exit Latency of the device
4440 static unsigned long long xhci_calculate_intel_u2_timeout(
4441 struct usb_device *udev,
4442 struct usb_endpoint_descriptor *desc)
4444 unsigned long long timeout_ns;
4445 unsigned long long u2_del_ns;
4447 timeout_ns = 10 * 1000 * 1000;
4449 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4450 (xhci_service_interval_to_ns(desc) > timeout_ns))
4451 timeout_ns = xhci_service_interval_to_ns(desc);
4453 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4454 if (u2_del_ns > timeout_ns)
4455 timeout_ns = u2_del_ns;
4460 /* Returns the hub-encoded U2 timeout value. */
4461 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4462 struct usb_device *udev,
4463 struct usb_endpoint_descriptor *desc)
4465 unsigned long long timeout_ns;
4467 /* Prevent U2 if service interval is shorter than U2 exit latency */
4468 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4469 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4470 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4471 return USB3_LPM_DISABLED;
4475 if (xhci->quirks & XHCI_INTEL_HOST)
4476 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4478 timeout_ns = udev->u2_params.sel;
4480 /* The U2 timeout is encoded in 256us intervals */
4481 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4482 /* If the necessary timeout value is bigger than what we can set in the
4483 * USB 3.0 hub, we have to disable hub-initiated U2.
4485 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4487 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4488 "due to long timeout %llu ms\n", timeout_ns);
4489 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4492 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4493 struct usb_device *udev,
4494 struct usb_endpoint_descriptor *desc,
4495 enum usb3_link_state state,
4498 if (state == USB3_LPM_U1)
4499 return xhci_calculate_u1_timeout(xhci, udev, desc);
4500 else if (state == USB3_LPM_U2)
4501 return xhci_calculate_u2_timeout(xhci, udev, desc);
4503 return USB3_LPM_DISABLED;
4506 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4507 struct usb_device *udev,
4508 struct usb_endpoint_descriptor *desc,
4509 enum usb3_link_state state,
4514 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4515 desc, state, timeout);
4517 /* If we found we can't enable hub-initiated LPM, and
4518 * the U1 or U2 exit latency was too high to allow
4519 * device-initiated LPM as well, then we will disable LPM
4520 * for this device, so stop searching any further.
4522 if (alt_timeout == USB3_LPM_DISABLED) {
4523 *timeout = alt_timeout;
4526 if (alt_timeout > *timeout)
4527 *timeout = alt_timeout;
4531 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4532 struct usb_device *udev,
4533 struct usb_host_interface *alt,
4534 enum usb3_link_state state,
4539 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4540 if (xhci_update_timeout_for_endpoint(xhci, udev,
4541 &alt->endpoint[j].desc, state, timeout))
4548 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4549 enum usb3_link_state state)
4551 struct usb_device *parent;
4552 unsigned int num_hubs;
4554 if (state == USB3_LPM_U2)
4557 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4558 for (parent = udev->parent, num_hubs = 0; parent->parent;
4559 parent = parent->parent)
4565 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4566 " below second-tier hub.\n");
4567 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4568 "to decrease power consumption.\n");
4572 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4573 struct usb_device *udev,
4574 enum usb3_link_state state)
4576 if (xhci->quirks & XHCI_INTEL_HOST)
4577 return xhci_check_intel_tier_policy(udev, state);
4582 /* Returns the U1 or U2 timeout that should be enabled.
4583 * If the tier check or timeout setting functions return with a non-zero exit
4584 * code, that means the timeout value has been finalized and we shouldn't look
4585 * at any more endpoints.
4587 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4588 struct usb_device *udev, enum usb3_link_state state)
4590 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4591 struct usb_host_config *config;
4594 u16 timeout = USB3_LPM_DISABLED;
4596 if (state == USB3_LPM_U1)
4598 else if (state == USB3_LPM_U2)
4601 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4606 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4609 /* Gather some information about the currently installed configuration
4610 * and alternate interface settings.
4612 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4616 config = udev->actconfig;
4620 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4621 struct usb_driver *driver;
4622 struct usb_interface *intf = config->interface[i];
4627 /* Check if any currently bound drivers want hub-initiated LPM
4630 if (intf->dev.driver) {
4631 driver = to_usb_driver(intf->dev.driver);
4632 if (driver && driver->disable_hub_initiated_lpm) {
4633 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4634 state_name, driver->name);
4635 timeout = xhci_get_timeout_no_hub_lpm(udev,
4637 if (timeout == USB3_LPM_DISABLED)
4642 /* Not sure how this could happen... */
4643 if (!intf->cur_altsetting)
4646 if (xhci_update_timeout_for_interface(xhci, udev,
4647 intf->cur_altsetting,
4654 static int calculate_max_exit_latency(struct usb_device *udev,
4655 enum usb3_link_state state_changed,
4656 u16 hub_encoded_timeout)
4658 unsigned long long u1_mel_us = 0;
4659 unsigned long long u2_mel_us = 0;
4660 unsigned long long mel_us = 0;
4666 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4667 hub_encoded_timeout == USB3_LPM_DISABLED);
4668 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4669 hub_encoded_timeout == USB3_LPM_DISABLED);
4671 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4672 hub_encoded_timeout != USB3_LPM_DISABLED);
4673 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4674 hub_encoded_timeout != USB3_LPM_DISABLED);
4676 /* If U1 was already enabled and we're not disabling it,
4677 * or we're going to enable U1, account for the U1 max exit latency.
4679 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4681 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4682 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4684 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4686 if (u1_mel_us > u2_mel_us)
4690 /* xHCI host controller max exit latency field is only 16 bits wide. */
4691 if (mel_us > MAX_EXIT) {
4692 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4693 "is too big.\n", mel_us);
4699 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4700 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4701 struct usb_device *udev, enum usb3_link_state state)
4703 struct xhci_hcd *xhci;
4704 u16 hub_encoded_timeout;
4708 xhci = hcd_to_xhci(hcd);
4709 /* The LPM timeout values are pretty host-controller specific, so don't
4710 * enable hub-initiated timeouts unless the vendor has provided
4711 * information about their timeout algorithm.
4713 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4714 !xhci->devs[udev->slot_id])
4715 return USB3_LPM_DISABLED;
4717 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4718 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4720 /* Max Exit Latency is too big, disable LPM. */
4721 hub_encoded_timeout = USB3_LPM_DISABLED;
4725 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4728 return hub_encoded_timeout;
4731 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4732 struct usb_device *udev, enum usb3_link_state state)
4734 struct xhci_hcd *xhci;
4737 xhci = hcd_to_xhci(hcd);
4738 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4739 !xhci->devs[udev->slot_id])
4742 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4743 return xhci_change_max_exit_latency(xhci, udev, mel);
4745 #else /* CONFIG_PM */
4747 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4748 struct usb_device *udev, int enable)
4753 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4758 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4759 struct usb_device *udev, enum usb3_link_state state)
4761 return USB3_LPM_DISABLED;
4764 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4765 struct usb_device *udev, enum usb3_link_state state)
4769 #endif /* CONFIG_PM */
4771 /*-------------------------------------------------------------------------*/
4773 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4774 * internal data structures for the device.
4776 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4777 struct usb_tt *tt, gfp_t mem_flags)
4779 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4780 struct xhci_virt_device *vdev;
4781 struct xhci_command *config_cmd;
4782 struct xhci_input_control_ctx *ctrl_ctx;
4783 struct xhci_slot_ctx *slot_ctx;
4784 unsigned long flags;
4785 unsigned think_time;
4788 /* Ignore root hubs */
4792 vdev = xhci->devs[hdev->slot_id];
4794 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4798 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4802 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4804 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4806 xhci_free_command(xhci, config_cmd);
4810 spin_lock_irqsave(&xhci->lock, flags);
4811 if (hdev->speed == USB_SPEED_HIGH &&
4812 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4813 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4814 xhci_free_command(xhci, config_cmd);
4815 spin_unlock_irqrestore(&xhci->lock, flags);
4819 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4820 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4821 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4822 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4824 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4825 * but it may be already set to 1 when setup an xHCI virtual
4826 * device, so clear it anyway.
4829 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4830 else if (hdev->speed == USB_SPEED_FULL)
4831 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4833 if (xhci->hci_version > 0x95) {
4834 xhci_dbg(xhci, "xHCI version %x needs hub "
4835 "TT think time and number of ports\n",
4836 (unsigned int) xhci->hci_version);
4837 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4838 /* Set TT think time - convert from ns to FS bit times.
4839 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4840 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4842 * xHCI 1.0: this field shall be 0 if the device is not a
4845 think_time = tt->think_time;
4846 if (think_time != 0)
4847 think_time = (think_time / 666) - 1;
4848 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4849 slot_ctx->tt_info |=
4850 cpu_to_le32(TT_THINK_TIME(think_time));
4852 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4853 "TT think time or number of ports\n",
4854 (unsigned int) xhci->hci_version);
4856 slot_ctx->dev_state = 0;
4857 spin_unlock_irqrestore(&xhci->lock, flags);
4859 xhci_dbg(xhci, "Set up %s for hub device.\n",
4860 (xhci->hci_version > 0x95) ?
4861 "configure endpoint" : "evaluate context");
4863 /* Issue and wait for the configure endpoint or
4864 * evaluate context command.
4866 if (xhci->hci_version > 0x95)
4867 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4870 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4873 xhci_free_command(xhci, config_cmd);
4877 static int xhci_get_frame(struct usb_hcd *hcd)
4879 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4880 /* EHCI mods by the periodic size. Why? */
4881 return readl(&xhci->run_regs->microframe_index) >> 3;
4884 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4886 struct xhci_hcd *xhci;
4888 * TODO: Check with DWC3 clients for sysdev according to
4891 struct device *dev = hcd->self.sysdev;
4892 unsigned int minor_rev;
4895 /* Accept arbitrarily long scatter-gather lists */
4896 hcd->self.sg_tablesize = ~0;
4898 /* support to build packet from discontinuous buffers */
4899 hcd->self.no_sg_constraint = 1;
4901 /* XHCI controllers don't stop the ep queue on short packets :| */
4902 hcd->self.no_stop_on_short = 1;
4904 xhci = hcd_to_xhci(hcd);
4906 if (usb_hcd_is_primary_hcd(hcd)) {
4907 xhci->main_hcd = hcd;
4908 /* Mark the first roothub as being USB 2.0.
4909 * The xHCI driver will register the USB 3.0 roothub.
4911 hcd->speed = HCD_USB2;
4912 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4914 * USB 2.0 roothub under xHCI has an integrated TT,
4915 * (rate matching hub) as opposed to having an OHCI/UHCI
4916 * companion controller.
4921 * Some 3.1 hosts return sbrn 0x30, use xhci supported protocol
4922 * minor revision instead of sbrn
4924 minor_rev = xhci->usb3_rhub.min_rev;
4926 hcd->speed = HCD_USB31;
4927 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
4929 xhci_info(xhci, "Host supports USB 3.%x %s SuperSpeed\n",
4931 minor_rev ? "Enhanced" : "");
4933 /* xHCI private pointer was set in xhci_pci_probe for the second
4934 * registered roothub.
4939 mutex_init(&xhci->mutex);
4940 xhci->cap_regs = hcd->regs;
4941 xhci->op_regs = hcd->regs +
4942 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4943 xhci->run_regs = hcd->regs +
4944 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4945 /* Cache read-only capability registers */
4946 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4947 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4948 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4949 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4950 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4951 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4952 if (xhci->hci_version > 0x100)
4953 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4954 xhci_print_registers(xhci);
4956 xhci->quirks |= quirks;
4958 get_quirks(dev, xhci);
4960 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4961 * success event after a short transfer. This quirk will ignore such
4964 if (xhci->hci_version > 0x96)
4965 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4967 /* Make sure the HC is halted. */
4968 retval = xhci_halt(xhci);
4972 xhci_dbg(xhci, "Resetting HCD\n");
4973 /* Reset the internal HC memory state and registers. */
4974 retval = xhci_reset(xhci);
4977 xhci_dbg(xhci, "Reset complete\n");
4980 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
4981 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
4982 * address memory pointers actually. So, this driver clears the AC64
4983 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
4984 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
4986 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
4987 xhci->hcc_params &= ~BIT(0);
4989 /* Set dma_mask and coherent_dma_mask to 64-bits,
4990 * if xHC supports 64-bit addressing */
4991 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
4992 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
4993 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4994 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
4997 * This is to avoid error in cases where a 32-bit USB
4998 * controller is used on a 64-bit capable system.
5000 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5003 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5004 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5007 xhci_dbg(xhci, "Calling HCD init\n");
5008 /* Initialize HCD and host controller data structures. */
5009 retval = xhci_init(hcd);
5012 xhci_dbg(xhci, "Called HCD init\n");
5014 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5015 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5019 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5021 static const struct hc_driver xhci_hc_driver = {
5022 .description = "xhci-hcd",
5023 .product_desc = "xHCI Host Controller",
5024 .hcd_priv_size = sizeof(struct xhci_hcd),
5027 * generic hardware linkage
5030 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
5033 * basic lifecycle operations
5035 .reset = NULL, /* set in xhci_init_driver() */
5038 .shutdown = xhci_shutdown,
5041 * managing i/o requests and associated device resources
5043 .urb_enqueue = xhci_urb_enqueue,
5044 .urb_dequeue = xhci_urb_dequeue,
5045 .alloc_dev = xhci_alloc_dev,
5046 .free_dev = xhci_free_dev,
5047 .alloc_streams = xhci_alloc_streams,
5048 .free_streams = xhci_free_streams,
5049 .add_endpoint = xhci_add_endpoint,
5050 .drop_endpoint = xhci_drop_endpoint,
5051 .endpoint_reset = xhci_endpoint_reset,
5052 .check_bandwidth = xhci_check_bandwidth,
5053 .reset_bandwidth = xhci_reset_bandwidth,
5054 .address_device = xhci_address_device,
5055 .enable_device = xhci_enable_device,
5056 .update_hub_device = xhci_update_hub_device,
5057 .reset_device = xhci_discover_or_reset_device,
5060 * scheduling support
5062 .get_frame_number = xhci_get_frame,
5067 .hub_control = xhci_hub_control,
5068 .hub_status_data = xhci_hub_status_data,
5069 .bus_suspend = xhci_bus_suspend,
5070 .bus_resume = xhci_bus_resume,
5073 * call back when device connected and addressed
5075 .update_device = xhci_update_device,
5076 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5077 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5078 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5079 .find_raw_port_number = xhci_find_raw_port_number,
5082 void xhci_init_driver(struct hc_driver *drv,
5083 const struct xhci_driver_overrides *over)
5087 /* Copy the generic table to drv then apply the overrides */
5088 *drv = xhci_hc_driver;
5091 drv->hcd_priv_size += over->extra_priv_size;
5093 drv->reset = over->reset;
5095 drv->start = over->start;
5098 EXPORT_SYMBOL_GPL(xhci_init_driver);
5100 MODULE_DESCRIPTION(DRIVER_DESC);
5101 MODULE_AUTHOR(DRIVER_AUTHOR);
5102 MODULE_LICENSE("GPL");
5104 static int __init xhci_hcd_init(void)
5107 * Check the compiler generated sizes of structures that must be laid
5108 * out in specific ways for hardware access.
5110 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5111 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5112 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5113 /* xhci_device_control has eight fields, and also
5114 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5116 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5117 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5118 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5119 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5120 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5121 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5122 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5131 * If an init function is provided, an exit function must also be provided
5132 * to allow module unload.
5134 static void __exit xhci_hcd_fini(void) { }
5136 module_init(xhci_hcd_init);
5137 module_exit(xhci_hcd_fini);