2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/iopoll.h>
25 #include <linux/irq.h>
26 #include <linux/log2.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/slab.h>
30 #include <linux/dmi.h>
31 #include <linux/dma-mapping.h>
34 #include "xhci-trace.h"
37 #define DRIVER_AUTHOR "Sarah Sharp"
38 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
40 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
42 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
43 static int link_quirk;
44 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
45 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
47 static unsigned int quirks;
48 module_param(quirks, uint, S_IRUGO);
49 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
52 * xhci_handshake - spin reading hc until handshake completes or fails
53 * @ptr: address of hc register to be read
54 * @mask: bits to look at in result of read
55 * @done: value of those bits when handshake succeeds
56 * @usec: timeout in microseconds
58 * Returns negative errno, or zero on success
60 * Success happens when the "mask" bits have the specified value (hardware
61 * handshake done). There are two failure modes: "usec" have passed (major
62 * hardware flakeout), or the register reads as all-ones (hardware removed).
64 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
69 ret = readl_poll_timeout_atomic(ptr, result,
70 (result & mask) == done ||
73 if (result == U32_MAX) /* card removed */
80 * Disable interrupts and begin the xHCI halting process.
82 void xhci_quiesce(struct xhci_hcd *xhci)
89 halted = readl(&xhci->op_regs->status) & STS_HALT;
93 cmd = readl(&xhci->op_regs->command);
95 writel(cmd, &xhci->op_regs->command);
99 * Force HC into halt state.
101 * Disable any IRQs and clear the run/stop bit.
102 * HC will complete any current and actively pipelined transactions, and
103 * should halt within 16 ms of the run/stop bit being cleared.
104 * Read HC Halted bit in the status register to see when the HC is finished.
106 int xhci_halt(struct xhci_hcd *xhci)
109 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
112 ret = xhci_handshake(&xhci->op_regs->status,
113 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
115 xhci->xhc_state |= XHCI_STATE_HALTED;
116 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
118 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
124 * Set the run bit and wait for the host to be running.
126 static int xhci_start(struct xhci_hcd *xhci)
131 temp = readl(&xhci->op_regs->command);
133 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
135 writel(temp, &xhci->op_regs->command);
138 * Wait for the HCHalted Status bit to be 0 to indicate the host is
141 ret = xhci_handshake(&xhci->op_regs->status,
142 STS_HALT, 0, XHCI_MAX_HALT_USEC);
143 if (ret == -ETIMEDOUT)
144 xhci_err(xhci, "Host took too long to start, "
145 "waited %u microseconds.\n",
148 /* clear state flags. Including dying, halted or removing */
150 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
159 * This resets pipelines, timers, counters, state machines, etc.
160 * Transactions will be terminated immediately, and operational registers
161 * will be set to their defaults.
163 int xhci_reset(struct xhci_hcd *xhci)
169 state = readl(&xhci->op_regs->status);
170 if ((state & STS_HALT) == 0) {
171 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
175 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
176 command = readl(&xhci->op_regs->command);
177 command |= CMD_RESET;
178 writel(command, &xhci->op_regs->command);
180 /* Existing Intel xHCI controllers require a delay of 1 mS,
181 * after setting the CMD_RESET bit, and before accessing any
182 * HC registers. This allows the HC to complete the
183 * reset operation and be ready for HC register access.
184 * Without this delay, the subsequent HC register access,
185 * may result in a system hang very rarely.
187 if (xhci->quirks & XHCI_INTEL_HOST)
190 ret = xhci_handshake(&xhci->op_regs->command,
191 CMD_RESET, 0, 10 * 1000 * 1000);
195 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
196 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
198 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
199 "Wait for controller to be ready for doorbell rings");
201 * xHCI cannot write to any doorbells or operational registers other
202 * than status until the "Controller Not Ready" flag is cleared.
204 ret = xhci_handshake(&xhci->op_regs->status,
205 STS_CNR, 0, 10 * 1000 * 1000);
207 for (i = 0; i < 2; ++i) {
208 xhci->bus_state[i].port_c_suspend = 0;
209 xhci->bus_state[i].suspended_ports = 0;
210 xhci->bus_state[i].resuming_ports = 0;
217 static int xhci_free_msi(struct xhci_hcd *xhci)
221 if (!xhci->msix_entries)
224 for (i = 0; i < xhci->msix_count; i++)
225 if (xhci->msix_entries[i].vector)
226 free_irq(xhci->msix_entries[i].vector,
234 static int xhci_setup_msi(struct xhci_hcd *xhci)
237 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
239 ret = pci_enable_msi(pdev);
241 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
242 "failed to allocate MSI entry");
246 ret = request_irq(pdev->irq, xhci_msi_irq,
247 0, "xhci_hcd", xhci_to_hcd(xhci));
249 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
250 "disable MSI interrupt");
251 pci_disable_msi(pdev);
259 * free all IRQs request
261 static void xhci_free_irq(struct xhci_hcd *xhci)
263 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
266 /* return if using legacy interrupt */
267 if (xhci_to_hcd(xhci)->irq > 0)
270 ret = xhci_free_msi(xhci);
274 free_irq(pdev->irq, xhci_to_hcd(xhci));
282 static int xhci_setup_msix(struct xhci_hcd *xhci)
285 struct usb_hcd *hcd = xhci_to_hcd(xhci);
286 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
289 * calculate number of msi-x vectors supported.
290 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
291 * with max number of interrupters based on the xhci HCSPARAMS1.
292 * - num_online_cpus: maximum msi-x vectors per CPUs core.
293 * Add additional 1 vector to ensure always available interrupt.
295 xhci->msix_count = min(num_online_cpus() + 1,
296 HCS_MAX_INTRS(xhci->hcs_params1));
299 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
301 if (!xhci->msix_entries)
304 for (i = 0; i < xhci->msix_count; i++) {
305 xhci->msix_entries[i].entry = i;
306 xhci->msix_entries[i].vector = 0;
309 ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count);
311 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
312 "Failed to enable MSI-X");
316 for (i = 0; i < xhci->msix_count; i++) {
317 ret = request_irq(xhci->msix_entries[i].vector,
319 0, "xhci_hcd", xhci_to_hcd(xhci));
324 hcd->msix_enabled = 1;
328 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
330 pci_disable_msix(pdev);
332 kfree(xhci->msix_entries);
333 xhci->msix_entries = NULL;
337 /* Free any IRQs and disable MSI-X */
338 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
340 struct usb_hcd *hcd = xhci_to_hcd(xhci);
341 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
343 if (xhci->quirks & XHCI_PLAT)
348 if (xhci->msix_entries) {
349 pci_disable_msix(pdev);
350 kfree(xhci->msix_entries);
351 xhci->msix_entries = NULL;
353 pci_disable_msi(pdev);
356 hcd->msix_enabled = 0;
360 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
364 if (xhci->msix_entries) {
365 for (i = 0; i < xhci->msix_count; i++)
366 synchronize_irq(xhci->msix_entries[i].vector);
370 static int xhci_try_enable_msi(struct usb_hcd *hcd)
372 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
373 struct pci_dev *pdev;
376 /* The xhci platform device has set up IRQs through usb_add_hcd. */
377 if (xhci->quirks & XHCI_PLAT)
380 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
382 * Some Fresco Logic host controllers advertise MSI, but fail to
383 * generate interrupts. Don't even try to enable MSI.
385 if (xhci->quirks & XHCI_BROKEN_MSI)
388 /* unregister the legacy interrupt */
390 free_irq(hcd->irq, hcd);
393 ret = xhci_setup_msix(xhci);
395 /* fall back to msi*/
396 ret = xhci_setup_msi(xhci);
399 /* hcd->irq is 0, we have MSI */
403 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
408 if (!strlen(hcd->irq_descr))
409 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
410 hcd->driver->description, hcd->self.busnum);
412 /* fall back to legacy interrupt*/
413 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
414 hcd->irq_descr, hcd);
416 xhci_err(xhci, "request interrupt %d failed\n",
420 hcd->irq = pdev->irq;
426 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
431 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
435 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
441 static void compliance_mode_recovery(unsigned long arg)
443 struct xhci_hcd *xhci;
448 xhci = (struct xhci_hcd *)arg;
450 for (i = 0; i < xhci->num_usb3_ports; i++) {
451 temp = readl(xhci->usb3_ports[i]);
452 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
454 * Compliance Mode Detected. Letting USB Core
455 * handle the Warm Reset
457 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
458 "Compliance mode detected->port %d",
460 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
461 "Attempting compliance mode recovery");
462 hcd = xhci->shared_hcd;
464 if (hcd->state == HC_STATE_SUSPENDED)
465 usb_hcd_resume_root_hub(hcd);
467 usb_hcd_poll_rh_status(hcd);
471 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
472 mod_timer(&xhci->comp_mode_recovery_timer,
473 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
477 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
478 * that causes ports behind that hardware to enter compliance mode sometimes.
479 * The quirk creates a timer that polls every 2 seconds the link state of
480 * each host controller's port and recovers it by issuing a Warm reset
481 * if Compliance mode is detected, otherwise the port will become "dead" (no
482 * device connections or disconnections will be detected anymore). Becasue no
483 * status event is generated when entering compliance mode (per xhci spec),
484 * this quirk is needed on systems that have the failing hardware installed.
486 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
488 xhci->port_status_u0 = 0;
489 setup_timer(&xhci->comp_mode_recovery_timer,
490 compliance_mode_recovery, (unsigned long)xhci);
491 xhci->comp_mode_recovery_timer.expires = jiffies +
492 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
494 add_timer(&xhci->comp_mode_recovery_timer);
495 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
496 "Compliance mode recovery timer initialized");
500 * This function identifies the systems that have installed the SN65LVPE502CP
501 * USB3.0 re-driver and that need the Compliance Mode Quirk.
503 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
505 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
507 const char *dmi_product_name, *dmi_sys_vendor;
509 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
510 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
511 if (!dmi_product_name || !dmi_sys_vendor)
514 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
517 if (strstr(dmi_product_name, "Z420") ||
518 strstr(dmi_product_name, "Z620") ||
519 strstr(dmi_product_name, "Z820") ||
520 strstr(dmi_product_name, "Z1 Workstation"))
526 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
528 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
533 * Initialize memory for HCD and xHC (one-time init).
535 * Program the PAGESIZE register, initialize the device context array, create
536 * device contexts (?), set up a command ring segment (or two?), create event
537 * ring (one for now).
539 int xhci_init(struct usb_hcd *hcd)
541 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
544 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
545 spin_lock_init(&xhci->lock);
546 if (xhci->hci_version == 0x95 && link_quirk) {
547 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
548 "QUIRK: Not clearing Link TRB chain bits.");
549 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
551 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
552 "xHCI doesn't need link TRB QUIRK");
554 retval = xhci_mem_init(xhci, GFP_KERNEL);
555 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
557 /* Initializing Compliance Mode Recovery Data If Needed */
558 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
559 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
560 compliance_mode_recovery_timer_init(xhci);
566 /*-------------------------------------------------------------------------*/
569 static int xhci_run_finished(struct xhci_hcd *xhci)
571 if (xhci_start(xhci)) {
575 xhci->shared_hcd->state = HC_STATE_RUNNING;
576 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
578 if (xhci->quirks & XHCI_NEC_HOST)
579 xhci_ring_cmd_db(xhci);
581 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
582 "Finished xhci_run for USB3 roothub");
587 * Start the HC after it was halted.
589 * This function is called by the USB core when the HC driver is added.
590 * Its opposite is xhci_stop().
592 * xhci_init() must be called once before this function can be called.
593 * Reset the HC, enable device slot contexts, program DCBAAP, and
594 * set command ring pointer and event ring pointer.
596 * Setup MSI-X vectors and enable interrupts.
598 int xhci_run(struct usb_hcd *hcd)
603 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
605 /* Start the xHCI host controller running only after the USB 2.0 roothub
609 hcd->uses_new_polling = 1;
610 if (!usb_hcd_is_primary_hcd(hcd))
611 return xhci_run_finished(xhci);
613 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
615 ret = xhci_try_enable_msi(hcd);
619 xhci_dbg(xhci, "Command ring memory map follows:\n");
620 xhci_debug_ring(xhci, xhci->cmd_ring);
621 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
622 xhci_dbg_cmd_ptrs(xhci);
624 xhci_dbg(xhci, "ERST memory map follows:\n");
625 xhci_dbg_erst(xhci, &xhci->erst);
626 xhci_dbg(xhci, "Event ring:\n");
627 xhci_debug_ring(xhci, xhci->event_ring);
628 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
629 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
630 temp_64 &= ~ERST_PTR_MASK;
631 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
632 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
634 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
635 "// Set the interrupt modulation register");
636 temp = readl(&xhci->ir_set->irq_control);
637 temp &= ~ER_IRQ_INTERVAL_MASK;
639 * the increment interval is 8 times as much as that defined
640 * in xHCI spec on MTK's controller
642 temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
643 writel(temp, &xhci->ir_set->irq_control);
645 /* Set the HCD state before we enable the irqs */
646 temp = readl(&xhci->op_regs->command);
648 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
649 "// Enable interrupts, cmd = 0x%x.", temp);
650 writel(temp, &xhci->op_regs->command);
652 temp = readl(&xhci->ir_set->irq_pending);
653 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
654 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
655 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
656 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
657 xhci_print_ir_set(xhci, 0);
659 if (xhci->quirks & XHCI_NEC_HOST) {
660 struct xhci_command *command;
661 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
664 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
665 TRB_TYPE(TRB_NEC_GET_FW));
667 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
668 "Finished xhci_run for USB2 roothub");
671 EXPORT_SYMBOL_GPL(xhci_run);
676 * This function is called by the USB core when the HC driver is removed.
677 * Its opposite is xhci_run().
679 * Disable device contexts, disable IRQs, and quiesce the HC.
680 * Reset the HC, finish any completed transactions, and cleanup memory.
682 void xhci_stop(struct usb_hcd *hcd)
685 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
687 mutex_lock(&xhci->mutex);
689 if (!(xhci->xhc_state & XHCI_STATE_HALTED)) {
690 spin_lock_irq(&xhci->lock);
692 xhci->xhc_state |= XHCI_STATE_HALTED;
693 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
697 spin_unlock_irq(&xhci->lock);
700 if (!usb_hcd_is_primary_hcd(hcd)) {
701 mutex_unlock(&xhci->mutex);
705 xhci_cleanup_msix(xhci);
707 /* Deleting Compliance Mode Recovery Timer */
708 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
709 (!(xhci_all_ports_seen_u0(xhci)))) {
710 del_timer_sync(&xhci->comp_mode_recovery_timer);
711 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
712 "%s: compliance mode recovery timer deleted",
716 if (xhci->quirks & XHCI_AMD_PLL_FIX)
719 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
720 "// Disabling event ring interrupts");
721 temp = readl(&xhci->op_regs->status);
722 writel(temp & ~STS_EINT, &xhci->op_regs->status);
723 temp = readl(&xhci->ir_set->irq_pending);
724 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
725 xhci_print_ir_set(xhci, 0);
727 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
728 xhci_mem_cleanup(xhci);
729 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
730 "xhci_stop completed - status = %x",
731 readl(&xhci->op_regs->status));
732 mutex_unlock(&xhci->mutex);
736 * Shutdown HC (not bus-specific)
738 * This is called when the machine is rebooting or halting. We assume that the
739 * machine will be powered off, and the HC's internal state will be reset.
740 * Don't bother to free memory.
742 * This will only ever be called with the main usb_hcd (the USB3 roothub).
744 void xhci_shutdown(struct usb_hcd *hcd)
746 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
748 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
749 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
751 /* Don't poll the roothubs after shutdown. */
752 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
753 __func__, hcd->self.busnum);
754 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
755 del_timer_sync(&hcd->rh_timer);
757 if (xhci->shared_hcd) {
758 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
759 del_timer_sync(&xhci->shared_hcd->rh_timer);
762 spin_lock_irq(&xhci->lock);
764 /* Workaround for spurious wakeups at shutdown with HSW */
765 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
767 spin_unlock_irq(&xhci->lock);
769 xhci_cleanup_msix(xhci);
771 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
772 "xhci_shutdown completed - status = %x",
773 readl(&xhci->op_regs->status));
775 EXPORT_SYMBOL_GPL(xhci_shutdown);
778 static void xhci_save_registers(struct xhci_hcd *xhci)
780 xhci->s3.command = readl(&xhci->op_regs->command);
781 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
782 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
783 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
784 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
785 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
786 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
787 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
788 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
791 static void xhci_restore_registers(struct xhci_hcd *xhci)
793 writel(xhci->s3.command, &xhci->op_regs->command);
794 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
795 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
796 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
797 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
798 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
799 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
800 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
801 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
804 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
808 /* step 2: initialize command ring buffer */
809 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
810 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
811 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
812 xhci->cmd_ring->dequeue) &
813 (u64) ~CMD_RING_RSVD_BITS) |
814 xhci->cmd_ring->cycle_state;
815 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
816 "// Setting command ring address to 0x%llx",
817 (long unsigned long) val_64);
818 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
822 * The whole command ring must be cleared to zero when we suspend the host.
824 * The host doesn't save the command ring pointer in the suspend well, so we
825 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
826 * aligned, because of the reserved bits in the command ring dequeue pointer
827 * register. Therefore, we can't just set the dequeue pointer back in the
828 * middle of the ring (TRBs are 16-byte aligned).
830 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
832 struct xhci_ring *ring;
833 struct xhci_segment *seg;
835 ring = xhci->cmd_ring;
839 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
840 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
841 cpu_to_le32(~TRB_CYCLE);
843 } while (seg != ring->deq_seg);
845 /* Reset the software enqueue and dequeue pointers */
846 ring->deq_seg = ring->first_seg;
847 ring->dequeue = ring->first_seg->trbs;
848 ring->enq_seg = ring->deq_seg;
849 ring->enqueue = ring->dequeue;
851 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
853 * Ring is now zeroed, so the HW should look for change of ownership
854 * when the cycle bit is set to 1.
856 ring->cycle_state = 1;
859 * Reset the hardware dequeue pointer.
860 * Yes, this will need to be re-written after resume, but we're paranoid
861 * and want to make sure the hardware doesn't access bogus memory
862 * because, say, the BIOS or an SMI started the host without changing
863 * the command ring pointers.
865 xhci_set_cmd_ring_deq(xhci);
868 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
871 __le32 __iomem **port_array;
875 spin_lock_irqsave(&xhci->lock, flags);
877 /* disble usb3 ports Wake bits*/
878 port_index = xhci->num_usb3_ports;
879 port_array = xhci->usb3_ports;
880 while (port_index--) {
881 t1 = readl(port_array[port_index]);
882 t1 = xhci_port_state_to_neutral(t1);
883 t2 = t1 & ~PORT_WAKE_BITS;
885 writel(t2, port_array[port_index]);
888 /* disble usb2 ports Wake bits*/
889 port_index = xhci->num_usb2_ports;
890 port_array = xhci->usb2_ports;
891 while (port_index--) {
892 t1 = readl(port_array[port_index]);
893 t1 = xhci_port_state_to_neutral(t1);
894 t2 = t1 & ~PORT_WAKE_BITS;
896 writel(t2, port_array[port_index]);
899 spin_unlock_irqrestore(&xhci->lock, flags);
902 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
904 __le32 __iomem **port_array;
909 status = readl(&xhci->op_regs->status);
910 if (status & STS_EINT)
913 * Checking STS_EINT is not enough as there is a lag between a change
914 * bit being set and the Port Status Change Event that it generated
915 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
918 port_index = xhci->num_usb2_ports;
919 port_array = xhci->usb2_ports;
920 while (port_index--) {
921 portsc = readl(port_array[port_index]);
922 if (portsc & PORT_CHANGE_MASK ||
923 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
926 port_index = xhci->num_usb3_ports;
927 port_array = xhci->usb3_ports;
928 while (port_index--) {
929 portsc = readl(port_array[port_index]);
930 if (portsc & PORT_CHANGE_MASK ||
931 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
938 * Stop HC (not bus-specific)
940 * This is called when the machine transition into S3/S4 mode.
943 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
946 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
947 struct usb_hcd *hcd = xhci_to_hcd(xhci);
953 if (hcd->state != HC_STATE_SUSPENDED ||
954 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
957 /* Clear root port wake on bits if wakeup not allowed. */
959 xhci_disable_port_wake_on_bits(xhci);
961 /* Don't poll the roothubs on bus suspend. */
962 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
963 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
964 del_timer_sync(&hcd->rh_timer);
965 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
966 del_timer_sync(&xhci->shared_hcd->rh_timer);
968 spin_lock_irq(&xhci->lock);
969 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
970 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
971 /* step 1: stop endpoint */
972 /* skipped assuming that port suspend has done */
974 /* step 2: clear Run/Stop bit */
975 command = readl(&xhci->op_regs->command);
977 writel(command, &xhci->op_regs->command);
979 /* Some chips from Fresco Logic need an extraordinary delay */
980 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
982 if (xhci_handshake(&xhci->op_regs->status,
983 STS_HALT, STS_HALT, delay)) {
984 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
985 spin_unlock_irq(&xhci->lock);
988 xhci_clear_command_ring(xhci);
990 /* step 3: save registers */
991 xhci_save_registers(xhci);
993 /* step 4: set CSS flag */
994 command = readl(&xhci->op_regs->command);
996 writel(command, &xhci->op_regs->command);
997 if (xhci_handshake(&xhci->op_regs->status,
998 STS_SAVE, 0, 20 * 1000)) {
999 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1000 spin_unlock_irq(&xhci->lock);
1003 spin_unlock_irq(&xhci->lock);
1006 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1007 * is about to be suspended.
1009 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1010 (!(xhci_all_ports_seen_u0(xhci)))) {
1011 del_timer_sync(&xhci->comp_mode_recovery_timer);
1012 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1013 "%s: compliance mode recovery timer deleted",
1017 /* step 5: remove core well power */
1018 /* synchronize irq when using MSI-X */
1019 xhci_msix_sync_irqs(xhci);
1023 EXPORT_SYMBOL_GPL(xhci_suspend);
1026 * start xHC (not bus-specific)
1028 * This is called when the machine transition from S3/S4 mode.
1031 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1033 u32 command, temp = 0;
1034 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1035 struct usb_hcd *secondary_hcd;
1037 bool comp_timer_running = false;
1038 bool pending_portevent = false;
1043 /* Wait a bit if either of the roothubs need to settle from the
1044 * transition into bus suspend.
1046 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1047 time_before(jiffies,
1048 xhci->bus_state[1].next_statechange))
1051 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1052 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1054 spin_lock_irq(&xhci->lock);
1055 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1060 * Some controllers might lose power during suspend, so wait
1061 * for controller not ready bit to clear, just as in xHC init.
1063 retval = xhci_handshake(&xhci->op_regs->status,
1064 STS_CNR, 0, 10 * 1000 * 1000);
1066 xhci_warn(xhci, "Controller not ready at resume %d\n",
1068 spin_unlock_irq(&xhci->lock);
1071 /* step 1: restore register */
1072 xhci_restore_registers(xhci);
1073 /* step 2: initialize command ring buffer */
1074 xhci_set_cmd_ring_deq(xhci);
1075 /* step 3: restore state and start state*/
1076 /* step 3: set CRS flag */
1077 command = readl(&xhci->op_regs->command);
1079 writel(command, &xhci->op_regs->command);
1081 * Some controllers take up to 55+ ms to complete the controller
1082 * restore so setting the timeout to 100ms. Xhci specification
1083 * doesn't mention any timeout value.
1085 if (xhci_handshake(&xhci->op_regs->status,
1086 STS_RESTORE, 0, 100 * 1000)) {
1087 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1088 spin_unlock_irq(&xhci->lock);
1091 temp = readl(&xhci->op_regs->status);
1094 /* If restore operation fails, re-initialize the HC during resume */
1095 if ((temp & STS_SRE) || hibernated) {
1097 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1098 !(xhci_all_ports_seen_u0(xhci))) {
1099 del_timer_sync(&xhci->comp_mode_recovery_timer);
1100 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1101 "Compliance Mode Recovery Timer deleted!");
1104 /* Let the USB core know _both_ roothubs lost power. */
1105 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1106 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1108 xhci_dbg(xhci, "Stop HCD\n");
1111 spin_unlock_irq(&xhci->lock);
1112 xhci_cleanup_msix(xhci);
1114 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1115 temp = readl(&xhci->op_regs->status);
1116 writel(temp & ~STS_EINT, &xhci->op_regs->status);
1117 temp = readl(&xhci->ir_set->irq_pending);
1118 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1119 xhci_print_ir_set(xhci, 0);
1121 xhci_dbg(xhci, "cleaning up memory\n");
1122 xhci_mem_cleanup(xhci);
1123 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1124 readl(&xhci->op_regs->status));
1126 /* USB core calls the PCI reinit and start functions twice:
1127 * first with the primary HCD, and then with the secondary HCD.
1128 * If we don't do the same, the host will never be started.
1130 if (!usb_hcd_is_primary_hcd(hcd))
1131 secondary_hcd = hcd;
1133 secondary_hcd = xhci->shared_hcd;
1135 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1136 retval = xhci_init(hcd->primary_hcd);
1139 comp_timer_running = true;
1141 xhci_dbg(xhci, "Start the primary HCD\n");
1142 retval = xhci_run(hcd->primary_hcd);
1144 xhci_dbg(xhci, "Start the secondary HCD\n");
1145 retval = xhci_run(secondary_hcd);
1147 hcd->state = HC_STATE_SUSPENDED;
1148 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1152 /* step 4: set Run/Stop bit */
1153 command = readl(&xhci->op_regs->command);
1155 writel(command, &xhci->op_regs->command);
1156 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1159 /* step 5: walk topology and initialize portsc,
1160 * portpmsc and portli
1162 /* this is done in bus_resume */
1164 /* step 6: restart each of the previously
1165 * Running endpoints by ringing their doorbells
1168 spin_unlock_irq(&xhci->lock);
1173 * Resume roothubs only if there are pending events.
1174 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1175 * the first wake signalling failed, give it that chance.
1177 pending_portevent = xhci_pending_portevent(xhci);
1178 if (!pending_portevent) {
1180 pending_portevent = xhci_pending_portevent(xhci);
1183 if (pending_portevent) {
1184 usb_hcd_resume_root_hub(xhci->shared_hcd);
1185 usb_hcd_resume_root_hub(hcd);
1189 * If system is subject to the Quirk, Compliance Mode Timer needs to
1190 * be re-initialized Always after a system resume. Ports are subject
1191 * to suffer the Compliance Mode issue again. It doesn't matter if
1192 * ports have entered previously to U0 before system's suspension.
1194 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1195 compliance_mode_recovery_timer_init(xhci);
1197 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1198 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1200 /* Re-enable port polling. */
1201 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1202 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1203 usb_hcd_poll_rh_status(xhci->shared_hcd);
1204 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1205 usb_hcd_poll_rh_status(hcd);
1209 EXPORT_SYMBOL_GPL(xhci_resume);
1210 #endif /* CONFIG_PM */
1212 /*-------------------------------------------------------------------------*/
1215 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1216 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1217 * value to right shift 1 for the bitmask.
1219 * Index = (epnum * 2) + direction - 1,
1220 * where direction = 0 for OUT, 1 for IN.
1221 * For control endpoints, the IN index is used (OUT index is unused), so
1222 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1224 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1227 if (usb_endpoint_xfer_control(desc))
1228 index = (unsigned int) (usb_endpoint_num(desc)*2);
1230 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1231 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1235 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1236 * address from the XHCI endpoint index.
1238 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1240 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1241 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1242 return direction | number;
1245 /* Find the flag for this endpoint (for use in the control context). Use the
1246 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1249 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1251 return 1 << (xhci_get_endpoint_index(desc) + 1);
1254 /* Find the flag for this endpoint (for use in the control context). Use the
1255 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1258 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1260 return 1 << (ep_index + 1);
1263 /* Compute the last valid endpoint context index. Basically, this is the
1264 * endpoint index plus one. For slot contexts with more than valid endpoint,
1265 * we find the most significant bit set in the added contexts flags.
1266 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1267 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1269 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1271 return fls(added_ctxs) - 1;
1274 /* Returns 1 if the arguments are OK;
1275 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1277 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1278 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1280 struct xhci_hcd *xhci;
1281 struct xhci_virt_device *virt_dev;
1283 if (!hcd || (check_ep && !ep) || !udev) {
1284 pr_debug("xHCI %s called with invalid args\n", func);
1287 if (!udev->parent) {
1288 pr_debug("xHCI %s called for root hub\n", func);
1292 xhci = hcd_to_xhci(hcd);
1293 if (check_virt_dev) {
1294 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1295 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1300 virt_dev = xhci->devs[udev->slot_id];
1301 if (virt_dev->udev != udev) {
1302 xhci_dbg(xhci, "xHCI %s called with udev and "
1303 "virt_dev does not match\n", func);
1308 if (xhci->xhc_state & XHCI_STATE_HALTED)
1314 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1315 struct usb_device *udev, struct xhci_command *command,
1316 bool ctx_change, bool must_succeed);
1319 * Full speed devices may have a max packet size greater than 8 bytes, but the
1320 * USB core doesn't know that until it reads the first 8 bytes of the
1321 * descriptor. If the usb_device's max packet size changes after that point,
1322 * we need to issue an evaluate context command and wait on it.
1324 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1325 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1327 struct xhci_container_ctx *out_ctx;
1328 struct xhci_input_control_ctx *ctrl_ctx;
1329 struct xhci_ep_ctx *ep_ctx;
1330 struct xhci_command *command;
1331 int max_packet_size;
1332 int hw_max_packet_size;
1335 out_ctx = xhci->devs[slot_id]->out_ctx;
1336 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1337 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1338 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1339 if (hw_max_packet_size != max_packet_size) {
1340 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1341 "Max Packet Size for ep 0 changed.");
1342 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1343 "Max packet size in usb_device = %d",
1345 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1346 "Max packet size in xHCI HW = %d",
1347 hw_max_packet_size);
1348 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1349 "Issuing evaluate context command.");
1351 /* Set up the input context flags for the command */
1352 /* FIXME: This won't work if a non-default control endpoint
1353 * changes max packet sizes.
1356 command = xhci_alloc_command(xhci, false, true, mem_flags);
1360 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1361 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1363 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1366 goto command_cleanup;
1368 /* Set up the modified control endpoint 0 */
1369 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1370 xhci->devs[slot_id]->out_ctx, ep_index);
1372 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1373 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1374 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1375 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1377 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1378 ctrl_ctx->drop_flags = 0;
1380 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1381 xhci_dbg_ctx(xhci, command->in_ctx, ep_index);
1382 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1383 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1385 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1388 /* Clean up the input context for later use by bandwidth
1391 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1393 kfree(command->completion);
1400 * non-error returns are a promise to giveback() the urb later
1401 * we drop ownership so next owner (or urb unlink) can get it
1403 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1405 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1406 struct xhci_td *buffer;
1407 unsigned long flags;
1409 unsigned int slot_id, ep_index;
1410 struct urb_priv *urb_priv;
1415 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1416 true, true, __func__);
1418 return ret ? ret : -EINVAL;
1420 slot_id = urb->dev->slot_id;
1421 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1423 if (!HCD_HW_ACCESSIBLE(hcd)) {
1424 if (!in_interrupt())
1425 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1430 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1431 size = urb->number_of_packets;
1432 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1433 urb->transfer_buffer_length > 0 &&
1434 urb->transfer_flags & URB_ZERO_PACKET &&
1435 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1440 urb_priv = kzalloc(sizeof(struct urb_priv) +
1441 size * sizeof(struct xhci_td *), mem_flags);
1445 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1451 for (i = 0; i < size; i++) {
1452 urb_priv->td[i] = buffer;
1456 urb_priv->length = size;
1457 urb_priv->td_cnt = 0;
1458 urb->hcpriv = urb_priv;
1460 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1461 /* Check to see if the max packet size for the default control
1462 * endpoint changed during FS device enumeration
1464 if (urb->dev->speed == USB_SPEED_FULL) {
1465 ret = xhci_check_maxpacket(xhci, slot_id,
1466 ep_index, urb, mem_flags);
1468 xhci_urb_free_priv(urb_priv);
1474 /* We have a spinlock and interrupts disabled, so we must pass
1475 * atomic context to this function, which may allocate memory.
1477 spin_lock_irqsave(&xhci->lock, flags);
1478 if (xhci->xhc_state & XHCI_STATE_DYING)
1480 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1484 spin_unlock_irqrestore(&xhci->lock, flags);
1485 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1486 spin_lock_irqsave(&xhci->lock, flags);
1487 if (xhci->xhc_state & XHCI_STATE_DYING)
1489 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1490 EP_GETTING_STREAMS) {
1491 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1492 "is transitioning to using streams.\n");
1494 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1495 EP_GETTING_NO_STREAMS) {
1496 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1497 "is transitioning to "
1498 "not having streams.\n");
1501 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1506 spin_unlock_irqrestore(&xhci->lock, flags);
1507 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1508 spin_lock_irqsave(&xhci->lock, flags);
1509 if (xhci->xhc_state & XHCI_STATE_DYING)
1511 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1515 spin_unlock_irqrestore(&xhci->lock, flags);
1517 spin_lock_irqsave(&xhci->lock, flags);
1518 if (xhci->xhc_state & XHCI_STATE_DYING)
1520 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1524 spin_unlock_irqrestore(&xhci->lock, flags);
1529 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1530 "non-responsive xHCI host.\n",
1531 urb->ep->desc.bEndpointAddress, urb);
1534 xhci_urb_free_priv(urb_priv);
1536 spin_unlock_irqrestore(&xhci->lock, flags);
1541 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1542 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1543 * should pick up where it left off in the TD, unless a Set Transfer Ring
1544 * Dequeue Pointer is issued.
1546 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1547 * the ring. Since the ring is a contiguous structure, they can't be physically
1548 * removed. Instead, there are two options:
1550 * 1) If the HC is in the middle of processing the URB to be canceled, we
1551 * simply move the ring's dequeue pointer past those TRBs using the Set
1552 * Transfer Ring Dequeue Pointer command. This will be the common case,
1553 * when drivers timeout on the last submitted URB and attempt to cancel.
1555 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1556 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1557 * HC will need to invalidate the any TRBs it has cached after the stop
1558 * endpoint command, as noted in the xHCI 0.95 errata.
1560 * 3) The TD may have completed by the time the Stop Endpoint Command
1561 * completes, so software needs to handle that case too.
1563 * This function should protect against the TD enqueueing code ringing the
1564 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1565 * It also needs to account for multiple cancellations on happening at the same
1566 * time for the same endpoint.
1568 * Note that this function can be called in any context, or so says
1569 * usb_hcd_unlink_urb()
1571 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1573 unsigned long flags;
1576 struct xhci_hcd *xhci;
1577 struct urb_priv *urb_priv;
1579 unsigned int ep_index;
1580 struct xhci_ring *ep_ring;
1581 struct xhci_virt_ep *ep;
1582 struct xhci_command *command;
1584 xhci = hcd_to_xhci(hcd);
1585 spin_lock_irqsave(&xhci->lock, flags);
1586 /* Make sure the URB hasn't completed or been unlinked already */
1587 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1588 if (ret || !urb->hcpriv)
1590 temp = readl(&xhci->op_regs->status);
1591 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1592 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1593 "HW died, freeing TD.");
1594 urb_priv = urb->hcpriv;
1595 for (i = urb_priv->td_cnt;
1596 i < urb_priv->length && xhci->devs[urb->dev->slot_id];
1598 td = urb_priv->td[i];
1599 if (!list_empty(&td->td_list))
1600 list_del_init(&td->td_list);
1601 if (!list_empty(&td->cancelled_td_list))
1602 list_del_init(&td->cancelled_td_list);
1605 usb_hcd_unlink_urb_from_ep(hcd, urb);
1606 spin_unlock_irqrestore(&xhci->lock, flags);
1607 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1608 xhci_urb_free_priv(urb_priv);
1612 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1613 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1614 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1620 urb_priv = urb->hcpriv;
1621 i = urb_priv->td_cnt;
1622 if (i < urb_priv->length)
1623 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1624 "Cancel URB %p, dev %s, ep 0x%x, "
1625 "starting at offset 0x%llx",
1626 urb, urb->dev->devpath,
1627 urb->ep->desc.bEndpointAddress,
1628 (unsigned long long) xhci_trb_virt_to_dma(
1629 urb_priv->td[i]->start_seg,
1630 urb_priv->td[i]->first_trb));
1632 for (; i < urb_priv->length; i++) {
1633 td = urb_priv->td[i];
1634 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1637 /* Queue a stop endpoint command, but only if this is
1638 * the first cancellation to be handled.
1640 if (!(ep->ep_state & EP_HALT_PENDING)) {
1641 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1646 ep->ep_state |= EP_HALT_PENDING;
1647 ep->stop_cmds_pending++;
1648 ep->stop_cmd_timer.expires = jiffies +
1649 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1650 add_timer(&ep->stop_cmd_timer);
1651 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1653 xhci_ring_cmd_db(xhci);
1656 spin_unlock_irqrestore(&xhci->lock, flags);
1660 /* Drop an endpoint from a new bandwidth configuration for this device.
1661 * Only one call to this function is allowed per endpoint before
1662 * check_bandwidth() or reset_bandwidth() must be called.
1663 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1664 * add the endpoint to the schedule with possibly new parameters denoted by a
1665 * different endpoint descriptor in usb_host_endpoint.
1666 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1669 * The USB core will not allow URBs to be queued to an endpoint that is being
1670 * disabled, so there's no need for mutual exclusion to protect
1671 * the xhci->devs[slot_id] structure.
1673 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1674 struct usb_host_endpoint *ep)
1676 struct xhci_hcd *xhci;
1677 struct xhci_container_ctx *in_ctx, *out_ctx;
1678 struct xhci_input_control_ctx *ctrl_ctx;
1679 unsigned int ep_index;
1680 struct xhci_ep_ctx *ep_ctx;
1682 u32 new_add_flags, new_drop_flags;
1685 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1688 xhci = hcd_to_xhci(hcd);
1689 if (xhci->xhc_state & XHCI_STATE_DYING)
1692 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1693 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1694 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1695 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1696 __func__, drop_flag);
1700 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1701 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1702 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1704 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1709 ep_index = xhci_get_endpoint_index(&ep->desc);
1710 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1711 /* If the HC already knows the endpoint is disabled,
1712 * or the HCD has noted it is disabled, ignore this request
1714 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1715 cpu_to_le32(EP_STATE_DISABLED)) ||
1716 le32_to_cpu(ctrl_ctx->drop_flags) &
1717 xhci_get_endpoint_flag(&ep->desc)) {
1718 /* Do not warn when called after a usb_device_reset */
1719 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1720 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1725 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1726 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1728 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1729 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1731 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1733 if (xhci->quirks & XHCI_MTK_HOST)
1734 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1736 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1737 (unsigned int) ep->desc.bEndpointAddress,
1739 (unsigned int) new_drop_flags,
1740 (unsigned int) new_add_flags);
1744 /* Add an endpoint to a new possible bandwidth configuration for this device.
1745 * Only one call to this function is allowed per endpoint before
1746 * check_bandwidth() or reset_bandwidth() must be called.
1747 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1748 * add the endpoint to the schedule with possibly new parameters denoted by a
1749 * different endpoint descriptor in usb_host_endpoint.
1750 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1753 * The USB core will not allow URBs to be queued to an endpoint until the
1754 * configuration or alt setting is installed in the device, so there's no need
1755 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1757 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1758 struct usb_host_endpoint *ep)
1760 struct xhci_hcd *xhci;
1761 struct xhci_container_ctx *in_ctx;
1762 unsigned int ep_index;
1763 struct xhci_input_control_ctx *ctrl_ctx;
1765 u32 new_add_flags, new_drop_flags;
1766 struct xhci_virt_device *virt_dev;
1769 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1771 /* So we won't queue a reset ep command for a root hub */
1775 xhci = hcd_to_xhci(hcd);
1776 if (xhci->xhc_state & XHCI_STATE_DYING)
1779 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1780 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1781 /* FIXME when we have to issue an evaluate endpoint command to
1782 * deal with ep0 max packet size changing once we get the
1785 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1786 __func__, added_ctxs);
1790 virt_dev = xhci->devs[udev->slot_id];
1791 in_ctx = virt_dev->in_ctx;
1792 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1794 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1799 ep_index = xhci_get_endpoint_index(&ep->desc);
1800 /* If this endpoint is already in use, and the upper layers are trying
1801 * to add it again without dropping it, reject the addition.
1803 if (virt_dev->eps[ep_index].ring &&
1804 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1805 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1806 "without dropping it.\n",
1807 (unsigned int) ep->desc.bEndpointAddress);
1811 /* If the HCD has already noted the endpoint is enabled,
1812 * ignore this request.
1814 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1815 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1821 * Configuration and alternate setting changes must be done in
1822 * process context, not interrupt context (or so documenation
1823 * for usb_set_interface() and usb_set_configuration() claim).
1825 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1826 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1827 __func__, ep->desc.bEndpointAddress);
1831 if (xhci->quirks & XHCI_MTK_HOST) {
1832 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1834 xhci_free_or_cache_endpoint_ring(xhci,
1835 virt_dev, ep_index);
1840 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1841 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1843 /* If xhci_endpoint_disable() was called for this endpoint, but the
1844 * xHC hasn't been notified yet through the check_bandwidth() call,
1845 * this re-adds a new state for the endpoint from the new endpoint
1846 * descriptors. We must drop and re-add this endpoint, so we leave the
1849 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1851 /* Store the usb_device pointer for later use */
1854 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1855 (unsigned int) ep->desc.bEndpointAddress,
1857 (unsigned int) new_drop_flags,
1858 (unsigned int) new_add_flags);
1862 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1864 struct xhci_input_control_ctx *ctrl_ctx;
1865 struct xhci_ep_ctx *ep_ctx;
1866 struct xhci_slot_ctx *slot_ctx;
1869 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1871 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1876 /* When a device's add flag and drop flag are zero, any subsequent
1877 * configure endpoint command will leave that endpoint's state
1878 * untouched. Make sure we don't leave any old state in the input
1879 * endpoint contexts.
1881 ctrl_ctx->drop_flags = 0;
1882 ctrl_ctx->add_flags = 0;
1883 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1884 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1885 /* Endpoint 0 is always valid */
1886 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1887 for (i = 1; i < 31; ++i) {
1888 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1889 ep_ctx->ep_info = 0;
1890 ep_ctx->ep_info2 = 0;
1892 ep_ctx->tx_info = 0;
1896 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1897 struct usb_device *udev, u32 *cmd_status)
1901 switch (*cmd_status) {
1902 case COMP_CMD_ABORT:
1904 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1908 dev_warn(&udev->dev,
1909 "Not enough host controller resources for new device state.\n");
1911 /* FIXME: can we allocate more resources for the HC? */
1914 case COMP_2ND_BW_ERR:
1915 dev_warn(&udev->dev,
1916 "Not enough bandwidth for new device state.\n");
1918 /* FIXME: can we go back to the old state? */
1921 /* the HCD set up something wrong */
1922 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1924 "and endpoint is not disabled.\n");
1928 dev_warn(&udev->dev,
1929 "ERROR: Incompatible device for endpoint configure command.\n");
1933 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1934 "Successful Endpoint Configure command");
1938 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1946 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1947 struct usb_device *udev, u32 *cmd_status)
1950 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1952 switch (*cmd_status) {
1953 case COMP_CMD_ABORT:
1955 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1959 dev_warn(&udev->dev,
1960 "WARN: xHCI driver setup invalid evaluate context command.\n");
1964 dev_warn(&udev->dev,
1965 "WARN: slot not enabled for evaluate context command.\n");
1968 case COMP_CTX_STATE:
1969 dev_warn(&udev->dev,
1970 "WARN: invalid context state for evaluate context command.\n");
1971 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1975 dev_warn(&udev->dev,
1976 "ERROR: Incompatible device for evaluate context command.\n");
1980 /* Max Exit Latency too large error */
1981 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1985 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1986 "Successful evaluate context command");
1990 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1998 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1999 struct xhci_input_control_ctx *ctrl_ctx)
2001 u32 valid_add_flags;
2002 u32 valid_drop_flags;
2004 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2005 * (bit 1). The default control endpoint is added during the Address
2006 * Device command and is never removed until the slot is disabled.
2008 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2009 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2011 /* Use hweight32 to count the number of ones in the add flags, or
2012 * number of endpoints added. Don't count endpoints that are changed
2013 * (both added and dropped).
2015 return hweight32(valid_add_flags) -
2016 hweight32(valid_add_flags & valid_drop_flags);
2019 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2020 struct xhci_input_control_ctx *ctrl_ctx)
2022 u32 valid_add_flags;
2023 u32 valid_drop_flags;
2025 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2026 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2028 return hweight32(valid_drop_flags) -
2029 hweight32(valid_add_flags & valid_drop_flags);
2033 * We need to reserve the new number of endpoints before the configure endpoint
2034 * command completes. We can't subtract the dropped endpoints from the number
2035 * of active endpoints until the command completes because we can oversubscribe
2036 * the host in this case:
2038 * - the first configure endpoint command drops more endpoints than it adds
2039 * - a second configure endpoint command that adds more endpoints is queued
2040 * - the first configure endpoint command fails, so the config is unchanged
2041 * - the second command may succeed, even though there isn't enough resources
2043 * Must be called with xhci->lock held.
2045 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2046 struct xhci_input_control_ctx *ctrl_ctx)
2050 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2051 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2052 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2053 "Not enough ep ctxs: "
2054 "%u active, need to add %u, limit is %u.",
2055 xhci->num_active_eps, added_eps,
2056 xhci->limit_active_eps);
2059 xhci->num_active_eps += added_eps;
2060 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2061 "Adding %u ep ctxs, %u now active.", added_eps,
2062 xhci->num_active_eps);
2067 * The configure endpoint was failed by the xHC for some other reason, so we
2068 * need to revert the resources that failed configuration would have used.
2070 * Must be called with xhci->lock held.
2072 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2073 struct xhci_input_control_ctx *ctrl_ctx)
2077 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2078 xhci->num_active_eps -= num_failed_eps;
2079 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2080 "Removing %u failed ep ctxs, %u now active.",
2082 xhci->num_active_eps);
2086 * Now that the command has completed, clean up the active endpoint count by
2087 * subtracting out the endpoints that were dropped (but not changed).
2089 * Must be called with xhci->lock held.
2091 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2092 struct xhci_input_control_ctx *ctrl_ctx)
2094 u32 num_dropped_eps;
2096 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2097 xhci->num_active_eps -= num_dropped_eps;
2098 if (num_dropped_eps)
2099 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2100 "Removing %u dropped ep ctxs, %u now active.",
2102 xhci->num_active_eps);
2105 static unsigned int xhci_get_block_size(struct usb_device *udev)
2107 switch (udev->speed) {
2109 case USB_SPEED_FULL:
2111 case USB_SPEED_HIGH:
2113 case USB_SPEED_SUPER:
2114 case USB_SPEED_SUPER_PLUS:
2116 case USB_SPEED_UNKNOWN:
2117 case USB_SPEED_WIRELESS:
2119 /* Should never happen */
2125 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2127 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2129 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2134 /* If we are changing a LS/FS device under a HS hub,
2135 * make sure (if we are activating a new TT) that the HS bus has enough
2136 * bandwidth for this new TT.
2138 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2139 struct xhci_virt_device *virt_dev,
2142 struct xhci_interval_bw_table *bw_table;
2143 struct xhci_tt_bw_info *tt_info;
2145 /* Find the bandwidth table for the root port this TT is attached to. */
2146 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2147 tt_info = virt_dev->tt_info;
2148 /* If this TT already had active endpoints, the bandwidth for this TT
2149 * has already been added. Removing all periodic endpoints (and thus
2150 * making the TT enactive) will only decrease the bandwidth used.
2154 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2155 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2159 /* Not sure why we would have no new active endpoints...
2161 * Maybe because of an Evaluate Context change for a hub update or a
2162 * control endpoint 0 max packet size change?
2163 * FIXME: skip the bandwidth calculation in that case.
2168 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2169 struct xhci_virt_device *virt_dev)
2171 unsigned int bw_reserved;
2173 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2174 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2177 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2178 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2185 * This algorithm is a very conservative estimate of the worst-case scheduling
2186 * scenario for any one interval. The hardware dynamically schedules the
2187 * packets, so we can't tell which microframe could be the limiting factor in
2188 * the bandwidth scheduling. This only takes into account periodic endpoints.
2190 * Obviously, we can't solve an NP complete problem to find the minimum worst
2191 * case scenario. Instead, we come up with an estimate that is no less than
2192 * the worst case bandwidth used for any one microframe, but may be an
2195 * We walk the requirements for each endpoint by interval, starting with the
2196 * smallest interval, and place packets in the schedule where there is only one
2197 * possible way to schedule packets for that interval. In order to simplify
2198 * this algorithm, we record the largest max packet size for each interval, and
2199 * assume all packets will be that size.
2201 * For interval 0, we obviously must schedule all packets for each interval.
2202 * The bandwidth for interval 0 is just the amount of data to be transmitted
2203 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2204 * the number of packets).
2206 * For interval 1, we have two possible microframes to schedule those packets
2207 * in. For this algorithm, if we can schedule the same number of packets for
2208 * each possible scheduling opportunity (each microframe), we will do so. The
2209 * remaining number of packets will be saved to be transmitted in the gaps in
2210 * the next interval's scheduling sequence.
2212 * As we move those remaining packets to be scheduled with interval 2 packets,
2213 * we have to double the number of remaining packets to transmit. This is
2214 * because the intervals are actually powers of 2, and we would be transmitting
2215 * the previous interval's packets twice in this interval. We also have to be
2216 * sure that when we look at the largest max packet size for this interval, we
2217 * also look at the largest max packet size for the remaining packets and take
2218 * the greater of the two.
2220 * The algorithm continues to evenly distribute packets in each scheduling
2221 * opportunity, and push the remaining packets out, until we get to the last
2222 * interval. Then those packets and their associated overhead are just added
2223 * to the bandwidth used.
2225 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2226 struct xhci_virt_device *virt_dev,
2229 unsigned int bw_reserved;
2230 unsigned int max_bandwidth;
2231 unsigned int bw_used;
2232 unsigned int block_size;
2233 struct xhci_interval_bw_table *bw_table;
2234 unsigned int packet_size = 0;
2235 unsigned int overhead = 0;
2236 unsigned int packets_transmitted = 0;
2237 unsigned int packets_remaining = 0;
2240 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2241 return xhci_check_ss_bw(xhci, virt_dev);
2243 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2244 max_bandwidth = HS_BW_LIMIT;
2245 /* Convert percent of bus BW reserved to blocks reserved */
2246 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2248 max_bandwidth = FS_BW_LIMIT;
2249 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2252 bw_table = virt_dev->bw_table;
2253 /* We need to translate the max packet size and max ESIT payloads into
2254 * the units the hardware uses.
2256 block_size = xhci_get_block_size(virt_dev->udev);
2258 /* If we are manipulating a LS/FS device under a HS hub, double check
2259 * that the HS bus has enough bandwidth if we are activing a new TT.
2261 if (virt_dev->tt_info) {
2262 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2263 "Recalculating BW for rootport %u",
2264 virt_dev->real_port);
2265 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2266 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2267 "newly activated TT.\n");
2270 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2271 "Recalculating BW for TT slot %u port %u",
2272 virt_dev->tt_info->slot_id,
2273 virt_dev->tt_info->ttport);
2275 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2276 "Recalculating BW for rootport %u",
2277 virt_dev->real_port);
2280 /* Add in how much bandwidth will be used for interval zero, or the
2281 * rounded max ESIT payload + number of packets * largest overhead.
2283 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2284 bw_table->interval_bw[0].num_packets *
2285 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2287 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2288 unsigned int bw_added;
2289 unsigned int largest_mps;
2290 unsigned int interval_overhead;
2293 * How many packets could we transmit in this interval?
2294 * If packets didn't fit in the previous interval, we will need
2295 * to transmit that many packets twice within this interval.
2297 packets_remaining = 2 * packets_remaining +
2298 bw_table->interval_bw[i].num_packets;
2300 /* Find the largest max packet size of this or the previous
2303 if (list_empty(&bw_table->interval_bw[i].endpoints))
2306 struct xhci_virt_ep *virt_ep;
2307 struct list_head *ep_entry;
2309 ep_entry = bw_table->interval_bw[i].endpoints.next;
2310 virt_ep = list_entry(ep_entry,
2311 struct xhci_virt_ep, bw_endpoint_list);
2312 /* Convert to blocks, rounding up */
2313 largest_mps = DIV_ROUND_UP(
2314 virt_ep->bw_info.max_packet_size,
2317 if (largest_mps > packet_size)
2318 packet_size = largest_mps;
2320 /* Use the larger overhead of this or the previous interval. */
2321 interval_overhead = xhci_get_largest_overhead(
2322 &bw_table->interval_bw[i]);
2323 if (interval_overhead > overhead)
2324 overhead = interval_overhead;
2326 /* How many packets can we evenly distribute across
2327 * (1 << (i + 1)) possible scheduling opportunities?
2329 packets_transmitted = packets_remaining >> (i + 1);
2331 /* Add in the bandwidth used for those scheduled packets */
2332 bw_added = packets_transmitted * (overhead + packet_size);
2334 /* How many packets do we have remaining to transmit? */
2335 packets_remaining = packets_remaining % (1 << (i + 1));
2337 /* What largest max packet size should those packets have? */
2338 /* If we've transmitted all packets, don't carry over the
2339 * largest packet size.
2341 if (packets_remaining == 0) {
2344 } else if (packets_transmitted > 0) {
2345 /* Otherwise if we do have remaining packets, and we've
2346 * scheduled some packets in this interval, take the
2347 * largest max packet size from endpoints with this
2350 packet_size = largest_mps;
2351 overhead = interval_overhead;
2353 /* Otherwise carry over packet_size and overhead from the last
2354 * time we had a remainder.
2356 bw_used += bw_added;
2357 if (bw_used > max_bandwidth) {
2358 xhci_warn(xhci, "Not enough bandwidth. "
2359 "Proposed: %u, Max: %u\n",
2360 bw_used, max_bandwidth);
2365 * Ok, we know we have some packets left over after even-handedly
2366 * scheduling interval 15. We don't know which microframes they will
2367 * fit into, so we over-schedule and say they will be scheduled every
2370 if (packets_remaining > 0)
2371 bw_used += overhead + packet_size;
2373 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2374 unsigned int port_index = virt_dev->real_port - 1;
2376 /* OK, we're manipulating a HS device attached to a
2377 * root port bandwidth domain. Include the number of active TTs
2378 * in the bandwidth used.
2380 bw_used += TT_HS_OVERHEAD *
2381 xhci->rh_bw[port_index].num_active_tts;
2384 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2385 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2386 "Available: %u " "percent",
2387 bw_used, max_bandwidth, bw_reserved,
2388 (max_bandwidth - bw_used - bw_reserved) * 100 /
2391 bw_used += bw_reserved;
2392 if (bw_used > max_bandwidth) {
2393 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2394 bw_used, max_bandwidth);
2398 bw_table->bw_used = bw_used;
2402 static bool xhci_is_async_ep(unsigned int ep_type)
2404 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2405 ep_type != ISOC_IN_EP &&
2406 ep_type != INT_IN_EP);
2409 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2411 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2414 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2416 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2418 if (ep_bw->ep_interval == 0)
2419 return SS_OVERHEAD_BURST +
2420 (ep_bw->mult * ep_bw->num_packets *
2421 (SS_OVERHEAD + mps));
2422 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2423 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2424 1 << ep_bw->ep_interval);
2428 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2429 struct xhci_bw_info *ep_bw,
2430 struct xhci_interval_bw_table *bw_table,
2431 struct usb_device *udev,
2432 struct xhci_virt_ep *virt_ep,
2433 struct xhci_tt_bw_info *tt_info)
2435 struct xhci_interval_bw *interval_bw;
2436 int normalized_interval;
2438 if (xhci_is_async_ep(ep_bw->type))
2441 if (udev->speed >= USB_SPEED_SUPER) {
2442 if (xhci_is_sync_in_ep(ep_bw->type))
2443 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2444 xhci_get_ss_bw_consumed(ep_bw);
2446 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2447 xhci_get_ss_bw_consumed(ep_bw);
2451 /* SuperSpeed endpoints never get added to intervals in the table, so
2452 * this check is only valid for HS/FS/LS devices.
2454 if (list_empty(&virt_ep->bw_endpoint_list))
2456 /* For LS/FS devices, we need to translate the interval expressed in
2457 * microframes to frames.
2459 if (udev->speed == USB_SPEED_HIGH)
2460 normalized_interval = ep_bw->ep_interval;
2462 normalized_interval = ep_bw->ep_interval - 3;
2464 if (normalized_interval == 0)
2465 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2466 interval_bw = &bw_table->interval_bw[normalized_interval];
2467 interval_bw->num_packets -= ep_bw->num_packets;
2468 switch (udev->speed) {
2470 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2472 case USB_SPEED_FULL:
2473 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2475 case USB_SPEED_HIGH:
2476 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2478 case USB_SPEED_SUPER:
2479 case USB_SPEED_SUPER_PLUS:
2480 case USB_SPEED_UNKNOWN:
2481 case USB_SPEED_WIRELESS:
2482 /* Should never happen because only LS/FS/HS endpoints will get
2483 * added to the endpoint list.
2488 tt_info->active_eps -= 1;
2489 list_del_init(&virt_ep->bw_endpoint_list);
2492 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2493 struct xhci_bw_info *ep_bw,
2494 struct xhci_interval_bw_table *bw_table,
2495 struct usb_device *udev,
2496 struct xhci_virt_ep *virt_ep,
2497 struct xhci_tt_bw_info *tt_info)
2499 struct xhci_interval_bw *interval_bw;
2500 struct xhci_virt_ep *smaller_ep;
2501 int normalized_interval;
2503 if (xhci_is_async_ep(ep_bw->type))
2506 if (udev->speed == USB_SPEED_SUPER) {
2507 if (xhci_is_sync_in_ep(ep_bw->type))
2508 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2509 xhci_get_ss_bw_consumed(ep_bw);
2511 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2512 xhci_get_ss_bw_consumed(ep_bw);
2516 /* For LS/FS devices, we need to translate the interval expressed in
2517 * microframes to frames.
2519 if (udev->speed == USB_SPEED_HIGH)
2520 normalized_interval = ep_bw->ep_interval;
2522 normalized_interval = ep_bw->ep_interval - 3;
2524 if (normalized_interval == 0)
2525 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2526 interval_bw = &bw_table->interval_bw[normalized_interval];
2527 interval_bw->num_packets += ep_bw->num_packets;
2528 switch (udev->speed) {
2530 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2532 case USB_SPEED_FULL:
2533 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2535 case USB_SPEED_HIGH:
2536 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2538 case USB_SPEED_SUPER:
2539 case USB_SPEED_SUPER_PLUS:
2540 case USB_SPEED_UNKNOWN:
2541 case USB_SPEED_WIRELESS:
2542 /* Should never happen because only LS/FS/HS endpoints will get
2543 * added to the endpoint list.
2549 tt_info->active_eps += 1;
2550 /* Insert the endpoint into the list, largest max packet size first. */
2551 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2553 if (ep_bw->max_packet_size >=
2554 smaller_ep->bw_info.max_packet_size) {
2555 /* Add the new ep before the smaller endpoint */
2556 list_add_tail(&virt_ep->bw_endpoint_list,
2557 &smaller_ep->bw_endpoint_list);
2561 /* Add the new endpoint at the end of the list. */
2562 list_add_tail(&virt_ep->bw_endpoint_list,
2563 &interval_bw->endpoints);
2566 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2567 struct xhci_virt_device *virt_dev,
2570 struct xhci_root_port_bw_info *rh_bw_info;
2571 if (!virt_dev->tt_info)
2574 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2575 if (old_active_eps == 0 &&
2576 virt_dev->tt_info->active_eps != 0) {
2577 rh_bw_info->num_active_tts += 1;
2578 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2579 } else if (old_active_eps != 0 &&
2580 virt_dev->tt_info->active_eps == 0) {
2581 rh_bw_info->num_active_tts -= 1;
2582 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2586 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2587 struct xhci_virt_device *virt_dev,
2588 struct xhci_container_ctx *in_ctx)
2590 struct xhci_bw_info ep_bw_info[31];
2592 struct xhci_input_control_ctx *ctrl_ctx;
2593 int old_active_eps = 0;
2595 if (virt_dev->tt_info)
2596 old_active_eps = virt_dev->tt_info->active_eps;
2598 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2600 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2605 for (i = 0; i < 31; i++) {
2606 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2609 /* Make a copy of the BW info in case we need to revert this */
2610 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2611 sizeof(ep_bw_info[i]));
2612 /* Drop the endpoint from the interval table if the endpoint is
2613 * being dropped or changed.
2615 if (EP_IS_DROPPED(ctrl_ctx, i))
2616 xhci_drop_ep_from_interval_table(xhci,
2617 &virt_dev->eps[i].bw_info,
2623 /* Overwrite the information stored in the endpoints' bw_info */
2624 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2625 for (i = 0; i < 31; i++) {
2626 /* Add any changed or added endpoints to the interval table */
2627 if (EP_IS_ADDED(ctrl_ctx, i))
2628 xhci_add_ep_to_interval_table(xhci,
2629 &virt_dev->eps[i].bw_info,
2636 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2637 /* Ok, this fits in the bandwidth we have.
2638 * Update the number of active TTs.
2640 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2644 /* We don't have enough bandwidth for this, revert the stored info. */
2645 for (i = 0; i < 31; i++) {
2646 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2649 /* Drop the new copies of any added or changed endpoints from
2650 * the interval table.
2652 if (EP_IS_ADDED(ctrl_ctx, i)) {
2653 xhci_drop_ep_from_interval_table(xhci,
2654 &virt_dev->eps[i].bw_info,
2660 /* Revert the endpoint back to its old information */
2661 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2662 sizeof(ep_bw_info[i]));
2663 /* Add any changed or dropped endpoints back into the table */
2664 if (EP_IS_DROPPED(ctrl_ctx, i))
2665 xhci_add_ep_to_interval_table(xhci,
2666 &virt_dev->eps[i].bw_info,
2676 /* Issue a configure endpoint command or evaluate context command
2677 * and wait for it to finish.
2679 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2680 struct usb_device *udev,
2681 struct xhci_command *command,
2682 bool ctx_change, bool must_succeed)
2685 unsigned long flags;
2686 struct xhci_input_control_ctx *ctrl_ctx;
2687 struct xhci_virt_device *virt_dev;
2692 spin_lock_irqsave(&xhci->lock, flags);
2693 virt_dev = xhci->devs[udev->slot_id];
2695 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2697 spin_unlock_irqrestore(&xhci->lock, flags);
2698 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2703 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2704 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2705 spin_unlock_irqrestore(&xhci->lock, flags);
2706 xhci_warn(xhci, "Not enough host resources, "
2707 "active endpoint contexts = %u\n",
2708 xhci->num_active_eps);
2711 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2712 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2713 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2714 xhci_free_host_resources(xhci, ctrl_ctx);
2715 spin_unlock_irqrestore(&xhci->lock, flags);
2716 xhci_warn(xhci, "Not enough bandwidth\n");
2721 ret = xhci_queue_configure_endpoint(xhci, command,
2722 command->in_ctx->dma,
2723 udev->slot_id, must_succeed);
2725 ret = xhci_queue_evaluate_context(xhci, command,
2726 command->in_ctx->dma,
2727 udev->slot_id, must_succeed);
2729 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2730 xhci_free_host_resources(xhci, ctrl_ctx);
2731 spin_unlock_irqrestore(&xhci->lock, flags);
2732 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2733 "FIXME allocate a new ring segment");
2736 xhci_ring_cmd_db(xhci);
2737 spin_unlock_irqrestore(&xhci->lock, flags);
2739 /* Wait for the configure endpoint command to complete */
2740 wait_for_completion(command->completion);
2743 ret = xhci_configure_endpoint_result(xhci, udev,
2746 ret = xhci_evaluate_context_result(xhci, udev,
2749 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2750 spin_lock_irqsave(&xhci->lock, flags);
2751 /* If the command failed, remove the reserved resources.
2752 * Otherwise, clean up the estimate to include dropped eps.
2755 xhci_free_host_resources(xhci, ctrl_ctx);
2757 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2758 spin_unlock_irqrestore(&xhci->lock, flags);
2763 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2764 struct xhci_virt_device *vdev, int i)
2766 struct xhci_virt_ep *ep = &vdev->eps[i];
2768 if (ep->ep_state & EP_HAS_STREAMS) {
2769 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2770 xhci_get_endpoint_address(i));
2771 xhci_free_stream_info(xhci, ep->stream_info);
2772 ep->stream_info = NULL;
2773 ep->ep_state &= ~EP_HAS_STREAMS;
2777 /* Called after one or more calls to xhci_add_endpoint() or
2778 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2779 * to call xhci_reset_bandwidth().
2781 * Since we are in the middle of changing either configuration or
2782 * installing a new alt setting, the USB core won't allow URBs to be
2783 * enqueued for any endpoint on the old config or interface. Nothing
2784 * else should be touching the xhci->devs[slot_id] structure, so we
2785 * don't need to take the xhci->lock for manipulating that.
2787 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2791 struct xhci_hcd *xhci;
2792 struct xhci_virt_device *virt_dev;
2793 struct xhci_input_control_ctx *ctrl_ctx;
2794 struct xhci_slot_ctx *slot_ctx;
2795 struct xhci_command *command;
2797 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2800 xhci = hcd_to_xhci(hcd);
2801 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2802 (xhci->xhc_state & XHCI_STATE_REMOVING))
2805 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2806 virt_dev = xhci->devs[udev->slot_id];
2808 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2812 command->in_ctx = virt_dev->in_ctx;
2814 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2815 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2817 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2820 goto command_cleanup;
2822 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2823 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2824 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2826 /* Don't issue the command if there's no endpoints to update. */
2827 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2828 ctrl_ctx->drop_flags == 0) {
2830 goto command_cleanup;
2832 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2833 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2834 for (i = 31; i >= 1; i--) {
2835 __le32 le32 = cpu_to_le32(BIT(i));
2837 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2838 || (ctrl_ctx->add_flags & le32) || i == 1) {
2839 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2840 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2844 xhci_dbg(xhci, "New Input Control Context:\n");
2845 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2846 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2848 ret = xhci_configure_endpoint(xhci, udev, command,
2851 /* Callee should call reset_bandwidth() */
2852 goto command_cleanup;
2854 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2855 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2856 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2858 /* Free any rings that were dropped, but not changed. */
2859 for (i = 1; i < 31; ++i) {
2860 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2861 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2862 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2863 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2866 xhci_zero_in_ctx(xhci, virt_dev);
2868 * Install any rings for completely new endpoints or changed endpoints,
2869 * and free or cache any old rings from changed endpoints.
2871 for (i = 1; i < 31; ++i) {
2872 if (!virt_dev->eps[i].new_ring)
2874 /* Only cache or free the old ring if it exists.
2875 * It may not if this is the first add of an endpoint.
2877 if (virt_dev->eps[i].ring) {
2878 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2880 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2881 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2882 virt_dev->eps[i].new_ring = NULL;
2885 kfree(command->completion);
2891 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2893 struct xhci_hcd *xhci;
2894 struct xhci_virt_device *virt_dev;
2897 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2900 xhci = hcd_to_xhci(hcd);
2902 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2903 virt_dev = xhci->devs[udev->slot_id];
2904 /* Free any rings allocated for added endpoints */
2905 for (i = 0; i < 31; ++i) {
2906 if (virt_dev->eps[i].new_ring) {
2907 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2908 virt_dev->eps[i].new_ring = NULL;
2911 xhci_zero_in_ctx(xhci, virt_dev);
2914 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2915 struct xhci_container_ctx *in_ctx,
2916 struct xhci_container_ctx *out_ctx,
2917 struct xhci_input_control_ctx *ctrl_ctx,
2918 u32 add_flags, u32 drop_flags)
2920 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2921 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2922 xhci_slot_copy(xhci, in_ctx, out_ctx);
2923 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2925 xhci_dbg(xhci, "Input Context:\n");
2926 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2929 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2930 unsigned int slot_id, unsigned int ep_index,
2931 struct xhci_dequeue_state *deq_state)
2933 struct xhci_input_control_ctx *ctrl_ctx;
2934 struct xhci_container_ctx *in_ctx;
2935 struct xhci_ep_ctx *ep_ctx;
2939 in_ctx = xhci->devs[slot_id]->in_ctx;
2940 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2942 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2947 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2948 xhci->devs[slot_id]->out_ctx, ep_index);
2949 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2950 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2951 deq_state->new_deq_ptr);
2953 xhci_warn(xhci, "WARN Cannot submit config ep after "
2954 "reset ep command\n");
2955 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2956 deq_state->new_deq_seg,
2957 deq_state->new_deq_ptr);
2960 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2962 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2963 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2964 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2965 added_ctxs, added_ctxs);
2968 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2969 unsigned int ep_index, struct xhci_td *td)
2971 struct xhci_dequeue_state deq_state;
2972 struct xhci_virt_ep *ep;
2973 struct usb_device *udev = td->urb->dev;
2975 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2976 "Cleaning up stalled endpoint ring");
2977 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2978 /* We need to move the HW's dequeue pointer past this TD,
2979 * or it will attempt to resend it on the next doorbell ring.
2981 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2982 ep_index, ep->stopped_stream, td, &deq_state);
2984 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2987 /* HW with the reset endpoint quirk will use the saved dequeue state to
2988 * issue a configure endpoint command later.
2990 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2991 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2992 "Queueing new dequeue state");
2993 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2994 ep_index, ep->stopped_stream, &deq_state);
2996 /* Better hope no one uses the input context between now and the
2997 * reset endpoint completion!
2998 * XXX: No idea how this hardware will react when stream rings
3001 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3002 "Setting up input context for "
3003 "configure endpoint command");
3004 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
3005 ep_index, &deq_state);
3009 /* Called when clearing halted device. The core should have sent the control
3010 * message to clear the device halt condition. The host side of the halt should
3011 * already be cleared with a reset endpoint command issued when the STALL tx
3012 * event was received.
3014 * Context: in_interrupt
3017 void xhci_endpoint_reset(struct usb_hcd *hcd,
3018 struct usb_host_endpoint *ep)
3020 struct xhci_hcd *xhci;
3022 xhci = hcd_to_xhci(hcd);
3025 * We might need to implement the config ep cmd in xhci 4.8.1 note:
3026 * The Reset Endpoint Command may only be issued to endpoints in the
3027 * Halted state. If software wishes reset the Data Toggle or Sequence
3028 * Number of an endpoint that isn't in the Halted state, then software
3029 * may issue a Configure Endpoint Command with the Drop and Add bits set
3030 * for the target endpoint. that is in the Stopped state.
3033 /* For now just print debug to follow the situation */
3034 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
3035 ep->desc.bEndpointAddress);
3038 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3039 struct usb_device *udev, struct usb_host_endpoint *ep,
3040 unsigned int slot_id)
3043 unsigned int ep_index;
3044 unsigned int ep_state;
3048 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3050 return ret ? ret : -EINVAL;
3051 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3052 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3053 " descriptor for ep 0x%x does not support streams\n",
3054 ep->desc.bEndpointAddress);
3058 ep_index = xhci_get_endpoint_index(&ep->desc);
3059 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3060 if (ep_state & EP_HAS_STREAMS ||
3061 ep_state & EP_GETTING_STREAMS) {
3062 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3063 "already has streams set up.\n",
3064 ep->desc.bEndpointAddress);
3065 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3066 "dynamic stream context array reallocation.\n");
3069 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3070 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3071 "endpoint 0x%x; URBs are pending.\n",
3072 ep->desc.bEndpointAddress);
3078 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3079 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3081 unsigned int max_streams;
3083 /* The stream context array size must be a power of two */
3084 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3086 * Find out how many primary stream array entries the host controller
3087 * supports. Later we may use secondary stream arrays (similar to 2nd
3088 * level page entries), but that's an optional feature for xHCI host
3089 * controllers. xHCs must support at least 4 stream IDs.
3091 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3092 if (*num_stream_ctxs > max_streams) {
3093 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3095 *num_stream_ctxs = max_streams;
3096 *num_streams = max_streams;
3100 /* Returns an error code if one of the endpoint already has streams.
3101 * This does not change any data structures, it only checks and gathers
3104 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3105 struct usb_device *udev,
3106 struct usb_host_endpoint **eps, unsigned int num_eps,
3107 unsigned int *num_streams, u32 *changed_ep_bitmask)
3109 unsigned int max_streams;
3110 unsigned int endpoint_flag;
3114 for (i = 0; i < num_eps; i++) {
3115 ret = xhci_check_streams_endpoint(xhci, udev,
3116 eps[i], udev->slot_id);
3120 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3121 if (max_streams < (*num_streams - 1)) {
3122 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3123 eps[i]->desc.bEndpointAddress,
3125 *num_streams = max_streams+1;
3128 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3129 if (*changed_ep_bitmask & endpoint_flag)
3131 *changed_ep_bitmask |= endpoint_flag;
3136 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3137 struct usb_device *udev,
3138 struct usb_host_endpoint **eps, unsigned int num_eps)
3140 u32 changed_ep_bitmask = 0;
3141 unsigned int slot_id;
3142 unsigned int ep_index;
3143 unsigned int ep_state;
3146 slot_id = udev->slot_id;
3147 if (!xhci->devs[slot_id])
3150 for (i = 0; i < num_eps; i++) {
3151 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3152 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3153 /* Are streams already being freed for the endpoint? */
3154 if (ep_state & EP_GETTING_NO_STREAMS) {
3155 xhci_warn(xhci, "WARN Can't disable streams for "
3157 "streams are being disabled already\n",
3158 eps[i]->desc.bEndpointAddress);
3161 /* Are there actually any streams to free? */
3162 if (!(ep_state & EP_HAS_STREAMS) &&
3163 !(ep_state & EP_GETTING_STREAMS)) {
3164 xhci_warn(xhci, "WARN Can't disable streams for "
3166 "streams are already disabled!\n",
3167 eps[i]->desc.bEndpointAddress);
3168 xhci_warn(xhci, "WARN xhci_free_streams() called "
3169 "with non-streams endpoint\n");
3172 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3174 return changed_ep_bitmask;
3178 * The USB device drivers use this function (through the HCD interface in USB
3179 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3180 * coordinate mass storage command queueing across multiple endpoints (basically
3181 * a stream ID == a task ID).
3183 * Setting up streams involves allocating the same size stream context array
3184 * for each endpoint and issuing a configure endpoint command for all endpoints.
3186 * Don't allow the call to succeed if one endpoint only supports one stream
3187 * (which means it doesn't support streams at all).
3189 * Drivers may get less stream IDs than they asked for, if the host controller
3190 * hardware or endpoints claim they can't support the number of requested
3193 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3194 struct usb_host_endpoint **eps, unsigned int num_eps,
3195 unsigned int num_streams, gfp_t mem_flags)
3198 struct xhci_hcd *xhci;
3199 struct xhci_virt_device *vdev;
3200 struct xhci_command *config_cmd;
3201 struct xhci_input_control_ctx *ctrl_ctx;
3202 unsigned int ep_index;
3203 unsigned int num_stream_ctxs;
3204 unsigned int max_packet;
3205 unsigned long flags;
3206 u32 changed_ep_bitmask = 0;
3211 /* Add one to the number of streams requested to account for
3212 * stream 0 that is reserved for xHCI usage.
3215 xhci = hcd_to_xhci(hcd);
3216 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3219 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3220 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3221 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3222 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3226 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3228 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3231 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3233 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3235 xhci_free_command(xhci, config_cmd);
3239 /* Check to make sure all endpoints are not already configured for
3240 * streams. While we're at it, find the maximum number of streams that
3241 * all the endpoints will support and check for duplicate endpoints.
3243 spin_lock_irqsave(&xhci->lock, flags);
3244 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3245 num_eps, &num_streams, &changed_ep_bitmask);
3247 xhci_free_command(xhci, config_cmd);
3248 spin_unlock_irqrestore(&xhci->lock, flags);
3251 if (num_streams <= 1) {
3252 xhci_warn(xhci, "WARN: endpoints can't handle "
3253 "more than one stream.\n");
3254 xhci_free_command(xhci, config_cmd);
3255 spin_unlock_irqrestore(&xhci->lock, flags);
3258 vdev = xhci->devs[udev->slot_id];
3259 /* Mark each endpoint as being in transition, so
3260 * xhci_urb_enqueue() will reject all URBs.
3262 for (i = 0; i < num_eps; i++) {
3263 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3264 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3266 spin_unlock_irqrestore(&xhci->lock, flags);
3268 /* Setup internal data structures and allocate HW data structures for
3269 * streams (but don't install the HW structures in the input context
3270 * until we're sure all memory allocation succeeded).
3272 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3273 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3274 num_stream_ctxs, num_streams);
3276 for (i = 0; i < num_eps; i++) {
3277 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3278 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&eps[i]->desc));
3279 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3282 max_packet, mem_flags);
3283 if (!vdev->eps[ep_index].stream_info)
3285 /* Set maxPstreams in endpoint context and update deq ptr to
3286 * point to stream context array. FIXME
3290 /* Set up the input context for a configure endpoint command. */
3291 for (i = 0; i < num_eps; i++) {
3292 struct xhci_ep_ctx *ep_ctx;
3294 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3295 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3297 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3298 vdev->out_ctx, ep_index);
3299 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3300 vdev->eps[ep_index].stream_info);
3302 /* Tell the HW to drop its old copy of the endpoint context info
3303 * and add the updated copy from the input context.
3305 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3306 vdev->out_ctx, ctrl_ctx,
3307 changed_ep_bitmask, changed_ep_bitmask);
3309 /* Issue and wait for the configure endpoint command */
3310 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3313 /* xHC rejected the configure endpoint command for some reason, so we
3314 * leave the old ring intact and free our internal streams data
3320 spin_lock_irqsave(&xhci->lock, flags);
3321 for (i = 0; i < num_eps; i++) {
3322 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3323 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3324 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3325 udev->slot_id, ep_index);
3326 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3328 xhci_free_command(xhci, config_cmd);
3329 spin_unlock_irqrestore(&xhci->lock, flags);
3331 /* Subtract 1 for stream 0, which drivers can't use */
3332 return num_streams - 1;
3335 /* If it didn't work, free the streams! */
3336 for (i = 0; i < num_eps; i++) {
3337 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3338 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3339 vdev->eps[ep_index].stream_info = NULL;
3340 /* FIXME Unset maxPstreams in endpoint context and
3341 * update deq ptr to point to normal string ring.
3343 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3344 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3345 xhci_endpoint_zero(xhci, vdev, eps[i]);
3347 xhci_free_command(xhci, config_cmd);
3351 /* Transition the endpoint from using streams to being a "normal" endpoint
3354 * Modify the endpoint context state, submit a configure endpoint command,
3355 * and free all endpoint rings for streams if that completes successfully.
3357 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3358 struct usb_host_endpoint **eps, unsigned int num_eps,
3362 struct xhci_hcd *xhci;
3363 struct xhci_virt_device *vdev;
3364 struct xhci_command *command;
3365 struct xhci_input_control_ctx *ctrl_ctx;
3366 unsigned int ep_index;
3367 unsigned long flags;
3368 u32 changed_ep_bitmask;
3370 xhci = hcd_to_xhci(hcd);
3371 vdev = xhci->devs[udev->slot_id];
3373 /* Set up a configure endpoint command to remove the streams rings */
3374 spin_lock_irqsave(&xhci->lock, flags);
3375 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3376 udev, eps, num_eps);
3377 if (changed_ep_bitmask == 0) {
3378 spin_unlock_irqrestore(&xhci->lock, flags);
3382 /* Use the xhci_command structure from the first endpoint. We may have
3383 * allocated too many, but the driver may call xhci_free_streams() for
3384 * each endpoint it grouped into one call to xhci_alloc_streams().
3386 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3387 command = vdev->eps[ep_index].stream_info->free_streams_command;
3388 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3390 spin_unlock_irqrestore(&xhci->lock, flags);
3391 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3396 for (i = 0; i < num_eps; i++) {
3397 struct xhci_ep_ctx *ep_ctx;
3399 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3400 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3401 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3402 EP_GETTING_NO_STREAMS;
3404 xhci_endpoint_copy(xhci, command->in_ctx,
3405 vdev->out_ctx, ep_index);
3406 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3407 &vdev->eps[ep_index]);
3409 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3410 vdev->out_ctx, ctrl_ctx,
3411 changed_ep_bitmask, changed_ep_bitmask);
3412 spin_unlock_irqrestore(&xhci->lock, flags);
3414 /* Issue and wait for the configure endpoint command,
3415 * which must succeed.
3417 ret = xhci_configure_endpoint(xhci, udev, command,
3420 /* xHC rejected the configure endpoint command for some reason, so we
3421 * leave the streams rings intact.
3426 spin_lock_irqsave(&xhci->lock, flags);
3427 for (i = 0; i < num_eps; i++) {
3428 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3429 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3430 vdev->eps[ep_index].stream_info = NULL;
3431 /* FIXME Unset maxPstreams in endpoint context and
3432 * update deq ptr to point to normal string ring.
3434 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3435 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3437 spin_unlock_irqrestore(&xhci->lock, flags);
3443 * Deletes endpoint resources for endpoints that were active before a Reset
3444 * Device command, or a Disable Slot command. The Reset Device command leaves
3445 * the control endpoint intact, whereas the Disable Slot command deletes it.
3447 * Must be called with xhci->lock held.
3449 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3450 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3453 unsigned int num_dropped_eps = 0;
3454 unsigned int drop_flags = 0;
3456 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3457 if (virt_dev->eps[i].ring) {
3458 drop_flags |= 1 << i;
3462 xhci->num_active_eps -= num_dropped_eps;
3463 if (num_dropped_eps)
3464 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3465 "Dropped %u ep ctxs, flags = 0x%x, "
3467 num_dropped_eps, drop_flags,
3468 xhci->num_active_eps);
3472 * This submits a Reset Device Command, which will set the device state to 0,
3473 * set the device address to 0, and disable all the endpoints except the default
3474 * control endpoint. The USB core should come back and call
3475 * xhci_address_device(), and then re-set up the configuration. If this is
3476 * called because of a usb_reset_and_verify_device(), then the old alternate
3477 * settings will be re-installed through the normal bandwidth allocation
3480 * Wait for the Reset Device command to finish. Remove all structures
3481 * associated with the endpoints that were disabled. Clear the input device
3482 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3484 * If the virt_dev to be reset does not exist or does not match the udev,
3485 * it means the device is lost, possibly due to the xHC restore error and
3486 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3487 * re-allocate the device.
3489 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3492 unsigned long flags;
3493 struct xhci_hcd *xhci;
3494 unsigned int slot_id;
3495 struct xhci_virt_device *virt_dev;
3496 struct xhci_command *reset_device_cmd;
3497 int last_freed_endpoint;
3498 struct xhci_slot_ctx *slot_ctx;
3499 int old_active_eps = 0;
3501 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3504 xhci = hcd_to_xhci(hcd);
3505 slot_id = udev->slot_id;
3506 virt_dev = xhci->devs[slot_id];
3508 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3509 "not exist. Re-allocate the device\n", slot_id);
3510 ret = xhci_alloc_dev(hcd, udev);
3517 if (virt_dev->tt_info)
3518 old_active_eps = virt_dev->tt_info->active_eps;
3520 if (virt_dev->udev != udev) {
3521 /* If the virt_dev and the udev does not match, this virt_dev
3522 * may belong to another udev.
3523 * Re-allocate the device.
3525 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3526 "not match the udev. Re-allocate the device\n",
3528 ret = xhci_alloc_dev(hcd, udev);
3535 /* If device is not setup, there is no point in resetting it */
3536 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3537 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3538 SLOT_STATE_DISABLED)
3541 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3542 /* Allocate the command structure that holds the struct completion.
3543 * Assume we're in process context, since the normal device reset
3544 * process has to wait for the device anyway. Storage devices are
3545 * reset as part of error handling, so use GFP_NOIO instead of
3548 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3549 if (!reset_device_cmd) {
3550 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3554 /* Attempt to submit the Reset Device command to the command ring */
3555 spin_lock_irqsave(&xhci->lock, flags);
3557 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3559 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3560 spin_unlock_irqrestore(&xhci->lock, flags);
3561 goto command_cleanup;
3563 xhci_ring_cmd_db(xhci);
3564 spin_unlock_irqrestore(&xhci->lock, flags);
3566 /* Wait for the Reset Device command to finish */
3567 wait_for_completion(reset_device_cmd->completion);
3569 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3570 * unless we tried to reset a slot ID that wasn't enabled,
3571 * or the device wasn't in the addressed or configured state.
3573 ret = reset_device_cmd->status;
3575 case COMP_CMD_ABORT:
3577 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3579 goto command_cleanup;
3580 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3581 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3582 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3584 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3585 xhci_dbg(xhci, "Not freeing device rings.\n");
3586 /* Don't treat this as an error. May change my mind later. */
3588 goto command_cleanup;
3590 xhci_dbg(xhci, "Successful reset device command.\n");
3593 if (xhci_is_vendor_info_code(xhci, ret))
3595 xhci_warn(xhci, "Unknown completion code %u for "
3596 "reset device command.\n", ret);
3598 goto command_cleanup;
3601 /* Free up host controller endpoint resources */
3602 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3603 spin_lock_irqsave(&xhci->lock, flags);
3604 /* Don't delete the default control endpoint resources */
3605 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3606 spin_unlock_irqrestore(&xhci->lock, flags);
3609 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3610 last_freed_endpoint = 1;
3611 for (i = 1; i < 31; ++i) {
3612 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3614 if (ep->ep_state & EP_HAS_STREAMS) {
3615 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3616 xhci_get_endpoint_address(i));
3617 xhci_free_stream_info(xhci, ep->stream_info);
3618 ep->stream_info = NULL;
3619 ep->ep_state &= ~EP_HAS_STREAMS;
3623 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3624 last_freed_endpoint = i;
3626 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3627 xhci_drop_ep_from_interval_table(xhci,
3628 &virt_dev->eps[i].bw_info,
3633 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3635 /* If necessary, update the number of active TTs on this root port */
3636 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3638 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3639 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3643 xhci_free_command(xhci, reset_device_cmd);
3648 * At this point, the struct usb_device is about to go away, the device has
3649 * disconnected, and all traffic has been stopped and the endpoints have been
3650 * disabled. Free any HC data structures associated with that device.
3652 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3654 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3655 struct xhci_virt_device *virt_dev;
3656 unsigned long flags;
3659 struct xhci_command *command;
3661 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3665 #ifndef CONFIG_USB_DEFAULT_PERSIST
3667 * We called pm_runtime_get_noresume when the device was attached.
3668 * Decrement the counter here to allow controller to runtime suspend
3669 * if no devices remain.
3671 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3672 pm_runtime_put_noidle(hcd->self.controller);
3675 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3676 /* If the host is halted due to driver unload, we still need to free the
3679 if (ret <= 0 && ret != -ENODEV) {
3684 virt_dev = xhci->devs[udev->slot_id];
3686 /* Stop any wayward timer functions (which may grab the lock) */
3687 for (i = 0; i < 31; ++i) {
3688 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3689 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3692 spin_lock_irqsave(&xhci->lock, flags);
3694 virt_dev->udev = NULL;
3696 /* Don't disable the slot if the host controller is dead. */
3697 state = readl(&xhci->op_regs->status);
3698 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3699 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3700 xhci_free_virt_device(xhci, udev->slot_id);
3701 spin_unlock_irqrestore(&xhci->lock, flags);
3706 if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3708 spin_unlock_irqrestore(&xhci->lock, flags);
3709 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3712 xhci_ring_cmd_db(xhci);
3713 spin_unlock_irqrestore(&xhci->lock, flags);
3716 * Event command completion handler will free any data structures
3717 * associated with the slot. XXX Can free sleep?
3722 * Checks if we have enough host controller resources for the default control
3725 * Must be called with xhci->lock held.
3727 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3729 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3730 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3731 "Not enough ep ctxs: "
3732 "%u active, need to add 1, limit is %u.",
3733 xhci->num_active_eps, xhci->limit_active_eps);
3736 xhci->num_active_eps += 1;
3737 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3738 "Adding 1 ep ctx, %u now active.",
3739 xhci->num_active_eps);
3745 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3746 * timed out, or allocating memory failed. Returns 1 on success.
3748 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3750 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3751 unsigned long flags;
3753 struct xhci_command *command;
3755 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3759 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3760 mutex_lock(&xhci->mutex);
3761 spin_lock_irqsave(&xhci->lock, flags);
3762 command->completion = &xhci->addr_dev;
3763 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3765 spin_unlock_irqrestore(&xhci->lock, flags);
3766 mutex_unlock(&xhci->mutex);
3767 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3771 xhci_ring_cmd_db(xhci);
3772 spin_unlock_irqrestore(&xhci->lock, flags);
3774 wait_for_completion(command->completion);
3775 slot_id = xhci->slot_id;
3776 mutex_unlock(&xhci->mutex);
3778 if (!slot_id || command->status != COMP_SUCCESS) {
3779 xhci_err(xhci, "Error while assigning device slot ID\n");
3780 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3782 readl(&xhci->cap_regs->hcs_params1)));
3787 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3788 spin_lock_irqsave(&xhci->lock, flags);
3789 ret = xhci_reserve_host_control_ep_resources(xhci);
3791 spin_unlock_irqrestore(&xhci->lock, flags);
3792 xhci_warn(xhci, "Not enough host resources, "
3793 "active endpoint contexts = %u\n",
3794 xhci->num_active_eps);
3797 spin_unlock_irqrestore(&xhci->lock, flags);
3799 /* Use GFP_NOIO, since this function can be called from
3800 * xhci_discover_or_reset_device(), which may be called as part of
3801 * mass storage driver error handling.
3803 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3804 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3807 udev->slot_id = slot_id;
3809 #ifndef CONFIG_USB_DEFAULT_PERSIST
3811 * If resetting upon resume, we can't put the controller into runtime
3812 * suspend if there is a device attached.
3814 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3815 pm_runtime_get_noresume(hcd->self.controller);
3820 /* Is this a LS or FS device under a HS hub? */
3821 /* Hub or peripherial? */
3825 /* Disable slot, if we can do it without mem alloc */
3826 spin_lock_irqsave(&xhci->lock, flags);
3827 command->completion = NULL;
3828 command->status = 0;
3829 if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3831 xhci_ring_cmd_db(xhci);
3832 spin_unlock_irqrestore(&xhci->lock, flags);
3837 * Issue an Address Device command and optionally send a corresponding
3838 * SetAddress request to the device.
3840 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3841 enum xhci_setup_dev setup)
3843 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3844 unsigned long flags;
3845 struct xhci_virt_device *virt_dev;
3847 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3848 struct xhci_slot_ctx *slot_ctx;
3849 struct xhci_input_control_ctx *ctrl_ctx;
3851 struct xhci_command *command = NULL;
3853 mutex_lock(&xhci->mutex);
3855 if (xhci->xhc_state) { /* dying, removing or halted */
3860 if (!udev->slot_id) {
3861 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3862 "Bad Slot ID %d", udev->slot_id);
3867 virt_dev = xhci->devs[udev->slot_id];
3869 if (WARN_ON(!virt_dev)) {
3871 * In plug/unplug torture test with an NEC controller,
3872 * a zero-dereference was observed once due to virt_dev = 0.
3873 * Print useful debug rather than crash if it is observed again!
3875 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3881 if (setup == SETUP_CONTEXT_ONLY) {
3882 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3883 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3884 SLOT_STATE_DEFAULT) {
3885 xhci_dbg(xhci, "Slot already in default state\n");
3890 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3896 command->in_ctx = virt_dev->in_ctx;
3897 command->completion = &xhci->addr_dev;
3899 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3900 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3902 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3908 * If this is the first Set Address since device plug-in or
3909 * virt_device realloaction after a resume with an xHCI power loss,
3910 * then set up the slot context.
3912 if (!slot_ctx->dev_info)
3913 xhci_setup_addressable_virt_dev(xhci, udev);
3914 /* Otherwise, update the control endpoint ring enqueue pointer. */
3916 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3917 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3918 ctrl_ctx->drop_flags = 0;
3920 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3921 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3922 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3923 le32_to_cpu(slot_ctx->dev_info) >> 27);
3925 spin_lock_irqsave(&xhci->lock, flags);
3926 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3927 udev->slot_id, setup);
3929 spin_unlock_irqrestore(&xhci->lock, flags);
3930 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3931 "FIXME: allocate a command ring segment");
3934 xhci_ring_cmd_db(xhci);
3935 spin_unlock_irqrestore(&xhci->lock, flags);
3937 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3938 wait_for_completion(command->completion);
3940 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3941 * the SetAddress() "recovery interval" required by USB and aborting the
3942 * command on a timeout.
3944 switch (command->status) {
3945 case COMP_CMD_ABORT:
3947 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3950 case COMP_CTX_STATE:
3952 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3953 act, udev->slot_id);
3957 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3961 dev_warn(&udev->dev,
3962 "ERROR: Incompatible device for setup %s command\n", act);
3966 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3967 "Successful setup %s command", act);
3971 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3972 act, command->status);
3973 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3974 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3975 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3981 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3982 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3983 "Op regs DCBAA ptr = %#016llx", temp_64);
3984 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3985 "Slot ID %d dcbaa entry @%p = %#016llx",
3987 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3988 (unsigned long long)
3989 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3990 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3991 "Output Context DMA address = %#08llx",
3992 (unsigned long long)virt_dev->out_ctx->dma);
3993 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3994 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3995 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3996 le32_to_cpu(slot_ctx->dev_info) >> 27);
3997 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3998 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
4000 * USB core uses address 1 for the roothubs, so we add one to the
4001 * address given back to us by the HC.
4003 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4004 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4005 le32_to_cpu(slot_ctx->dev_info) >> 27);
4006 /* Zero the input context control for later use */
4007 ctrl_ctx->add_flags = 0;
4008 ctrl_ctx->drop_flags = 0;
4010 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4011 "Internal device address = %d",
4012 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4014 mutex_unlock(&xhci->mutex);
4019 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4021 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4024 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4026 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4030 * Transfer the port index into real index in the HW port status
4031 * registers. Caculate offset between the port's PORTSC register
4032 * and port status base. Divide the number of per port register
4033 * to get the real index. The raw port number bases 1.
4035 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4037 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4038 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
4039 __le32 __iomem *addr;
4042 if (hcd->speed < HCD_USB3)
4043 addr = xhci->usb2_ports[port1 - 1];
4045 addr = xhci->usb3_ports[port1 - 1];
4047 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
4052 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4053 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4055 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4056 struct usb_device *udev, u16 max_exit_latency)
4058 struct xhci_virt_device *virt_dev;
4059 struct xhci_command *command;
4060 struct xhci_input_control_ctx *ctrl_ctx;
4061 struct xhci_slot_ctx *slot_ctx;
4062 unsigned long flags;
4065 spin_lock_irqsave(&xhci->lock, flags);
4067 virt_dev = xhci->devs[udev->slot_id];
4070 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4071 * xHC was re-initialized. Exit latency will be set later after
4072 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4075 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4076 spin_unlock_irqrestore(&xhci->lock, flags);
4080 /* Attempt to issue an Evaluate Context command to change the MEL. */
4081 command = xhci->lpm_command;
4082 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4084 spin_unlock_irqrestore(&xhci->lock, flags);
4085 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4090 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4091 spin_unlock_irqrestore(&xhci->lock, flags);
4093 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4094 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4095 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4096 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4097 slot_ctx->dev_state = 0;
4099 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4100 "Set up evaluate context for LPM MEL change.");
4101 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4102 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4104 /* Issue and wait for the evaluate context command. */
4105 ret = xhci_configure_endpoint(xhci, udev, command,
4107 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4108 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4111 spin_lock_irqsave(&xhci->lock, flags);
4112 virt_dev->current_mel = max_exit_latency;
4113 spin_unlock_irqrestore(&xhci->lock, flags);
4120 /* BESL to HIRD Encoding array for USB2 LPM */
4121 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4122 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4124 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4125 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4126 struct usb_device *udev)
4128 int u2del, besl, besl_host;
4129 int besl_device = 0;
4132 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4133 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4135 if (field & USB_BESL_SUPPORT) {
4136 for (besl_host = 0; besl_host < 16; besl_host++) {
4137 if (xhci_besl_encoding[besl_host] >= u2del)
4140 /* Use baseline BESL value as default */
4141 if (field & USB_BESL_BASELINE_VALID)
4142 besl_device = USB_GET_BESL_BASELINE(field);
4143 else if (field & USB_BESL_DEEP_VALID)
4144 besl_device = USB_GET_BESL_DEEP(field);
4149 besl_host = (u2del - 51) / 75 + 1;
4152 besl = besl_host + besl_device;
4159 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4160 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4167 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4169 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4170 l1 = udev->l1_params.timeout / 256;
4172 /* device has preferred BESLD */
4173 if (field & USB_BESL_DEEP_VALID) {
4174 besld = USB_GET_BESL_DEEP(field);
4178 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4181 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4182 struct usb_device *udev, int enable)
4184 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4185 __le32 __iomem **port_array;
4186 __le32 __iomem *pm_addr, *hlpm_addr;
4187 u32 pm_val, hlpm_val, field;
4188 unsigned int port_num;
4189 unsigned long flags;
4190 int hird, exit_latency;
4193 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4197 if (!udev->parent || udev->parent->parent ||
4198 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4201 if (udev->usb2_hw_lpm_capable != 1)
4204 spin_lock_irqsave(&xhci->lock, flags);
4206 port_array = xhci->usb2_ports;
4207 port_num = udev->portnum - 1;
4208 pm_addr = port_array[port_num] + PORTPMSC;
4209 pm_val = readl(pm_addr);
4210 hlpm_addr = port_array[port_num] + PORTHLPMC;
4212 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4213 enable ? "enable" : "disable", port_num + 1);
4216 /* Host supports BESL timeout instead of HIRD */
4217 if (udev->usb2_hw_lpm_besl_capable) {
4218 /* if device doesn't have a preferred BESL value use a
4219 * default one which works with mixed HIRD and BESL
4220 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4222 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4223 if ((field & USB_BESL_SUPPORT) &&
4224 (field & USB_BESL_BASELINE_VALID))
4225 hird = USB_GET_BESL_BASELINE(field);
4227 hird = udev->l1_params.besl;
4229 exit_latency = xhci_besl_encoding[hird];
4230 spin_unlock_irqrestore(&xhci->lock, flags);
4232 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4233 * input context for link powermanagement evaluate
4234 * context commands. It is protected by hcd->bandwidth
4235 * mutex and is shared by all devices. We need to set
4236 * the max ext latency in USB 2 BESL LPM as well, so
4237 * use the same mutex and xhci_change_max_exit_latency()
4239 mutex_lock(hcd->bandwidth_mutex);
4240 ret = xhci_change_max_exit_latency(xhci, udev,
4242 mutex_unlock(hcd->bandwidth_mutex);
4246 spin_lock_irqsave(&xhci->lock, flags);
4248 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4249 writel(hlpm_val, hlpm_addr);
4253 hird = xhci_calculate_hird_besl(xhci, udev);
4256 pm_val &= ~PORT_HIRD_MASK;
4257 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4258 writel(pm_val, pm_addr);
4259 pm_val = readl(pm_addr);
4261 writel(pm_val, pm_addr);
4265 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4266 writel(pm_val, pm_addr);
4269 if (udev->usb2_hw_lpm_besl_capable) {
4270 spin_unlock_irqrestore(&xhci->lock, flags);
4271 mutex_lock(hcd->bandwidth_mutex);
4272 xhci_change_max_exit_latency(xhci, udev, 0);
4273 mutex_unlock(hcd->bandwidth_mutex);
4274 readl_poll_timeout(port_array[port_num], pm_val,
4275 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4281 spin_unlock_irqrestore(&xhci->lock, flags);
4285 /* check if a usb2 port supports a given extened capability protocol
4286 * only USB2 ports extended protocol capability values are cached.
4287 * Return 1 if capability is supported
4289 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4290 unsigned capability)
4292 u32 port_offset, port_count;
4295 for (i = 0; i < xhci->num_ext_caps; i++) {
4296 if (xhci->ext_caps[i] & capability) {
4297 /* port offsets starts at 1 */
4298 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4299 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4300 if (port >= port_offset &&
4301 port < port_offset + port_count)
4308 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4310 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4311 int portnum = udev->portnum - 1;
4313 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4317 /* we only support lpm for non-hub device connected to root hub yet */
4318 if (!udev->parent || udev->parent->parent ||
4319 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4322 if (xhci->hw_lpm_support == 1 &&
4323 xhci_check_usb2_port_capability(
4324 xhci, portnum, XHCI_HLC)) {
4325 udev->usb2_hw_lpm_capable = 1;
4326 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4327 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4328 if (xhci_check_usb2_port_capability(xhci, portnum,
4330 udev->usb2_hw_lpm_besl_capable = 1;
4336 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4338 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4339 static unsigned long long xhci_service_interval_to_ns(
4340 struct usb_endpoint_descriptor *desc)
4342 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4345 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4346 enum usb3_link_state state)
4348 unsigned long long sel;
4349 unsigned long long pel;
4350 unsigned int max_sel_pel;
4355 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4356 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4357 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4358 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4362 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4363 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4364 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4368 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4370 return USB3_LPM_DISABLED;
4373 if (sel <= max_sel_pel && pel <= max_sel_pel)
4374 return USB3_LPM_DEVICE_INITIATED;
4376 if (sel > max_sel_pel)
4377 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4378 "due to long SEL %llu ms\n",
4381 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4382 "due to long PEL %llu ms\n",
4384 return USB3_LPM_DISABLED;
4387 /* The U1 timeout should be the maximum of the following values:
4388 * - For control endpoints, U1 system exit latency (SEL) * 3
4389 * - For bulk endpoints, U1 SEL * 5
4390 * - For interrupt endpoints:
4391 * - Notification EPs, U1 SEL * 3
4392 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4393 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4395 static unsigned long long xhci_calculate_intel_u1_timeout(
4396 struct usb_device *udev,
4397 struct usb_endpoint_descriptor *desc)
4399 unsigned long long timeout_ns;
4403 ep_type = usb_endpoint_type(desc);
4405 case USB_ENDPOINT_XFER_CONTROL:
4406 timeout_ns = udev->u1_params.sel * 3;
4408 case USB_ENDPOINT_XFER_BULK:
4409 timeout_ns = udev->u1_params.sel * 5;
4411 case USB_ENDPOINT_XFER_INT:
4412 intr_type = usb_endpoint_interrupt_type(desc);
4413 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4414 timeout_ns = udev->u1_params.sel * 3;
4417 /* Otherwise the calculation is the same as isoc eps */
4418 case USB_ENDPOINT_XFER_ISOC:
4419 timeout_ns = xhci_service_interval_to_ns(desc);
4420 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4421 if (timeout_ns < udev->u1_params.sel * 2)
4422 timeout_ns = udev->u1_params.sel * 2;
4431 /* Returns the hub-encoded U1 timeout value. */
4432 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4433 struct usb_device *udev,
4434 struct usb_endpoint_descriptor *desc)
4436 unsigned long long timeout_ns;
4438 /* Prevent U1 if service interval is shorter than U1 exit latency */
4439 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4440 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4441 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4442 return USB3_LPM_DISABLED;
4446 if (xhci->quirks & XHCI_INTEL_HOST)
4447 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4449 timeout_ns = udev->u1_params.sel;
4451 /* The U1 timeout is encoded in 1us intervals.
4452 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4454 if (timeout_ns == USB3_LPM_DISABLED)
4457 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4459 /* If the necessary timeout value is bigger than what we can set in the
4460 * USB 3.0 hub, we have to disable hub-initiated U1.
4462 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4464 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4465 "due to long timeout %llu ms\n", timeout_ns);
4466 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4469 /* The U2 timeout should be the maximum of:
4470 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4471 * - largest bInterval of any active periodic endpoint (to avoid going
4472 * into lower power link states between intervals).
4473 * - the U2 Exit Latency of the device
4475 static unsigned long long xhci_calculate_intel_u2_timeout(
4476 struct usb_device *udev,
4477 struct usb_endpoint_descriptor *desc)
4479 unsigned long long timeout_ns;
4480 unsigned long long u2_del_ns;
4482 timeout_ns = 10 * 1000 * 1000;
4484 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4485 (xhci_service_interval_to_ns(desc) > timeout_ns))
4486 timeout_ns = xhci_service_interval_to_ns(desc);
4488 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4489 if (u2_del_ns > timeout_ns)
4490 timeout_ns = u2_del_ns;
4495 /* Returns the hub-encoded U2 timeout value. */
4496 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4497 struct usb_device *udev,
4498 struct usb_endpoint_descriptor *desc)
4500 unsigned long long timeout_ns;
4502 /* Prevent U2 if service interval is shorter than U2 exit latency */
4503 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4504 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4505 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4506 return USB3_LPM_DISABLED;
4510 if (xhci->quirks & XHCI_INTEL_HOST)
4511 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4513 timeout_ns = udev->u2_params.sel;
4515 /* The U2 timeout is encoded in 256us intervals */
4516 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4517 /* If the necessary timeout value is bigger than what we can set in the
4518 * USB 3.0 hub, we have to disable hub-initiated U2.
4520 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4522 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4523 "due to long timeout %llu ms\n", timeout_ns);
4524 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4527 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4528 struct usb_device *udev,
4529 struct usb_endpoint_descriptor *desc,
4530 enum usb3_link_state state,
4533 if (state == USB3_LPM_U1)
4534 return xhci_calculate_u1_timeout(xhci, udev, desc);
4535 else if (state == USB3_LPM_U2)
4536 return xhci_calculate_u2_timeout(xhci, udev, desc);
4538 return USB3_LPM_DISABLED;
4541 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4542 struct usb_device *udev,
4543 struct usb_endpoint_descriptor *desc,
4544 enum usb3_link_state state,
4549 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4550 desc, state, timeout);
4552 /* If we found we can't enable hub-initiated LPM, and
4553 * the U1 or U2 exit latency was too high to allow
4554 * device-initiated LPM as well, then we will disable LPM
4555 * for this device, so stop searching any further.
4557 if (alt_timeout == USB3_LPM_DISABLED) {
4558 *timeout = alt_timeout;
4561 if (alt_timeout > *timeout)
4562 *timeout = alt_timeout;
4566 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4567 struct usb_device *udev,
4568 struct usb_host_interface *alt,
4569 enum usb3_link_state state,
4574 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4575 if (xhci_update_timeout_for_endpoint(xhci, udev,
4576 &alt->endpoint[j].desc, state, timeout))
4583 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4584 enum usb3_link_state state)
4586 struct usb_device *parent;
4587 unsigned int num_hubs;
4589 if (state == USB3_LPM_U2)
4592 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4593 for (parent = udev->parent, num_hubs = 0; parent->parent;
4594 parent = parent->parent)
4600 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4601 " below second-tier hub.\n");
4602 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4603 "to decrease power consumption.\n");
4607 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4608 struct usb_device *udev,
4609 enum usb3_link_state state)
4611 if (xhci->quirks & XHCI_INTEL_HOST)
4612 return xhci_check_intel_tier_policy(udev, state);
4617 /* Returns the U1 or U2 timeout that should be enabled.
4618 * If the tier check or timeout setting functions return with a non-zero exit
4619 * code, that means the timeout value has been finalized and we shouldn't look
4620 * at any more endpoints.
4622 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4623 struct usb_device *udev, enum usb3_link_state state)
4625 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4626 struct usb_host_config *config;
4629 u16 timeout = USB3_LPM_DISABLED;
4631 if (state == USB3_LPM_U1)
4633 else if (state == USB3_LPM_U2)
4636 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4641 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4644 /* Gather some information about the currently installed configuration
4645 * and alternate interface settings.
4647 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4651 config = udev->actconfig;
4655 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4656 struct usb_driver *driver;
4657 struct usb_interface *intf = config->interface[i];
4662 /* Check if any currently bound drivers want hub-initiated LPM
4665 if (intf->dev.driver) {
4666 driver = to_usb_driver(intf->dev.driver);
4667 if (driver && driver->disable_hub_initiated_lpm) {
4668 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4669 state_name, driver->name);
4670 timeout = xhci_get_timeout_no_hub_lpm(udev,
4672 if (timeout == USB3_LPM_DISABLED)
4677 /* Not sure how this could happen... */
4678 if (!intf->cur_altsetting)
4681 if (xhci_update_timeout_for_interface(xhci, udev,
4682 intf->cur_altsetting,
4689 static int calculate_max_exit_latency(struct usb_device *udev,
4690 enum usb3_link_state state_changed,
4691 u16 hub_encoded_timeout)
4693 unsigned long long u1_mel_us = 0;
4694 unsigned long long u2_mel_us = 0;
4695 unsigned long long mel_us = 0;
4701 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4702 hub_encoded_timeout == USB3_LPM_DISABLED);
4703 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4704 hub_encoded_timeout == USB3_LPM_DISABLED);
4706 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4707 hub_encoded_timeout != USB3_LPM_DISABLED);
4708 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4709 hub_encoded_timeout != USB3_LPM_DISABLED);
4711 /* If U1 was already enabled and we're not disabling it,
4712 * or we're going to enable U1, account for the U1 max exit latency.
4714 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4716 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4717 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4719 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4721 if (u1_mel_us > u2_mel_us)
4725 /* xHCI host controller max exit latency field is only 16 bits wide. */
4726 if (mel_us > MAX_EXIT) {
4727 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4728 "is too big.\n", mel_us);
4734 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4735 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4736 struct usb_device *udev, enum usb3_link_state state)
4738 struct xhci_hcd *xhci;
4739 u16 hub_encoded_timeout;
4743 xhci = hcd_to_xhci(hcd);
4744 /* The LPM timeout values are pretty host-controller specific, so don't
4745 * enable hub-initiated timeouts unless the vendor has provided
4746 * information about their timeout algorithm.
4748 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4749 !xhci->devs[udev->slot_id])
4750 return USB3_LPM_DISABLED;
4752 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4753 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4755 /* Max Exit Latency is too big, disable LPM. */
4756 hub_encoded_timeout = USB3_LPM_DISABLED;
4760 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4763 return hub_encoded_timeout;
4766 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4767 struct usb_device *udev, enum usb3_link_state state)
4769 struct xhci_hcd *xhci;
4772 xhci = hcd_to_xhci(hcd);
4773 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4774 !xhci->devs[udev->slot_id])
4777 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4778 return xhci_change_max_exit_latency(xhci, udev, mel);
4780 #else /* CONFIG_PM */
4782 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4783 struct usb_device *udev, int enable)
4788 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4793 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4794 struct usb_device *udev, enum usb3_link_state state)
4796 return USB3_LPM_DISABLED;
4799 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4800 struct usb_device *udev, enum usb3_link_state state)
4804 #endif /* CONFIG_PM */
4806 /*-------------------------------------------------------------------------*/
4808 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4809 * internal data structures for the device.
4811 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4812 struct usb_tt *tt, gfp_t mem_flags)
4814 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4815 struct xhci_virt_device *vdev;
4816 struct xhci_command *config_cmd;
4817 struct xhci_input_control_ctx *ctrl_ctx;
4818 struct xhci_slot_ctx *slot_ctx;
4819 unsigned long flags;
4820 unsigned think_time;
4823 /* Ignore root hubs */
4827 vdev = xhci->devs[hdev->slot_id];
4829 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4832 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4834 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4837 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4839 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4841 xhci_free_command(xhci, config_cmd);
4845 spin_lock_irqsave(&xhci->lock, flags);
4846 if (hdev->speed == USB_SPEED_HIGH &&
4847 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4848 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4849 xhci_free_command(xhci, config_cmd);
4850 spin_unlock_irqrestore(&xhci->lock, flags);
4854 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4855 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4856 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4857 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4859 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4860 * but it may be already set to 1 when setup an xHCI virtual
4861 * device, so clear it anyway.
4864 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4865 else if (hdev->speed == USB_SPEED_FULL)
4866 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4868 if (xhci->hci_version > 0x95) {
4869 xhci_dbg(xhci, "xHCI version %x needs hub "
4870 "TT think time and number of ports\n",
4871 (unsigned int) xhci->hci_version);
4872 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4873 /* Set TT think time - convert from ns to FS bit times.
4874 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4875 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4877 * xHCI 1.0: this field shall be 0 if the device is not a
4880 think_time = tt->think_time;
4881 if (think_time != 0)
4882 think_time = (think_time / 666) - 1;
4883 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4884 slot_ctx->tt_info |=
4885 cpu_to_le32(TT_THINK_TIME(think_time));
4887 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4888 "TT think time or number of ports\n",
4889 (unsigned int) xhci->hci_version);
4891 slot_ctx->dev_state = 0;
4892 spin_unlock_irqrestore(&xhci->lock, flags);
4894 xhci_dbg(xhci, "Set up %s for hub device.\n",
4895 (xhci->hci_version > 0x95) ?
4896 "configure endpoint" : "evaluate context");
4897 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4898 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4900 /* Issue and wait for the configure endpoint or
4901 * evaluate context command.
4903 if (xhci->hci_version > 0x95)
4904 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4907 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4910 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4911 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4913 xhci_free_command(xhci, config_cmd);
4917 int xhci_get_frame(struct usb_hcd *hcd)
4919 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4920 /* EHCI mods by the periodic size. Why? */
4921 return readl(&xhci->run_regs->microframe_index) >> 3;
4924 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4926 struct xhci_hcd *xhci;
4927 struct device *dev = hcd->self.controller;
4930 /* Accept arbitrarily long scatter-gather lists */
4931 hcd->self.sg_tablesize = ~0;
4933 /* support to build packet from discontinuous buffers */
4934 hcd->self.no_sg_constraint = 1;
4936 /* XHCI controllers don't stop the ep queue on short packets :| */
4937 hcd->self.no_stop_on_short = 1;
4939 xhci = hcd_to_xhci(hcd);
4941 if (usb_hcd_is_primary_hcd(hcd)) {
4942 xhci->main_hcd = hcd;
4943 /* Mark the first roothub as being USB 2.0.
4944 * The xHCI driver will register the USB 3.0 roothub.
4946 hcd->speed = HCD_USB2;
4947 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4949 * USB 2.0 roothub under xHCI has an integrated TT,
4950 * (rate matching hub) as opposed to having an OHCI/UHCI
4951 * companion controller.
4955 /* Some 3.1 hosts return sbrn 0x30, can't rely on sbrn alone */
4956 if (xhci->sbrn == 0x31 || xhci->usb3_rhub.min_rev >= 1) {
4957 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4958 hcd->speed = HCD_USB31;
4959 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
4961 /* xHCI private pointer was set in xhci_pci_probe for the second
4962 * registered roothub.
4967 mutex_init(&xhci->mutex);
4968 xhci->cap_regs = hcd->regs;
4969 xhci->op_regs = hcd->regs +
4970 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4971 xhci->run_regs = hcd->regs +
4972 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4973 /* Cache read-only capability registers */
4974 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4975 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4976 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4977 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4978 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4979 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4980 if (xhci->hci_version > 0x100)
4981 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4982 xhci_print_registers(xhci);
4984 xhci->quirks |= quirks;
4986 get_quirks(dev, xhci);
4988 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4989 * success event after a short transfer. This quirk will ignore such
4992 if (xhci->hci_version > 0x96)
4993 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4995 /* Make sure the HC is halted. */
4996 retval = xhci_halt(xhci);
5000 xhci_dbg(xhci, "Resetting HCD\n");
5001 /* Reset the internal HC memory state and registers. */
5002 retval = xhci_reset(xhci);
5005 xhci_dbg(xhci, "Reset complete\n");
5008 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5009 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5010 * address memory pointers actually. So, this driver clears the AC64
5011 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5012 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5014 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5015 xhci->hcc_params &= ~BIT(0);
5017 /* Set dma_mask and coherent_dma_mask to 64-bits,
5018 * if xHC supports 64-bit addressing */
5019 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5020 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5021 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5022 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5025 * This is to avoid error in cases where a 32-bit USB
5026 * controller is used on a 64-bit capable system.
5028 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5031 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5032 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5035 xhci_dbg(xhci, "Calling HCD init\n");
5036 /* Initialize HCD and host controller data structures. */
5037 retval = xhci_init(hcd);
5040 xhci_dbg(xhci, "Called HCD init\n");
5042 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
5043 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5047 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5049 static const struct hc_driver xhci_hc_driver = {
5050 .description = "xhci-hcd",
5051 .product_desc = "xHCI Host Controller",
5052 .hcd_priv_size = sizeof(struct xhci_hcd),
5055 * generic hardware linkage
5058 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
5061 * basic lifecycle operations
5063 .reset = NULL, /* set in xhci_init_driver() */
5066 .shutdown = xhci_shutdown,
5069 * managing i/o requests and associated device resources
5071 .urb_enqueue = xhci_urb_enqueue,
5072 .urb_dequeue = xhci_urb_dequeue,
5073 .alloc_dev = xhci_alloc_dev,
5074 .free_dev = xhci_free_dev,
5075 .alloc_streams = xhci_alloc_streams,
5076 .free_streams = xhci_free_streams,
5077 .add_endpoint = xhci_add_endpoint,
5078 .drop_endpoint = xhci_drop_endpoint,
5079 .endpoint_reset = xhci_endpoint_reset,
5080 .check_bandwidth = xhci_check_bandwidth,
5081 .reset_bandwidth = xhci_reset_bandwidth,
5082 .address_device = xhci_address_device,
5083 .enable_device = xhci_enable_device,
5084 .update_hub_device = xhci_update_hub_device,
5085 .reset_device = xhci_discover_or_reset_device,
5088 * scheduling support
5090 .get_frame_number = xhci_get_frame,
5095 .hub_control = xhci_hub_control,
5096 .hub_status_data = xhci_hub_status_data,
5097 .bus_suspend = xhci_bus_suspend,
5098 .bus_resume = xhci_bus_resume,
5101 * call back when device connected and addressed
5103 .update_device = xhci_update_device,
5104 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5105 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5106 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5107 .find_raw_port_number = xhci_find_raw_port_number,
5110 void xhci_init_driver(struct hc_driver *drv,
5111 const struct xhci_driver_overrides *over)
5115 /* Copy the generic table to drv then apply the overrides */
5116 *drv = xhci_hc_driver;
5119 drv->hcd_priv_size += over->extra_priv_size;
5121 drv->reset = over->reset;
5123 drv->start = over->start;
5126 EXPORT_SYMBOL_GPL(xhci_init_driver);
5128 MODULE_DESCRIPTION(DRIVER_DESC);
5129 MODULE_AUTHOR(DRIVER_AUTHOR);
5130 MODULE_LICENSE("GPL");
5132 static int __init xhci_hcd_init(void)
5135 * Check the compiler generated sizes of structures that must be laid
5136 * out in specific ways for hardware access.
5138 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5139 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5140 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5141 /* xhci_device_control has eight fields, and also
5142 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5144 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5145 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5146 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5147 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5148 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5149 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5150 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5159 * If an init function is provided, an exit function must also be provided
5160 * to allow module unload.
5162 static void __exit xhci_hcd_fini(void) { }
5164 module_init(xhci_hcd_init);
5165 module_exit(xhci_hcd_fini);