1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/slab.h>
18 #include <linux/dmi.h>
19 #include <linux/dma-mapping.h>
22 #include "xhci-trace.h"
24 #include "xhci-debugfs.h"
25 #include "xhci-dbgcap.h"
27 #define DRIVER_AUTHOR "Sarah Sharp"
28 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
32 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
33 static int link_quirk;
34 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
35 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
37 static unsigned long long quirks;
38 module_param(quirks, ullong, S_IRUGO);
39 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
41 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
43 struct xhci_segment *seg = ring->first_seg;
45 if (!td || !td->start_seg)
48 if (seg == td->start_seg)
51 } while (seg && seg != ring->first_seg);
57 * xhci_handshake - spin reading hc until handshake completes or fails
58 * @ptr: address of hc register to be read
59 * @mask: bits to look at in result of read
60 * @done: value of those bits when handshake succeeds
61 * @usec: timeout in microseconds
63 * Returns negative errno, or zero on success
65 * Success happens when the "mask" bits have the specified value (hardware
66 * handshake done). There are two failure modes: "usec" have passed (major
67 * hardware flakeout), or the register reads as all-ones (hardware removed).
69 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
74 ret = readl_poll_timeout_atomic(ptr, result,
75 (result & mask) == done ||
78 if (result == U32_MAX) /* card removed */
85 * Disable interrupts and begin the xHCI halting process.
87 void xhci_quiesce(struct xhci_hcd *xhci)
94 halted = readl(&xhci->op_regs->status) & STS_HALT;
98 cmd = readl(&xhci->op_regs->command);
100 writel(cmd, &xhci->op_regs->command);
104 * Force HC into halt state.
106 * Disable any IRQs and clear the run/stop bit.
107 * HC will complete any current and actively pipelined transactions, and
108 * should halt within 16 ms of the run/stop bit being cleared.
109 * Read HC Halted bit in the status register to see when the HC is finished.
111 int xhci_halt(struct xhci_hcd *xhci)
114 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
117 ret = xhci_handshake(&xhci->op_regs->status,
118 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
120 xhci_warn(xhci, "Host halt failed, %d\n", ret);
123 xhci->xhc_state |= XHCI_STATE_HALTED;
124 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
129 * Set the run bit and wait for the host to be running.
131 int xhci_start(struct xhci_hcd *xhci)
136 temp = readl(&xhci->op_regs->command);
138 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
140 writel(temp, &xhci->op_regs->command);
143 * Wait for the HCHalted Status bit to be 0 to indicate the host is
146 ret = xhci_handshake(&xhci->op_regs->status,
147 STS_HALT, 0, XHCI_MAX_HALT_USEC);
148 if (ret == -ETIMEDOUT)
149 xhci_err(xhci, "Host took too long to start, "
150 "waited %u microseconds.\n",
153 /* clear state flags. Including dying, halted or removing */
155 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
164 * This resets pipelines, timers, counters, state machines, etc.
165 * Transactions will be terminated immediately, and operational registers
166 * will be set to their defaults.
168 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
174 state = readl(&xhci->op_regs->status);
176 if (state == ~(u32)0) {
177 xhci_warn(xhci, "Host not accessible, reset failed.\n");
181 if ((state & STS_HALT) == 0) {
182 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
186 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
187 command = readl(&xhci->op_regs->command);
188 command |= CMD_RESET;
189 writel(command, &xhci->op_regs->command);
191 /* Existing Intel xHCI controllers require a delay of 1 mS,
192 * after setting the CMD_RESET bit, and before accessing any
193 * HC registers. This allows the HC to complete the
194 * reset operation and be ready for HC register access.
195 * Without this delay, the subsequent HC register access,
196 * may result in a system hang very rarely.
198 if (xhci->quirks & XHCI_INTEL_HOST)
201 ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
205 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
206 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
208 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
209 "Wait for controller to be ready for doorbell rings");
211 * xHCI cannot write to any doorbells or operational registers other
212 * than status until the "Controller Not Ready" flag is cleared.
214 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
216 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
217 xhci->usb2_rhub.bus_state.suspended_ports = 0;
218 xhci->usb2_rhub.bus_state.resuming_ports = 0;
219 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
220 xhci->usb3_rhub.bus_state.suspended_ports = 0;
221 xhci->usb3_rhub.bus_state.resuming_ports = 0;
226 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
228 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
234 * Some Renesas controllers get into a weird state if they are
235 * reset while programmed with 64bit addresses (they will preserve
236 * the top half of the address in internal, non visible
237 * registers). You end up with half the address coming from the
238 * kernel, and the other half coming from the firmware. Also,
239 * changing the programming leads to extra accesses even if the
240 * controller is supposed to be halted. The controller ends up with
241 * a fatal fault, and is then ripe for being properly reset.
243 * Special care is taken to only apply this if the device is behind
244 * an iommu. Doing anything when there is no iommu is definitely
247 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
250 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
252 /* Clear HSEIE so that faults do not get signaled */
253 val = readl(&xhci->op_regs->command);
255 writel(val, &xhci->op_regs->command);
257 /* Clear HSE (aka FATAL) */
258 val = readl(&xhci->op_regs->status);
260 writel(val, &xhci->op_regs->status);
262 /* Now zero the registers, and brace for impact */
263 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
264 if (upper_32_bits(val))
265 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
266 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
267 if (upper_32_bits(val))
268 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
270 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
271 ARRAY_SIZE(xhci->run_regs->ir_set));
273 for (i = 0; i < intrs; i++) {
274 struct xhci_intr_reg __iomem *ir;
276 ir = &xhci->run_regs->ir_set[i];
277 val = xhci_read_64(xhci, &ir->erst_base);
278 if (upper_32_bits(val))
279 xhci_write_64(xhci, 0, &ir->erst_base);
280 val= xhci_read_64(xhci, &ir->erst_dequeue);
281 if (upper_32_bits(val))
282 xhci_write_64(xhci, 0, &ir->erst_dequeue);
285 /* Wait for the fault to appear. It will be cleared on reset */
286 err = xhci_handshake(&xhci->op_regs->status,
287 STS_FATAL, STS_FATAL,
290 xhci_info(xhci, "Fault detected\n");
293 #ifdef CONFIG_USB_PCI
297 static int xhci_setup_msi(struct xhci_hcd *xhci)
301 * TODO:Check with MSI Soc for sysdev
303 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
305 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
307 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
308 "failed to allocate MSI entry");
312 ret = request_irq(pdev->irq, xhci_msi_irq,
313 0, "xhci_hcd", xhci_to_hcd(xhci));
315 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
316 "disable MSI interrupt");
317 pci_free_irq_vectors(pdev);
326 static int xhci_setup_msix(struct xhci_hcd *xhci)
329 struct usb_hcd *hcd = xhci_to_hcd(xhci);
330 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
333 * calculate number of msi-x vectors supported.
334 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
335 * with max number of interrupters based on the xhci HCSPARAMS1.
336 * - num_online_cpus: maximum msi-x vectors per CPUs core.
337 * Add additional 1 vector to ensure always available interrupt.
339 xhci->msix_count = min(num_online_cpus() + 1,
340 HCS_MAX_INTRS(xhci->hcs_params1));
342 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
345 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
346 "Failed to enable MSI-X");
350 for (i = 0; i < xhci->msix_count; i++) {
351 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
352 "xhci_hcd", xhci_to_hcd(xhci));
357 hcd->msix_enabled = 1;
361 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
363 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
364 pci_free_irq_vectors(pdev);
368 /* Free any IRQs and disable MSI-X */
369 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
371 struct usb_hcd *hcd = xhci_to_hcd(xhci);
372 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
374 if (xhci->quirks & XHCI_PLAT)
377 /* return if using legacy interrupt */
381 if (hcd->msix_enabled) {
384 for (i = 0; i < xhci->msix_count; i++)
385 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
387 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
390 pci_free_irq_vectors(pdev);
391 hcd->msix_enabled = 0;
394 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
396 struct usb_hcd *hcd = xhci_to_hcd(xhci);
398 if (hcd->msix_enabled) {
399 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
402 for (i = 0; i < xhci->msix_count; i++)
403 synchronize_irq(pci_irq_vector(pdev, i));
407 static int xhci_try_enable_msi(struct usb_hcd *hcd)
409 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
410 struct pci_dev *pdev;
413 /* The xhci platform device has set up IRQs through usb_add_hcd. */
414 if (xhci->quirks & XHCI_PLAT)
417 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
419 * Some Fresco Logic host controllers advertise MSI, but fail to
420 * generate interrupts. Don't even try to enable MSI.
422 if (xhci->quirks & XHCI_BROKEN_MSI)
425 /* unregister the legacy interrupt */
427 free_irq(hcd->irq, hcd);
430 ret = xhci_setup_msix(xhci);
432 /* fall back to msi*/
433 ret = xhci_setup_msi(xhci);
436 hcd->msi_enabled = 1;
441 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
446 if (!strlen(hcd->irq_descr))
447 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
448 hcd->driver->description, hcd->self.busnum);
450 /* fall back to legacy interrupt*/
451 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
452 hcd->irq_descr, hcd);
454 xhci_err(xhci, "request interrupt %d failed\n",
458 hcd->irq = pdev->irq;
464 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
469 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
473 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
479 static void compliance_mode_recovery(struct timer_list *t)
481 struct xhci_hcd *xhci;
483 struct xhci_hub *rhub;
487 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
488 rhub = &xhci->usb3_rhub;
490 for (i = 0; i < rhub->num_ports; i++) {
491 temp = readl(rhub->ports[i]->addr);
492 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
494 * Compliance Mode Detected. Letting USB Core
495 * handle the Warm Reset
497 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
498 "Compliance mode detected->port %d",
500 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
501 "Attempting compliance mode recovery");
502 hcd = xhci->shared_hcd;
504 if (hcd->state == HC_STATE_SUSPENDED)
505 usb_hcd_resume_root_hub(hcd);
507 usb_hcd_poll_rh_status(hcd);
511 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
512 mod_timer(&xhci->comp_mode_recovery_timer,
513 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
517 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
518 * that causes ports behind that hardware to enter compliance mode sometimes.
519 * The quirk creates a timer that polls every 2 seconds the link state of
520 * each host controller's port and recovers it by issuing a Warm reset
521 * if Compliance mode is detected, otherwise the port will become "dead" (no
522 * device connections or disconnections will be detected anymore). Becasue no
523 * status event is generated when entering compliance mode (per xhci spec),
524 * this quirk is needed on systems that have the failing hardware installed.
526 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
528 xhci->port_status_u0 = 0;
529 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
531 xhci->comp_mode_recovery_timer.expires = jiffies +
532 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
534 add_timer(&xhci->comp_mode_recovery_timer);
535 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
536 "Compliance mode recovery timer initialized");
540 * This function identifies the systems that have installed the SN65LVPE502CP
541 * USB3.0 re-driver and that need the Compliance Mode Quirk.
543 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
545 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
547 const char *dmi_product_name, *dmi_sys_vendor;
549 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
550 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
551 if (!dmi_product_name || !dmi_sys_vendor)
554 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
557 if (strstr(dmi_product_name, "Z420") ||
558 strstr(dmi_product_name, "Z620") ||
559 strstr(dmi_product_name, "Z820") ||
560 strstr(dmi_product_name, "Z1 Workstation"))
566 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
568 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
573 * Initialize memory for HCD and xHC (one-time init).
575 * Program the PAGESIZE register, initialize the device context array, create
576 * device contexts (?), set up a command ring segment (or two?), create event
577 * ring (one for now).
579 static int xhci_init(struct usb_hcd *hcd)
581 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
584 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
585 spin_lock_init(&xhci->lock);
586 if (xhci->hci_version == 0x95 && link_quirk) {
587 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
588 "QUIRK: Not clearing Link TRB chain bits.");
589 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
591 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
592 "xHCI doesn't need link TRB QUIRK");
594 retval = xhci_mem_init(xhci, GFP_KERNEL);
595 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
597 /* Initializing Compliance Mode Recovery Data If Needed */
598 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
599 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
600 compliance_mode_recovery_timer_init(xhci);
606 /*-------------------------------------------------------------------------*/
609 static int xhci_run_finished(struct xhci_hcd *xhci)
611 if (xhci_start(xhci)) {
615 xhci->shared_hcd->state = HC_STATE_RUNNING;
616 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
618 if (xhci->quirks & XHCI_NEC_HOST)
619 xhci_ring_cmd_db(xhci);
621 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
622 "Finished xhci_run for USB3 roothub");
627 * Start the HC after it was halted.
629 * This function is called by the USB core when the HC driver is added.
630 * Its opposite is xhci_stop().
632 * xhci_init() must be called once before this function can be called.
633 * Reset the HC, enable device slot contexts, program DCBAAP, and
634 * set command ring pointer and event ring pointer.
636 * Setup MSI-X vectors and enable interrupts.
638 int xhci_run(struct usb_hcd *hcd)
643 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
645 /* Start the xHCI host controller running only after the USB 2.0 roothub
649 hcd->uses_new_polling = 1;
650 if (!usb_hcd_is_primary_hcd(hcd))
651 return xhci_run_finished(xhci);
653 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
655 ret = xhci_try_enable_msi(hcd);
659 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
660 temp_64 &= ~ERST_PTR_MASK;
661 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
662 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
664 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
665 "// Set the interrupt modulation register");
666 temp = readl(&xhci->ir_set->irq_control);
667 temp &= ~ER_IRQ_INTERVAL_MASK;
668 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
669 writel(temp, &xhci->ir_set->irq_control);
671 /* Set the HCD state before we enable the irqs */
672 temp = readl(&xhci->op_regs->command);
674 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
675 "// Enable interrupts, cmd = 0x%x.", temp);
676 writel(temp, &xhci->op_regs->command);
678 temp = readl(&xhci->ir_set->irq_pending);
679 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
680 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
681 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
682 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
684 if (xhci->quirks & XHCI_NEC_HOST) {
685 struct xhci_command *command;
687 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
691 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
692 TRB_TYPE(TRB_NEC_GET_FW));
694 xhci_free_command(xhci, command);
696 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
697 "Finished xhci_run for USB2 roothub");
701 xhci_debugfs_init(xhci);
705 EXPORT_SYMBOL_GPL(xhci_run);
710 * This function is called by the USB core when the HC driver is removed.
711 * Its opposite is xhci_run().
713 * Disable device contexts, disable IRQs, and quiesce the HC.
714 * Reset the HC, finish any completed transactions, and cleanup memory.
716 static void xhci_stop(struct usb_hcd *hcd)
719 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
721 mutex_lock(&xhci->mutex);
723 /* Only halt host and free memory after both hcds are removed */
724 if (!usb_hcd_is_primary_hcd(hcd)) {
725 mutex_unlock(&xhci->mutex);
731 spin_lock_irq(&xhci->lock);
732 xhci->xhc_state |= XHCI_STATE_HALTED;
733 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
735 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
736 spin_unlock_irq(&xhci->lock);
738 xhci_cleanup_msix(xhci);
740 /* Deleting Compliance Mode Recovery Timer */
741 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
742 (!(xhci_all_ports_seen_u0(xhci)))) {
743 del_timer_sync(&xhci->comp_mode_recovery_timer);
744 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
745 "%s: compliance mode recovery timer deleted",
749 if (xhci->quirks & XHCI_AMD_PLL_FIX)
752 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
753 "// Disabling event ring interrupts");
754 temp = readl(&xhci->op_regs->status);
755 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
756 temp = readl(&xhci->ir_set->irq_pending);
757 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
759 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
760 xhci_mem_cleanup(xhci);
761 xhci_debugfs_exit(xhci);
762 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
763 "xhci_stop completed - status = %x",
764 readl(&xhci->op_regs->status));
765 mutex_unlock(&xhci->mutex);
769 * Shutdown HC (not bus-specific)
771 * This is called when the machine is rebooting or halting. We assume that the
772 * machine will be powered off, and the HC's internal state will be reset.
773 * Don't bother to free memory.
775 * This will only ever be called with the main usb_hcd (the USB3 roothub).
777 void xhci_shutdown(struct usb_hcd *hcd)
779 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
781 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
782 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
784 /* Don't poll the roothubs after shutdown. */
785 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
786 __func__, hcd->self.busnum);
787 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
788 del_timer_sync(&hcd->rh_timer);
790 if (xhci->shared_hcd) {
791 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
792 del_timer_sync(&xhci->shared_hcd->rh_timer);
795 spin_lock_irq(&xhci->lock);
799 * Workaround for spurious wakeps at shutdown with HSW, and for boot
800 * firmware delay in ADL-P PCH if port are left in U3 at shutdown
802 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
803 xhci->quirks & XHCI_RESET_TO_DEFAULT)
804 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
806 spin_unlock_irq(&xhci->lock);
808 xhci_cleanup_msix(xhci);
810 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
811 "xhci_shutdown completed - status = %x",
812 readl(&xhci->op_regs->status));
814 EXPORT_SYMBOL_GPL(xhci_shutdown);
817 static void xhci_save_registers(struct xhci_hcd *xhci)
819 xhci->s3.command = readl(&xhci->op_regs->command);
820 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
821 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
822 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
823 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
824 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
825 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
826 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
827 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
830 static void xhci_restore_registers(struct xhci_hcd *xhci)
832 writel(xhci->s3.command, &xhci->op_regs->command);
833 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
834 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
835 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
836 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
837 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
838 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
839 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
840 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
843 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
847 /* step 2: initialize command ring buffer */
848 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
849 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
850 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
851 xhci->cmd_ring->dequeue) &
852 (u64) ~CMD_RING_RSVD_BITS) |
853 xhci->cmd_ring->cycle_state;
854 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
855 "// Setting command ring address to 0x%llx",
856 (long unsigned long) val_64);
857 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
861 * The whole command ring must be cleared to zero when we suspend the host.
863 * The host doesn't save the command ring pointer in the suspend well, so we
864 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
865 * aligned, because of the reserved bits in the command ring dequeue pointer
866 * register. Therefore, we can't just set the dequeue pointer back in the
867 * middle of the ring (TRBs are 16-byte aligned).
869 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
871 struct xhci_ring *ring;
872 struct xhci_segment *seg;
874 ring = xhci->cmd_ring;
878 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
879 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
880 cpu_to_le32(~TRB_CYCLE);
882 } while (seg != ring->deq_seg);
884 /* Reset the software enqueue and dequeue pointers */
885 ring->deq_seg = ring->first_seg;
886 ring->dequeue = ring->first_seg->trbs;
887 ring->enq_seg = ring->deq_seg;
888 ring->enqueue = ring->dequeue;
890 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
892 * Ring is now zeroed, so the HW should look for change of ownership
893 * when the cycle bit is set to 1.
895 ring->cycle_state = 1;
898 * Reset the hardware dequeue pointer.
899 * Yes, this will need to be re-written after resume, but we're paranoid
900 * and want to make sure the hardware doesn't access bogus memory
901 * because, say, the BIOS or an SMI started the host without changing
902 * the command ring pointers.
904 xhci_set_cmd_ring_deq(xhci);
908 * Disable port wake bits if do_wakeup is not set.
910 * Also clear a possible internal port wake state left hanging for ports that
911 * detected termination but never successfully enumerated (trained to 0U).
912 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
913 * at enumeration clears this wake, force one here as well for unconnected ports
916 static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
917 struct xhci_hub *rhub,
924 spin_lock_irqsave(&xhci->lock, flags);
926 for (i = 0; i < rhub->num_ports; i++) {
927 portsc = readl(rhub->ports[i]->addr);
928 t1 = xhci_port_state_to_neutral(portsc);
931 /* clear wake bits if do_wake is not set */
933 t2 &= ~PORT_WAKE_BITS;
935 /* Don't touch csc bit if connected or connect change is set */
936 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
940 writel(t2, rhub->ports[i]->addr);
941 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
942 rhub->hcd->self.busnum, i + 1, portsc, t2);
945 spin_unlock_irqrestore(&xhci->lock, flags);
948 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
950 struct xhci_port **ports;
955 status = readl(&xhci->op_regs->status);
956 if (status & STS_EINT)
959 * Checking STS_EINT is not enough as there is a lag between a change
960 * bit being set and the Port Status Change Event that it generated
961 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
964 port_index = xhci->usb2_rhub.num_ports;
965 ports = xhci->usb2_rhub.ports;
966 while (port_index--) {
967 portsc = readl(ports[port_index]->addr);
968 if (portsc & PORT_CHANGE_MASK ||
969 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
972 port_index = xhci->usb3_rhub.num_ports;
973 ports = xhci->usb3_rhub.ports;
974 while (port_index--) {
975 portsc = readl(ports[port_index]->addr);
976 if (portsc & PORT_CHANGE_MASK ||
977 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
984 * Stop HC (not bus-specific)
986 * This is called when the machine transition into S3/S4 mode.
989 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
992 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
993 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1000 if (hcd->state != HC_STATE_SUSPENDED ||
1001 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
1004 /* Clear root port wake on bits if wakeup not allowed. */
1005 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
1006 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
1008 if (!HCD_HW_ACCESSIBLE(hcd))
1011 xhci_dbc_suspend(xhci);
1013 /* Don't poll the roothubs on bus suspend. */
1014 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1015 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1016 del_timer_sync(&hcd->rh_timer);
1017 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1018 del_timer_sync(&xhci->shared_hcd->rh_timer);
1020 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1021 usleep_range(1000, 1500);
1023 spin_lock_irq(&xhci->lock);
1024 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1025 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1026 /* step 1: stop endpoint */
1027 /* skipped assuming that port suspend has done */
1029 /* step 2: clear Run/Stop bit */
1030 command = readl(&xhci->op_regs->command);
1031 command &= ~CMD_RUN;
1032 writel(command, &xhci->op_regs->command);
1034 /* Some chips from Fresco Logic need an extraordinary delay */
1035 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1037 if (xhci_handshake(&xhci->op_regs->status,
1038 STS_HALT, STS_HALT, delay)) {
1039 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1040 spin_unlock_irq(&xhci->lock);
1043 xhci_clear_command_ring(xhci);
1045 /* step 3: save registers */
1046 xhci_save_registers(xhci);
1048 /* step 4: set CSS flag */
1049 command = readl(&xhci->op_regs->command);
1051 writel(command, &xhci->op_regs->command);
1052 xhci->broken_suspend = 0;
1053 if (xhci_handshake(&xhci->op_regs->status,
1054 STS_SAVE, 0, 20 * 1000)) {
1056 * AMD SNPS xHC 3.0 occasionally does not clear the
1057 * SSS bit of USBSTS and when driver tries to poll
1058 * to see if the xHC clears BIT(8) which never happens
1059 * and driver assumes that controller is not responding
1060 * and times out. To workaround this, its good to check
1061 * if SRE and HCE bits are not set (as per xhci
1062 * Section 5.4.2) and bypass the timeout.
1064 res = readl(&xhci->op_regs->status);
1065 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1066 (((res & STS_SRE) == 0) &&
1067 ((res & STS_HCE) == 0))) {
1068 xhci->broken_suspend = 1;
1070 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1071 spin_unlock_irq(&xhci->lock);
1075 spin_unlock_irq(&xhci->lock);
1078 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1079 * is about to be suspended.
1081 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1082 (!(xhci_all_ports_seen_u0(xhci)))) {
1083 del_timer_sync(&xhci->comp_mode_recovery_timer);
1084 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1085 "%s: compliance mode recovery timer deleted",
1089 /* step 5: remove core well power */
1090 /* synchronize irq when using MSI-X */
1091 xhci_msix_sync_irqs(xhci);
1095 EXPORT_SYMBOL_GPL(xhci_suspend);
1098 * start xHC (not bus-specific)
1100 * This is called when the machine transition from S3/S4 mode.
1103 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1105 u32 command, temp = 0;
1106 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1107 struct usb_hcd *secondary_hcd;
1109 bool comp_timer_running = false;
1110 bool pending_portevent = false;
1111 bool reinit_xhc = false;
1116 /* Wait a bit if either of the roothubs need to settle from the
1117 * transition into bus suspend.
1120 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1121 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1124 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1125 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1127 spin_lock_irq(&xhci->lock);
1129 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1134 * Some controllers might lose power during suspend, so wait
1135 * for controller not ready bit to clear, just as in xHC init.
1137 retval = xhci_handshake(&xhci->op_regs->status,
1138 STS_CNR, 0, 10 * 1000 * 1000);
1140 xhci_warn(xhci, "Controller not ready at resume %d\n",
1142 spin_unlock_irq(&xhci->lock);
1145 /* step 1: restore register */
1146 xhci_restore_registers(xhci);
1147 /* step 2: initialize command ring buffer */
1148 xhci_set_cmd_ring_deq(xhci);
1149 /* step 3: restore state and start state*/
1150 /* step 3: set CRS flag */
1151 command = readl(&xhci->op_regs->command);
1153 writel(command, &xhci->op_regs->command);
1155 * Some controllers take up to 55+ ms to complete the controller
1156 * restore so setting the timeout to 100ms. Xhci specification
1157 * doesn't mention any timeout value.
1159 if (xhci_handshake(&xhci->op_regs->status,
1160 STS_RESTORE, 0, 100 * 1000)) {
1161 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1162 spin_unlock_irq(&xhci->lock);
1167 temp = readl(&xhci->op_regs->status);
1169 /* re-initialize the HC on Restore Error, or Host Controller Error */
1170 if (temp & (STS_SRE | STS_HCE)) {
1172 if (!xhci->broken_suspend)
1173 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1177 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1178 !(xhci_all_ports_seen_u0(xhci))) {
1179 del_timer_sync(&xhci->comp_mode_recovery_timer);
1180 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1181 "Compliance Mode Recovery Timer deleted!");
1184 /* Let the USB core know _both_ roothubs lost power. */
1185 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1186 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1188 xhci_dbg(xhci, "Stop HCD\n");
1190 xhci_zero_64b_regs(xhci);
1191 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1192 spin_unlock_irq(&xhci->lock);
1195 xhci_cleanup_msix(xhci);
1197 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1198 temp = readl(&xhci->op_regs->status);
1199 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1200 temp = readl(&xhci->ir_set->irq_pending);
1201 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1203 xhci_dbg(xhci, "cleaning up memory\n");
1204 xhci_mem_cleanup(xhci);
1205 xhci_debugfs_exit(xhci);
1206 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1207 readl(&xhci->op_regs->status));
1209 /* USB core calls the PCI reinit and start functions twice:
1210 * first with the primary HCD, and then with the secondary HCD.
1211 * If we don't do the same, the host will never be started.
1213 if (!usb_hcd_is_primary_hcd(hcd))
1214 secondary_hcd = hcd;
1216 secondary_hcd = xhci->shared_hcd;
1218 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1219 retval = xhci_init(hcd->primary_hcd);
1222 comp_timer_running = true;
1224 xhci_dbg(xhci, "Start the primary HCD\n");
1225 retval = xhci_run(hcd->primary_hcd);
1227 xhci_dbg(xhci, "Start the secondary HCD\n");
1228 retval = xhci_run(secondary_hcd);
1230 hcd->state = HC_STATE_SUSPENDED;
1231 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1235 /* step 4: set Run/Stop bit */
1236 command = readl(&xhci->op_regs->command);
1238 writel(command, &xhci->op_regs->command);
1239 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1242 /* step 5: walk topology and initialize portsc,
1243 * portpmsc and portli
1245 /* this is done in bus_resume */
1247 /* step 6: restart each of the previously
1248 * Running endpoints by ringing their doorbells
1251 spin_unlock_irq(&xhci->lock);
1253 xhci_dbc_resume(xhci);
1258 * Resume roothubs only if there are pending events.
1259 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1260 * the first wake signalling failed, give it that chance.
1262 pending_portevent = xhci_pending_portevent(xhci);
1263 if (!pending_portevent) {
1265 pending_portevent = xhci_pending_portevent(xhci);
1268 if (pending_portevent) {
1269 usb_hcd_resume_root_hub(xhci->shared_hcd);
1270 usb_hcd_resume_root_hub(hcd);
1274 * If system is subject to the Quirk, Compliance Mode Timer needs to
1275 * be re-initialized Always after a system resume. Ports are subject
1276 * to suffer the Compliance Mode issue again. It doesn't matter if
1277 * ports have entered previously to U0 before system's suspension.
1279 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1280 compliance_mode_recovery_timer_init(xhci);
1282 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1283 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1285 /* Re-enable port polling. */
1286 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1287 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1288 usb_hcd_poll_rh_status(xhci->shared_hcd);
1289 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1290 usb_hcd_poll_rh_status(hcd);
1294 EXPORT_SYMBOL_GPL(xhci_resume);
1295 #endif /* CONFIG_PM */
1297 /*-------------------------------------------------------------------------*/
1300 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1301 * we'll copy the actual data into the TRB address register. This is limited to
1302 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1303 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1305 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1308 if (xhci_urb_suitable_for_idt(urb))
1311 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1315 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1316 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1317 * value to right shift 1 for the bitmask.
1319 * Index = (epnum * 2) + direction - 1,
1320 * where direction = 0 for OUT, 1 for IN.
1321 * For control endpoints, the IN index is used (OUT index is unused), so
1322 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1324 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1327 if (usb_endpoint_xfer_control(desc))
1328 index = (unsigned int) (usb_endpoint_num(desc)*2);
1330 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1331 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1335 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1336 * address from the XHCI endpoint index.
1338 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1340 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1341 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1342 return direction | number;
1345 /* Find the flag for this endpoint (for use in the control context). Use the
1346 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1349 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1351 return 1 << (xhci_get_endpoint_index(desc) + 1);
1354 /* Find the flag for this endpoint (for use in the control context). Use the
1355 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1358 static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1360 return 1 << (ep_index + 1);
1363 /* Compute the last valid endpoint context index. Basically, this is the
1364 * endpoint index plus one. For slot contexts with more than valid endpoint,
1365 * we find the most significant bit set in the added contexts flags.
1366 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1367 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1369 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1371 return fls(added_ctxs) - 1;
1374 /* Returns 1 if the arguments are OK;
1375 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1377 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1378 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1380 struct xhci_hcd *xhci;
1381 struct xhci_virt_device *virt_dev;
1383 if (!hcd || (check_ep && !ep) || !udev) {
1384 pr_debug("xHCI %s called with invalid args\n", func);
1387 if (!udev->parent) {
1388 pr_debug("xHCI %s called for root hub\n", func);
1392 xhci = hcd_to_xhci(hcd);
1393 if (check_virt_dev) {
1394 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1395 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1400 virt_dev = xhci->devs[udev->slot_id];
1401 if (virt_dev->udev != udev) {
1402 xhci_dbg(xhci, "xHCI %s called with udev and "
1403 "virt_dev does not match\n", func);
1408 if (xhci->xhc_state & XHCI_STATE_HALTED)
1414 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1415 struct usb_device *udev, struct xhci_command *command,
1416 bool ctx_change, bool must_succeed);
1419 * Full speed devices may have a max packet size greater than 8 bytes, but the
1420 * USB core doesn't know that until it reads the first 8 bytes of the
1421 * descriptor. If the usb_device's max packet size changes after that point,
1422 * we need to issue an evaluate context command and wait on it.
1424 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1425 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1427 struct xhci_container_ctx *out_ctx;
1428 struct xhci_input_control_ctx *ctrl_ctx;
1429 struct xhci_ep_ctx *ep_ctx;
1430 struct xhci_command *command;
1431 int max_packet_size;
1432 int hw_max_packet_size;
1435 out_ctx = xhci->devs[slot_id]->out_ctx;
1436 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1437 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1438 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1439 if (hw_max_packet_size != max_packet_size) {
1440 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1441 "Max Packet Size for ep 0 changed.");
1442 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1443 "Max packet size in usb_device = %d",
1445 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1446 "Max packet size in xHCI HW = %d",
1447 hw_max_packet_size);
1448 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1449 "Issuing evaluate context command.");
1451 /* Set up the input context flags for the command */
1452 /* FIXME: This won't work if a non-default control endpoint
1453 * changes max packet sizes.
1456 command = xhci_alloc_command(xhci, true, mem_flags);
1460 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1461 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1463 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1466 goto command_cleanup;
1468 /* Set up the modified control endpoint 0 */
1469 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1470 xhci->devs[slot_id]->out_ctx, ep_index);
1472 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1473 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1474 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1475 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1477 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1478 ctrl_ctx->drop_flags = 0;
1480 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1483 /* Clean up the input context for later use by bandwidth
1486 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1488 kfree(command->completion);
1495 * non-error returns are a promise to giveback() the urb later
1496 * we drop ownership so next owner (or urb unlink) can get it
1498 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1500 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1501 unsigned long flags;
1503 unsigned int slot_id, ep_index;
1504 unsigned int *ep_state;
1505 struct urb_priv *urb_priv;
1510 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1511 true, true, __func__);
1513 return ret ? ret : -EINVAL;
1515 slot_id = urb->dev->slot_id;
1516 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1517 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1519 if (!HCD_HW_ACCESSIBLE(hcd)) {
1520 if (!in_interrupt())
1521 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1524 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1525 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1529 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1530 num_tds = urb->number_of_packets;
1531 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1532 urb->transfer_buffer_length > 0 &&
1533 urb->transfer_flags & URB_ZERO_PACKET &&
1534 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1539 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1543 urb_priv->num_tds = num_tds;
1544 urb_priv->num_tds_done = 0;
1545 urb->hcpriv = urb_priv;
1547 trace_xhci_urb_enqueue(urb);
1549 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1550 /* Check to see if the max packet size for the default control
1551 * endpoint changed during FS device enumeration
1553 if (urb->dev->speed == USB_SPEED_FULL) {
1554 ret = xhci_check_maxpacket(xhci, slot_id,
1555 ep_index, urb, mem_flags);
1557 xhci_urb_free_priv(urb_priv);
1564 spin_lock_irqsave(&xhci->lock, flags);
1566 if (xhci->xhc_state & XHCI_STATE_DYING) {
1567 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1568 urb->ep->desc.bEndpointAddress, urb);
1572 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1573 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1578 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1579 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1584 switch (usb_endpoint_type(&urb->ep->desc)) {
1586 case USB_ENDPOINT_XFER_CONTROL:
1587 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1590 case USB_ENDPOINT_XFER_BULK:
1591 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1594 case USB_ENDPOINT_XFER_INT:
1595 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1598 case USB_ENDPOINT_XFER_ISOC:
1599 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1605 xhci_urb_free_priv(urb_priv);
1608 spin_unlock_irqrestore(&xhci->lock, flags);
1613 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1614 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1615 * should pick up where it left off in the TD, unless a Set Transfer Ring
1616 * Dequeue Pointer is issued.
1618 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1619 * the ring. Since the ring is a contiguous structure, they can't be physically
1620 * removed. Instead, there are two options:
1622 * 1) If the HC is in the middle of processing the URB to be canceled, we
1623 * simply move the ring's dequeue pointer past those TRBs using the Set
1624 * Transfer Ring Dequeue Pointer command. This will be the common case,
1625 * when drivers timeout on the last submitted URB and attempt to cancel.
1627 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1628 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1629 * HC will need to invalidate the any TRBs it has cached after the stop
1630 * endpoint command, as noted in the xHCI 0.95 errata.
1632 * 3) The TD may have completed by the time the Stop Endpoint Command
1633 * completes, so software needs to handle that case too.
1635 * This function should protect against the TD enqueueing code ringing the
1636 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1637 * It also needs to account for multiple cancellations on happening at the same
1638 * time for the same endpoint.
1640 * Note that this function can be called in any context, or so says
1641 * usb_hcd_unlink_urb()
1643 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1645 unsigned long flags;
1648 struct xhci_hcd *xhci;
1649 struct urb_priv *urb_priv;
1651 unsigned int ep_index;
1652 struct xhci_ring *ep_ring;
1653 struct xhci_virt_ep *ep;
1654 struct xhci_command *command;
1655 struct xhci_virt_device *vdev;
1657 xhci = hcd_to_xhci(hcd);
1658 spin_lock_irqsave(&xhci->lock, flags);
1660 trace_xhci_urb_dequeue(urb);
1662 /* Make sure the URB hasn't completed or been unlinked already */
1663 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1667 /* give back URB now if we can't queue it for cancel */
1668 vdev = xhci->devs[urb->dev->slot_id];
1669 urb_priv = urb->hcpriv;
1670 if (!vdev || !urb_priv)
1673 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1674 ep = &vdev->eps[ep_index];
1675 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1676 if (!ep || !ep_ring)
1679 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1680 temp = readl(&xhci->op_regs->status);
1681 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1687 * check ring is not re-allocated since URB was enqueued. If it is, then
1688 * make sure none of the ring related pointers in this URB private data
1689 * are touched, such as td_list, otherwise we overwrite freed data
1691 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1692 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1693 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1694 td = &urb_priv->td[i];
1695 if (!list_empty(&td->cancelled_td_list))
1696 list_del_init(&td->cancelled_td_list);
1701 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1702 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1703 "HC halted, freeing TD manually.");
1704 for (i = urb_priv->num_tds_done;
1705 i < urb_priv->num_tds;
1707 td = &urb_priv->td[i];
1708 if (!list_empty(&td->td_list))
1709 list_del_init(&td->td_list);
1710 if (!list_empty(&td->cancelled_td_list))
1711 list_del_init(&td->cancelled_td_list);
1716 i = urb_priv->num_tds_done;
1717 if (i < urb_priv->num_tds)
1718 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1719 "Cancel URB %p, dev %s, ep 0x%x, "
1720 "starting at offset 0x%llx",
1721 urb, urb->dev->devpath,
1722 urb->ep->desc.bEndpointAddress,
1723 (unsigned long long) xhci_trb_virt_to_dma(
1724 urb_priv->td[i].start_seg,
1725 urb_priv->td[i].first_trb));
1727 for (; i < urb_priv->num_tds; i++) {
1728 td = &urb_priv->td[i];
1729 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1732 /* Queue a stop endpoint command, but only if this is
1733 * the first cancellation to be handled.
1735 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1736 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1741 ep->ep_state |= EP_STOP_CMD_PENDING;
1742 ep->stop_cmd_timer.expires = jiffies +
1743 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1744 add_timer(&ep->stop_cmd_timer);
1745 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1747 xhci_ring_cmd_db(xhci);
1750 spin_unlock_irqrestore(&xhci->lock, flags);
1755 xhci_urb_free_priv(urb_priv);
1756 usb_hcd_unlink_urb_from_ep(hcd, urb);
1757 spin_unlock_irqrestore(&xhci->lock, flags);
1758 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1762 /* Drop an endpoint from a new bandwidth configuration for this device.
1763 * Only one call to this function is allowed per endpoint before
1764 * check_bandwidth() or reset_bandwidth() must be called.
1765 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1766 * add the endpoint to the schedule with possibly new parameters denoted by a
1767 * different endpoint descriptor in usb_host_endpoint.
1768 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1771 * The USB core will not allow URBs to be queued to an endpoint that is being
1772 * disabled, so there's no need for mutual exclusion to protect
1773 * the xhci->devs[slot_id] structure.
1775 static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1776 struct usb_host_endpoint *ep)
1778 struct xhci_hcd *xhci;
1779 struct xhci_container_ctx *in_ctx, *out_ctx;
1780 struct xhci_input_control_ctx *ctrl_ctx;
1781 unsigned int ep_index;
1782 struct xhci_ep_ctx *ep_ctx;
1784 u32 new_add_flags, new_drop_flags;
1787 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1790 xhci = hcd_to_xhci(hcd);
1791 if (xhci->xhc_state & XHCI_STATE_DYING)
1794 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1795 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1796 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1797 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1798 __func__, drop_flag);
1802 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1803 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1804 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1806 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1811 ep_index = xhci_get_endpoint_index(&ep->desc);
1812 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1813 /* If the HC already knows the endpoint is disabled,
1814 * or the HCD has noted it is disabled, ignore this request
1816 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1817 le32_to_cpu(ctrl_ctx->drop_flags) &
1818 xhci_get_endpoint_flag(&ep->desc)) {
1819 /* Do not warn when called after a usb_device_reset */
1820 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1821 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1826 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1827 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1829 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1830 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1832 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1834 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1836 if (xhci->quirks & XHCI_MTK_HOST)
1837 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1839 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1840 (unsigned int) ep->desc.bEndpointAddress,
1842 (unsigned int) new_drop_flags,
1843 (unsigned int) new_add_flags);
1847 /* Add an endpoint to a new possible bandwidth configuration for this device.
1848 * Only one call to this function is allowed per endpoint before
1849 * check_bandwidth() or reset_bandwidth() must be called.
1850 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1851 * add the endpoint to the schedule with possibly new parameters denoted by a
1852 * different endpoint descriptor in usb_host_endpoint.
1853 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1856 * The USB core will not allow URBs to be queued to an endpoint until the
1857 * configuration or alt setting is installed in the device, so there's no need
1858 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1860 static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1861 struct usb_host_endpoint *ep)
1863 struct xhci_hcd *xhci;
1864 struct xhci_container_ctx *in_ctx;
1865 unsigned int ep_index;
1866 struct xhci_input_control_ctx *ctrl_ctx;
1867 struct xhci_ep_ctx *ep_ctx;
1869 u32 new_add_flags, new_drop_flags;
1870 struct xhci_virt_device *virt_dev;
1873 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1875 /* So we won't queue a reset ep command for a root hub */
1879 xhci = hcd_to_xhci(hcd);
1880 if (xhci->xhc_state & XHCI_STATE_DYING)
1883 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1884 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1885 /* FIXME when we have to issue an evaluate endpoint command to
1886 * deal with ep0 max packet size changing once we get the
1889 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1890 __func__, added_ctxs);
1894 virt_dev = xhci->devs[udev->slot_id];
1895 in_ctx = virt_dev->in_ctx;
1896 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1898 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1903 ep_index = xhci_get_endpoint_index(&ep->desc);
1904 /* If this endpoint is already in use, and the upper layers are trying
1905 * to add it again without dropping it, reject the addition.
1907 if (virt_dev->eps[ep_index].ring &&
1908 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1909 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1910 "without dropping it.\n",
1911 (unsigned int) ep->desc.bEndpointAddress);
1915 /* If the HCD has already noted the endpoint is enabled,
1916 * ignore this request.
1918 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1919 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1925 * Configuration and alternate setting changes must be done in
1926 * process context, not interrupt context (or so documenation
1927 * for usb_set_interface() and usb_set_configuration() claim).
1929 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1930 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1931 __func__, ep->desc.bEndpointAddress);
1935 if (xhci->quirks & XHCI_MTK_HOST) {
1936 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1938 xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring);
1939 virt_dev->eps[ep_index].new_ring = NULL;
1944 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1945 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1947 /* If xhci_endpoint_disable() was called for this endpoint, but the
1948 * xHC hasn't been notified yet through the check_bandwidth() call,
1949 * this re-adds a new state for the endpoint from the new endpoint
1950 * descriptors. We must drop and re-add this endpoint, so we leave the
1953 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1955 /* Store the usb_device pointer for later use */
1958 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1959 trace_xhci_add_endpoint(ep_ctx);
1961 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1962 (unsigned int) ep->desc.bEndpointAddress,
1964 (unsigned int) new_drop_flags,
1965 (unsigned int) new_add_flags);
1969 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1971 struct xhci_input_control_ctx *ctrl_ctx;
1972 struct xhci_ep_ctx *ep_ctx;
1973 struct xhci_slot_ctx *slot_ctx;
1976 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1978 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1983 /* When a device's add flag and drop flag are zero, any subsequent
1984 * configure endpoint command will leave that endpoint's state
1985 * untouched. Make sure we don't leave any old state in the input
1986 * endpoint contexts.
1988 ctrl_ctx->drop_flags = 0;
1989 ctrl_ctx->add_flags = 0;
1990 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1991 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1992 /* Endpoint 0 is always valid */
1993 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1994 for (i = 1; i < 31; i++) {
1995 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1996 ep_ctx->ep_info = 0;
1997 ep_ctx->ep_info2 = 0;
1999 ep_ctx->tx_info = 0;
2003 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2004 struct usb_device *udev, u32 *cmd_status)
2008 switch (*cmd_status) {
2009 case COMP_COMMAND_ABORTED:
2010 case COMP_COMMAND_RING_STOPPED:
2011 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2014 case COMP_RESOURCE_ERROR:
2015 dev_warn(&udev->dev,
2016 "Not enough host controller resources for new device state.\n");
2018 /* FIXME: can we allocate more resources for the HC? */
2020 case COMP_BANDWIDTH_ERROR:
2021 case COMP_SECONDARY_BANDWIDTH_ERROR:
2022 dev_warn(&udev->dev,
2023 "Not enough bandwidth for new device state.\n");
2025 /* FIXME: can we go back to the old state? */
2027 case COMP_TRB_ERROR:
2028 /* the HCD set up something wrong */
2029 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2031 "and endpoint is not disabled.\n");
2034 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2035 dev_warn(&udev->dev,
2036 "ERROR: Incompatible device for endpoint configure command.\n");
2040 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2041 "Successful Endpoint Configure command");
2045 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2053 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2054 struct usb_device *udev, u32 *cmd_status)
2058 switch (*cmd_status) {
2059 case COMP_COMMAND_ABORTED:
2060 case COMP_COMMAND_RING_STOPPED:
2061 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2064 case COMP_PARAMETER_ERROR:
2065 dev_warn(&udev->dev,
2066 "WARN: xHCI driver setup invalid evaluate context command.\n");
2069 case COMP_SLOT_NOT_ENABLED_ERROR:
2070 dev_warn(&udev->dev,
2071 "WARN: slot not enabled for evaluate context command.\n");
2074 case COMP_CONTEXT_STATE_ERROR:
2075 dev_warn(&udev->dev,
2076 "WARN: invalid context state for evaluate context command.\n");
2079 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2080 dev_warn(&udev->dev,
2081 "ERROR: Incompatible device for evaluate context command.\n");
2084 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2085 /* Max Exit Latency too large error */
2086 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2090 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2091 "Successful evaluate context command");
2095 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2103 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2104 struct xhci_input_control_ctx *ctrl_ctx)
2106 u32 valid_add_flags;
2107 u32 valid_drop_flags;
2109 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2110 * (bit 1). The default control endpoint is added during the Address
2111 * Device command and is never removed until the slot is disabled.
2113 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2114 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2116 /* Use hweight32 to count the number of ones in the add flags, or
2117 * number of endpoints added. Don't count endpoints that are changed
2118 * (both added and dropped).
2120 return hweight32(valid_add_flags) -
2121 hweight32(valid_add_flags & valid_drop_flags);
2124 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2125 struct xhci_input_control_ctx *ctrl_ctx)
2127 u32 valid_add_flags;
2128 u32 valid_drop_flags;
2130 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2131 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2133 return hweight32(valid_drop_flags) -
2134 hweight32(valid_add_flags & valid_drop_flags);
2138 * We need to reserve the new number of endpoints before the configure endpoint
2139 * command completes. We can't subtract the dropped endpoints from the number
2140 * of active endpoints until the command completes because we can oversubscribe
2141 * the host in this case:
2143 * - the first configure endpoint command drops more endpoints than it adds
2144 * - a second configure endpoint command that adds more endpoints is queued
2145 * - the first configure endpoint command fails, so the config is unchanged
2146 * - the second command may succeed, even though there isn't enough resources
2148 * Must be called with xhci->lock held.
2150 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2151 struct xhci_input_control_ctx *ctrl_ctx)
2155 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2156 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2157 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2158 "Not enough ep ctxs: "
2159 "%u active, need to add %u, limit is %u.",
2160 xhci->num_active_eps, added_eps,
2161 xhci->limit_active_eps);
2164 xhci->num_active_eps += added_eps;
2165 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2166 "Adding %u ep ctxs, %u now active.", added_eps,
2167 xhci->num_active_eps);
2172 * The configure endpoint was failed by the xHC for some other reason, so we
2173 * need to revert the resources that failed configuration would have used.
2175 * Must be called with xhci->lock held.
2177 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2178 struct xhci_input_control_ctx *ctrl_ctx)
2182 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2183 xhci->num_active_eps -= num_failed_eps;
2184 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2185 "Removing %u failed ep ctxs, %u now active.",
2187 xhci->num_active_eps);
2191 * Now that the command has completed, clean up the active endpoint count by
2192 * subtracting out the endpoints that were dropped (but not changed).
2194 * Must be called with xhci->lock held.
2196 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2197 struct xhci_input_control_ctx *ctrl_ctx)
2199 u32 num_dropped_eps;
2201 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2202 xhci->num_active_eps -= num_dropped_eps;
2203 if (num_dropped_eps)
2204 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2205 "Removing %u dropped ep ctxs, %u now active.",
2207 xhci->num_active_eps);
2210 static unsigned int xhci_get_block_size(struct usb_device *udev)
2212 switch (udev->speed) {
2214 case USB_SPEED_FULL:
2216 case USB_SPEED_HIGH:
2218 case USB_SPEED_SUPER:
2219 case USB_SPEED_SUPER_PLUS:
2221 case USB_SPEED_UNKNOWN:
2222 case USB_SPEED_WIRELESS:
2224 /* Should never happen */
2230 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2232 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2234 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2239 /* If we are changing a LS/FS device under a HS hub,
2240 * make sure (if we are activating a new TT) that the HS bus has enough
2241 * bandwidth for this new TT.
2243 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2244 struct xhci_virt_device *virt_dev,
2247 struct xhci_interval_bw_table *bw_table;
2248 struct xhci_tt_bw_info *tt_info;
2250 /* Find the bandwidth table for the root port this TT is attached to. */
2251 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2252 tt_info = virt_dev->tt_info;
2253 /* If this TT already had active endpoints, the bandwidth for this TT
2254 * has already been added. Removing all periodic endpoints (and thus
2255 * making the TT enactive) will only decrease the bandwidth used.
2259 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2260 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2264 /* Not sure why we would have no new active endpoints...
2266 * Maybe because of an Evaluate Context change for a hub update or a
2267 * control endpoint 0 max packet size change?
2268 * FIXME: skip the bandwidth calculation in that case.
2273 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2274 struct xhci_virt_device *virt_dev)
2276 unsigned int bw_reserved;
2278 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2279 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2282 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2283 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2290 * This algorithm is a very conservative estimate of the worst-case scheduling
2291 * scenario for any one interval. The hardware dynamically schedules the
2292 * packets, so we can't tell which microframe could be the limiting factor in
2293 * the bandwidth scheduling. This only takes into account periodic endpoints.
2295 * Obviously, we can't solve an NP complete problem to find the minimum worst
2296 * case scenario. Instead, we come up with an estimate that is no less than
2297 * the worst case bandwidth used for any one microframe, but may be an
2300 * We walk the requirements for each endpoint by interval, starting with the
2301 * smallest interval, and place packets in the schedule where there is only one
2302 * possible way to schedule packets for that interval. In order to simplify
2303 * this algorithm, we record the largest max packet size for each interval, and
2304 * assume all packets will be that size.
2306 * For interval 0, we obviously must schedule all packets for each interval.
2307 * The bandwidth for interval 0 is just the amount of data to be transmitted
2308 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2309 * the number of packets).
2311 * For interval 1, we have two possible microframes to schedule those packets
2312 * in. For this algorithm, if we can schedule the same number of packets for
2313 * each possible scheduling opportunity (each microframe), we will do so. The
2314 * remaining number of packets will be saved to be transmitted in the gaps in
2315 * the next interval's scheduling sequence.
2317 * As we move those remaining packets to be scheduled with interval 2 packets,
2318 * we have to double the number of remaining packets to transmit. This is
2319 * because the intervals are actually powers of 2, and we would be transmitting
2320 * the previous interval's packets twice in this interval. We also have to be
2321 * sure that when we look at the largest max packet size for this interval, we
2322 * also look at the largest max packet size for the remaining packets and take
2323 * the greater of the two.
2325 * The algorithm continues to evenly distribute packets in each scheduling
2326 * opportunity, and push the remaining packets out, until we get to the last
2327 * interval. Then those packets and their associated overhead are just added
2328 * to the bandwidth used.
2330 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2331 struct xhci_virt_device *virt_dev,
2334 unsigned int bw_reserved;
2335 unsigned int max_bandwidth;
2336 unsigned int bw_used;
2337 unsigned int block_size;
2338 struct xhci_interval_bw_table *bw_table;
2339 unsigned int packet_size = 0;
2340 unsigned int overhead = 0;
2341 unsigned int packets_transmitted = 0;
2342 unsigned int packets_remaining = 0;
2345 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2346 return xhci_check_ss_bw(xhci, virt_dev);
2348 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2349 max_bandwidth = HS_BW_LIMIT;
2350 /* Convert percent of bus BW reserved to blocks reserved */
2351 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2353 max_bandwidth = FS_BW_LIMIT;
2354 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2357 bw_table = virt_dev->bw_table;
2358 /* We need to translate the max packet size and max ESIT payloads into
2359 * the units the hardware uses.
2361 block_size = xhci_get_block_size(virt_dev->udev);
2363 /* If we are manipulating a LS/FS device under a HS hub, double check
2364 * that the HS bus has enough bandwidth if we are activing a new TT.
2366 if (virt_dev->tt_info) {
2367 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2368 "Recalculating BW for rootport %u",
2369 virt_dev->real_port);
2370 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2371 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2372 "newly activated TT.\n");
2375 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2376 "Recalculating BW for TT slot %u port %u",
2377 virt_dev->tt_info->slot_id,
2378 virt_dev->tt_info->ttport);
2380 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2381 "Recalculating BW for rootport %u",
2382 virt_dev->real_port);
2385 /* Add in how much bandwidth will be used for interval zero, or the
2386 * rounded max ESIT payload + number of packets * largest overhead.
2388 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2389 bw_table->interval_bw[0].num_packets *
2390 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2392 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2393 unsigned int bw_added;
2394 unsigned int largest_mps;
2395 unsigned int interval_overhead;
2398 * How many packets could we transmit in this interval?
2399 * If packets didn't fit in the previous interval, we will need
2400 * to transmit that many packets twice within this interval.
2402 packets_remaining = 2 * packets_remaining +
2403 bw_table->interval_bw[i].num_packets;
2405 /* Find the largest max packet size of this or the previous
2408 if (list_empty(&bw_table->interval_bw[i].endpoints))
2411 struct xhci_virt_ep *virt_ep;
2412 struct list_head *ep_entry;
2414 ep_entry = bw_table->interval_bw[i].endpoints.next;
2415 virt_ep = list_entry(ep_entry,
2416 struct xhci_virt_ep, bw_endpoint_list);
2417 /* Convert to blocks, rounding up */
2418 largest_mps = DIV_ROUND_UP(
2419 virt_ep->bw_info.max_packet_size,
2422 if (largest_mps > packet_size)
2423 packet_size = largest_mps;
2425 /* Use the larger overhead of this or the previous interval. */
2426 interval_overhead = xhci_get_largest_overhead(
2427 &bw_table->interval_bw[i]);
2428 if (interval_overhead > overhead)
2429 overhead = interval_overhead;
2431 /* How many packets can we evenly distribute across
2432 * (1 << (i + 1)) possible scheduling opportunities?
2434 packets_transmitted = packets_remaining >> (i + 1);
2436 /* Add in the bandwidth used for those scheduled packets */
2437 bw_added = packets_transmitted * (overhead + packet_size);
2439 /* How many packets do we have remaining to transmit? */
2440 packets_remaining = packets_remaining % (1 << (i + 1));
2442 /* What largest max packet size should those packets have? */
2443 /* If we've transmitted all packets, don't carry over the
2444 * largest packet size.
2446 if (packets_remaining == 0) {
2449 } else if (packets_transmitted > 0) {
2450 /* Otherwise if we do have remaining packets, and we've
2451 * scheduled some packets in this interval, take the
2452 * largest max packet size from endpoints with this
2455 packet_size = largest_mps;
2456 overhead = interval_overhead;
2458 /* Otherwise carry over packet_size and overhead from the last
2459 * time we had a remainder.
2461 bw_used += bw_added;
2462 if (bw_used > max_bandwidth) {
2463 xhci_warn(xhci, "Not enough bandwidth. "
2464 "Proposed: %u, Max: %u\n",
2465 bw_used, max_bandwidth);
2470 * Ok, we know we have some packets left over after even-handedly
2471 * scheduling interval 15. We don't know which microframes they will
2472 * fit into, so we over-schedule and say they will be scheduled every
2475 if (packets_remaining > 0)
2476 bw_used += overhead + packet_size;
2478 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2479 unsigned int port_index = virt_dev->real_port - 1;
2481 /* OK, we're manipulating a HS device attached to a
2482 * root port bandwidth domain. Include the number of active TTs
2483 * in the bandwidth used.
2485 bw_used += TT_HS_OVERHEAD *
2486 xhci->rh_bw[port_index].num_active_tts;
2489 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2490 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2491 "Available: %u " "percent",
2492 bw_used, max_bandwidth, bw_reserved,
2493 (max_bandwidth - bw_used - bw_reserved) * 100 /
2496 bw_used += bw_reserved;
2497 if (bw_used > max_bandwidth) {
2498 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2499 bw_used, max_bandwidth);
2503 bw_table->bw_used = bw_used;
2507 static bool xhci_is_async_ep(unsigned int ep_type)
2509 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2510 ep_type != ISOC_IN_EP &&
2511 ep_type != INT_IN_EP);
2514 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2516 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2519 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2521 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2523 if (ep_bw->ep_interval == 0)
2524 return SS_OVERHEAD_BURST +
2525 (ep_bw->mult * ep_bw->num_packets *
2526 (SS_OVERHEAD + mps));
2527 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2528 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2529 1 << ep_bw->ep_interval);
2533 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2534 struct xhci_bw_info *ep_bw,
2535 struct xhci_interval_bw_table *bw_table,
2536 struct usb_device *udev,
2537 struct xhci_virt_ep *virt_ep,
2538 struct xhci_tt_bw_info *tt_info)
2540 struct xhci_interval_bw *interval_bw;
2541 int normalized_interval;
2543 if (xhci_is_async_ep(ep_bw->type))
2546 if (udev->speed >= USB_SPEED_SUPER) {
2547 if (xhci_is_sync_in_ep(ep_bw->type))
2548 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2549 xhci_get_ss_bw_consumed(ep_bw);
2551 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2552 xhci_get_ss_bw_consumed(ep_bw);
2556 /* SuperSpeed endpoints never get added to intervals in the table, so
2557 * this check is only valid for HS/FS/LS devices.
2559 if (list_empty(&virt_ep->bw_endpoint_list))
2561 /* For LS/FS devices, we need to translate the interval expressed in
2562 * microframes to frames.
2564 if (udev->speed == USB_SPEED_HIGH)
2565 normalized_interval = ep_bw->ep_interval;
2567 normalized_interval = ep_bw->ep_interval - 3;
2569 if (normalized_interval == 0)
2570 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2571 interval_bw = &bw_table->interval_bw[normalized_interval];
2572 interval_bw->num_packets -= ep_bw->num_packets;
2573 switch (udev->speed) {
2575 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2577 case USB_SPEED_FULL:
2578 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2580 case USB_SPEED_HIGH:
2581 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2583 case USB_SPEED_SUPER:
2584 case USB_SPEED_SUPER_PLUS:
2585 case USB_SPEED_UNKNOWN:
2586 case USB_SPEED_WIRELESS:
2587 /* Should never happen because only LS/FS/HS endpoints will get
2588 * added to the endpoint list.
2593 tt_info->active_eps -= 1;
2594 list_del_init(&virt_ep->bw_endpoint_list);
2597 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2598 struct xhci_bw_info *ep_bw,
2599 struct xhci_interval_bw_table *bw_table,
2600 struct usb_device *udev,
2601 struct xhci_virt_ep *virt_ep,
2602 struct xhci_tt_bw_info *tt_info)
2604 struct xhci_interval_bw *interval_bw;
2605 struct xhci_virt_ep *smaller_ep;
2606 int normalized_interval;
2608 if (xhci_is_async_ep(ep_bw->type))
2611 if (udev->speed == USB_SPEED_SUPER) {
2612 if (xhci_is_sync_in_ep(ep_bw->type))
2613 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2614 xhci_get_ss_bw_consumed(ep_bw);
2616 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2617 xhci_get_ss_bw_consumed(ep_bw);
2621 /* For LS/FS devices, we need to translate the interval expressed in
2622 * microframes to frames.
2624 if (udev->speed == USB_SPEED_HIGH)
2625 normalized_interval = ep_bw->ep_interval;
2627 normalized_interval = ep_bw->ep_interval - 3;
2629 if (normalized_interval == 0)
2630 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2631 interval_bw = &bw_table->interval_bw[normalized_interval];
2632 interval_bw->num_packets += ep_bw->num_packets;
2633 switch (udev->speed) {
2635 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2637 case USB_SPEED_FULL:
2638 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2640 case USB_SPEED_HIGH:
2641 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2643 case USB_SPEED_SUPER:
2644 case USB_SPEED_SUPER_PLUS:
2645 case USB_SPEED_UNKNOWN:
2646 case USB_SPEED_WIRELESS:
2647 /* Should never happen because only LS/FS/HS endpoints will get
2648 * added to the endpoint list.
2654 tt_info->active_eps += 1;
2655 /* Insert the endpoint into the list, largest max packet size first. */
2656 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2658 if (ep_bw->max_packet_size >=
2659 smaller_ep->bw_info.max_packet_size) {
2660 /* Add the new ep before the smaller endpoint */
2661 list_add_tail(&virt_ep->bw_endpoint_list,
2662 &smaller_ep->bw_endpoint_list);
2666 /* Add the new endpoint at the end of the list. */
2667 list_add_tail(&virt_ep->bw_endpoint_list,
2668 &interval_bw->endpoints);
2671 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2672 struct xhci_virt_device *virt_dev,
2675 struct xhci_root_port_bw_info *rh_bw_info;
2676 if (!virt_dev->tt_info)
2679 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2680 if (old_active_eps == 0 &&
2681 virt_dev->tt_info->active_eps != 0) {
2682 rh_bw_info->num_active_tts += 1;
2683 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2684 } else if (old_active_eps != 0 &&
2685 virt_dev->tt_info->active_eps == 0) {
2686 rh_bw_info->num_active_tts -= 1;
2687 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2691 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2692 struct xhci_virt_device *virt_dev,
2693 struct xhci_container_ctx *in_ctx)
2695 struct xhci_bw_info ep_bw_info[31];
2697 struct xhci_input_control_ctx *ctrl_ctx;
2698 int old_active_eps = 0;
2700 if (virt_dev->tt_info)
2701 old_active_eps = virt_dev->tt_info->active_eps;
2703 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2705 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2710 for (i = 0; i < 31; i++) {
2711 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2714 /* Make a copy of the BW info in case we need to revert this */
2715 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2716 sizeof(ep_bw_info[i]));
2717 /* Drop the endpoint from the interval table if the endpoint is
2718 * being dropped or changed.
2720 if (EP_IS_DROPPED(ctrl_ctx, i))
2721 xhci_drop_ep_from_interval_table(xhci,
2722 &virt_dev->eps[i].bw_info,
2728 /* Overwrite the information stored in the endpoints' bw_info */
2729 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2730 for (i = 0; i < 31; i++) {
2731 /* Add any changed or added endpoints to the interval table */
2732 if (EP_IS_ADDED(ctrl_ctx, i))
2733 xhci_add_ep_to_interval_table(xhci,
2734 &virt_dev->eps[i].bw_info,
2741 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2742 /* Ok, this fits in the bandwidth we have.
2743 * Update the number of active TTs.
2745 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2749 /* We don't have enough bandwidth for this, revert the stored info. */
2750 for (i = 0; i < 31; i++) {
2751 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2754 /* Drop the new copies of any added or changed endpoints from
2755 * the interval table.
2757 if (EP_IS_ADDED(ctrl_ctx, i)) {
2758 xhci_drop_ep_from_interval_table(xhci,
2759 &virt_dev->eps[i].bw_info,
2765 /* Revert the endpoint back to its old information */
2766 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2767 sizeof(ep_bw_info[i]));
2768 /* Add any changed or dropped endpoints back into the table */
2769 if (EP_IS_DROPPED(ctrl_ctx, i))
2770 xhci_add_ep_to_interval_table(xhci,
2771 &virt_dev->eps[i].bw_info,
2781 /* Issue a configure endpoint command or evaluate context command
2782 * and wait for it to finish.
2784 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2785 struct usb_device *udev,
2786 struct xhci_command *command,
2787 bool ctx_change, bool must_succeed)
2790 unsigned long flags;
2791 struct xhci_input_control_ctx *ctrl_ctx;
2792 struct xhci_virt_device *virt_dev;
2793 struct xhci_slot_ctx *slot_ctx;
2798 spin_lock_irqsave(&xhci->lock, flags);
2800 if (xhci->xhc_state & XHCI_STATE_DYING) {
2801 spin_unlock_irqrestore(&xhci->lock, flags);
2805 virt_dev = xhci->devs[udev->slot_id];
2807 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2809 spin_unlock_irqrestore(&xhci->lock, flags);
2810 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2815 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2816 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2817 spin_unlock_irqrestore(&xhci->lock, flags);
2818 xhci_warn(xhci, "Not enough host resources, "
2819 "active endpoint contexts = %u\n",
2820 xhci->num_active_eps);
2823 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2824 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2825 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2826 xhci_free_host_resources(xhci, ctrl_ctx);
2827 spin_unlock_irqrestore(&xhci->lock, flags);
2828 xhci_warn(xhci, "Not enough bandwidth\n");
2832 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2834 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2835 trace_xhci_configure_endpoint(slot_ctx);
2838 ret = xhci_queue_configure_endpoint(xhci, command,
2839 command->in_ctx->dma,
2840 udev->slot_id, must_succeed);
2842 ret = xhci_queue_evaluate_context(xhci, command,
2843 command->in_ctx->dma,
2844 udev->slot_id, must_succeed);
2846 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2847 xhci_free_host_resources(xhci, ctrl_ctx);
2848 spin_unlock_irqrestore(&xhci->lock, flags);
2849 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2850 "FIXME allocate a new ring segment");
2853 xhci_ring_cmd_db(xhci);
2854 spin_unlock_irqrestore(&xhci->lock, flags);
2856 /* Wait for the configure endpoint command to complete */
2857 wait_for_completion(command->completion);
2860 ret = xhci_configure_endpoint_result(xhci, udev,
2863 ret = xhci_evaluate_context_result(xhci, udev,
2866 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2867 spin_lock_irqsave(&xhci->lock, flags);
2868 /* If the command failed, remove the reserved resources.
2869 * Otherwise, clean up the estimate to include dropped eps.
2872 xhci_free_host_resources(xhci, ctrl_ctx);
2874 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2875 spin_unlock_irqrestore(&xhci->lock, flags);
2880 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2881 struct xhci_virt_device *vdev, int i)
2883 struct xhci_virt_ep *ep = &vdev->eps[i];
2885 if (ep->ep_state & EP_HAS_STREAMS) {
2886 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2887 xhci_get_endpoint_address(i));
2888 xhci_free_stream_info(xhci, ep->stream_info);
2889 ep->stream_info = NULL;
2890 ep->ep_state &= ~EP_HAS_STREAMS;
2894 /* Called after one or more calls to xhci_add_endpoint() or
2895 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2896 * to call xhci_reset_bandwidth().
2898 * Since we are in the middle of changing either configuration or
2899 * installing a new alt setting, the USB core won't allow URBs to be
2900 * enqueued for any endpoint on the old config or interface. Nothing
2901 * else should be touching the xhci->devs[slot_id] structure, so we
2902 * don't need to take the xhci->lock for manipulating that.
2904 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2908 struct xhci_hcd *xhci;
2909 struct xhci_virt_device *virt_dev;
2910 struct xhci_input_control_ctx *ctrl_ctx;
2911 struct xhci_slot_ctx *slot_ctx;
2912 struct xhci_command *command;
2914 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2917 xhci = hcd_to_xhci(hcd);
2918 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2919 (xhci->xhc_state & XHCI_STATE_REMOVING))
2922 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2923 virt_dev = xhci->devs[udev->slot_id];
2925 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2929 command->in_ctx = virt_dev->in_ctx;
2931 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2932 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2934 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2937 goto command_cleanup;
2939 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2940 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2941 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2943 /* Don't issue the command if there's no endpoints to update. */
2944 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2945 ctrl_ctx->drop_flags == 0) {
2947 goto command_cleanup;
2949 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2950 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2951 for (i = 31; i >= 1; i--) {
2952 __le32 le32 = cpu_to_le32(BIT(i));
2954 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2955 || (ctrl_ctx->add_flags & le32) || i == 1) {
2956 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2957 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2962 ret = xhci_configure_endpoint(xhci, udev, command,
2965 /* Callee should call reset_bandwidth() */
2966 goto command_cleanup;
2968 /* Free any rings that were dropped, but not changed. */
2969 for (i = 1; i < 31; i++) {
2970 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2971 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2972 xhci_free_endpoint_ring(xhci, virt_dev, i);
2973 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2976 xhci_zero_in_ctx(xhci, virt_dev);
2978 * Install any rings for completely new endpoints or changed endpoints,
2979 * and free any old rings from changed endpoints.
2981 for (i = 1; i < 31; i++) {
2982 if (!virt_dev->eps[i].new_ring)
2984 /* Only free the old ring if it exists.
2985 * It may not if this is the first add of an endpoint.
2987 if (virt_dev->eps[i].ring) {
2988 xhci_free_endpoint_ring(xhci, virt_dev, i);
2990 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2991 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2992 virt_dev->eps[i].new_ring = NULL;
2993 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
2996 kfree(command->completion);
3002 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3004 struct xhci_hcd *xhci;
3005 struct xhci_virt_device *virt_dev;
3008 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3011 xhci = hcd_to_xhci(hcd);
3013 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3014 virt_dev = xhci->devs[udev->slot_id];
3015 /* Free any rings allocated for added endpoints */
3016 for (i = 0; i < 31; i++) {
3017 if (virt_dev->eps[i].new_ring) {
3018 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3019 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3020 virt_dev->eps[i].new_ring = NULL;
3023 xhci_zero_in_ctx(xhci, virt_dev);
3026 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3027 struct xhci_container_ctx *in_ctx,
3028 struct xhci_container_ctx *out_ctx,
3029 struct xhci_input_control_ctx *ctrl_ctx,
3030 u32 add_flags, u32 drop_flags)
3032 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3033 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3034 xhci_slot_copy(xhci, in_ctx, out_ctx);
3035 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3038 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
3039 unsigned int slot_id, unsigned int ep_index,
3040 struct xhci_dequeue_state *deq_state)
3042 struct xhci_input_control_ctx *ctrl_ctx;
3043 struct xhci_container_ctx *in_ctx;
3044 struct xhci_ep_ctx *ep_ctx;
3048 in_ctx = xhci->devs[slot_id]->in_ctx;
3049 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
3051 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3056 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
3057 xhci->devs[slot_id]->out_ctx, ep_index);
3058 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
3059 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
3060 deq_state->new_deq_ptr);
3062 xhci_warn(xhci, "WARN Cannot submit config ep after "
3063 "reset ep command\n");
3064 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
3065 deq_state->new_deq_seg,
3066 deq_state->new_deq_ptr);
3069 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
3071 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
3072 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
3073 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
3074 added_ctxs, added_ctxs);
3077 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
3078 unsigned int ep_index, unsigned int stream_id,
3081 struct xhci_dequeue_state deq_state;
3083 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3084 "Cleaning up stalled endpoint ring");
3085 /* We need to move the HW's dequeue pointer past this TD,
3086 * or it will attempt to resend it on the next doorbell ring.
3088 xhci_find_new_dequeue_state(xhci, slot_id, ep_index, stream_id, td,
3091 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
3094 /* HW with the reset endpoint quirk will use the saved dequeue state to
3095 * issue a configure endpoint command later.
3097 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
3098 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3099 "Queueing new dequeue state");
3100 xhci_queue_new_dequeue_state(xhci, slot_id,
3101 ep_index, &deq_state);
3103 /* Better hope no one uses the input context between now and the
3104 * reset endpoint completion!
3105 * XXX: No idea how this hardware will react when stream rings
3108 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3109 "Setting up input context for "
3110 "configure endpoint command");
3111 xhci_setup_input_ctx_for_quirk(xhci, slot_id,
3112 ep_index, &deq_state);
3116 static void xhci_endpoint_disable(struct usb_hcd *hcd,
3117 struct usb_host_endpoint *host_ep)
3119 struct xhci_hcd *xhci;
3120 struct xhci_virt_device *vdev;
3121 struct xhci_virt_ep *ep;
3122 struct usb_device *udev;
3123 unsigned long flags;
3124 unsigned int ep_index;
3126 xhci = hcd_to_xhci(hcd);
3128 spin_lock_irqsave(&xhci->lock, flags);
3130 udev = (struct usb_device *)host_ep->hcpriv;
3131 if (!udev || !udev->slot_id)
3134 vdev = xhci->devs[udev->slot_id];
3138 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3139 ep = &vdev->eps[ep_index];
3143 /* wait for hub_tt_work to finish clearing hub TT */
3144 if (ep->ep_state & EP_CLEARING_TT) {
3145 spin_unlock_irqrestore(&xhci->lock, flags);
3146 schedule_timeout_uninterruptible(1);
3151 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3154 host_ep->hcpriv = NULL;
3155 spin_unlock_irqrestore(&xhci->lock, flags);
3159 * Called after usb core issues a clear halt control message.
3160 * The host side of the halt should already be cleared by a reset endpoint
3161 * command issued when the STALL event was received.
3163 * The reset endpoint command may only be issued to endpoints in the halted
3164 * state. For software that wishes to reset the data toggle or sequence number
3165 * of an endpoint that isn't in the halted state this function will issue a
3166 * configure endpoint command with the Drop and Add bits set for the target
3167 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3170 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3171 struct usb_host_endpoint *host_ep)
3173 struct xhci_hcd *xhci;
3174 struct usb_device *udev;
3175 struct xhci_virt_device *vdev;
3176 struct xhci_virt_ep *ep;
3177 struct xhci_input_control_ctx *ctrl_ctx;
3178 struct xhci_command *stop_cmd, *cfg_cmd;
3179 unsigned int ep_index;
3180 unsigned long flags;
3184 xhci = hcd_to_xhci(hcd);
3185 if (!host_ep->hcpriv)
3187 udev = (struct usb_device *) host_ep->hcpriv;
3188 vdev = xhci->devs[udev->slot_id];
3191 * vdev may be lost due to xHC restore error and re-initialization
3192 * during S3/S4 resume. A new vdev will be allocated later by
3193 * xhci_discover_or_reset_device()
3195 if (!udev->slot_id || !vdev)
3197 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3198 ep = &vdev->eps[ep_index];
3202 /* Bail out if toggle is already being cleared by a endpoint reset */
3203 spin_lock_irqsave(&xhci->lock, flags);
3204 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3205 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3206 spin_unlock_irqrestore(&xhci->lock, flags);
3209 spin_unlock_irqrestore(&xhci->lock, flags);
3210 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3211 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3212 usb_endpoint_xfer_isoc(&host_ep->desc))
3215 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3217 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3220 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3224 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3228 spin_lock_irqsave(&xhci->lock, flags);
3230 /* block queuing new trbs and ringing ep doorbell */
3231 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3234 * Make sure endpoint ring is empty before resetting the toggle/seq.
3235 * Driver is required to synchronously cancel all transfer request.
3236 * Stop the endpoint to force xHC to update the output context
3239 if (!list_empty(&ep->ring->td_list)) {
3240 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3241 spin_unlock_irqrestore(&xhci->lock, flags);
3242 xhci_free_command(xhci, cfg_cmd);
3246 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3249 spin_unlock_irqrestore(&xhci->lock, flags);
3250 xhci_free_command(xhci, cfg_cmd);
3251 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3256 xhci_ring_cmd_db(xhci);
3257 spin_unlock_irqrestore(&xhci->lock, flags);
3259 wait_for_completion(stop_cmd->completion);
3261 spin_lock_irqsave(&xhci->lock, flags);
3263 /* config ep command clears toggle if add and drop ep flags are set */
3264 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3266 spin_unlock_irqrestore(&xhci->lock, flags);
3267 xhci_free_command(xhci, cfg_cmd);
3268 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3273 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3274 ctrl_ctx, ep_flag, ep_flag);
3275 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3277 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3278 udev->slot_id, false);
3280 spin_unlock_irqrestore(&xhci->lock, flags);
3281 xhci_free_command(xhci, cfg_cmd);
3282 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3287 xhci_ring_cmd_db(xhci);
3288 spin_unlock_irqrestore(&xhci->lock, flags);
3290 wait_for_completion(cfg_cmd->completion);
3292 xhci_free_command(xhci, cfg_cmd);
3294 xhci_free_command(xhci, stop_cmd);
3295 spin_lock_irqsave(&xhci->lock, flags);
3296 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3297 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3298 spin_unlock_irqrestore(&xhci->lock, flags);
3301 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3302 struct usb_device *udev, struct usb_host_endpoint *ep,
3303 unsigned int slot_id)
3306 unsigned int ep_index;
3307 unsigned int ep_state;
3311 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3313 return ret ? ret : -EINVAL;
3314 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3315 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3316 " descriptor for ep 0x%x does not support streams\n",
3317 ep->desc.bEndpointAddress);
3321 ep_index = xhci_get_endpoint_index(&ep->desc);
3322 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3323 if (ep_state & EP_HAS_STREAMS ||
3324 ep_state & EP_GETTING_STREAMS) {
3325 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3326 "already has streams set up.\n",
3327 ep->desc.bEndpointAddress);
3328 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3329 "dynamic stream context array reallocation.\n");
3332 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3333 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3334 "endpoint 0x%x; URBs are pending.\n",
3335 ep->desc.bEndpointAddress);
3341 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3342 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3344 unsigned int max_streams;
3346 /* The stream context array size must be a power of two */
3347 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3349 * Find out how many primary stream array entries the host controller
3350 * supports. Later we may use secondary stream arrays (similar to 2nd
3351 * level page entries), but that's an optional feature for xHCI host
3352 * controllers. xHCs must support at least 4 stream IDs.
3354 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3355 if (*num_stream_ctxs > max_streams) {
3356 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3358 *num_stream_ctxs = max_streams;
3359 *num_streams = max_streams;
3363 /* Returns an error code if one of the endpoint already has streams.
3364 * This does not change any data structures, it only checks and gathers
3367 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3368 struct usb_device *udev,
3369 struct usb_host_endpoint **eps, unsigned int num_eps,
3370 unsigned int *num_streams, u32 *changed_ep_bitmask)
3372 unsigned int max_streams;
3373 unsigned int endpoint_flag;
3377 for (i = 0; i < num_eps; i++) {
3378 ret = xhci_check_streams_endpoint(xhci, udev,
3379 eps[i], udev->slot_id);
3383 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3384 if (max_streams < (*num_streams - 1)) {
3385 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3386 eps[i]->desc.bEndpointAddress,
3388 *num_streams = max_streams+1;
3391 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3392 if (*changed_ep_bitmask & endpoint_flag)
3394 *changed_ep_bitmask |= endpoint_flag;
3399 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3400 struct usb_device *udev,
3401 struct usb_host_endpoint **eps, unsigned int num_eps)
3403 u32 changed_ep_bitmask = 0;
3404 unsigned int slot_id;
3405 unsigned int ep_index;
3406 unsigned int ep_state;
3409 slot_id = udev->slot_id;
3410 if (!xhci->devs[slot_id])
3413 for (i = 0; i < num_eps; i++) {
3414 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3415 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3416 /* Are streams already being freed for the endpoint? */
3417 if (ep_state & EP_GETTING_NO_STREAMS) {
3418 xhci_warn(xhci, "WARN Can't disable streams for "
3420 "streams are being disabled already\n",
3421 eps[i]->desc.bEndpointAddress);
3424 /* Are there actually any streams to free? */
3425 if (!(ep_state & EP_HAS_STREAMS) &&
3426 !(ep_state & EP_GETTING_STREAMS)) {
3427 xhci_warn(xhci, "WARN Can't disable streams for "
3429 "streams are already disabled!\n",
3430 eps[i]->desc.bEndpointAddress);
3431 xhci_warn(xhci, "WARN xhci_free_streams() called "
3432 "with non-streams endpoint\n");
3435 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3437 return changed_ep_bitmask;
3441 * The USB device drivers use this function (through the HCD interface in USB
3442 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3443 * coordinate mass storage command queueing across multiple endpoints (basically
3444 * a stream ID == a task ID).
3446 * Setting up streams involves allocating the same size stream context array
3447 * for each endpoint and issuing a configure endpoint command for all endpoints.
3449 * Don't allow the call to succeed if one endpoint only supports one stream
3450 * (which means it doesn't support streams at all).
3452 * Drivers may get less stream IDs than they asked for, if the host controller
3453 * hardware or endpoints claim they can't support the number of requested
3456 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3457 struct usb_host_endpoint **eps, unsigned int num_eps,
3458 unsigned int num_streams, gfp_t mem_flags)
3461 struct xhci_hcd *xhci;
3462 struct xhci_virt_device *vdev;
3463 struct xhci_command *config_cmd;
3464 struct xhci_input_control_ctx *ctrl_ctx;
3465 unsigned int ep_index;
3466 unsigned int num_stream_ctxs;
3467 unsigned int max_packet;
3468 unsigned long flags;
3469 u32 changed_ep_bitmask = 0;
3474 /* Add one to the number of streams requested to account for
3475 * stream 0 that is reserved for xHCI usage.
3478 xhci = hcd_to_xhci(hcd);
3479 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3482 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3483 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3484 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3485 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3489 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3493 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3495 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3497 xhci_free_command(xhci, config_cmd);
3501 /* Check to make sure all endpoints are not already configured for
3502 * streams. While we're at it, find the maximum number of streams that
3503 * all the endpoints will support and check for duplicate endpoints.
3505 spin_lock_irqsave(&xhci->lock, flags);
3506 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3507 num_eps, &num_streams, &changed_ep_bitmask);
3509 xhci_free_command(xhci, config_cmd);
3510 spin_unlock_irqrestore(&xhci->lock, flags);
3513 if (num_streams <= 1) {
3514 xhci_warn(xhci, "WARN: endpoints can't handle "
3515 "more than one stream.\n");
3516 xhci_free_command(xhci, config_cmd);
3517 spin_unlock_irqrestore(&xhci->lock, flags);
3520 vdev = xhci->devs[udev->slot_id];
3521 /* Mark each endpoint as being in transition, so
3522 * xhci_urb_enqueue() will reject all URBs.
3524 for (i = 0; i < num_eps; i++) {
3525 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3526 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3528 spin_unlock_irqrestore(&xhci->lock, flags);
3530 /* Setup internal data structures and allocate HW data structures for
3531 * streams (but don't install the HW structures in the input context
3532 * until we're sure all memory allocation succeeded).
3534 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3535 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3536 num_stream_ctxs, num_streams);
3538 for (i = 0; i < num_eps; i++) {
3539 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3540 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3541 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3544 max_packet, mem_flags);
3545 if (!vdev->eps[ep_index].stream_info)
3547 /* Set maxPstreams in endpoint context and update deq ptr to
3548 * point to stream context array. FIXME
3552 /* Set up the input context for a configure endpoint command. */
3553 for (i = 0; i < num_eps; i++) {
3554 struct xhci_ep_ctx *ep_ctx;
3556 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3557 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3559 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3560 vdev->out_ctx, ep_index);
3561 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3562 vdev->eps[ep_index].stream_info);
3564 /* Tell the HW to drop its old copy of the endpoint context info
3565 * and add the updated copy from the input context.
3567 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3568 vdev->out_ctx, ctrl_ctx,
3569 changed_ep_bitmask, changed_ep_bitmask);
3571 /* Issue and wait for the configure endpoint command */
3572 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3575 /* xHC rejected the configure endpoint command for some reason, so we
3576 * leave the old ring intact and free our internal streams data
3582 spin_lock_irqsave(&xhci->lock, flags);
3583 for (i = 0; i < num_eps; i++) {
3584 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3585 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3586 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3587 udev->slot_id, ep_index);
3588 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3590 xhci_free_command(xhci, config_cmd);
3591 spin_unlock_irqrestore(&xhci->lock, flags);
3593 for (i = 0; i < num_eps; i++) {
3594 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3595 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3597 /* Subtract 1 for stream 0, which drivers can't use */
3598 return num_streams - 1;
3601 /* If it didn't work, free the streams! */
3602 for (i = 0; i < num_eps; i++) {
3603 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3604 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3605 vdev->eps[ep_index].stream_info = NULL;
3606 /* FIXME Unset maxPstreams in endpoint context and
3607 * update deq ptr to point to normal string ring.
3609 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3610 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3611 xhci_endpoint_zero(xhci, vdev, eps[i]);
3613 xhci_free_command(xhci, config_cmd);
3617 /* Transition the endpoint from using streams to being a "normal" endpoint
3620 * Modify the endpoint context state, submit a configure endpoint command,
3621 * and free all endpoint rings for streams if that completes successfully.
3623 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3624 struct usb_host_endpoint **eps, unsigned int num_eps,
3628 struct xhci_hcd *xhci;
3629 struct xhci_virt_device *vdev;
3630 struct xhci_command *command;
3631 struct xhci_input_control_ctx *ctrl_ctx;
3632 unsigned int ep_index;
3633 unsigned long flags;
3634 u32 changed_ep_bitmask;
3636 xhci = hcd_to_xhci(hcd);
3637 vdev = xhci->devs[udev->slot_id];
3639 /* Set up a configure endpoint command to remove the streams rings */
3640 spin_lock_irqsave(&xhci->lock, flags);
3641 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3642 udev, eps, num_eps);
3643 if (changed_ep_bitmask == 0) {
3644 spin_unlock_irqrestore(&xhci->lock, flags);
3648 /* Use the xhci_command structure from the first endpoint. We may have
3649 * allocated too many, but the driver may call xhci_free_streams() for
3650 * each endpoint it grouped into one call to xhci_alloc_streams().
3652 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3653 command = vdev->eps[ep_index].stream_info->free_streams_command;
3654 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3656 spin_unlock_irqrestore(&xhci->lock, flags);
3657 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3662 for (i = 0; i < num_eps; i++) {
3663 struct xhci_ep_ctx *ep_ctx;
3665 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3666 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3667 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3668 EP_GETTING_NO_STREAMS;
3670 xhci_endpoint_copy(xhci, command->in_ctx,
3671 vdev->out_ctx, ep_index);
3672 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3673 &vdev->eps[ep_index]);
3675 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3676 vdev->out_ctx, ctrl_ctx,
3677 changed_ep_bitmask, changed_ep_bitmask);
3678 spin_unlock_irqrestore(&xhci->lock, flags);
3680 /* Issue and wait for the configure endpoint command,
3681 * which must succeed.
3683 ret = xhci_configure_endpoint(xhci, udev, command,
3686 /* xHC rejected the configure endpoint command for some reason, so we
3687 * leave the streams rings intact.
3692 spin_lock_irqsave(&xhci->lock, flags);
3693 for (i = 0; i < num_eps; i++) {
3694 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3695 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3696 vdev->eps[ep_index].stream_info = NULL;
3697 /* FIXME Unset maxPstreams in endpoint context and
3698 * update deq ptr to point to normal string ring.
3700 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3701 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3703 spin_unlock_irqrestore(&xhci->lock, flags);
3709 * Deletes endpoint resources for endpoints that were active before a Reset
3710 * Device command, or a Disable Slot command. The Reset Device command leaves
3711 * the control endpoint intact, whereas the Disable Slot command deletes it.
3713 * Must be called with xhci->lock held.
3715 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3716 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3719 unsigned int num_dropped_eps = 0;
3720 unsigned int drop_flags = 0;
3722 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3723 if (virt_dev->eps[i].ring) {
3724 drop_flags |= 1 << i;
3728 xhci->num_active_eps -= num_dropped_eps;
3729 if (num_dropped_eps)
3730 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3731 "Dropped %u ep ctxs, flags = 0x%x, "
3733 num_dropped_eps, drop_flags,
3734 xhci->num_active_eps);
3738 * This submits a Reset Device Command, which will set the device state to 0,
3739 * set the device address to 0, and disable all the endpoints except the default
3740 * control endpoint. The USB core should come back and call
3741 * xhci_address_device(), and then re-set up the configuration. If this is
3742 * called because of a usb_reset_and_verify_device(), then the old alternate
3743 * settings will be re-installed through the normal bandwidth allocation
3746 * Wait for the Reset Device command to finish. Remove all structures
3747 * associated with the endpoints that were disabled. Clear the input device
3748 * structure? Reset the control endpoint 0 max packet size?
3750 * If the virt_dev to be reset does not exist or does not match the udev,
3751 * it means the device is lost, possibly due to the xHC restore error and
3752 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3753 * re-allocate the device.
3755 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3756 struct usb_device *udev)
3759 unsigned long flags;
3760 struct xhci_hcd *xhci;
3761 unsigned int slot_id;
3762 struct xhci_virt_device *virt_dev;
3763 struct xhci_command *reset_device_cmd;
3764 struct xhci_slot_ctx *slot_ctx;
3765 int old_active_eps = 0;
3767 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3770 xhci = hcd_to_xhci(hcd);
3771 slot_id = udev->slot_id;
3772 virt_dev = xhci->devs[slot_id];
3774 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3775 "not exist. Re-allocate the device\n", slot_id);
3776 ret = xhci_alloc_dev(hcd, udev);
3783 if (virt_dev->tt_info)
3784 old_active_eps = virt_dev->tt_info->active_eps;
3786 if (virt_dev->udev != udev) {
3787 /* If the virt_dev and the udev does not match, this virt_dev
3788 * may belong to another udev.
3789 * Re-allocate the device.
3791 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3792 "not match the udev. Re-allocate the device\n",
3794 ret = xhci_alloc_dev(hcd, udev);
3801 /* If device is not setup, there is no point in resetting it */
3802 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3803 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3804 SLOT_STATE_DISABLED)
3807 trace_xhci_discover_or_reset_device(slot_ctx);
3809 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3810 /* Allocate the command structure that holds the struct completion.
3811 * Assume we're in process context, since the normal device reset
3812 * process has to wait for the device anyway. Storage devices are
3813 * reset as part of error handling, so use GFP_NOIO instead of
3816 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3817 if (!reset_device_cmd) {
3818 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3822 /* Attempt to submit the Reset Device command to the command ring */
3823 spin_lock_irqsave(&xhci->lock, flags);
3825 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3827 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3828 spin_unlock_irqrestore(&xhci->lock, flags);
3829 goto command_cleanup;
3831 xhci_ring_cmd_db(xhci);
3832 spin_unlock_irqrestore(&xhci->lock, flags);
3834 /* Wait for the Reset Device command to finish */
3835 wait_for_completion(reset_device_cmd->completion);
3837 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3838 * unless we tried to reset a slot ID that wasn't enabled,
3839 * or the device wasn't in the addressed or configured state.
3841 ret = reset_device_cmd->status;
3843 case COMP_COMMAND_ABORTED:
3844 case COMP_COMMAND_RING_STOPPED:
3845 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3847 goto command_cleanup;
3848 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3849 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3850 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3852 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3853 xhci_dbg(xhci, "Not freeing device rings.\n");
3854 /* Don't treat this as an error. May change my mind later. */
3856 goto command_cleanup;
3858 xhci_dbg(xhci, "Successful reset device command.\n");
3861 if (xhci_is_vendor_info_code(xhci, ret))
3863 xhci_warn(xhci, "Unknown completion code %u for "
3864 "reset device command.\n", ret);
3866 goto command_cleanup;
3869 /* Free up host controller endpoint resources */
3870 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3871 spin_lock_irqsave(&xhci->lock, flags);
3872 /* Don't delete the default control endpoint resources */
3873 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3874 spin_unlock_irqrestore(&xhci->lock, flags);
3877 /* Everything but endpoint 0 is disabled, so free the rings. */
3878 for (i = 1; i < 31; i++) {
3879 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3881 if (ep->ep_state & EP_HAS_STREAMS) {
3882 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3883 xhci_get_endpoint_address(i));
3884 xhci_free_stream_info(xhci, ep->stream_info);
3885 ep->stream_info = NULL;
3886 ep->ep_state &= ~EP_HAS_STREAMS;
3890 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3891 xhci_free_endpoint_ring(xhci, virt_dev, i);
3893 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3894 xhci_drop_ep_from_interval_table(xhci,
3895 &virt_dev->eps[i].bw_info,
3900 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3902 /* If necessary, update the number of active TTs on this root port */
3903 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3904 virt_dev->flags = 0;
3908 xhci_free_command(xhci, reset_device_cmd);
3913 * At this point, the struct usb_device is about to go away, the device has
3914 * disconnected, and all traffic has been stopped and the endpoints have been
3915 * disabled. Free any HC data structures associated with that device.
3917 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3919 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3920 struct xhci_virt_device *virt_dev;
3921 struct xhci_slot_ctx *slot_ctx;
3925 * We called pm_runtime_get_noresume when the device was attached.
3926 * Decrement the counter here to allow controller to runtime suspend
3927 * if no devices remain.
3929 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3930 pm_runtime_put_noidle(hcd->self.controller);
3932 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3933 /* If the host is halted due to driver unload, we still need to free the
3936 if (ret <= 0 && ret != -ENODEV)
3939 virt_dev = xhci->devs[udev->slot_id];
3940 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3941 trace_xhci_free_dev(slot_ctx);
3943 /* Stop any wayward timer functions (which may grab the lock) */
3944 for (i = 0; i < 31; i++) {
3945 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3946 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3948 virt_dev->udev = NULL;
3949 xhci_disable_slot(xhci, udev->slot_id);
3950 xhci_free_virt_device(xhci, udev->slot_id);
3953 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3955 struct xhci_command *command;
3956 unsigned long flags;
3960 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3964 xhci_debugfs_remove_slot(xhci, slot_id);
3966 spin_lock_irqsave(&xhci->lock, flags);
3967 /* Don't disable the slot if the host controller is dead. */
3968 state = readl(&xhci->op_regs->status);
3969 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3970 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3971 spin_unlock_irqrestore(&xhci->lock, flags);
3976 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3979 spin_unlock_irqrestore(&xhci->lock, flags);
3983 xhci_ring_cmd_db(xhci);
3984 spin_unlock_irqrestore(&xhci->lock, flags);
3986 wait_for_completion(command->completion);
3988 if (command->status != COMP_SUCCESS)
3989 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
3990 slot_id, command->status);
3992 xhci_free_command(xhci, command);
3998 * Checks if we have enough host controller resources for the default control
4001 * Must be called with xhci->lock held.
4003 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4005 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4006 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4007 "Not enough ep ctxs: "
4008 "%u active, need to add 1, limit is %u.",
4009 xhci->num_active_eps, xhci->limit_active_eps);
4012 xhci->num_active_eps += 1;
4013 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4014 "Adding 1 ep ctx, %u now active.",
4015 xhci->num_active_eps);
4021 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4022 * timed out, or allocating memory failed. Returns 1 on success.
4024 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4026 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4027 struct xhci_virt_device *vdev;
4028 struct xhci_slot_ctx *slot_ctx;
4029 unsigned long flags;
4031 struct xhci_command *command;
4033 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4037 spin_lock_irqsave(&xhci->lock, flags);
4038 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4040 spin_unlock_irqrestore(&xhci->lock, flags);
4041 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4042 xhci_free_command(xhci, command);
4045 xhci_ring_cmd_db(xhci);
4046 spin_unlock_irqrestore(&xhci->lock, flags);
4048 wait_for_completion(command->completion);
4049 slot_id = command->slot_id;
4051 if (!slot_id || command->status != COMP_SUCCESS) {
4052 xhci_err(xhci, "Error while assigning device slot ID\n");
4053 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4055 readl(&xhci->cap_regs->hcs_params1)));
4056 xhci_free_command(xhci, command);
4060 xhci_free_command(xhci, command);
4062 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4063 spin_lock_irqsave(&xhci->lock, flags);
4064 ret = xhci_reserve_host_control_ep_resources(xhci);
4066 spin_unlock_irqrestore(&xhci->lock, flags);
4067 xhci_warn(xhci, "Not enough host resources, "
4068 "active endpoint contexts = %u\n",
4069 xhci->num_active_eps);
4072 spin_unlock_irqrestore(&xhci->lock, flags);
4074 /* Use GFP_NOIO, since this function can be called from
4075 * xhci_discover_or_reset_device(), which may be called as part of
4076 * mass storage driver error handling.
4078 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4079 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4082 vdev = xhci->devs[slot_id];
4083 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4084 trace_xhci_alloc_dev(slot_ctx);
4086 udev->slot_id = slot_id;
4088 xhci_debugfs_create_slot(xhci, slot_id);
4091 * If resetting upon resume, we can't put the controller into runtime
4092 * suspend if there is a device attached.
4094 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4095 pm_runtime_get_noresume(hcd->self.controller);
4097 /* Is this a LS or FS device under a HS hub? */
4098 /* Hub or peripherial? */
4102 xhci_disable_slot(xhci, udev->slot_id);
4103 xhci_free_virt_device(xhci, udev->slot_id);
4109 * Issue an Address Device command and optionally send a corresponding
4110 * SetAddress request to the device.
4112 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4113 enum xhci_setup_dev setup)
4115 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4116 unsigned long flags;
4117 struct xhci_virt_device *virt_dev;
4119 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4120 struct xhci_slot_ctx *slot_ctx;
4121 struct xhci_input_control_ctx *ctrl_ctx;
4123 struct xhci_command *command = NULL;
4125 mutex_lock(&xhci->mutex);
4127 if (xhci->xhc_state) { /* dying, removing or halted */
4132 if (!udev->slot_id) {
4133 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4134 "Bad Slot ID %d", udev->slot_id);
4139 virt_dev = xhci->devs[udev->slot_id];
4141 if (WARN_ON(!virt_dev)) {
4143 * In plug/unplug torture test with an NEC controller,
4144 * a zero-dereference was observed once due to virt_dev = 0.
4145 * Print useful debug rather than crash if it is observed again!
4147 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4152 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4153 trace_xhci_setup_device_slot(slot_ctx);
4155 if (setup == SETUP_CONTEXT_ONLY) {
4156 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4157 SLOT_STATE_DEFAULT) {
4158 xhci_dbg(xhci, "Slot already in default state\n");
4163 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4169 command->in_ctx = virt_dev->in_ctx;
4171 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4172 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4174 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4180 * If this is the first Set Address since device plug-in or
4181 * virt_device realloaction after a resume with an xHCI power loss,
4182 * then set up the slot context.
4184 if (!slot_ctx->dev_info)
4185 xhci_setup_addressable_virt_dev(xhci, udev);
4186 /* Otherwise, update the control endpoint ring enqueue pointer. */
4188 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4189 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4190 ctrl_ctx->drop_flags = 0;
4192 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4193 le32_to_cpu(slot_ctx->dev_info) >> 27);
4195 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4196 spin_lock_irqsave(&xhci->lock, flags);
4197 trace_xhci_setup_device(virt_dev);
4198 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4199 udev->slot_id, setup);
4201 spin_unlock_irqrestore(&xhci->lock, flags);
4202 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4203 "FIXME: allocate a command ring segment");
4206 xhci_ring_cmd_db(xhci);
4207 spin_unlock_irqrestore(&xhci->lock, flags);
4209 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4210 wait_for_completion(command->completion);
4212 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4213 * the SetAddress() "recovery interval" required by USB and aborting the
4214 * command on a timeout.
4216 switch (command->status) {
4217 case COMP_COMMAND_ABORTED:
4218 case COMP_COMMAND_RING_STOPPED:
4219 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4222 case COMP_CONTEXT_STATE_ERROR:
4223 case COMP_SLOT_NOT_ENABLED_ERROR:
4224 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4225 act, udev->slot_id);
4228 case COMP_USB_TRANSACTION_ERROR:
4229 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4231 mutex_unlock(&xhci->mutex);
4232 ret = xhci_disable_slot(xhci, udev->slot_id);
4233 xhci_free_virt_device(xhci, udev->slot_id);
4235 xhci_alloc_dev(hcd, udev);
4236 kfree(command->completion);
4239 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4240 dev_warn(&udev->dev,
4241 "ERROR: Incompatible device for setup %s command\n", act);
4245 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4246 "Successful setup %s command", act);
4250 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4251 act, command->status);
4252 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4258 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4259 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4260 "Op regs DCBAA ptr = %#016llx", temp_64);
4261 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4262 "Slot ID %d dcbaa entry @%p = %#016llx",
4264 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4265 (unsigned long long)
4266 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4267 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4268 "Output Context DMA address = %#08llx",
4269 (unsigned long long)virt_dev->out_ctx->dma);
4270 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4271 le32_to_cpu(slot_ctx->dev_info) >> 27);
4273 * USB core uses address 1 for the roothubs, so we add one to the
4274 * address given back to us by the HC.
4276 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4277 le32_to_cpu(slot_ctx->dev_info) >> 27);
4278 /* Zero the input context control for later use */
4279 ctrl_ctx->add_flags = 0;
4280 ctrl_ctx->drop_flags = 0;
4281 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4282 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4284 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4285 "Internal device address = %d",
4286 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4288 mutex_unlock(&xhci->mutex);
4290 kfree(command->completion);
4296 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4298 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4301 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4303 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4307 * Transfer the port index into real index in the HW port status
4308 * registers. Caculate offset between the port's PORTSC register
4309 * and port status base. Divide the number of per port register
4310 * to get the real index. The raw port number bases 1.
4312 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4314 struct xhci_hub *rhub;
4316 rhub = xhci_get_rhub(hcd);
4317 return rhub->ports[port1 - 1]->hw_portnum + 1;
4321 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4322 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4324 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4325 struct usb_device *udev, u16 max_exit_latency)
4327 struct xhci_virt_device *virt_dev;
4328 struct xhci_command *command;
4329 struct xhci_input_control_ctx *ctrl_ctx;
4330 struct xhci_slot_ctx *slot_ctx;
4331 unsigned long flags;
4334 spin_lock_irqsave(&xhci->lock, flags);
4336 virt_dev = xhci->devs[udev->slot_id];
4339 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4340 * xHC was re-initialized. Exit latency will be set later after
4341 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4344 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4345 spin_unlock_irqrestore(&xhci->lock, flags);
4349 /* Attempt to issue an Evaluate Context command to change the MEL. */
4350 command = xhci->lpm_command;
4351 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4353 spin_unlock_irqrestore(&xhci->lock, flags);
4354 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4359 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4360 spin_unlock_irqrestore(&xhci->lock, flags);
4362 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4363 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4364 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4365 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4366 slot_ctx->dev_state = 0;
4368 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4369 "Set up evaluate context for LPM MEL change.");
4371 /* Issue and wait for the evaluate context command. */
4372 ret = xhci_configure_endpoint(xhci, udev, command,
4376 spin_lock_irqsave(&xhci->lock, flags);
4377 virt_dev->current_mel = max_exit_latency;
4378 spin_unlock_irqrestore(&xhci->lock, flags);
4385 /* BESL to HIRD Encoding array for USB2 LPM */
4386 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4387 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4389 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4390 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4391 struct usb_device *udev)
4393 int u2del, besl, besl_host;
4394 int besl_device = 0;
4397 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4398 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4400 if (field & USB_BESL_SUPPORT) {
4401 for (besl_host = 0; besl_host < 16; besl_host++) {
4402 if (xhci_besl_encoding[besl_host] >= u2del)
4405 /* Use baseline BESL value as default */
4406 if (field & USB_BESL_BASELINE_VALID)
4407 besl_device = USB_GET_BESL_BASELINE(field);
4408 else if (field & USB_BESL_DEEP_VALID)
4409 besl_device = USB_GET_BESL_DEEP(field);
4414 besl_host = (u2del - 51) / 75 + 1;
4417 besl = besl_host + besl_device;
4424 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4425 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4432 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4434 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4435 l1 = udev->l1_params.timeout / 256;
4437 /* device has preferred BESLD */
4438 if (field & USB_BESL_DEEP_VALID) {
4439 besld = USB_GET_BESL_DEEP(field);
4443 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4446 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4447 struct usb_device *udev, int enable)
4449 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4450 struct xhci_port **ports;
4451 __le32 __iomem *pm_addr, *hlpm_addr;
4452 u32 pm_val, hlpm_val, field;
4453 unsigned int port_num;
4454 unsigned long flags;
4455 int hird, exit_latency;
4458 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4461 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4465 if (!udev->parent || udev->parent->parent ||
4466 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4469 if (udev->usb2_hw_lpm_capable != 1)
4472 spin_lock_irqsave(&xhci->lock, flags);
4474 ports = xhci->usb2_rhub.ports;
4475 port_num = udev->portnum - 1;
4476 pm_addr = ports[port_num]->addr + PORTPMSC;
4477 pm_val = readl(pm_addr);
4478 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4480 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4481 enable ? "enable" : "disable", port_num + 1);
4484 /* Host supports BESL timeout instead of HIRD */
4485 if (udev->usb2_hw_lpm_besl_capable) {
4486 /* if device doesn't have a preferred BESL value use a
4487 * default one which works with mixed HIRD and BESL
4488 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4490 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4491 if ((field & USB_BESL_SUPPORT) &&
4492 (field & USB_BESL_BASELINE_VALID))
4493 hird = USB_GET_BESL_BASELINE(field);
4495 hird = udev->l1_params.besl;
4497 exit_latency = xhci_besl_encoding[hird];
4498 spin_unlock_irqrestore(&xhci->lock, flags);
4500 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4501 * input context for link powermanagement evaluate
4502 * context commands. It is protected by hcd->bandwidth
4503 * mutex and is shared by all devices. We need to set
4504 * the max ext latency in USB 2 BESL LPM as well, so
4505 * use the same mutex and xhci_change_max_exit_latency()
4507 mutex_lock(hcd->bandwidth_mutex);
4508 ret = xhci_change_max_exit_latency(xhci, udev,
4510 mutex_unlock(hcd->bandwidth_mutex);
4514 spin_lock_irqsave(&xhci->lock, flags);
4516 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4517 writel(hlpm_val, hlpm_addr);
4521 hird = xhci_calculate_hird_besl(xhci, udev);
4524 pm_val &= ~PORT_HIRD_MASK;
4525 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4526 writel(pm_val, pm_addr);
4527 pm_val = readl(pm_addr);
4529 writel(pm_val, pm_addr);
4533 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4534 writel(pm_val, pm_addr);
4537 if (udev->usb2_hw_lpm_besl_capable) {
4538 spin_unlock_irqrestore(&xhci->lock, flags);
4539 mutex_lock(hcd->bandwidth_mutex);
4540 xhci_change_max_exit_latency(xhci, udev, 0);
4541 mutex_unlock(hcd->bandwidth_mutex);
4542 readl_poll_timeout(ports[port_num]->addr, pm_val,
4543 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4549 spin_unlock_irqrestore(&xhci->lock, flags);
4553 /* check if a usb2 port supports a given extened capability protocol
4554 * only USB2 ports extended protocol capability values are cached.
4555 * Return 1 if capability is supported
4557 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4558 unsigned capability)
4560 u32 port_offset, port_count;
4563 for (i = 0; i < xhci->num_ext_caps; i++) {
4564 if (xhci->ext_caps[i] & capability) {
4565 /* port offsets starts at 1 */
4566 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4567 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4568 if (port >= port_offset &&
4569 port < port_offset + port_count)
4576 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4578 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4579 int portnum = udev->portnum - 1;
4581 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4584 /* we only support lpm for non-hub device connected to root hub yet */
4585 if (!udev->parent || udev->parent->parent ||
4586 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4589 if (xhci->hw_lpm_support == 1 &&
4590 xhci_check_usb2_port_capability(
4591 xhci, portnum, XHCI_HLC)) {
4592 udev->usb2_hw_lpm_capable = 1;
4593 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4594 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4595 if (xhci_check_usb2_port_capability(xhci, portnum,
4597 udev->usb2_hw_lpm_besl_capable = 1;
4603 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4605 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4606 static unsigned long long xhci_service_interval_to_ns(
4607 struct usb_endpoint_descriptor *desc)
4609 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4612 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4613 enum usb3_link_state state)
4615 unsigned long long sel;
4616 unsigned long long pel;
4617 unsigned int max_sel_pel;
4622 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4623 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4624 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4625 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4629 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4630 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4631 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4635 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4637 return USB3_LPM_DISABLED;
4640 if (sel <= max_sel_pel && pel <= max_sel_pel)
4641 return USB3_LPM_DEVICE_INITIATED;
4643 if (sel > max_sel_pel)
4644 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4645 "due to long SEL %llu ms\n",
4648 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4649 "due to long PEL %llu ms\n",
4651 return USB3_LPM_DISABLED;
4654 /* The U1 timeout should be the maximum of the following values:
4655 * - For control endpoints, U1 system exit latency (SEL) * 3
4656 * - For bulk endpoints, U1 SEL * 5
4657 * - For interrupt endpoints:
4658 * - Notification EPs, U1 SEL * 3
4659 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4660 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4662 static unsigned long long xhci_calculate_intel_u1_timeout(
4663 struct usb_device *udev,
4664 struct usb_endpoint_descriptor *desc)
4666 unsigned long long timeout_ns;
4670 ep_type = usb_endpoint_type(desc);
4672 case USB_ENDPOINT_XFER_CONTROL:
4673 timeout_ns = udev->u1_params.sel * 3;
4675 case USB_ENDPOINT_XFER_BULK:
4676 timeout_ns = udev->u1_params.sel * 5;
4678 case USB_ENDPOINT_XFER_INT:
4679 intr_type = usb_endpoint_interrupt_type(desc);
4680 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4681 timeout_ns = udev->u1_params.sel * 3;
4684 /* Otherwise the calculation is the same as isoc eps */
4686 case USB_ENDPOINT_XFER_ISOC:
4687 timeout_ns = xhci_service_interval_to_ns(desc);
4688 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4689 if (timeout_ns < udev->u1_params.sel * 2)
4690 timeout_ns = udev->u1_params.sel * 2;
4699 /* Returns the hub-encoded U1 timeout value. */
4700 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4701 struct usb_device *udev,
4702 struct usb_endpoint_descriptor *desc)
4704 unsigned long long timeout_ns;
4706 /* Prevent U1 if service interval is shorter than U1 exit latency */
4707 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4708 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4709 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4710 return USB3_LPM_DISABLED;
4714 if (xhci->quirks & XHCI_INTEL_HOST)
4715 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4717 timeout_ns = udev->u1_params.sel;
4719 /* The U1 timeout is encoded in 1us intervals.
4720 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4722 if (timeout_ns == USB3_LPM_DISABLED)
4725 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4727 /* If the necessary timeout value is bigger than what we can set in the
4728 * USB 3.0 hub, we have to disable hub-initiated U1.
4730 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4732 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4733 "due to long timeout %llu ms\n", timeout_ns);
4734 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4737 /* The U2 timeout should be the maximum of:
4738 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4739 * - largest bInterval of any active periodic endpoint (to avoid going
4740 * into lower power link states between intervals).
4741 * - the U2 Exit Latency of the device
4743 static unsigned long long xhci_calculate_intel_u2_timeout(
4744 struct usb_device *udev,
4745 struct usb_endpoint_descriptor *desc)
4747 unsigned long long timeout_ns;
4748 unsigned long long u2_del_ns;
4750 timeout_ns = 10 * 1000 * 1000;
4752 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4753 (xhci_service_interval_to_ns(desc) > timeout_ns))
4754 timeout_ns = xhci_service_interval_to_ns(desc);
4756 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4757 if (u2_del_ns > timeout_ns)
4758 timeout_ns = u2_del_ns;
4763 /* Returns the hub-encoded U2 timeout value. */
4764 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4765 struct usb_device *udev,
4766 struct usb_endpoint_descriptor *desc)
4768 unsigned long long timeout_ns;
4770 /* Prevent U2 if service interval is shorter than U2 exit latency */
4771 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4772 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4773 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4774 return USB3_LPM_DISABLED;
4778 if (xhci->quirks & XHCI_INTEL_HOST)
4779 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4781 timeout_ns = udev->u2_params.sel;
4783 /* The U2 timeout is encoded in 256us intervals */
4784 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4785 /* If the necessary timeout value is bigger than what we can set in the
4786 * USB 3.0 hub, we have to disable hub-initiated U2.
4788 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4790 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4791 "due to long timeout %llu ms\n", timeout_ns);
4792 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4795 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4796 struct usb_device *udev,
4797 struct usb_endpoint_descriptor *desc,
4798 enum usb3_link_state state,
4801 if (state == USB3_LPM_U1)
4802 return xhci_calculate_u1_timeout(xhci, udev, desc);
4803 else if (state == USB3_LPM_U2)
4804 return xhci_calculate_u2_timeout(xhci, udev, desc);
4806 return USB3_LPM_DISABLED;
4809 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4810 struct usb_device *udev,
4811 struct usb_endpoint_descriptor *desc,
4812 enum usb3_link_state state,
4817 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4818 desc, state, timeout);
4820 /* If we found we can't enable hub-initiated LPM, and
4821 * the U1 or U2 exit latency was too high to allow
4822 * device-initiated LPM as well, then we will disable LPM
4823 * for this device, so stop searching any further.
4825 if (alt_timeout == USB3_LPM_DISABLED) {
4826 *timeout = alt_timeout;
4829 if (alt_timeout > *timeout)
4830 *timeout = alt_timeout;
4834 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4835 struct usb_device *udev,
4836 struct usb_host_interface *alt,
4837 enum usb3_link_state state,
4842 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4843 if (xhci_update_timeout_for_endpoint(xhci, udev,
4844 &alt->endpoint[j].desc, state, timeout))
4851 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4852 enum usb3_link_state state)
4854 struct usb_device *parent;
4855 unsigned int num_hubs;
4857 if (state == USB3_LPM_U2)
4860 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4861 for (parent = udev->parent, num_hubs = 0; parent->parent;
4862 parent = parent->parent)
4868 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4869 " below second-tier hub.\n");
4870 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4871 "to decrease power consumption.\n");
4875 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4876 struct usb_device *udev,
4877 enum usb3_link_state state)
4879 if (xhci->quirks & XHCI_INTEL_HOST)
4880 return xhci_check_intel_tier_policy(udev, state);
4885 /* Returns the U1 or U2 timeout that should be enabled.
4886 * If the tier check or timeout setting functions return with a non-zero exit
4887 * code, that means the timeout value has been finalized and we shouldn't look
4888 * at any more endpoints.
4890 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4891 struct usb_device *udev, enum usb3_link_state state)
4893 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4894 struct usb_host_config *config;
4897 u16 timeout = USB3_LPM_DISABLED;
4899 if (state == USB3_LPM_U1)
4901 else if (state == USB3_LPM_U2)
4904 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4909 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4912 /* Gather some information about the currently installed configuration
4913 * and alternate interface settings.
4915 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4919 config = udev->actconfig;
4923 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4924 struct usb_driver *driver;
4925 struct usb_interface *intf = config->interface[i];
4930 /* Check if any currently bound drivers want hub-initiated LPM
4933 if (intf->dev.driver) {
4934 driver = to_usb_driver(intf->dev.driver);
4935 if (driver && driver->disable_hub_initiated_lpm) {
4936 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4937 state_name, driver->name);
4938 timeout = xhci_get_timeout_no_hub_lpm(udev,
4940 if (timeout == USB3_LPM_DISABLED)
4945 /* Not sure how this could happen... */
4946 if (!intf->cur_altsetting)
4949 if (xhci_update_timeout_for_interface(xhci, udev,
4950 intf->cur_altsetting,
4957 static int calculate_max_exit_latency(struct usb_device *udev,
4958 enum usb3_link_state state_changed,
4959 u16 hub_encoded_timeout)
4961 unsigned long long u1_mel_us = 0;
4962 unsigned long long u2_mel_us = 0;
4963 unsigned long long mel_us = 0;
4969 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4970 hub_encoded_timeout == USB3_LPM_DISABLED);
4971 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4972 hub_encoded_timeout == USB3_LPM_DISABLED);
4974 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4975 hub_encoded_timeout != USB3_LPM_DISABLED);
4976 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4977 hub_encoded_timeout != USB3_LPM_DISABLED);
4979 /* If U1 was already enabled and we're not disabling it,
4980 * or we're going to enable U1, account for the U1 max exit latency.
4982 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4984 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4985 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4987 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4989 if (u1_mel_us > u2_mel_us)
4993 /* xHCI host controller max exit latency field is only 16 bits wide. */
4994 if (mel_us > MAX_EXIT) {
4995 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4996 "is too big.\n", mel_us);
5002 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5003 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5004 struct usb_device *udev, enum usb3_link_state state)
5006 struct xhci_hcd *xhci;
5007 u16 hub_encoded_timeout;
5011 xhci = hcd_to_xhci(hcd);
5012 /* The LPM timeout values are pretty host-controller specific, so don't
5013 * enable hub-initiated timeouts unless the vendor has provided
5014 * information about their timeout algorithm.
5016 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5017 !xhci->devs[udev->slot_id])
5018 return USB3_LPM_DISABLED;
5020 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5021 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5023 /* Max Exit Latency is too big, disable LPM. */
5024 hub_encoded_timeout = USB3_LPM_DISABLED;
5028 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5031 return hub_encoded_timeout;
5034 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5035 struct usb_device *udev, enum usb3_link_state state)
5037 struct xhci_hcd *xhci;
5040 xhci = hcd_to_xhci(hcd);
5041 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5042 !xhci->devs[udev->slot_id])
5045 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5046 return xhci_change_max_exit_latency(xhci, udev, mel);
5048 #else /* CONFIG_PM */
5050 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5051 struct usb_device *udev, int enable)
5056 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5061 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5062 struct usb_device *udev, enum usb3_link_state state)
5064 return USB3_LPM_DISABLED;
5067 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5068 struct usb_device *udev, enum usb3_link_state state)
5072 #endif /* CONFIG_PM */
5074 /*-------------------------------------------------------------------------*/
5076 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5077 * internal data structures for the device.
5079 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5080 struct usb_tt *tt, gfp_t mem_flags)
5082 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5083 struct xhci_virt_device *vdev;
5084 struct xhci_command *config_cmd;
5085 struct xhci_input_control_ctx *ctrl_ctx;
5086 struct xhci_slot_ctx *slot_ctx;
5087 unsigned long flags;
5088 unsigned think_time;
5091 /* Ignore root hubs */
5095 vdev = xhci->devs[hdev->slot_id];
5097 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5101 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5105 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5107 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5109 xhci_free_command(xhci, config_cmd);
5113 spin_lock_irqsave(&xhci->lock, flags);
5114 if (hdev->speed == USB_SPEED_HIGH &&
5115 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5116 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5117 xhci_free_command(xhci, config_cmd);
5118 spin_unlock_irqrestore(&xhci->lock, flags);
5122 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5123 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5124 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5125 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5127 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5128 * but it may be already set to 1 when setup an xHCI virtual
5129 * device, so clear it anyway.
5132 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5133 else if (hdev->speed == USB_SPEED_FULL)
5134 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5136 if (xhci->hci_version > 0x95) {
5137 xhci_dbg(xhci, "xHCI version %x needs hub "
5138 "TT think time and number of ports\n",
5139 (unsigned int) xhci->hci_version);
5140 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5141 /* Set TT think time - convert from ns to FS bit times.
5142 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5143 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5145 * xHCI 1.0: this field shall be 0 if the device is not a
5148 think_time = tt->think_time;
5149 if (think_time != 0)
5150 think_time = (think_time / 666) - 1;
5151 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5152 slot_ctx->tt_info |=
5153 cpu_to_le32(TT_THINK_TIME(think_time));
5155 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5156 "TT think time or number of ports\n",
5157 (unsigned int) xhci->hci_version);
5159 slot_ctx->dev_state = 0;
5160 spin_unlock_irqrestore(&xhci->lock, flags);
5162 xhci_dbg(xhci, "Set up %s for hub device.\n",
5163 (xhci->hci_version > 0x95) ?
5164 "configure endpoint" : "evaluate context");
5166 /* Issue and wait for the configure endpoint or
5167 * evaluate context command.
5169 if (xhci->hci_version > 0x95)
5170 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5173 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5176 xhci_free_command(xhci, config_cmd);
5180 static int xhci_get_frame(struct usb_hcd *hcd)
5182 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5183 /* EHCI mods by the periodic size. Why? */
5184 return readl(&xhci->run_regs->microframe_index) >> 3;
5187 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5189 struct xhci_hcd *xhci;
5191 * TODO: Check with DWC3 clients for sysdev according to
5194 struct device *dev = hcd->self.sysdev;
5195 unsigned int minor_rev;
5198 /* Accept arbitrarily long scatter-gather lists */
5199 hcd->self.sg_tablesize = ~0;
5201 /* support to build packet from discontinuous buffers */
5202 hcd->self.no_sg_constraint = 1;
5204 /* XHCI controllers don't stop the ep queue on short packets :| */
5205 hcd->self.no_stop_on_short = 1;
5207 xhci = hcd_to_xhci(hcd);
5209 if (usb_hcd_is_primary_hcd(hcd)) {
5210 xhci->main_hcd = hcd;
5211 xhci->usb2_rhub.hcd = hcd;
5212 /* Mark the first roothub as being USB 2.0.
5213 * The xHCI driver will register the USB 3.0 roothub.
5215 hcd->speed = HCD_USB2;
5216 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5218 * USB 2.0 roothub under xHCI has an integrated TT,
5219 * (rate matching hub) as opposed to having an OHCI/UHCI
5220 * companion controller.
5225 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5226 * should return 0x31 for sbrn, or that the minor revision
5227 * is a two digit BCD containig minor and sub-minor numbers.
5228 * This was later clarified in xHCI 1.2.
5230 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5231 * minor revision set to 0x1 instead of 0x10.
5233 if (xhci->usb3_rhub.min_rev == 0x1)
5236 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5238 switch (minor_rev) {
5240 hcd->speed = HCD_USB32;
5241 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5242 hcd->self.root_hub->rx_lanes = 2;
5243 hcd->self.root_hub->tx_lanes = 2;
5246 hcd->speed = HCD_USB31;
5247 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5250 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5252 minor_rev ? "Enhanced " : "");
5254 xhci->usb3_rhub.hcd = hcd;
5255 /* xHCI private pointer was set in xhci_pci_probe for the second
5256 * registered roothub.
5261 mutex_init(&xhci->mutex);
5262 xhci->cap_regs = hcd->regs;
5263 xhci->op_regs = hcd->regs +
5264 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5265 xhci->run_regs = hcd->regs +
5266 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5267 /* Cache read-only capability registers */
5268 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5269 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5270 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5271 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5272 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5273 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5274 if (xhci->hci_version > 0x100)
5275 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5277 xhci->quirks |= quirks;
5279 get_quirks(dev, xhci);
5281 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5282 * success event after a short transfer. This quirk will ignore such
5285 if (xhci->hci_version > 0x96)
5286 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5288 /* Make sure the HC is halted. */
5289 retval = xhci_halt(xhci);
5293 xhci_zero_64b_regs(xhci);
5295 xhci_dbg(xhci, "Resetting HCD\n");
5296 /* Reset the internal HC memory state and registers. */
5297 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5300 xhci_dbg(xhci, "Reset complete\n");
5303 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5304 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5305 * address memory pointers actually. So, this driver clears the AC64
5306 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5307 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5309 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5310 xhci->hcc_params &= ~BIT(0);
5312 /* Set dma_mask and coherent_dma_mask to 64-bits,
5313 * if xHC supports 64-bit addressing */
5314 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5315 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5316 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5317 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5320 * This is to avoid error in cases where a 32-bit USB
5321 * controller is used on a 64-bit capable system.
5323 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5326 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5327 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5330 xhci_dbg(xhci, "Calling HCD init\n");
5331 /* Initialize HCD and host controller data structures. */
5332 retval = xhci_init(hcd);
5335 xhci_dbg(xhci, "Called HCD init\n");
5337 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5338 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5342 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5344 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5345 struct usb_host_endpoint *ep)
5347 struct xhci_hcd *xhci;
5348 struct usb_device *udev;
5349 unsigned int slot_id;
5350 unsigned int ep_index;
5351 unsigned long flags;
5353 xhci = hcd_to_xhci(hcd);
5355 spin_lock_irqsave(&xhci->lock, flags);
5356 udev = (struct usb_device *)ep->hcpriv;
5357 slot_id = udev->slot_id;
5358 ep_index = xhci_get_endpoint_index(&ep->desc);
5360 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5361 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5362 spin_unlock_irqrestore(&xhci->lock, flags);
5365 static const struct hc_driver xhci_hc_driver = {
5366 .description = "xhci-hcd",
5367 .product_desc = "xHCI Host Controller",
5368 .hcd_priv_size = sizeof(struct xhci_hcd),
5371 * generic hardware linkage
5374 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5378 * basic lifecycle operations
5380 .reset = NULL, /* set in xhci_init_driver() */
5383 .shutdown = xhci_shutdown,
5386 * managing i/o requests and associated device resources
5388 .map_urb_for_dma = xhci_map_urb_for_dma,
5389 .urb_enqueue = xhci_urb_enqueue,
5390 .urb_dequeue = xhci_urb_dequeue,
5391 .alloc_dev = xhci_alloc_dev,
5392 .free_dev = xhci_free_dev,
5393 .alloc_streams = xhci_alloc_streams,
5394 .free_streams = xhci_free_streams,
5395 .add_endpoint = xhci_add_endpoint,
5396 .drop_endpoint = xhci_drop_endpoint,
5397 .endpoint_disable = xhci_endpoint_disable,
5398 .endpoint_reset = xhci_endpoint_reset,
5399 .check_bandwidth = xhci_check_bandwidth,
5400 .reset_bandwidth = xhci_reset_bandwidth,
5401 .address_device = xhci_address_device,
5402 .enable_device = xhci_enable_device,
5403 .update_hub_device = xhci_update_hub_device,
5404 .reset_device = xhci_discover_or_reset_device,
5407 * scheduling support
5409 .get_frame_number = xhci_get_frame,
5414 .hub_control = xhci_hub_control,
5415 .hub_status_data = xhci_hub_status_data,
5416 .bus_suspend = xhci_bus_suspend,
5417 .bus_resume = xhci_bus_resume,
5418 .get_resuming_ports = xhci_get_resuming_ports,
5421 * call back when device connected and addressed
5423 .update_device = xhci_update_device,
5424 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5425 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5426 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5427 .find_raw_port_number = xhci_find_raw_port_number,
5428 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5431 void xhci_init_driver(struct hc_driver *drv,
5432 const struct xhci_driver_overrides *over)
5436 /* Copy the generic table to drv then apply the overrides */
5437 *drv = xhci_hc_driver;
5440 drv->hcd_priv_size += over->extra_priv_size;
5442 drv->reset = over->reset;
5444 drv->start = over->start;
5445 if (over->check_bandwidth)
5446 drv->check_bandwidth = over->check_bandwidth;
5447 if (over->reset_bandwidth)
5448 drv->reset_bandwidth = over->reset_bandwidth;
5451 EXPORT_SYMBOL_GPL(xhci_init_driver);
5453 MODULE_DESCRIPTION(DRIVER_DESC);
5454 MODULE_AUTHOR(DRIVER_AUTHOR);
5455 MODULE_LICENSE("GPL");
5457 static int __init xhci_hcd_init(void)
5460 * Check the compiler generated sizes of structures that must be laid
5461 * out in specific ways for hardware access.
5463 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5464 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5465 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5466 /* xhci_device_control has eight fields, and also
5467 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5469 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5470 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5471 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5472 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5473 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5474 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5475 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5480 xhci_debugfs_create_root();
5486 * If an init function is provided, an exit function must also be provided
5487 * to allow module unload.
5489 static void __exit xhci_hcd_fini(void)
5491 xhci_debugfs_remove_root();
5494 module_init(xhci_hcd_init);
5495 module_exit(xhci_hcd_fini);