1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iommu.h>
13 #include <linux/iopoll.h>
14 #include <linux/irq.h>
15 #include <linux/log2.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/slab.h>
19 #include <linux/dmi.h>
20 #include <linux/dma-mapping.h>
23 #include "xhci-trace.h"
25 #include "xhci-debugfs.h"
26 #include "xhci-dbgcap.h"
28 #define DRIVER_AUTHOR "Sarah Sharp"
29 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
31 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
33 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
34 static int link_quirk;
35 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
36 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
38 static unsigned long long quirks;
39 module_param(quirks, ullong, S_IRUGO);
40 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
42 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
44 struct xhci_segment *seg = ring->first_seg;
46 if (!td || !td->start_seg)
49 if (seg == td->start_seg)
52 } while (seg && seg != ring->first_seg);
58 * xhci_handshake - spin reading hc until handshake completes or fails
59 * @ptr: address of hc register to be read
60 * @mask: bits to look at in result of read
61 * @done: value of those bits when handshake succeeds
62 * @usec: timeout in microseconds
64 * Returns negative errno, or zero on success
66 * Success happens when the "mask" bits have the specified value (hardware
67 * handshake done). There are two failure modes: "usec" have passed (major
68 * hardware flakeout), or the register reads as all-ones (hardware removed).
70 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
75 ret = readl_poll_timeout_atomic(ptr, result,
76 (result & mask) == done ||
79 if (result == U32_MAX) /* card removed */
86 * Disable interrupts and begin the xHCI halting process.
88 void xhci_quiesce(struct xhci_hcd *xhci)
95 halted = readl(&xhci->op_regs->status) & STS_HALT;
99 cmd = readl(&xhci->op_regs->command);
101 writel(cmd, &xhci->op_regs->command);
105 * Force HC into halt state.
107 * Disable any IRQs and clear the run/stop bit.
108 * HC will complete any current and actively pipelined transactions, and
109 * should halt within 16 ms of the run/stop bit being cleared.
110 * Read HC Halted bit in the status register to see when the HC is finished.
112 int xhci_halt(struct xhci_hcd *xhci)
115 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
118 ret = xhci_handshake(&xhci->op_regs->status,
119 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
121 xhci_warn(xhci, "Host halt failed, %d\n", ret);
124 xhci->xhc_state |= XHCI_STATE_HALTED;
125 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
130 * Set the run bit and wait for the host to be running.
132 int xhci_start(struct xhci_hcd *xhci)
137 temp = readl(&xhci->op_regs->command);
139 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
141 writel(temp, &xhci->op_regs->command);
144 * Wait for the HCHalted Status bit to be 0 to indicate the host is
147 ret = xhci_handshake(&xhci->op_regs->status,
148 STS_HALT, 0, XHCI_MAX_HALT_USEC);
149 if (ret == -ETIMEDOUT)
150 xhci_err(xhci, "Host took too long to start, "
151 "waited %u microseconds.\n",
154 /* clear state flags. Including dying, halted or removing */
156 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
165 * This resets pipelines, timers, counters, state machines, etc.
166 * Transactions will be terminated immediately, and operational registers
167 * will be set to their defaults.
169 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
175 state = readl(&xhci->op_regs->status);
177 if (state == ~(u32)0) {
178 xhci_warn(xhci, "Host not accessible, reset failed.\n");
182 if ((state & STS_HALT) == 0) {
183 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
187 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
188 command = readl(&xhci->op_regs->command);
189 command |= CMD_RESET;
190 writel(command, &xhci->op_regs->command);
192 /* Existing Intel xHCI controllers require a delay of 1 mS,
193 * after setting the CMD_RESET bit, and before accessing any
194 * HC registers. This allows the HC to complete the
195 * reset operation and be ready for HC register access.
196 * Without this delay, the subsequent HC register access,
197 * may result in a system hang very rarely.
199 if (xhci->quirks & XHCI_INTEL_HOST)
202 ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
206 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
207 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
209 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
210 "Wait for controller to be ready for doorbell rings");
212 * xHCI cannot write to any doorbells or operational registers other
213 * than status until the "Controller Not Ready" flag is cleared.
215 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
217 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
218 xhci->usb2_rhub.bus_state.suspended_ports = 0;
219 xhci->usb2_rhub.bus_state.resuming_ports = 0;
220 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
221 xhci->usb3_rhub.bus_state.suspended_ports = 0;
222 xhci->usb3_rhub.bus_state.resuming_ports = 0;
227 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
229 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
230 struct iommu_domain *domain;
236 * Some Renesas controllers get into a weird state if they are
237 * reset while programmed with 64bit addresses (they will preserve
238 * the top half of the address in internal, non visible
239 * registers). You end up with half the address coming from the
240 * kernel, and the other half coming from the firmware. Also,
241 * changing the programming leads to extra accesses even if the
242 * controller is supposed to be halted. The controller ends up with
243 * a fatal fault, and is then ripe for being properly reset.
245 * Special care is taken to only apply this if the device is behind
246 * an iommu. Doing anything when there is no iommu is definitely
249 domain = iommu_get_domain_for_dev(dev);
250 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !domain ||
251 domain->type == IOMMU_DOMAIN_IDENTITY)
254 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
256 /* Clear HSEIE so that faults do not get signaled */
257 val = readl(&xhci->op_regs->command);
259 writel(val, &xhci->op_regs->command);
261 /* Clear HSE (aka FATAL) */
262 val = readl(&xhci->op_regs->status);
264 writel(val, &xhci->op_regs->status);
266 /* Now zero the registers, and brace for impact */
267 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
268 if (upper_32_bits(val))
269 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
270 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
271 if (upper_32_bits(val))
272 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
274 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
275 ARRAY_SIZE(xhci->run_regs->ir_set));
277 for (i = 0; i < intrs; i++) {
278 struct xhci_intr_reg __iomem *ir;
280 ir = &xhci->run_regs->ir_set[i];
281 val = xhci_read_64(xhci, &ir->erst_base);
282 if (upper_32_bits(val))
283 xhci_write_64(xhci, 0, &ir->erst_base);
284 val= xhci_read_64(xhci, &ir->erst_dequeue);
285 if (upper_32_bits(val))
286 xhci_write_64(xhci, 0, &ir->erst_dequeue);
289 /* Wait for the fault to appear. It will be cleared on reset */
290 err = xhci_handshake(&xhci->op_regs->status,
291 STS_FATAL, STS_FATAL,
294 xhci_info(xhci, "Fault detected\n");
297 #ifdef CONFIG_USB_PCI
301 static int xhci_setup_msi(struct xhci_hcd *xhci)
305 * TODO:Check with MSI Soc for sysdev
307 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
309 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
311 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
312 "failed to allocate MSI entry");
316 ret = request_irq(pdev->irq, xhci_msi_irq,
317 0, "xhci_hcd", xhci_to_hcd(xhci));
319 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
320 "disable MSI interrupt");
321 pci_free_irq_vectors(pdev);
330 static int xhci_setup_msix(struct xhci_hcd *xhci)
333 struct usb_hcd *hcd = xhci_to_hcd(xhci);
334 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
337 * calculate number of msi-x vectors supported.
338 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
339 * with max number of interrupters based on the xhci HCSPARAMS1.
340 * - num_online_cpus: maximum msi-x vectors per CPUs core.
341 * Add additional 1 vector to ensure always available interrupt.
343 xhci->msix_count = min(num_online_cpus() + 1,
344 HCS_MAX_INTRS(xhci->hcs_params1));
346 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
349 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
350 "Failed to enable MSI-X");
354 for (i = 0; i < xhci->msix_count; i++) {
355 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
356 "xhci_hcd", xhci_to_hcd(xhci));
361 hcd->msix_enabled = 1;
365 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
367 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
368 pci_free_irq_vectors(pdev);
372 /* Free any IRQs and disable MSI-X */
373 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
375 struct usb_hcd *hcd = xhci_to_hcd(xhci);
376 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
378 if (xhci->quirks & XHCI_PLAT)
381 /* return if using legacy interrupt */
385 if (hcd->msix_enabled) {
388 for (i = 0; i < xhci->msix_count; i++)
389 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
391 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
394 pci_free_irq_vectors(pdev);
395 hcd->msix_enabled = 0;
398 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
400 struct usb_hcd *hcd = xhci_to_hcd(xhci);
402 if (hcd->msix_enabled) {
403 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
406 for (i = 0; i < xhci->msix_count; i++)
407 synchronize_irq(pci_irq_vector(pdev, i));
411 static int xhci_try_enable_msi(struct usb_hcd *hcd)
413 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
414 struct pci_dev *pdev;
417 /* The xhci platform device has set up IRQs through usb_add_hcd. */
418 if (xhci->quirks & XHCI_PLAT)
421 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
423 * Some Fresco Logic host controllers advertise MSI, but fail to
424 * generate interrupts. Don't even try to enable MSI.
426 if (xhci->quirks & XHCI_BROKEN_MSI)
429 /* unregister the legacy interrupt */
431 free_irq(hcd->irq, hcd);
434 ret = xhci_setup_msix(xhci);
436 /* fall back to msi*/
437 ret = xhci_setup_msi(xhci);
440 hcd->msi_enabled = 1;
445 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
450 if (!strlen(hcd->irq_descr))
451 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
452 hcd->driver->description, hcd->self.busnum);
454 /* fall back to legacy interrupt*/
455 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
456 hcd->irq_descr, hcd);
458 xhci_err(xhci, "request interrupt %d failed\n",
462 hcd->irq = pdev->irq;
468 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
473 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
477 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
483 static void compliance_mode_recovery(struct timer_list *t)
485 struct xhci_hcd *xhci;
487 struct xhci_hub *rhub;
491 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
492 rhub = &xhci->usb3_rhub;
494 for (i = 0; i < rhub->num_ports; i++) {
495 temp = readl(rhub->ports[i]->addr);
496 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
498 * Compliance Mode Detected. Letting USB Core
499 * handle the Warm Reset
501 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
502 "Compliance mode detected->port %d",
504 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
505 "Attempting compliance mode recovery");
506 hcd = xhci->shared_hcd;
508 if (hcd->state == HC_STATE_SUSPENDED)
509 usb_hcd_resume_root_hub(hcd);
511 usb_hcd_poll_rh_status(hcd);
515 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
516 mod_timer(&xhci->comp_mode_recovery_timer,
517 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
521 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
522 * that causes ports behind that hardware to enter compliance mode sometimes.
523 * The quirk creates a timer that polls every 2 seconds the link state of
524 * each host controller's port and recovers it by issuing a Warm reset
525 * if Compliance mode is detected, otherwise the port will become "dead" (no
526 * device connections or disconnections will be detected anymore). Becasue no
527 * status event is generated when entering compliance mode (per xhci spec),
528 * this quirk is needed on systems that have the failing hardware installed.
530 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
532 xhci->port_status_u0 = 0;
533 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
535 xhci->comp_mode_recovery_timer.expires = jiffies +
536 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
538 add_timer(&xhci->comp_mode_recovery_timer);
539 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
540 "Compliance mode recovery timer initialized");
544 * This function identifies the systems that have installed the SN65LVPE502CP
545 * USB3.0 re-driver and that need the Compliance Mode Quirk.
547 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
549 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
551 const char *dmi_product_name, *dmi_sys_vendor;
553 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
554 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
555 if (!dmi_product_name || !dmi_sys_vendor)
558 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
561 if (strstr(dmi_product_name, "Z420") ||
562 strstr(dmi_product_name, "Z620") ||
563 strstr(dmi_product_name, "Z820") ||
564 strstr(dmi_product_name, "Z1 Workstation"))
570 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
572 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
577 * Initialize memory for HCD and xHC (one-time init).
579 * Program the PAGESIZE register, initialize the device context array, create
580 * device contexts (?), set up a command ring segment (or two?), create event
581 * ring (one for now).
583 static int xhci_init(struct usb_hcd *hcd)
585 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
588 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
589 spin_lock_init(&xhci->lock);
590 if (xhci->hci_version == 0x95 && link_quirk) {
591 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
592 "QUIRK: Not clearing Link TRB chain bits.");
593 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
595 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
596 "xHCI doesn't need link TRB QUIRK");
598 retval = xhci_mem_init(xhci, GFP_KERNEL);
599 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
601 /* Initializing Compliance Mode Recovery Data If Needed */
602 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
603 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
604 compliance_mode_recovery_timer_init(xhci);
610 /*-------------------------------------------------------------------------*/
613 static int xhci_run_finished(struct xhci_hcd *xhci)
615 if (xhci_start(xhci)) {
619 xhci->shared_hcd->state = HC_STATE_RUNNING;
620 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
622 if (xhci->quirks & XHCI_NEC_HOST)
623 xhci_ring_cmd_db(xhci);
625 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
626 "Finished xhci_run for USB3 roothub");
631 * Start the HC after it was halted.
633 * This function is called by the USB core when the HC driver is added.
634 * Its opposite is xhci_stop().
636 * xhci_init() must be called once before this function can be called.
637 * Reset the HC, enable device slot contexts, program DCBAAP, and
638 * set command ring pointer and event ring pointer.
640 * Setup MSI-X vectors and enable interrupts.
642 int xhci_run(struct usb_hcd *hcd)
647 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
649 /* Start the xHCI host controller running only after the USB 2.0 roothub
653 hcd->uses_new_polling = 1;
654 if (!usb_hcd_is_primary_hcd(hcd))
655 return xhci_run_finished(xhci);
657 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
659 ret = xhci_try_enable_msi(hcd);
663 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
664 temp_64 &= ~ERST_PTR_MASK;
665 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
666 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
668 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
669 "// Set the interrupt modulation register");
670 temp = readl(&xhci->ir_set->irq_control);
671 temp &= ~ER_IRQ_INTERVAL_MASK;
672 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
673 writel(temp, &xhci->ir_set->irq_control);
675 /* Set the HCD state before we enable the irqs */
676 temp = readl(&xhci->op_regs->command);
678 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
679 "// Enable interrupts, cmd = 0x%x.", temp);
680 writel(temp, &xhci->op_regs->command);
682 temp = readl(&xhci->ir_set->irq_pending);
683 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
684 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
685 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
686 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
688 if (xhci->quirks & XHCI_NEC_HOST) {
689 struct xhci_command *command;
691 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
695 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
696 TRB_TYPE(TRB_NEC_GET_FW));
698 xhci_free_command(xhci, command);
700 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
701 "Finished xhci_run for USB2 roothub");
703 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
707 xhci_debugfs_init(xhci);
711 EXPORT_SYMBOL_GPL(xhci_run);
716 * This function is called by the USB core when the HC driver is removed.
717 * Its opposite is xhci_run().
719 * Disable device contexts, disable IRQs, and quiesce the HC.
720 * Reset the HC, finish any completed transactions, and cleanup memory.
722 static void xhci_stop(struct usb_hcd *hcd)
725 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
727 mutex_lock(&xhci->mutex);
729 /* Only halt host and free memory after both hcds are removed */
730 if (!usb_hcd_is_primary_hcd(hcd)) {
731 mutex_unlock(&xhci->mutex);
737 spin_lock_irq(&xhci->lock);
738 xhci->xhc_state |= XHCI_STATE_HALTED;
739 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
741 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
742 spin_unlock_irq(&xhci->lock);
744 xhci_cleanup_msix(xhci);
746 /* Deleting Compliance Mode Recovery Timer */
747 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
748 (!(xhci_all_ports_seen_u0(xhci)))) {
749 del_timer_sync(&xhci->comp_mode_recovery_timer);
750 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
751 "%s: compliance mode recovery timer deleted",
755 if (xhci->quirks & XHCI_AMD_PLL_FIX)
758 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
759 "// Disabling event ring interrupts");
760 temp = readl(&xhci->op_regs->status);
761 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
762 temp = readl(&xhci->ir_set->irq_pending);
763 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
765 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
766 xhci_mem_cleanup(xhci);
767 xhci_debugfs_exit(xhci);
768 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
769 "xhci_stop completed - status = %x",
770 readl(&xhci->op_regs->status));
771 mutex_unlock(&xhci->mutex);
775 * Shutdown HC (not bus-specific)
777 * This is called when the machine is rebooting or halting. We assume that the
778 * machine will be powered off, and the HC's internal state will be reset.
779 * Don't bother to free memory.
781 * This will only ever be called with the main usb_hcd (the USB3 roothub).
783 void xhci_shutdown(struct usb_hcd *hcd)
785 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
787 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
788 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
790 /* Don't poll the roothubs after shutdown. */
791 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
792 __func__, hcd->self.busnum);
793 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
794 del_timer_sync(&hcd->rh_timer);
796 if (xhci->shared_hcd) {
797 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
798 del_timer_sync(&xhci->shared_hcd->rh_timer);
801 spin_lock_irq(&xhci->lock);
805 * Workaround for spurious wakeps at shutdown with HSW, and for boot
806 * firmware delay in ADL-P PCH if port are left in U3 at shutdown
808 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
809 xhci->quirks & XHCI_RESET_TO_DEFAULT)
810 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
812 spin_unlock_irq(&xhci->lock);
814 xhci_cleanup_msix(xhci);
816 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
817 "xhci_shutdown completed - status = %x",
818 readl(&xhci->op_regs->status));
820 EXPORT_SYMBOL_GPL(xhci_shutdown);
823 static void xhci_save_registers(struct xhci_hcd *xhci)
825 xhci->s3.command = readl(&xhci->op_regs->command);
826 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
827 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
828 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
829 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
830 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
831 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
832 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
833 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
836 static void xhci_restore_registers(struct xhci_hcd *xhci)
838 writel(xhci->s3.command, &xhci->op_regs->command);
839 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
840 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
841 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
842 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
843 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
844 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
845 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
846 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
849 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
853 /* step 2: initialize command ring buffer */
854 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
855 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
856 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
857 xhci->cmd_ring->dequeue) &
858 (u64) ~CMD_RING_RSVD_BITS) |
859 xhci->cmd_ring->cycle_state;
860 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
861 "// Setting command ring address to 0x%llx",
862 (long unsigned long) val_64);
863 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
867 * The whole command ring must be cleared to zero when we suspend the host.
869 * The host doesn't save the command ring pointer in the suspend well, so we
870 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
871 * aligned, because of the reserved bits in the command ring dequeue pointer
872 * register. Therefore, we can't just set the dequeue pointer back in the
873 * middle of the ring (TRBs are 16-byte aligned).
875 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
877 struct xhci_ring *ring;
878 struct xhci_segment *seg;
880 ring = xhci->cmd_ring;
884 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
885 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
886 cpu_to_le32(~TRB_CYCLE);
888 } while (seg != ring->deq_seg);
890 /* Reset the software enqueue and dequeue pointers */
891 ring->deq_seg = ring->first_seg;
892 ring->dequeue = ring->first_seg->trbs;
893 ring->enq_seg = ring->deq_seg;
894 ring->enqueue = ring->dequeue;
896 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
898 * Ring is now zeroed, so the HW should look for change of ownership
899 * when the cycle bit is set to 1.
901 ring->cycle_state = 1;
904 * Reset the hardware dequeue pointer.
905 * Yes, this will need to be re-written after resume, but we're paranoid
906 * and want to make sure the hardware doesn't access bogus memory
907 * because, say, the BIOS or an SMI started the host without changing
908 * the command ring pointers.
910 xhci_set_cmd_ring_deq(xhci);
914 * Disable port wake bits if do_wakeup is not set.
916 * Also clear a possible internal port wake state left hanging for ports that
917 * detected termination but never successfully enumerated (trained to 0U).
918 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
919 * at enumeration clears this wake, force one here as well for unconnected ports
922 static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
923 struct xhci_hub *rhub,
930 spin_lock_irqsave(&xhci->lock, flags);
932 for (i = 0; i < rhub->num_ports; i++) {
933 portsc = readl(rhub->ports[i]->addr);
934 t1 = xhci_port_state_to_neutral(portsc);
937 /* clear wake bits if do_wake is not set */
939 t2 &= ~PORT_WAKE_BITS;
941 /* Don't touch csc bit if connected or connect change is set */
942 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
946 writel(t2, rhub->ports[i]->addr);
947 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
948 rhub->hcd->self.busnum, i + 1, portsc, t2);
951 spin_unlock_irqrestore(&xhci->lock, flags);
954 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
956 struct xhci_port **ports;
961 status = readl(&xhci->op_regs->status);
962 if (status & STS_EINT)
965 * Checking STS_EINT is not enough as there is a lag between a change
966 * bit being set and the Port Status Change Event that it generated
967 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
970 port_index = xhci->usb2_rhub.num_ports;
971 ports = xhci->usb2_rhub.ports;
972 while (port_index--) {
973 portsc = readl(ports[port_index]->addr);
974 if (portsc & PORT_CHANGE_MASK ||
975 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
978 port_index = xhci->usb3_rhub.num_ports;
979 ports = xhci->usb3_rhub.ports;
980 while (port_index--) {
981 portsc = readl(ports[port_index]->addr);
982 if (portsc & PORT_CHANGE_MASK ||
983 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
990 * Stop HC (not bus-specific)
992 * This is called when the machine transition into S3/S4 mode.
995 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
998 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
999 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1006 if (hcd->state != HC_STATE_SUSPENDED ||
1007 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
1010 /* Clear root port wake on bits if wakeup not allowed. */
1011 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
1012 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
1014 if (!HCD_HW_ACCESSIBLE(hcd))
1017 xhci_dbc_suspend(xhci);
1019 /* Don't poll the roothubs on bus suspend. */
1020 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1021 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1022 del_timer_sync(&hcd->rh_timer);
1023 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1024 del_timer_sync(&xhci->shared_hcd->rh_timer);
1026 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1027 usleep_range(1000, 1500);
1029 spin_lock_irq(&xhci->lock);
1030 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1031 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1032 /* step 1: stop endpoint */
1033 /* skipped assuming that port suspend has done */
1035 /* step 2: clear Run/Stop bit */
1036 command = readl(&xhci->op_regs->command);
1037 command &= ~CMD_RUN;
1038 writel(command, &xhci->op_regs->command);
1040 /* Some chips from Fresco Logic need an extraordinary delay */
1041 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1043 if (xhci_handshake(&xhci->op_regs->status,
1044 STS_HALT, STS_HALT, delay)) {
1045 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1046 spin_unlock_irq(&xhci->lock);
1049 xhci_clear_command_ring(xhci);
1051 /* step 3: save registers */
1052 xhci_save_registers(xhci);
1054 /* step 4: set CSS flag */
1055 command = readl(&xhci->op_regs->command);
1057 writel(command, &xhci->op_regs->command);
1058 xhci->broken_suspend = 0;
1059 if (xhci_handshake(&xhci->op_regs->status,
1060 STS_SAVE, 0, 20 * 1000)) {
1062 * AMD SNPS xHC 3.0 occasionally does not clear the
1063 * SSS bit of USBSTS and when driver tries to poll
1064 * to see if the xHC clears BIT(8) which never happens
1065 * and driver assumes that controller is not responding
1066 * and times out. To workaround this, its good to check
1067 * if SRE and HCE bits are not set (as per xhci
1068 * Section 5.4.2) and bypass the timeout.
1070 res = readl(&xhci->op_regs->status);
1071 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1072 (((res & STS_SRE) == 0) &&
1073 ((res & STS_HCE) == 0))) {
1074 xhci->broken_suspend = 1;
1076 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1077 spin_unlock_irq(&xhci->lock);
1081 spin_unlock_irq(&xhci->lock);
1084 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1085 * is about to be suspended.
1087 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1088 (!(xhci_all_ports_seen_u0(xhci)))) {
1089 del_timer_sync(&xhci->comp_mode_recovery_timer);
1090 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1091 "%s: compliance mode recovery timer deleted",
1095 /* step 5: remove core well power */
1096 /* synchronize irq when using MSI-X */
1097 xhci_msix_sync_irqs(xhci);
1101 EXPORT_SYMBOL_GPL(xhci_suspend);
1104 * start xHC (not bus-specific)
1106 * This is called when the machine transition from S3/S4 mode.
1109 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1111 u32 command, temp = 0;
1112 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1113 struct usb_hcd *secondary_hcd;
1115 bool comp_timer_running = false;
1116 bool pending_portevent = false;
1117 bool reinit_xhc = false;
1122 /* Wait a bit if either of the roothubs need to settle from the
1123 * transition into bus suspend.
1126 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1127 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1130 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1131 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1133 spin_lock_irq(&xhci->lock);
1135 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1140 * Some controllers might lose power during suspend, so wait
1141 * for controller not ready bit to clear, just as in xHC init.
1143 retval = xhci_handshake(&xhci->op_regs->status,
1144 STS_CNR, 0, 10 * 1000 * 1000);
1146 xhci_warn(xhci, "Controller not ready at resume %d\n",
1148 spin_unlock_irq(&xhci->lock);
1151 /* step 1: restore register */
1152 xhci_restore_registers(xhci);
1153 /* step 2: initialize command ring buffer */
1154 xhci_set_cmd_ring_deq(xhci);
1155 /* step 3: restore state and start state*/
1156 /* step 3: set CRS flag */
1157 command = readl(&xhci->op_regs->command);
1159 writel(command, &xhci->op_regs->command);
1161 * Some controllers take up to 55+ ms to complete the controller
1162 * restore so setting the timeout to 100ms. Xhci specification
1163 * doesn't mention any timeout value.
1165 if (xhci_handshake(&xhci->op_regs->status,
1166 STS_RESTORE, 0, 100 * 1000)) {
1167 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1168 spin_unlock_irq(&xhci->lock);
1173 temp = readl(&xhci->op_regs->status);
1175 /* re-initialize the HC on Restore Error, or Host Controller Error */
1176 if (temp & (STS_SRE | STS_HCE)) {
1178 if (!xhci->broken_suspend)
1179 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1183 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1184 !(xhci_all_ports_seen_u0(xhci))) {
1185 del_timer_sync(&xhci->comp_mode_recovery_timer);
1186 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1187 "Compliance Mode Recovery Timer deleted!");
1190 /* Let the USB core know _both_ roothubs lost power. */
1191 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1192 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1194 xhci_dbg(xhci, "Stop HCD\n");
1196 xhci_zero_64b_regs(xhci);
1197 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1198 spin_unlock_irq(&xhci->lock);
1201 xhci_cleanup_msix(xhci);
1203 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1204 temp = readl(&xhci->op_regs->status);
1205 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1206 temp = readl(&xhci->ir_set->irq_pending);
1207 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1209 xhci_dbg(xhci, "cleaning up memory\n");
1210 xhci_mem_cleanup(xhci);
1211 xhci_debugfs_exit(xhci);
1212 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1213 readl(&xhci->op_regs->status));
1215 /* USB core calls the PCI reinit and start functions twice:
1216 * first with the primary HCD, and then with the secondary HCD.
1217 * If we don't do the same, the host will never be started.
1219 if (!usb_hcd_is_primary_hcd(hcd))
1220 secondary_hcd = hcd;
1222 secondary_hcd = xhci->shared_hcd;
1224 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1225 retval = xhci_init(hcd->primary_hcd);
1228 comp_timer_running = true;
1230 xhci_dbg(xhci, "Start the primary HCD\n");
1231 retval = xhci_run(hcd->primary_hcd);
1233 xhci_dbg(xhci, "Start the secondary HCD\n");
1234 retval = xhci_run(secondary_hcd);
1236 hcd->state = HC_STATE_SUSPENDED;
1237 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1241 /* step 4: set Run/Stop bit */
1242 command = readl(&xhci->op_regs->command);
1244 writel(command, &xhci->op_regs->command);
1245 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1248 /* step 5: walk topology and initialize portsc,
1249 * portpmsc and portli
1251 /* this is done in bus_resume */
1253 /* step 6: restart each of the previously
1254 * Running endpoints by ringing their doorbells
1257 spin_unlock_irq(&xhci->lock);
1259 xhci_dbc_resume(xhci);
1264 * Resume roothubs only if there are pending events.
1265 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1266 * the first wake signalling failed, give it that chance.
1268 pending_portevent = xhci_pending_portevent(xhci);
1269 if (!pending_portevent) {
1271 pending_portevent = xhci_pending_portevent(xhci);
1274 if (pending_portevent) {
1275 usb_hcd_resume_root_hub(xhci->shared_hcd);
1276 usb_hcd_resume_root_hub(hcd);
1280 * If system is subject to the Quirk, Compliance Mode Timer needs to
1281 * be re-initialized Always after a system resume. Ports are subject
1282 * to suffer the Compliance Mode issue again. It doesn't matter if
1283 * ports have entered previously to U0 before system's suspension.
1285 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1286 compliance_mode_recovery_timer_init(xhci);
1288 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1289 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1291 /* Re-enable port polling. */
1292 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1293 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1294 usb_hcd_poll_rh_status(xhci->shared_hcd);
1295 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1296 usb_hcd_poll_rh_status(hcd);
1300 EXPORT_SYMBOL_GPL(xhci_resume);
1301 #endif /* CONFIG_PM */
1303 /*-------------------------------------------------------------------------*/
1306 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1307 * we'll copy the actual data into the TRB address register. This is limited to
1308 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1309 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1311 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1314 if (xhci_urb_suitable_for_idt(urb))
1317 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1321 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1322 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1323 * value to right shift 1 for the bitmask.
1325 * Index = (epnum * 2) + direction - 1,
1326 * where direction = 0 for OUT, 1 for IN.
1327 * For control endpoints, the IN index is used (OUT index is unused), so
1328 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1330 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1333 if (usb_endpoint_xfer_control(desc))
1334 index = (unsigned int) (usb_endpoint_num(desc)*2);
1336 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1337 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1341 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1342 * address from the XHCI endpoint index.
1344 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1346 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1347 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1348 return direction | number;
1351 /* Find the flag for this endpoint (for use in the control context). Use the
1352 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1355 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1357 return 1 << (xhci_get_endpoint_index(desc) + 1);
1360 /* Find the flag for this endpoint (for use in the control context). Use the
1361 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1364 static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1366 return 1 << (ep_index + 1);
1369 /* Compute the last valid endpoint context index. Basically, this is the
1370 * endpoint index plus one. For slot contexts with more than valid endpoint,
1371 * we find the most significant bit set in the added contexts flags.
1372 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1373 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1375 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1377 return fls(added_ctxs) - 1;
1380 /* Returns 1 if the arguments are OK;
1381 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1383 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1384 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1386 struct xhci_hcd *xhci;
1387 struct xhci_virt_device *virt_dev;
1389 if (!hcd || (check_ep && !ep) || !udev) {
1390 pr_debug("xHCI %s called with invalid args\n", func);
1393 if (!udev->parent) {
1394 pr_debug("xHCI %s called for root hub\n", func);
1398 xhci = hcd_to_xhci(hcd);
1399 if (check_virt_dev) {
1400 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1401 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1406 virt_dev = xhci->devs[udev->slot_id];
1407 if (virt_dev->udev != udev) {
1408 xhci_dbg(xhci, "xHCI %s called with udev and "
1409 "virt_dev does not match\n", func);
1414 if (xhci->xhc_state & XHCI_STATE_HALTED)
1420 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1421 struct usb_device *udev, struct xhci_command *command,
1422 bool ctx_change, bool must_succeed);
1425 * Full speed devices may have a max packet size greater than 8 bytes, but the
1426 * USB core doesn't know that until it reads the first 8 bytes of the
1427 * descriptor. If the usb_device's max packet size changes after that point,
1428 * we need to issue an evaluate context command and wait on it.
1430 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1431 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1433 struct xhci_container_ctx *out_ctx;
1434 struct xhci_input_control_ctx *ctrl_ctx;
1435 struct xhci_ep_ctx *ep_ctx;
1436 struct xhci_command *command;
1437 int max_packet_size;
1438 int hw_max_packet_size;
1441 out_ctx = xhci->devs[slot_id]->out_ctx;
1442 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1443 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1444 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1445 if (hw_max_packet_size != max_packet_size) {
1446 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1447 "Max Packet Size for ep 0 changed.");
1448 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1449 "Max packet size in usb_device = %d",
1451 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1452 "Max packet size in xHCI HW = %d",
1453 hw_max_packet_size);
1454 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1455 "Issuing evaluate context command.");
1457 /* Set up the input context flags for the command */
1458 /* FIXME: This won't work if a non-default control endpoint
1459 * changes max packet sizes.
1462 command = xhci_alloc_command(xhci, true, mem_flags);
1466 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1467 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1469 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1472 goto command_cleanup;
1474 /* Set up the modified control endpoint 0 */
1475 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1476 xhci->devs[slot_id]->out_ctx, ep_index);
1478 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1479 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1480 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1481 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1483 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1484 ctrl_ctx->drop_flags = 0;
1486 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1489 /* Clean up the input context for later use by bandwidth
1492 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1494 kfree(command->completion);
1501 * non-error returns are a promise to giveback() the urb later
1502 * we drop ownership so next owner (or urb unlink) can get it
1504 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1506 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1507 unsigned long flags;
1509 unsigned int slot_id, ep_index;
1510 unsigned int *ep_state;
1511 struct urb_priv *urb_priv;
1516 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1517 true, true, __func__);
1519 return ret ? ret : -EINVAL;
1521 slot_id = urb->dev->slot_id;
1522 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1523 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1525 if (!HCD_HW_ACCESSIBLE(hcd)) {
1526 if (!in_interrupt())
1527 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1530 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1531 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1535 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1536 num_tds = urb->number_of_packets;
1537 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1538 urb->transfer_buffer_length > 0 &&
1539 urb->transfer_flags & URB_ZERO_PACKET &&
1540 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1545 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1549 urb_priv->num_tds = num_tds;
1550 urb_priv->num_tds_done = 0;
1551 urb->hcpriv = urb_priv;
1553 trace_xhci_urb_enqueue(urb);
1555 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1556 /* Check to see if the max packet size for the default control
1557 * endpoint changed during FS device enumeration
1559 if (urb->dev->speed == USB_SPEED_FULL) {
1560 ret = xhci_check_maxpacket(xhci, slot_id,
1561 ep_index, urb, mem_flags);
1563 xhci_urb_free_priv(urb_priv);
1570 spin_lock_irqsave(&xhci->lock, flags);
1572 if (xhci->xhc_state & XHCI_STATE_DYING) {
1573 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1574 urb->ep->desc.bEndpointAddress, urb);
1578 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1579 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1584 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1585 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1590 switch (usb_endpoint_type(&urb->ep->desc)) {
1592 case USB_ENDPOINT_XFER_CONTROL:
1593 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1596 case USB_ENDPOINT_XFER_BULK:
1597 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1600 case USB_ENDPOINT_XFER_INT:
1601 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1604 case USB_ENDPOINT_XFER_ISOC:
1605 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1611 xhci_urb_free_priv(urb_priv);
1614 spin_unlock_irqrestore(&xhci->lock, flags);
1619 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1620 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1621 * should pick up where it left off in the TD, unless a Set Transfer Ring
1622 * Dequeue Pointer is issued.
1624 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1625 * the ring. Since the ring is a contiguous structure, they can't be physically
1626 * removed. Instead, there are two options:
1628 * 1) If the HC is in the middle of processing the URB to be canceled, we
1629 * simply move the ring's dequeue pointer past those TRBs using the Set
1630 * Transfer Ring Dequeue Pointer command. This will be the common case,
1631 * when drivers timeout on the last submitted URB and attempt to cancel.
1633 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1634 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1635 * HC will need to invalidate the any TRBs it has cached after the stop
1636 * endpoint command, as noted in the xHCI 0.95 errata.
1638 * 3) The TD may have completed by the time the Stop Endpoint Command
1639 * completes, so software needs to handle that case too.
1641 * This function should protect against the TD enqueueing code ringing the
1642 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1643 * It also needs to account for multiple cancellations on happening at the same
1644 * time for the same endpoint.
1646 * Note that this function can be called in any context, or so says
1647 * usb_hcd_unlink_urb()
1649 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1651 unsigned long flags;
1654 struct xhci_hcd *xhci;
1655 struct urb_priv *urb_priv;
1657 unsigned int ep_index;
1658 struct xhci_ring *ep_ring;
1659 struct xhci_virt_ep *ep;
1660 struct xhci_command *command;
1661 struct xhci_virt_device *vdev;
1663 xhci = hcd_to_xhci(hcd);
1664 spin_lock_irqsave(&xhci->lock, flags);
1666 trace_xhci_urb_dequeue(urb);
1668 /* Make sure the URB hasn't completed or been unlinked already */
1669 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1673 /* give back URB now if we can't queue it for cancel */
1674 vdev = xhci->devs[urb->dev->slot_id];
1675 urb_priv = urb->hcpriv;
1676 if (!vdev || !urb_priv)
1679 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1680 ep = &vdev->eps[ep_index];
1681 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1682 if (!ep || !ep_ring)
1685 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1686 temp = readl(&xhci->op_regs->status);
1687 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1693 * check ring is not re-allocated since URB was enqueued. If it is, then
1694 * make sure none of the ring related pointers in this URB private data
1695 * are touched, such as td_list, otherwise we overwrite freed data
1697 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1698 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1699 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1700 td = &urb_priv->td[i];
1701 if (!list_empty(&td->cancelled_td_list))
1702 list_del_init(&td->cancelled_td_list);
1707 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1708 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1709 "HC halted, freeing TD manually.");
1710 for (i = urb_priv->num_tds_done;
1711 i < urb_priv->num_tds;
1713 td = &urb_priv->td[i];
1714 if (!list_empty(&td->td_list))
1715 list_del_init(&td->td_list);
1716 if (!list_empty(&td->cancelled_td_list))
1717 list_del_init(&td->cancelled_td_list);
1722 i = urb_priv->num_tds_done;
1723 if (i < urb_priv->num_tds)
1724 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1725 "Cancel URB %p, dev %s, ep 0x%x, "
1726 "starting at offset 0x%llx",
1727 urb, urb->dev->devpath,
1728 urb->ep->desc.bEndpointAddress,
1729 (unsigned long long) xhci_trb_virt_to_dma(
1730 urb_priv->td[i].start_seg,
1731 urb_priv->td[i].first_trb));
1733 for (; i < urb_priv->num_tds; i++) {
1734 td = &urb_priv->td[i];
1735 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1738 /* Queue a stop endpoint command, but only if this is
1739 * the first cancellation to be handled.
1741 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1742 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1747 ep->ep_state |= EP_STOP_CMD_PENDING;
1748 ep->stop_cmd_timer.expires = jiffies +
1749 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1750 add_timer(&ep->stop_cmd_timer);
1751 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1753 xhci_ring_cmd_db(xhci);
1756 spin_unlock_irqrestore(&xhci->lock, flags);
1761 xhci_urb_free_priv(urb_priv);
1762 usb_hcd_unlink_urb_from_ep(hcd, urb);
1763 spin_unlock_irqrestore(&xhci->lock, flags);
1764 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1768 /* Drop an endpoint from a new bandwidth configuration for this device.
1769 * Only one call to this function is allowed per endpoint before
1770 * check_bandwidth() or reset_bandwidth() must be called.
1771 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1772 * add the endpoint to the schedule with possibly new parameters denoted by a
1773 * different endpoint descriptor in usb_host_endpoint.
1774 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1777 * The USB core will not allow URBs to be queued to an endpoint that is being
1778 * disabled, so there's no need for mutual exclusion to protect
1779 * the xhci->devs[slot_id] structure.
1781 static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1782 struct usb_host_endpoint *ep)
1784 struct xhci_hcd *xhci;
1785 struct xhci_container_ctx *in_ctx, *out_ctx;
1786 struct xhci_input_control_ctx *ctrl_ctx;
1787 unsigned int ep_index;
1788 struct xhci_ep_ctx *ep_ctx;
1790 u32 new_add_flags, new_drop_flags;
1793 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1796 xhci = hcd_to_xhci(hcd);
1797 if (xhci->xhc_state & XHCI_STATE_DYING)
1800 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1801 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1802 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1803 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1804 __func__, drop_flag);
1808 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1809 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1810 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1812 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1817 ep_index = xhci_get_endpoint_index(&ep->desc);
1818 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1819 /* If the HC already knows the endpoint is disabled,
1820 * or the HCD has noted it is disabled, ignore this request
1822 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1823 le32_to_cpu(ctrl_ctx->drop_flags) &
1824 xhci_get_endpoint_flag(&ep->desc)) {
1825 /* Do not warn when called after a usb_device_reset */
1826 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1827 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1832 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1833 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1835 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1836 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1838 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1840 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1842 if (xhci->quirks & XHCI_MTK_HOST)
1843 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1845 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1846 (unsigned int) ep->desc.bEndpointAddress,
1848 (unsigned int) new_drop_flags,
1849 (unsigned int) new_add_flags);
1853 /* Add an endpoint to a new possible bandwidth configuration for this device.
1854 * Only one call to this function is allowed per endpoint before
1855 * check_bandwidth() or reset_bandwidth() must be called.
1856 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1857 * add the endpoint to the schedule with possibly new parameters denoted by a
1858 * different endpoint descriptor in usb_host_endpoint.
1859 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1862 * The USB core will not allow URBs to be queued to an endpoint until the
1863 * configuration or alt setting is installed in the device, so there's no need
1864 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1866 static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1867 struct usb_host_endpoint *ep)
1869 struct xhci_hcd *xhci;
1870 struct xhci_container_ctx *in_ctx;
1871 unsigned int ep_index;
1872 struct xhci_input_control_ctx *ctrl_ctx;
1873 struct xhci_ep_ctx *ep_ctx;
1875 u32 new_add_flags, new_drop_flags;
1876 struct xhci_virt_device *virt_dev;
1879 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1881 /* So we won't queue a reset ep command for a root hub */
1885 xhci = hcd_to_xhci(hcd);
1886 if (xhci->xhc_state & XHCI_STATE_DYING)
1889 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1890 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1891 /* FIXME when we have to issue an evaluate endpoint command to
1892 * deal with ep0 max packet size changing once we get the
1895 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1896 __func__, added_ctxs);
1900 virt_dev = xhci->devs[udev->slot_id];
1901 in_ctx = virt_dev->in_ctx;
1902 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1904 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1909 ep_index = xhci_get_endpoint_index(&ep->desc);
1910 /* If this endpoint is already in use, and the upper layers are trying
1911 * to add it again without dropping it, reject the addition.
1913 if (virt_dev->eps[ep_index].ring &&
1914 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1915 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1916 "without dropping it.\n",
1917 (unsigned int) ep->desc.bEndpointAddress);
1921 /* If the HCD has already noted the endpoint is enabled,
1922 * ignore this request.
1924 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1925 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1931 * Configuration and alternate setting changes must be done in
1932 * process context, not interrupt context (or so documenation
1933 * for usb_set_interface() and usb_set_configuration() claim).
1935 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1936 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1937 __func__, ep->desc.bEndpointAddress);
1941 if (xhci->quirks & XHCI_MTK_HOST) {
1942 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1944 xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring);
1945 virt_dev->eps[ep_index].new_ring = NULL;
1950 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1951 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1953 /* If xhci_endpoint_disable() was called for this endpoint, but the
1954 * xHC hasn't been notified yet through the check_bandwidth() call,
1955 * this re-adds a new state for the endpoint from the new endpoint
1956 * descriptors. We must drop and re-add this endpoint, so we leave the
1959 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1961 /* Store the usb_device pointer for later use */
1964 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1965 trace_xhci_add_endpoint(ep_ctx);
1967 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1968 (unsigned int) ep->desc.bEndpointAddress,
1970 (unsigned int) new_drop_flags,
1971 (unsigned int) new_add_flags);
1975 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1977 struct xhci_input_control_ctx *ctrl_ctx;
1978 struct xhci_ep_ctx *ep_ctx;
1979 struct xhci_slot_ctx *slot_ctx;
1982 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1984 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1989 /* When a device's add flag and drop flag are zero, any subsequent
1990 * configure endpoint command will leave that endpoint's state
1991 * untouched. Make sure we don't leave any old state in the input
1992 * endpoint contexts.
1994 ctrl_ctx->drop_flags = 0;
1995 ctrl_ctx->add_flags = 0;
1996 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1997 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1998 /* Endpoint 0 is always valid */
1999 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2000 for (i = 1; i < 31; i++) {
2001 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2002 ep_ctx->ep_info = 0;
2003 ep_ctx->ep_info2 = 0;
2005 ep_ctx->tx_info = 0;
2009 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2010 struct usb_device *udev, u32 *cmd_status)
2014 switch (*cmd_status) {
2015 case COMP_COMMAND_ABORTED:
2016 case COMP_COMMAND_RING_STOPPED:
2017 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2020 case COMP_RESOURCE_ERROR:
2021 dev_warn(&udev->dev,
2022 "Not enough host controller resources for new device state.\n");
2024 /* FIXME: can we allocate more resources for the HC? */
2026 case COMP_BANDWIDTH_ERROR:
2027 case COMP_SECONDARY_BANDWIDTH_ERROR:
2028 dev_warn(&udev->dev,
2029 "Not enough bandwidth for new device state.\n");
2031 /* FIXME: can we go back to the old state? */
2033 case COMP_TRB_ERROR:
2034 /* the HCD set up something wrong */
2035 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2037 "and endpoint is not disabled.\n");
2040 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2041 dev_warn(&udev->dev,
2042 "ERROR: Incompatible device for endpoint configure command.\n");
2046 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2047 "Successful Endpoint Configure command");
2051 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2059 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2060 struct usb_device *udev, u32 *cmd_status)
2064 switch (*cmd_status) {
2065 case COMP_COMMAND_ABORTED:
2066 case COMP_COMMAND_RING_STOPPED:
2067 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2070 case COMP_PARAMETER_ERROR:
2071 dev_warn(&udev->dev,
2072 "WARN: xHCI driver setup invalid evaluate context command.\n");
2075 case COMP_SLOT_NOT_ENABLED_ERROR:
2076 dev_warn(&udev->dev,
2077 "WARN: slot not enabled for evaluate context command.\n");
2080 case COMP_CONTEXT_STATE_ERROR:
2081 dev_warn(&udev->dev,
2082 "WARN: invalid context state for evaluate context command.\n");
2085 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2086 dev_warn(&udev->dev,
2087 "ERROR: Incompatible device for evaluate context command.\n");
2090 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2091 /* Max Exit Latency too large error */
2092 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2096 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2097 "Successful evaluate context command");
2101 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2109 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2110 struct xhci_input_control_ctx *ctrl_ctx)
2112 u32 valid_add_flags;
2113 u32 valid_drop_flags;
2115 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2116 * (bit 1). The default control endpoint is added during the Address
2117 * Device command and is never removed until the slot is disabled.
2119 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2120 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2122 /* Use hweight32 to count the number of ones in the add flags, or
2123 * number of endpoints added. Don't count endpoints that are changed
2124 * (both added and dropped).
2126 return hweight32(valid_add_flags) -
2127 hweight32(valid_add_flags & valid_drop_flags);
2130 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2131 struct xhci_input_control_ctx *ctrl_ctx)
2133 u32 valid_add_flags;
2134 u32 valid_drop_flags;
2136 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2137 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2139 return hweight32(valid_drop_flags) -
2140 hweight32(valid_add_flags & valid_drop_flags);
2144 * We need to reserve the new number of endpoints before the configure endpoint
2145 * command completes. We can't subtract the dropped endpoints from the number
2146 * of active endpoints until the command completes because we can oversubscribe
2147 * the host in this case:
2149 * - the first configure endpoint command drops more endpoints than it adds
2150 * - a second configure endpoint command that adds more endpoints is queued
2151 * - the first configure endpoint command fails, so the config is unchanged
2152 * - the second command may succeed, even though there isn't enough resources
2154 * Must be called with xhci->lock held.
2156 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2157 struct xhci_input_control_ctx *ctrl_ctx)
2161 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2162 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2163 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2164 "Not enough ep ctxs: "
2165 "%u active, need to add %u, limit is %u.",
2166 xhci->num_active_eps, added_eps,
2167 xhci->limit_active_eps);
2170 xhci->num_active_eps += added_eps;
2171 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2172 "Adding %u ep ctxs, %u now active.", added_eps,
2173 xhci->num_active_eps);
2178 * The configure endpoint was failed by the xHC for some other reason, so we
2179 * need to revert the resources that failed configuration would have used.
2181 * Must be called with xhci->lock held.
2183 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2184 struct xhci_input_control_ctx *ctrl_ctx)
2188 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2189 xhci->num_active_eps -= num_failed_eps;
2190 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2191 "Removing %u failed ep ctxs, %u now active.",
2193 xhci->num_active_eps);
2197 * Now that the command has completed, clean up the active endpoint count by
2198 * subtracting out the endpoints that were dropped (but not changed).
2200 * Must be called with xhci->lock held.
2202 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2203 struct xhci_input_control_ctx *ctrl_ctx)
2205 u32 num_dropped_eps;
2207 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2208 xhci->num_active_eps -= num_dropped_eps;
2209 if (num_dropped_eps)
2210 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2211 "Removing %u dropped ep ctxs, %u now active.",
2213 xhci->num_active_eps);
2216 static unsigned int xhci_get_block_size(struct usb_device *udev)
2218 switch (udev->speed) {
2220 case USB_SPEED_FULL:
2222 case USB_SPEED_HIGH:
2224 case USB_SPEED_SUPER:
2225 case USB_SPEED_SUPER_PLUS:
2227 case USB_SPEED_UNKNOWN:
2228 case USB_SPEED_WIRELESS:
2230 /* Should never happen */
2236 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2238 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2240 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2245 /* If we are changing a LS/FS device under a HS hub,
2246 * make sure (if we are activating a new TT) that the HS bus has enough
2247 * bandwidth for this new TT.
2249 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2250 struct xhci_virt_device *virt_dev,
2253 struct xhci_interval_bw_table *bw_table;
2254 struct xhci_tt_bw_info *tt_info;
2256 /* Find the bandwidth table for the root port this TT is attached to. */
2257 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2258 tt_info = virt_dev->tt_info;
2259 /* If this TT already had active endpoints, the bandwidth for this TT
2260 * has already been added. Removing all periodic endpoints (and thus
2261 * making the TT enactive) will only decrease the bandwidth used.
2265 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2266 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2270 /* Not sure why we would have no new active endpoints...
2272 * Maybe because of an Evaluate Context change for a hub update or a
2273 * control endpoint 0 max packet size change?
2274 * FIXME: skip the bandwidth calculation in that case.
2279 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2280 struct xhci_virt_device *virt_dev)
2282 unsigned int bw_reserved;
2284 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2285 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2288 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2289 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2296 * This algorithm is a very conservative estimate of the worst-case scheduling
2297 * scenario for any one interval. The hardware dynamically schedules the
2298 * packets, so we can't tell which microframe could be the limiting factor in
2299 * the bandwidth scheduling. This only takes into account periodic endpoints.
2301 * Obviously, we can't solve an NP complete problem to find the minimum worst
2302 * case scenario. Instead, we come up with an estimate that is no less than
2303 * the worst case bandwidth used for any one microframe, but may be an
2306 * We walk the requirements for each endpoint by interval, starting with the
2307 * smallest interval, and place packets in the schedule where there is only one
2308 * possible way to schedule packets for that interval. In order to simplify
2309 * this algorithm, we record the largest max packet size for each interval, and
2310 * assume all packets will be that size.
2312 * For interval 0, we obviously must schedule all packets for each interval.
2313 * The bandwidth for interval 0 is just the amount of data to be transmitted
2314 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2315 * the number of packets).
2317 * For interval 1, we have two possible microframes to schedule those packets
2318 * in. For this algorithm, if we can schedule the same number of packets for
2319 * each possible scheduling opportunity (each microframe), we will do so. The
2320 * remaining number of packets will be saved to be transmitted in the gaps in
2321 * the next interval's scheduling sequence.
2323 * As we move those remaining packets to be scheduled with interval 2 packets,
2324 * we have to double the number of remaining packets to transmit. This is
2325 * because the intervals are actually powers of 2, and we would be transmitting
2326 * the previous interval's packets twice in this interval. We also have to be
2327 * sure that when we look at the largest max packet size for this interval, we
2328 * also look at the largest max packet size for the remaining packets and take
2329 * the greater of the two.
2331 * The algorithm continues to evenly distribute packets in each scheduling
2332 * opportunity, and push the remaining packets out, until we get to the last
2333 * interval. Then those packets and their associated overhead are just added
2334 * to the bandwidth used.
2336 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2337 struct xhci_virt_device *virt_dev,
2340 unsigned int bw_reserved;
2341 unsigned int max_bandwidth;
2342 unsigned int bw_used;
2343 unsigned int block_size;
2344 struct xhci_interval_bw_table *bw_table;
2345 unsigned int packet_size = 0;
2346 unsigned int overhead = 0;
2347 unsigned int packets_transmitted = 0;
2348 unsigned int packets_remaining = 0;
2351 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2352 return xhci_check_ss_bw(xhci, virt_dev);
2354 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2355 max_bandwidth = HS_BW_LIMIT;
2356 /* Convert percent of bus BW reserved to blocks reserved */
2357 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2359 max_bandwidth = FS_BW_LIMIT;
2360 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2363 bw_table = virt_dev->bw_table;
2364 /* We need to translate the max packet size and max ESIT payloads into
2365 * the units the hardware uses.
2367 block_size = xhci_get_block_size(virt_dev->udev);
2369 /* If we are manipulating a LS/FS device under a HS hub, double check
2370 * that the HS bus has enough bandwidth if we are activing a new TT.
2372 if (virt_dev->tt_info) {
2373 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2374 "Recalculating BW for rootport %u",
2375 virt_dev->real_port);
2376 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2377 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2378 "newly activated TT.\n");
2381 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2382 "Recalculating BW for TT slot %u port %u",
2383 virt_dev->tt_info->slot_id,
2384 virt_dev->tt_info->ttport);
2386 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2387 "Recalculating BW for rootport %u",
2388 virt_dev->real_port);
2391 /* Add in how much bandwidth will be used for interval zero, or the
2392 * rounded max ESIT payload + number of packets * largest overhead.
2394 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2395 bw_table->interval_bw[0].num_packets *
2396 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2398 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2399 unsigned int bw_added;
2400 unsigned int largest_mps;
2401 unsigned int interval_overhead;
2404 * How many packets could we transmit in this interval?
2405 * If packets didn't fit in the previous interval, we will need
2406 * to transmit that many packets twice within this interval.
2408 packets_remaining = 2 * packets_remaining +
2409 bw_table->interval_bw[i].num_packets;
2411 /* Find the largest max packet size of this or the previous
2414 if (list_empty(&bw_table->interval_bw[i].endpoints))
2417 struct xhci_virt_ep *virt_ep;
2418 struct list_head *ep_entry;
2420 ep_entry = bw_table->interval_bw[i].endpoints.next;
2421 virt_ep = list_entry(ep_entry,
2422 struct xhci_virt_ep, bw_endpoint_list);
2423 /* Convert to blocks, rounding up */
2424 largest_mps = DIV_ROUND_UP(
2425 virt_ep->bw_info.max_packet_size,
2428 if (largest_mps > packet_size)
2429 packet_size = largest_mps;
2431 /* Use the larger overhead of this or the previous interval. */
2432 interval_overhead = xhci_get_largest_overhead(
2433 &bw_table->interval_bw[i]);
2434 if (interval_overhead > overhead)
2435 overhead = interval_overhead;
2437 /* How many packets can we evenly distribute across
2438 * (1 << (i + 1)) possible scheduling opportunities?
2440 packets_transmitted = packets_remaining >> (i + 1);
2442 /* Add in the bandwidth used for those scheduled packets */
2443 bw_added = packets_transmitted * (overhead + packet_size);
2445 /* How many packets do we have remaining to transmit? */
2446 packets_remaining = packets_remaining % (1 << (i + 1));
2448 /* What largest max packet size should those packets have? */
2449 /* If we've transmitted all packets, don't carry over the
2450 * largest packet size.
2452 if (packets_remaining == 0) {
2455 } else if (packets_transmitted > 0) {
2456 /* Otherwise if we do have remaining packets, and we've
2457 * scheduled some packets in this interval, take the
2458 * largest max packet size from endpoints with this
2461 packet_size = largest_mps;
2462 overhead = interval_overhead;
2464 /* Otherwise carry over packet_size and overhead from the last
2465 * time we had a remainder.
2467 bw_used += bw_added;
2468 if (bw_used > max_bandwidth) {
2469 xhci_warn(xhci, "Not enough bandwidth. "
2470 "Proposed: %u, Max: %u\n",
2471 bw_used, max_bandwidth);
2476 * Ok, we know we have some packets left over after even-handedly
2477 * scheduling interval 15. We don't know which microframes they will
2478 * fit into, so we over-schedule and say they will be scheduled every
2481 if (packets_remaining > 0)
2482 bw_used += overhead + packet_size;
2484 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2485 unsigned int port_index = virt_dev->real_port - 1;
2487 /* OK, we're manipulating a HS device attached to a
2488 * root port bandwidth domain. Include the number of active TTs
2489 * in the bandwidth used.
2491 bw_used += TT_HS_OVERHEAD *
2492 xhci->rh_bw[port_index].num_active_tts;
2495 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2496 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2497 "Available: %u " "percent",
2498 bw_used, max_bandwidth, bw_reserved,
2499 (max_bandwidth - bw_used - bw_reserved) * 100 /
2502 bw_used += bw_reserved;
2503 if (bw_used > max_bandwidth) {
2504 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2505 bw_used, max_bandwidth);
2509 bw_table->bw_used = bw_used;
2513 static bool xhci_is_async_ep(unsigned int ep_type)
2515 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2516 ep_type != ISOC_IN_EP &&
2517 ep_type != INT_IN_EP);
2520 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2522 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2525 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2527 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2529 if (ep_bw->ep_interval == 0)
2530 return SS_OVERHEAD_BURST +
2531 (ep_bw->mult * ep_bw->num_packets *
2532 (SS_OVERHEAD + mps));
2533 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2534 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2535 1 << ep_bw->ep_interval);
2539 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2540 struct xhci_bw_info *ep_bw,
2541 struct xhci_interval_bw_table *bw_table,
2542 struct usb_device *udev,
2543 struct xhci_virt_ep *virt_ep,
2544 struct xhci_tt_bw_info *tt_info)
2546 struct xhci_interval_bw *interval_bw;
2547 int normalized_interval;
2549 if (xhci_is_async_ep(ep_bw->type))
2552 if (udev->speed >= USB_SPEED_SUPER) {
2553 if (xhci_is_sync_in_ep(ep_bw->type))
2554 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2555 xhci_get_ss_bw_consumed(ep_bw);
2557 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2558 xhci_get_ss_bw_consumed(ep_bw);
2562 /* SuperSpeed endpoints never get added to intervals in the table, so
2563 * this check is only valid for HS/FS/LS devices.
2565 if (list_empty(&virt_ep->bw_endpoint_list))
2567 /* For LS/FS devices, we need to translate the interval expressed in
2568 * microframes to frames.
2570 if (udev->speed == USB_SPEED_HIGH)
2571 normalized_interval = ep_bw->ep_interval;
2573 normalized_interval = ep_bw->ep_interval - 3;
2575 if (normalized_interval == 0)
2576 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2577 interval_bw = &bw_table->interval_bw[normalized_interval];
2578 interval_bw->num_packets -= ep_bw->num_packets;
2579 switch (udev->speed) {
2581 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2583 case USB_SPEED_FULL:
2584 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2586 case USB_SPEED_HIGH:
2587 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2589 case USB_SPEED_SUPER:
2590 case USB_SPEED_SUPER_PLUS:
2591 case USB_SPEED_UNKNOWN:
2592 case USB_SPEED_WIRELESS:
2593 /* Should never happen because only LS/FS/HS endpoints will get
2594 * added to the endpoint list.
2599 tt_info->active_eps -= 1;
2600 list_del_init(&virt_ep->bw_endpoint_list);
2603 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2604 struct xhci_bw_info *ep_bw,
2605 struct xhci_interval_bw_table *bw_table,
2606 struct usb_device *udev,
2607 struct xhci_virt_ep *virt_ep,
2608 struct xhci_tt_bw_info *tt_info)
2610 struct xhci_interval_bw *interval_bw;
2611 struct xhci_virt_ep *smaller_ep;
2612 int normalized_interval;
2614 if (xhci_is_async_ep(ep_bw->type))
2617 if (udev->speed == USB_SPEED_SUPER) {
2618 if (xhci_is_sync_in_ep(ep_bw->type))
2619 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2620 xhci_get_ss_bw_consumed(ep_bw);
2622 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2623 xhci_get_ss_bw_consumed(ep_bw);
2627 /* For LS/FS devices, we need to translate the interval expressed in
2628 * microframes to frames.
2630 if (udev->speed == USB_SPEED_HIGH)
2631 normalized_interval = ep_bw->ep_interval;
2633 normalized_interval = ep_bw->ep_interval - 3;
2635 if (normalized_interval == 0)
2636 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2637 interval_bw = &bw_table->interval_bw[normalized_interval];
2638 interval_bw->num_packets += ep_bw->num_packets;
2639 switch (udev->speed) {
2641 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2643 case USB_SPEED_FULL:
2644 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2646 case USB_SPEED_HIGH:
2647 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2649 case USB_SPEED_SUPER:
2650 case USB_SPEED_SUPER_PLUS:
2651 case USB_SPEED_UNKNOWN:
2652 case USB_SPEED_WIRELESS:
2653 /* Should never happen because only LS/FS/HS endpoints will get
2654 * added to the endpoint list.
2660 tt_info->active_eps += 1;
2661 /* Insert the endpoint into the list, largest max packet size first. */
2662 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2664 if (ep_bw->max_packet_size >=
2665 smaller_ep->bw_info.max_packet_size) {
2666 /* Add the new ep before the smaller endpoint */
2667 list_add_tail(&virt_ep->bw_endpoint_list,
2668 &smaller_ep->bw_endpoint_list);
2672 /* Add the new endpoint at the end of the list. */
2673 list_add_tail(&virt_ep->bw_endpoint_list,
2674 &interval_bw->endpoints);
2677 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2678 struct xhci_virt_device *virt_dev,
2681 struct xhci_root_port_bw_info *rh_bw_info;
2682 if (!virt_dev->tt_info)
2685 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2686 if (old_active_eps == 0 &&
2687 virt_dev->tt_info->active_eps != 0) {
2688 rh_bw_info->num_active_tts += 1;
2689 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2690 } else if (old_active_eps != 0 &&
2691 virt_dev->tt_info->active_eps == 0) {
2692 rh_bw_info->num_active_tts -= 1;
2693 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2697 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2698 struct xhci_virt_device *virt_dev,
2699 struct xhci_container_ctx *in_ctx)
2701 struct xhci_bw_info ep_bw_info[31];
2703 struct xhci_input_control_ctx *ctrl_ctx;
2704 int old_active_eps = 0;
2706 if (virt_dev->tt_info)
2707 old_active_eps = virt_dev->tt_info->active_eps;
2709 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2711 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2716 for (i = 0; i < 31; i++) {
2717 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2720 /* Make a copy of the BW info in case we need to revert this */
2721 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2722 sizeof(ep_bw_info[i]));
2723 /* Drop the endpoint from the interval table if the endpoint is
2724 * being dropped or changed.
2726 if (EP_IS_DROPPED(ctrl_ctx, i))
2727 xhci_drop_ep_from_interval_table(xhci,
2728 &virt_dev->eps[i].bw_info,
2734 /* Overwrite the information stored in the endpoints' bw_info */
2735 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2736 for (i = 0; i < 31; i++) {
2737 /* Add any changed or added endpoints to the interval table */
2738 if (EP_IS_ADDED(ctrl_ctx, i))
2739 xhci_add_ep_to_interval_table(xhci,
2740 &virt_dev->eps[i].bw_info,
2747 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2748 /* Ok, this fits in the bandwidth we have.
2749 * Update the number of active TTs.
2751 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2755 /* We don't have enough bandwidth for this, revert the stored info. */
2756 for (i = 0; i < 31; i++) {
2757 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2760 /* Drop the new copies of any added or changed endpoints from
2761 * the interval table.
2763 if (EP_IS_ADDED(ctrl_ctx, i)) {
2764 xhci_drop_ep_from_interval_table(xhci,
2765 &virt_dev->eps[i].bw_info,
2771 /* Revert the endpoint back to its old information */
2772 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2773 sizeof(ep_bw_info[i]));
2774 /* Add any changed or dropped endpoints back into the table */
2775 if (EP_IS_DROPPED(ctrl_ctx, i))
2776 xhci_add_ep_to_interval_table(xhci,
2777 &virt_dev->eps[i].bw_info,
2787 /* Issue a configure endpoint command or evaluate context command
2788 * and wait for it to finish.
2790 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2791 struct usb_device *udev,
2792 struct xhci_command *command,
2793 bool ctx_change, bool must_succeed)
2796 unsigned long flags;
2797 struct xhci_input_control_ctx *ctrl_ctx;
2798 struct xhci_virt_device *virt_dev;
2799 struct xhci_slot_ctx *slot_ctx;
2804 spin_lock_irqsave(&xhci->lock, flags);
2806 if (xhci->xhc_state & XHCI_STATE_DYING) {
2807 spin_unlock_irqrestore(&xhci->lock, flags);
2811 virt_dev = xhci->devs[udev->slot_id];
2813 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2815 spin_unlock_irqrestore(&xhci->lock, flags);
2816 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2821 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2822 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2823 spin_unlock_irqrestore(&xhci->lock, flags);
2824 xhci_warn(xhci, "Not enough host resources, "
2825 "active endpoint contexts = %u\n",
2826 xhci->num_active_eps);
2829 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2830 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2831 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2832 xhci_free_host_resources(xhci, ctrl_ctx);
2833 spin_unlock_irqrestore(&xhci->lock, flags);
2834 xhci_warn(xhci, "Not enough bandwidth\n");
2838 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2840 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2841 trace_xhci_configure_endpoint(slot_ctx);
2844 ret = xhci_queue_configure_endpoint(xhci, command,
2845 command->in_ctx->dma,
2846 udev->slot_id, must_succeed);
2848 ret = xhci_queue_evaluate_context(xhci, command,
2849 command->in_ctx->dma,
2850 udev->slot_id, must_succeed);
2852 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2853 xhci_free_host_resources(xhci, ctrl_ctx);
2854 spin_unlock_irqrestore(&xhci->lock, flags);
2855 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2856 "FIXME allocate a new ring segment");
2859 xhci_ring_cmd_db(xhci);
2860 spin_unlock_irqrestore(&xhci->lock, flags);
2862 /* Wait for the configure endpoint command to complete */
2863 wait_for_completion(command->completion);
2866 ret = xhci_configure_endpoint_result(xhci, udev,
2869 ret = xhci_evaluate_context_result(xhci, udev,
2872 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2873 spin_lock_irqsave(&xhci->lock, flags);
2874 /* If the command failed, remove the reserved resources.
2875 * Otherwise, clean up the estimate to include dropped eps.
2878 xhci_free_host_resources(xhci, ctrl_ctx);
2880 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2881 spin_unlock_irqrestore(&xhci->lock, flags);
2886 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2887 struct xhci_virt_device *vdev, int i)
2889 struct xhci_virt_ep *ep = &vdev->eps[i];
2891 if (ep->ep_state & EP_HAS_STREAMS) {
2892 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2893 xhci_get_endpoint_address(i));
2894 xhci_free_stream_info(xhci, ep->stream_info);
2895 ep->stream_info = NULL;
2896 ep->ep_state &= ~EP_HAS_STREAMS;
2900 /* Called after one or more calls to xhci_add_endpoint() or
2901 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2902 * to call xhci_reset_bandwidth().
2904 * Since we are in the middle of changing either configuration or
2905 * installing a new alt setting, the USB core won't allow URBs to be
2906 * enqueued for any endpoint on the old config or interface. Nothing
2907 * else should be touching the xhci->devs[slot_id] structure, so we
2908 * don't need to take the xhci->lock for manipulating that.
2910 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2914 struct xhci_hcd *xhci;
2915 struct xhci_virt_device *virt_dev;
2916 struct xhci_input_control_ctx *ctrl_ctx;
2917 struct xhci_slot_ctx *slot_ctx;
2918 struct xhci_command *command;
2920 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2923 xhci = hcd_to_xhci(hcd);
2924 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2925 (xhci->xhc_state & XHCI_STATE_REMOVING))
2928 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2929 virt_dev = xhci->devs[udev->slot_id];
2931 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2935 command->in_ctx = virt_dev->in_ctx;
2937 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2938 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2940 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2943 goto command_cleanup;
2945 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2946 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2947 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2949 /* Don't issue the command if there's no endpoints to update. */
2950 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2951 ctrl_ctx->drop_flags == 0) {
2953 goto command_cleanup;
2955 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2956 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2957 for (i = 31; i >= 1; i--) {
2958 __le32 le32 = cpu_to_le32(BIT(i));
2960 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2961 || (ctrl_ctx->add_flags & le32) || i == 1) {
2962 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2963 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2968 ret = xhci_configure_endpoint(xhci, udev, command,
2971 /* Callee should call reset_bandwidth() */
2972 goto command_cleanup;
2974 /* Free any rings that were dropped, but not changed. */
2975 for (i = 1; i < 31; i++) {
2976 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2977 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2978 xhci_free_endpoint_ring(xhci, virt_dev, i);
2979 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2982 xhci_zero_in_ctx(xhci, virt_dev);
2984 * Install any rings for completely new endpoints or changed endpoints,
2985 * and free any old rings from changed endpoints.
2987 for (i = 1; i < 31; i++) {
2988 if (!virt_dev->eps[i].new_ring)
2990 /* Only free the old ring if it exists.
2991 * It may not if this is the first add of an endpoint.
2993 if (virt_dev->eps[i].ring) {
2994 xhci_free_endpoint_ring(xhci, virt_dev, i);
2996 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2997 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2998 virt_dev->eps[i].new_ring = NULL;
2999 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3002 kfree(command->completion);
3008 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3010 struct xhci_hcd *xhci;
3011 struct xhci_virt_device *virt_dev;
3014 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3017 xhci = hcd_to_xhci(hcd);
3019 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3020 virt_dev = xhci->devs[udev->slot_id];
3021 /* Free any rings allocated for added endpoints */
3022 for (i = 0; i < 31; i++) {
3023 if (virt_dev->eps[i].new_ring) {
3024 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3025 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3026 virt_dev->eps[i].new_ring = NULL;
3029 xhci_zero_in_ctx(xhci, virt_dev);
3032 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3033 struct xhci_container_ctx *in_ctx,
3034 struct xhci_container_ctx *out_ctx,
3035 struct xhci_input_control_ctx *ctrl_ctx,
3036 u32 add_flags, u32 drop_flags)
3038 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3039 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3040 xhci_slot_copy(xhci, in_ctx, out_ctx);
3041 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3044 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
3045 unsigned int slot_id, unsigned int ep_index,
3046 struct xhci_dequeue_state *deq_state)
3048 struct xhci_input_control_ctx *ctrl_ctx;
3049 struct xhci_container_ctx *in_ctx;
3050 struct xhci_ep_ctx *ep_ctx;
3054 in_ctx = xhci->devs[slot_id]->in_ctx;
3055 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
3057 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3062 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
3063 xhci->devs[slot_id]->out_ctx, ep_index);
3064 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
3065 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
3066 deq_state->new_deq_ptr);
3068 xhci_warn(xhci, "WARN Cannot submit config ep after "
3069 "reset ep command\n");
3070 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
3071 deq_state->new_deq_seg,
3072 deq_state->new_deq_ptr);
3075 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
3077 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
3078 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
3079 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
3080 added_ctxs, added_ctxs);
3083 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
3084 unsigned int ep_index, unsigned int stream_id,
3087 struct xhci_dequeue_state deq_state;
3089 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3090 "Cleaning up stalled endpoint ring");
3091 /* We need to move the HW's dequeue pointer past this TD,
3092 * or it will attempt to resend it on the next doorbell ring.
3094 xhci_find_new_dequeue_state(xhci, slot_id, ep_index, stream_id, td,
3097 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
3100 /* HW with the reset endpoint quirk will use the saved dequeue state to
3101 * issue a configure endpoint command later.
3103 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
3104 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3105 "Queueing new dequeue state");
3106 xhci_queue_new_dequeue_state(xhci, slot_id,
3107 ep_index, &deq_state);
3109 /* Better hope no one uses the input context between now and the
3110 * reset endpoint completion!
3111 * XXX: No idea how this hardware will react when stream rings
3114 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3115 "Setting up input context for "
3116 "configure endpoint command");
3117 xhci_setup_input_ctx_for_quirk(xhci, slot_id,
3118 ep_index, &deq_state);
3122 static void xhci_endpoint_disable(struct usb_hcd *hcd,
3123 struct usb_host_endpoint *host_ep)
3125 struct xhci_hcd *xhci;
3126 struct xhci_virt_device *vdev;
3127 struct xhci_virt_ep *ep;
3128 struct usb_device *udev;
3129 unsigned long flags;
3130 unsigned int ep_index;
3132 xhci = hcd_to_xhci(hcd);
3134 spin_lock_irqsave(&xhci->lock, flags);
3136 udev = (struct usb_device *)host_ep->hcpriv;
3137 if (!udev || !udev->slot_id)
3140 vdev = xhci->devs[udev->slot_id];
3144 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3145 ep = &vdev->eps[ep_index];
3149 /* wait for hub_tt_work to finish clearing hub TT */
3150 if (ep->ep_state & EP_CLEARING_TT) {
3151 spin_unlock_irqrestore(&xhci->lock, flags);
3152 schedule_timeout_uninterruptible(1);
3157 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3160 host_ep->hcpriv = NULL;
3161 spin_unlock_irqrestore(&xhci->lock, flags);
3165 * Called after usb core issues a clear halt control message.
3166 * The host side of the halt should already be cleared by a reset endpoint
3167 * command issued when the STALL event was received.
3169 * The reset endpoint command may only be issued to endpoints in the halted
3170 * state. For software that wishes to reset the data toggle or sequence number
3171 * of an endpoint that isn't in the halted state this function will issue a
3172 * configure endpoint command with the Drop and Add bits set for the target
3173 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3176 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3177 struct usb_host_endpoint *host_ep)
3179 struct xhci_hcd *xhci;
3180 struct usb_device *udev;
3181 struct xhci_virt_device *vdev;
3182 struct xhci_virt_ep *ep;
3183 struct xhci_input_control_ctx *ctrl_ctx;
3184 struct xhci_command *stop_cmd, *cfg_cmd;
3185 unsigned int ep_index;
3186 unsigned long flags;
3190 xhci = hcd_to_xhci(hcd);
3191 if (!host_ep->hcpriv)
3193 udev = (struct usb_device *) host_ep->hcpriv;
3194 vdev = xhci->devs[udev->slot_id];
3197 * vdev may be lost due to xHC restore error and re-initialization
3198 * during S3/S4 resume. A new vdev will be allocated later by
3199 * xhci_discover_or_reset_device()
3201 if (!udev->slot_id || !vdev)
3203 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3204 ep = &vdev->eps[ep_index];
3208 /* Bail out if toggle is already being cleared by a endpoint reset */
3209 spin_lock_irqsave(&xhci->lock, flags);
3210 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3211 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3212 spin_unlock_irqrestore(&xhci->lock, flags);
3215 spin_unlock_irqrestore(&xhci->lock, flags);
3216 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3217 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3218 usb_endpoint_xfer_isoc(&host_ep->desc))
3221 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3223 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3226 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3230 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3234 spin_lock_irqsave(&xhci->lock, flags);
3236 /* block queuing new trbs and ringing ep doorbell */
3237 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3240 * Make sure endpoint ring is empty before resetting the toggle/seq.
3241 * Driver is required to synchronously cancel all transfer request.
3242 * Stop the endpoint to force xHC to update the output context
3245 if (!list_empty(&ep->ring->td_list)) {
3246 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3247 spin_unlock_irqrestore(&xhci->lock, flags);
3248 xhci_free_command(xhci, cfg_cmd);
3252 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3255 spin_unlock_irqrestore(&xhci->lock, flags);
3256 xhci_free_command(xhci, cfg_cmd);
3257 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3262 xhci_ring_cmd_db(xhci);
3263 spin_unlock_irqrestore(&xhci->lock, flags);
3265 wait_for_completion(stop_cmd->completion);
3267 spin_lock_irqsave(&xhci->lock, flags);
3269 /* config ep command clears toggle if add and drop ep flags are set */
3270 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3272 spin_unlock_irqrestore(&xhci->lock, flags);
3273 xhci_free_command(xhci, cfg_cmd);
3274 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3279 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3280 ctrl_ctx, ep_flag, ep_flag);
3281 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3283 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3284 udev->slot_id, false);
3286 spin_unlock_irqrestore(&xhci->lock, flags);
3287 xhci_free_command(xhci, cfg_cmd);
3288 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3293 xhci_ring_cmd_db(xhci);
3294 spin_unlock_irqrestore(&xhci->lock, flags);
3296 wait_for_completion(cfg_cmd->completion);
3298 xhci_free_command(xhci, cfg_cmd);
3300 xhci_free_command(xhci, stop_cmd);
3301 spin_lock_irqsave(&xhci->lock, flags);
3302 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3303 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3304 spin_unlock_irqrestore(&xhci->lock, flags);
3307 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3308 struct usb_device *udev, struct usb_host_endpoint *ep,
3309 unsigned int slot_id)
3312 unsigned int ep_index;
3313 unsigned int ep_state;
3317 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3319 return ret ? ret : -EINVAL;
3320 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3321 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3322 " descriptor for ep 0x%x does not support streams\n",
3323 ep->desc.bEndpointAddress);
3327 ep_index = xhci_get_endpoint_index(&ep->desc);
3328 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3329 if (ep_state & EP_HAS_STREAMS ||
3330 ep_state & EP_GETTING_STREAMS) {
3331 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3332 "already has streams set up.\n",
3333 ep->desc.bEndpointAddress);
3334 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3335 "dynamic stream context array reallocation.\n");
3338 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3339 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3340 "endpoint 0x%x; URBs are pending.\n",
3341 ep->desc.bEndpointAddress);
3347 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3348 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3350 unsigned int max_streams;
3352 /* The stream context array size must be a power of two */
3353 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3355 * Find out how many primary stream array entries the host controller
3356 * supports. Later we may use secondary stream arrays (similar to 2nd
3357 * level page entries), but that's an optional feature for xHCI host
3358 * controllers. xHCs must support at least 4 stream IDs.
3360 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3361 if (*num_stream_ctxs > max_streams) {
3362 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3364 *num_stream_ctxs = max_streams;
3365 *num_streams = max_streams;
3369 /* Returns an error code if one of the endpoint already has streams.
3370 * This does not change any data structures, it only checks and gathers
3373 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3374 struct usb_device *udev,
3375 struct usb_host_endpoint **eps, unsigned int num_eps,
3376 unsigned int *num_streams, u32 *changed_ep_bitmask)
3378 unsigned int max_streams;
3379 unsigned int endpoint_flag;
3383 for (i = 0; i < num_eps; i++) {
3384 ret = xhci_check_streams_endpoint(xhci, udev,
3385 eps[i], udev->slot_id);
3389 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3390 if (max_streams < (*num_streams - 1)) {
3391 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3392 eps[i]->desc.bEndpointAddress,
3394 *num_streams = max_streams+1;
3397 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3398 if (*changed_ep_bitmask & endpoint_flag)
3400 *changed_ep_bitmask |= endpoint_flag;
3405 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3406 struct usb_device *udev,
3407 struct usb_host_endpoint **eps, unsigned int num_eps)
3409 u32 changed_ep_bitmask = 0;
3410 unsigned int slot_id;
3411 unsigned int ep_index;
3412 unsigned int ep_state;
3415 slot_id = udev->slot_id;
3416 if (!xhci->devs[slot_id])
3419 for (i = 0; i < num_eps; i++) {
3420 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3421 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3422 /* Are streams already being freed for the endpoint? */
3423 if (ep_state & EP_GETTING_NO_STREAMS) {
3424 xhci_warn(xhci, "WARN Can't disable streams for "
3426 "streams are being disabled already\n",
3427 eps[i]->desc.bEndpointAddress);
3430 /* Are there actually any streams to free? */
3431 if (!(ep_state & EP_HAS_STREAMS) &&
3432 !(ep_state & EP_GETTING_STREAMS)) {
3433 xhci_warn(xhci, "WARN Can't disable streams for "
3435 "streams are already disabled!\n",
3436 eps[i]->desc.bEndpointAddress);
3437 xhci_warn(xhci, "WARN xhci_free_streams() called "
3438 "with non-streams endpoint\n");
3441 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3443 return changed_ep_bitmask;
3447 * The USB device drivers use this function (through the HCD interface in USB
3448 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3449 * coordinate mass storage command queueing across multiple endpoints (basically
3450 * a stream ID == a task ID).
3452 * Setting up streams involves allocating the same size stream context array
3453 * for each endpoint and issuing a configure endpoint command for all endpoints.
3455 * Don't allow the call to succeed if one endpoint only supports one stream
3456 * (which means it doesn't support streams at all).
3458 * Drivers may get less stream IDs than they asked for, if the host controller
3459 * hardware or endpoints claim they can't support the number of requested
3462 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3463 struct usb_host_endpoint **eps, unsigned int num_eps,
3464 unsigned int num_streams, gfp_t mem_flags)
3467 struct xhci_hcd *xhci;
3468 struct xhci_virt_device *vdev;
3469 struct xhci_command *config_cmd;
3470 struct xhci_input_control_ctx *ctrl_ctx;
3471 unsigned int ep_index;
3472 unsigned int num_stream_ctxs;
3473 unsigned int max_packet;
3474 unsigned long flags;
3475 u32 changed_ep_bitmask = 0;
3480 /* Add one to the number of streams requested to account for
3481 * stream 0 that is reserved for xHCI usage.
3484 xhci = hcd_to_xhci(hcd);
3485 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3488 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3489 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3490 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3491 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3495 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3499 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3501 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3503 xhci_free_command(xhci, config_cmd);
3507 /* Check to make sure all endpoints are not already configured for
3508 * streams. While we're at it, find the maximum number of streams that
3509 * all the endpoints will support and check for duplicate endpoints.
3511 spin_lock_irqsave(&xhci->lock, flags);
3512 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3513 num_eps, &num_streams, &changed_ep_bitmask);
3515 xhci_free_command(xhci, config_cmd);
3516 spin_unlock_irqrestore(&xhci->lock, flags);
3519 if (num_streams <= 1) {
3520 xhci_warn(xhci, "WARN: endpoints can't handle "
3521 "more than one stream.\n");
3522 xhci_free_command(xhci, config_cmd);
3523 spin_unlock_irqrestore(&xhci->lock, flags);
3526 vdev = xhci->devs[udev->slot_id];
3527 /* Mark each endpoint as being in transition, so
3528 * xhci_urb_enqueue() will reject all URBs.
3530 for (i = 0; i < num_eps; i++) {
3531 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3532 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3534 spin_unlock_irqrestore(&xhci->lock, flags);
3536 /* Setup internal data structures and allocate HW data structures for
3537 * streams (but don't install the HW structures in the input context
3538 * until we're sure all memory allocation succeeded).
3540 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3541 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3542 num_stream_ctxs, num_streams);
3544 for (i = 0; i < num_eps; i++) {
3545 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3546 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3547 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3550 max_packet, mem_flags);
3551 if (!vdev->eps[ep_index].stream_info)
3553 /* Set maxPstreams in endpoint context and update deq ptr to
3554 * point to stream context array. FIXME
3558 /* Set up the input context for a configure endpoint command. */
3559 for (i = 0; i < num_eps; i++) {
3560 struct xhci_ep_ctx *ep_ctx;
3562 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3563 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3565 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3566 vdev->out_ctx, ep_index);
3567 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3568 vdev->eps[ep_index].stream_info);
3570 /* Tell the HW to drop its old copy of the endpoint context info
3571 * and add the updated copy from the input context.
3573 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3574 vdev->out_ctx, ctrl_ctx,
3575 changed_ep_bitmask, changed_ep_bitmask);
3577 /* Issue and wait for the configure endpoint command */
3578 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3581 /* xHC rejected the configure endpoint command for some reason, so we
3582 * leave the old ring intact and free our internal streams data
3588 spin_lock_irqsave(&xhci->lock, flags);
3589 for (i = 0; i < num_eps; i++) {
3590 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3591 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3592 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3593 udev->slot_id, ep_index);
3594 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3596 xhci_free_command(xhci, config_cmd);
3597 spin_unlock_irqrestore(&xhci->lock, flags);
3599 for (i = 0; i < num_eps; i++) {
3600 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3601 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3603 /* Subtract 1 for stream 0, which drivers can't use */
3604 return num_streams - 1;
3607 /* If it didn't work, free the streams! */
3608 for (i = 0; i < num_eps; i++) {
3609 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3610 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3611 vdev->eps[ep_index].stream_info = NULL;
3612 /* FIXME Unset maxPstreams in endpoint context and
3613 * update deq ptr to point to normal string ring.
3615 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3616 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3617 xhci_endpoint_zero(xhci, vdev, eps[i]);
3619 xhci_free_command(xhci, config_cmd);
3623 /* Transition the endpoint from using streams to being a "normal" endpoint
3626 * Modify the endpoint context state, submit a configure endpoint command,
3627 * and free all endpoint rings for streams if that completes successfully.
3629 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3630 struct usb_host_endpoint **eps, unsigned int num_eps,
3634 struct xhci_hcd *xhci;
3635 struct xhci_virt_device *vdev;
3636 struct xhci_command *command;
3637 struct xhci_input_control_ctx *ctrl_ctx;
3638 unsigned int ep_index;
3639 unsigned long flags;
3640 u32 changed_ep_bitmask;
3642 xhci = hcd_to_xhci(hcd);
3643 vdev = xhci->devs[udev->slot_id];
3645 /* Set up a configure endpoint command to remove the streams rings */
3646 spin_lock_irqsave(&xhci->lock, flags);
3647 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3648 udev, eps, num_eps);
3649 if (changed_ep_bitmask == 0) {
3650 spin_unlock_irqrestore(&xhci->lock, flags);
3654 /* Use the xhci_command structure from the first endpoint. We may have
3655 * allocated too many, but the driver may call xhci_free_streams() for
3656 * each endpoint it grouped into one call to xhci_alloc_streams().
3658 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3659 command = vdev->eps[ep_index].stream_info->free_streams_command;
3660 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3662 spin_unlock_irqrestore(&xhci->lock, flags);
3663 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3668 for (i = 0; i < num_eps; i++) {
3669 struct xhci_ep_ctx *ep_ctx;
3671 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3672 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3673 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3674 EP_GETTING_NO_STREAMS;
3676 xhci_endpoint_copy(xhci, command->in_ctx,
3677 vdev->out_ctx, ep_index);
3678 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3679 &vdev->eps[ep_index]);
3681 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3682 vdev->out_ctx, ctrl_ctx,
3683 changed_ep_bitmask, changed_ep_bitmask);
3684 spin_unlock_irqrestore(&xhci->lock, flags);
3686 /* Issue and wait for the configure endpoint command,
3687 * which must succeed.
3689 ret = xhci_configure_endpoint(xhci, udev, command,
3692 /* xHC rejected the configure endpoint command for some reason, so we
3693 * leave the streams rings intact.
3698 spin_lock_irqsave(&xhci->lock, flags);
3699 for (i = 0; i < num_eps; i++) {
3700 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3701 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3702 vdev->eps[ep_index].stream_info = NULL;
3703 /* FIXME Unset maxPstreams in endpoint context and
3704 * update deq ptr to point to normal string ring.
3706 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3707 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3709 spin_unlock_irqrestore(&xhci->lock, flags);
3715 * Deletes endpoint resources for endpoints that were active before a Reset
3716 * Device command, or a Disable Slot command. The Reset Device command leaves
3717 * the control endpoint intact, whereas the Disable Slot command deletes it.
3719 * Must be called with xhci->lock held.
3721 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3722 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3725 unsigned int num_dropped_eps = 0;
3726 unsigned int drop_flags = 0;
3728 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3729 if (virt_dev->eps[i].ring) {
3730 drop_flags |= 1 << i;
3734 xhci->num_active_eps -= num_dropped_eps;
3735 if (num_dropped_eps)
3736 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3737 "Dropped %u ep ctxs, flags = 0x%x, "
3739 num_dropped_eps, drop_flags,
3740 xhci->num_active_eps);
3744 * This submits a Reset Device Command, which will set the device state to 0,
3745 * set the device address to 0, and disable all the endpoints except the default
3746 * control endpoint. The USB core should come back and call
3747 * xhci_address_device(), and then re-set up the configuration. If this is
3748 * called because of a usb_reset_and_verify_device(), then the old alternate
3749 * settings will be re-installed through the normal bandwidth allocation
3752 * Wait for the Reset Device command to finish. Remove all structures
3753 * associated with the endpoints that were disabled. Clear the input device
3754 * structure? Reset the control endpoint 0 max packet size?
3756 * If the virt_dev to be reset does not exist or does not match the udev,
3757 * it means the device is lost, possibly due to the xHC restore error and
3758 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3759 * re-allocate the device.
3761 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3762 struct usb_device *udev)
3765 unsigned long flags;
3766 struct xhci_hcd *xhci;
3767 unsigned int slot_id;
3768 struct xhci_virt_device *virt_dev;
3769 struct xhci_command *reset_device_cmd;
3770 struct xhci_slot_ctx *slot_ctx;
3771 int old_active_eps = 0;
3773 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3776 xhci = hcd_to_xhci(hcd);
3777 slot_id = udev->slot_id;
3778 virt_dev = xhci->devs[slot_id];
3780 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3781 "not exist. Re-allocate the device\n", slot_id);
3782 ret = xhci_alloc_dev(hcd, udev);
3789 if (virt_dev->tt_info)
3790 old_active_eps = virt_dev->tt_info->active_eps;
3792 if (virt_dev->udev != udev) {
3793 /* If the virt_dev and the udev does not match, this virt_dev
3794 * may belong to another udev.
3795 * Re-allocate the device.
3797 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3798 "not match the udev. Re-allocate the device\n",
3800 ret = xhci_alloc_dev(hcd, udev);
3807 /* If device is not setup, there is no point in resetting it */
3808 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3809 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3810 SLOT_STATE_DISABLED)
3813 trace_xhci_discover_or_reset_device(slot_ctx);
3815 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3816 /* Allocate the command structure that holds the struct completion.
3817 * Assume we're in process context, since the normal device reset
3818 * process has to wait for the device anyway. Storage devices are
3819 * reset as part of error handling, so use GFP_NOIO instead of
3822 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3823 if (!reset_device_cmd) {
3824 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3828 /* Attempt to submit the Reset Device command to the command ring */
3829 spin_lock_irqsave(&xhci->lock, flags);
3831 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3833 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3834 spin_unlock_irqrestore(&xhci->lock, flags);
3835 goto command_cleanup;
3837 xhci_ring_cmd_db(xhci);
3838 spin_unlock_irqrestore(&xhci->lock, flags);
3840 /* Wait for the Reset Device command to finish */
3841 wait_for_completion(reset_device_cmd->completion);
3843 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3844 * unless we tried to reset a slot ID that wasn't enabled,
3845 * or the device wasn't in the addressed or configured state.
3847 ret = reset_device_cmd->status;
3849 case COMP_COMMAND_ABORTED:
3850 case COMP_COMMAND_RING_STOPPED:
3851 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3853 goto command_cleanup;
3854 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3855 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3856 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3858 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3859 xhci_dbg(xhci, "Not freeing device rings.\n");
3860 /* Don't treat this as an error. May change my mind later. */
3862 goto command_cleanup;
3864 xhci_dbg(xhci, "Successful reset device command.\n");
3867 if (xhci_is_vendor_info_code(xhci, ret))
3869 xhci_warn(xhci, "Unknown completion code %u for "
3870 "reset device command.\n", ret);
3872 goto command_cleanup;
3875 /* Free up host controller endpoint resources */
3876 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3877 spin_lock_irqsave(&xhci->lock, flags);
3878 /* Don't delete the default control endpoint resources */
3879 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3880 spin_unlock_irqrestore(&xhci->lock, flags);
3883 /* Everything but endpoint 0 is disabled, so free the rings. */
3884 for (i = 1; i < 31; i++) {
3885 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3887 if (ep->ep_state & EP_HAS_STREAMS) {
3888 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3889 xhci_get_endpoint_address(i));
3890 xhci_free_stream_info(xhci, ep->stream_info);
3891 ep->stream_info = NULL;
3892 ep->ep_state &= ~EP_HAS_STREAMS;
3896 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3897 xhci_free_endpoint_ring(xhci, virt_dev, i);
3899 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3900 xhci_drop_ep_from_interval_table(xhci,
3901 &virt_dev->eps[i].bw_info,
3906 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3908 /* If necessary, update the number of active TTs on this root port */
3909 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3910 virt_dev->flags = 0;
3914 xhci_free_command(xhci, reset_device_cmd);
3919 * At this point, the struct usb_device is about to go away, the device has
3920 * disconnected, and all traffic has been stopped and the endpoints have been
3921 * disabled. Free any HC data structures associated with that device.
3923 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3925 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3926 struct xhci_virt_device *virt_dev;
3927 struct xhci_slot_ctx *slot_ctx;
3928 unsigned long flags;
3932 * We called pm_runtime_get_noresume when the device was attached.
3933 * Decrement the counter here to allow controller to runtime suspend
3934 * if no devices remain.
3936 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3937 pm_runtime_put_noidle(hcd->self.controller);
3939 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3940 /* If the host is halted due to driver unload, we still need to free the
3943 if (ret <= 0 && ret != -ENODEV)
3946 virt_dev = xhci->devs[udev->slot_id];
3947 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3948 trace_xhci_free_dev(slot_ctx);
3950 /* Stop any wayward timer functions (which may grab the lock) */
3951 for (i = 0; i < 31; i++) {
3952 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3953 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3955 virt_dev->udev = NULL;
3956 xhci_disable_slot(xhci, udev->slot_id);
3958 spin_lock_irqsave(&xhci->lock, flags);
3959 xhci_free_virt_device(xhci, udev->slot_id);
3960 spin_unlock_irqrestore(&xhci->lock, flags);
3964 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3966 struct xhci_command *command;
3967 unsigned long flags;
3971 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3975 xhci_debugfs_remove_slot(xhci, slot_id);
3977 spin_lock_irqsave(&xhci->lock, flags);
3978 /* Don't disable the slot if the host controller is dead. */
3979 state = readl(&xhci->op_regs->status);
3980 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3981 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3982 spin_unlock_irqrestore(&xhci->lock, flags);
3987 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3990 spin_unlock_irqrestore(&xhci->lock, flags);
3994 xhci_ring_cmd_db(xhci);
3995 spin_unlock_irqrestore(&xhci->lock, flags);
3997 wait_for_completion(command->completion);
3999 if (command->status != COMP_SUCCESS)
4000 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
4001 slot_id, command->status);
4003 xhci_free_command(xhci, command);
4009 * Checks if we have enough host controller resources for the default control
4012 * Must be called with xhci->lock held.
4014 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4016 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4017 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4018 "Not enough ep ctxs: "
4019 "%u active, need to add 1, limit is %u.",
4020 xhci->num_active_eps, xhci->limit_active_eps);
4023 xhci->num_active_eps += 1;
4024 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4025 "Adding 1 ep ctx, %u now active.",
4026 xhci->num_active_eps);
4032 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4033 * timed out, or allocating memory failed. Returns 1 on success.
4035 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4037 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4038 struct xhci_virt_device *vdev;
4039 struct xhci_slot_ctx *slot_ctx;
4040 unsigned long flags;
4042 struct xhci_command *command;
4044 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4048 spin_lock_irqsave(&xhci->lock, flags);
4049 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4051 spin_unlock_irqrestore(&xhci->lock, flags);
4052 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4053 xhci_free_command(xhci, command);
4056 xhci_ring_cmd_db(xhci);
4057 spin_unlock_irqrestore(&xhci->lock, flags);
4059 wait_for_completion(command->completion);
4060 slot_id = command->slot_id;
4062 if (!slot_id || command->status != COMP_SUCCESS) {
4063 xhci_err(xhci, "Error while assigning device slot ID\n");
4064 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4066 readl(&xhci->cap_regs->hcs_params1)));
4067 xhci_free_command(xhci, command);
4071 xhci_free_command(xhci, command);
4073 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4074 spin_lock_irqsave(&xhci->lock, flags);
4075 ret = xhci_reserve_host_control_ep_resources(xhci);
4077 spin_unlock_irqrestore(&xhci->lock, flags);
4078 xhci_warn(xhci, "Not enough host resources, "
4079 "active endpoint contexts = %u\n",
4080 xhci->num_active_eps);
4083 spin_unlock_irqrestore(&xhci->lock, flags);
4085 /* Use GFP_NOIO, since this function can be called from
4086 * xhci_discover_or_reset_device(), which may be called as part of
4087 * mass storage driver error handling.
4089 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4090 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4093 vdev = xhci->devs[slot_id];
4094 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4095 trace_xhci_alloc_dev(slot_ctx);
4097 udev->slot_id = slot_id;
4099 xhci_debugfs_create_slot(xhci, slot_id);
4102 * If resetting upon resume, we can't put the controller into runtime
4103 * suspend if there is a device attached.
4105 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4106 pm_runtime_get_noresume(hcd->self.controller);
4108 /* Is this a LS or FS device under a HS hub? */
4109 /* Hub or peripherial? */
4113 xhci_disable_slot(xhci, udev->slot_id);
4114 xhci_free_virt_device(xhci, udev->slot_id);
4120 * Issue an Address Device command and optionally send a corresponding
4121 * SetAddress request to the device.
4123 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4124 enum xhci_setup_dev setup)
4126 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4127 unsigned long flags;
4128 struct xhci_virt_device *virt_dev;
4130 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4131 struct xhci_slot_ctx *slot_ctx;
4132 struct xhci_input_control_ctx *ctrl_ctx;
4134 struct xhci_command *command = NULL;
4136 mutex_lock(&xhci->mutex);
4138 if (xhci->xhc_state) { /* dying, removing or halted */
4143 if (!udev->slot_id) {
4144 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4145 "Bad Slot ID %d", udev->slot_id);
4150 virt_dev = xhci->devs[udev->slot_id];
4152 if (WARN_ON(!virt_dev)) {
4154 * In plug/unplug torture test with an NEC controller,
4155 * a zero-dereference was observed once due to virt_dev = 0.
4156 * Print useful debug rather than crash if it is observed again!
4158 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4163 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4164 trace_xhci_setup_device_slot(slot_ctx);
4166 if (setup == SETUP_CONTEXT_ONLY) {
4167 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4168 SLOT_STATE_DEFAULT) {
4169 xhci_dbg(xhci, "Slot already in default state\n");
4174 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4180 command->in_ctx = virt_dev->in_ctx;
4182 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4183 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4185 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4191 * If this is the first Set Address since device plug-in or
4192 * virt_device realloaction after a resume with an xHCI power loss,
4193 * then set up the slot context.
4195 if (!slot_ctx->dev_info)
4196 xhci_setup_addressable_virt_dev(xhci, udev);
4197 /* Otherwise, update the control endpoint ring enqueue pointer. */
4199 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4200 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4201 ctrl_ctx->drop_flags = 0;
4203 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4204 le32_to_cpu(slot_ctx->dev_info) >> 27);
4206 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4207 spin_lock_irqsave(&xhci->lock, flags);
4208 trace_xhci_setup_device(virt_dev);
4209 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4210 udev->slot_id, setup);
4212 spin_unlock_irqrestore(&xhci->lock, flags);
4213 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4214 "FIXME: allocate a command ring segment");
4217 xhci_ring_cmd_db(xhci);
4218 spin_unlock_irqrestore(&xhci->lock, flags);
4220 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4221 wait_for_completion(command->completion);
4223 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4224 * the SetAddress() "recovery interval" required by USB and aborting the
4225 * command on a timeout.
4227 switch (command->status) {
4228 case COMP_COMMAND_ABORTED:
4229 case COMP_COMMAND_RING_STOPPED:
4230 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4233 case COMP_CONTEXT_STATE_ERROR:
4234 case COMP_SLOT_NOT_ENABLED_ERROR:
4235 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4236 act, udev->slot_id);
4239 case COMP_USB_TRANSACTION_ERROR:
4240 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4242 mutex_unlock(&xhci->mutex);
4243 ret = xhci_disable_slot(xhci, udev->slot_id);
4244 xhci_free_virt_device(xhci, udev->slot_id);
4246 xhci_alloc_dev(hcd, udev);
4247 kfree(command->completion);
4250 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4251 dev_warn(&udev->dev,
4252 "ERROR: Incompatible device for setup %s command\n", act);
4256 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4257 "Successful setup %s command", act);
4261 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4262 act, command->status);
4263 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4269 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4270 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4271 "Op regs DCBAA ptr = %#016llx", temp_64);
4272 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4273 "Slot ID %d dcbaa entry @%p = %#016llx",
4275 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4276 (unsigned long long)
4277 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4278 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4279 "Output Context DMA address = %#08llx",
4280 (unsigned long long)virt_dev->out_ctx->dma);
4281 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4282 le32_to_cpu(slot_ctx->dev_info) >> 27);
4284 * USB core uses address 1 for the roothubs, so we add one to the
4285 * address given back to us by the HC.
4287 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4288 le32_to_cpu(slot_ctx->dev_info) >> 27);
4289 /* Zero the input context control for later use */
4290 ctrl_ctx->add_flags = 0;
4291 ctrl_ctx->drop_flags = 0;
4292 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4293 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4295 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4296 "Internal device address = %d",
4297 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4299 mutex_unlock(&xhci->mutex);
4301 kfree(command->completion);
4307 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4309 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4312 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4314 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4318 * Transfer the port index into real index in the HW port status
4319 * registers. Caculate offset between the port's PORTSC register
4320 * and port status base. Divide the number of per port register
4321 * to get the real index. The raw port number bases 1.
4323 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4325 struct xhci_hub *rhub;
4327 rhub = xhci_get_rhub(hcd);
4328 return rhub->ports[port1 - 1]->hw_portnum + 1;
4332 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4333 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4335 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4336 struct usb_device *udev, u16 max_exit_latency)
4338 struct xhci_virt_device *virt_dev;
4339 struct xhci_command *command;
4340 struct xhci_input_control_ctx *ctrl_ctx;
4341 struct xhci_slot_ctx *slot_ctx;
4342 unsigned long flags;
4345 spin_lock_irqsave(&xhci->lock, flags);
4347 virt_dev = xhci->devs[udev->slot_id];
4350 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4351 * xHC was re-initialized. Exit latency will be set later after
4352 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4355 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4356 spin_unlock_irqrestore(&xhci->lock, flags);
4360 /* Attempt to issue an Evaluate Context command to change the MEL. */
4361 command = xhci->lpm_command;
4362 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4364 spin_unlock_irqrestore(&xhci->lock, flags);
4365 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4370 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4371 spin_unlock_irqrestore(&xhci->lock, flags);
4373 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4374 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4375 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4376 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4377 slot_ctx->dev_state = 0;
4379 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4380 "Set up evaluate context for LPM MEL change.");
4382 /* Issue and wait for the evaluate context command. */
4383 ret = xhci_configure_endpoint(xhci, udev, command,
4387 spin_lock_irqsave(&xhci->lock, flags);
4388 virt_dev->current_mel = max_exit_latency;
4389 spin_unlock_irqrestore(&xhci->lock, flags);
4396 /* BESL to HIRD Encoding array for USB2 LPM */
4397 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4398 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4400 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4401 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4402 struct usb_device *udev)
4404 int u2del, besl, besl_host;
4405 int besl_device = 0;
4408 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4409 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4411 if (field & USB_BESL_SUPPORT) {
4412 for (besl_host = 0; besl_host < 16; besl_host++) {
4413 if (xhci_besl_encoding[besl_host] >= u2del)
4416 /* Use baseline BESL value as default */
4417 if (field & USB_BESL_BASELINE_VALID)
4418 besl_device = USB_GET_BESL_BASELINE(field);
4419 else if (field & USB_BESL_DEEP_VALID)
4420 besl_device = USB_GET_BESL_DEEP(field);
4425 besl_host = (u2del - 51) / 75 + 1;
4428 besl = besl_host + besl_device;
4435 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4436 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4443 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4445 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4446 l1 = udev->l1_params.timeout / 256;
4448 /* device has preferred BESLD */
4449 if (field & USB_BESL_DEEP_VALID) {
4450 besld = USB_GET_BESL_DEEP(field);
4454 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4457 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4458 struct usb_device *udev, int enable)
4460 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4461 struct xhci_port **ports;
4462 __le32 __iomem *pm_addr, *hlpm_addr;
4463 u32 pm_val, hlpm_val, field;
4464 unsigned int port_num;
4465 unsigned long flags;
4466 int hird, exit_latency;
4469 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4472 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4476 if (!udev->parent || udev->parent->parent ||
4477 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4480 if (udev->usb2_hw_lpm_capable != 1)
4483 spin_lock_irqsave(&xhci->lock, flags);
4485 ports = xhci->usb2_rhub.ports;
4486 port_num = udev->portnum - 1;
4487 pm_addr = ports[port_num]->addr + PORTPMSC;
4488 pm_val = readl(pm_addr);
4489 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4491 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4492 enable ? "enable" : "disable", port_num + 1);
4495 /* Host supports BESL timeout instead of HIRD */
4496 if (udev->usb2_hw_lpm_besl_capable) {
4497 /* if device doesn't have a preferred BESL value use a
4498 * default one which works with mixed HIRD and BESL
4499 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4501 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4502 if ((field & USB_BESL_SUPPORT) &&
4503 (field & USB_BESL_BASELINE_VALID))
4504 hird = USB_GET_BESL_BASELINE(field);
4506 hird = udev->l1_params.besl;
4508 exit_latency = xhci_besl_encoding[hird];
4509 spin_unlock_irqrestore(&xhci->lock, flags);
4511 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4512 * input context for link powermanagement evaluate
4513 * context commands. It is protected by hcd->bandwidth
4514 * mutex and is shared by all devices. We need to set
4515 * the max ext latency in USB 2 BESL LPM as well, so
4516 * use the same mutex and xhci_change_max_exit_latency()
4518 mutex_lock(hcd->bandwidth_mutex);
4519 ret = xhci_change_max_exit_latency(xhci, udev,
4521 mutex_unlock(hcd->bandwidth_mutex);
4525 spin_lock_irqsave(&xhci->lock, flags);
4527 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4528 writel(hlpm_val, hlpm_addr);
4532 hird = xhci_calculate_hird_besl(xhci, udev);
4535 pm_val &= ~PORT_HIRD_MASK;
4536 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4537 writel(pm_val, pm_addr);
4538 pm_val = readl(pm_addr);
4540 writel(pm_val, pm_addr);
4544 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4545 writel(pm_val, pm_addr);
4548 if (udev->usb2_hw_lpm_besl_capable) {
4549 spin_unlock_irqrestore(&xhci->lock, flags);
4550 mutex_lock(hcd->bandwidth_mutex);
4551 xhci_change_max_exit_latency(xhci, udev, 0);
4552 mutex_unlock(hcd->bandwidth_mutex);
4553 readl_poll_timeout(ports[port_num]->addr, pm_val,
4554 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4560 spin_unlock_irqrestore(&xhci->lock, flags);
4564 /* check if a usb2 port supports a given extened capability protocol
4565 * only USB2 ports extended protocol capability values are cached.
4566 * Return 1 if capability is supported
4568 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4569 unsigned capability)
4571 u32 port_offset, port_count;
4574 for (i = 0; i < xhci->num_ext_caps; i++) {
4575 if (xhci->ext_caps[i] & capability) {
4576 /* port offsets starts at 1 */
4577 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4578 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4579 if (port >= port_offset &&
4580 port < port_offset + port_count)
4587 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4589 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4590 int portnum = udev->portnum - 1;
4592 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4595 /* we only support lpm for non-hub device connected to root hub yet */
4596 if (!udev->parent || udev->parent->parent ||
4597 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4600 if (xhci->hw_lpm_support == 1 &&
4601 xhci_check_usb2_port_capability(
4602 xhci, portnum, XHCI_HLC)) {
4603 udev->usb2_hw_lpm_capable = 1;
4604 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4605 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4606 if (xhci_check_usb2_port_capability(xhci, portnum,
4608 udev->usb2_hw_lpm_besl_capable = 1;
4614 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4616 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4617 static unsigned long long xhci_service_interval_to_ns(
4618 struct usb_endpoint_descriptor *desc)
4620 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4623 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4624 enum usb3_link_state state)
4626 unsigned long long sel;
4627 unsigned long long pel;
4628 unsigned int max_sel_pel;
4633 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4634 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4635 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4636 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4640 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4641 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4642 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4646 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4648 return USB3_LPM_DISABLED;
4651 if (sel <= max_sel_pel && pel <= max_sel_pel)
4652 return USB3_LPM_DEVICE_INITIATED;
4654 if (sel > max_sel_pel)
4655 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4656 "due to long SEL %llu ms\n",
4659 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4660 "due to long PEL %llu ms\n",
4662 return USB3_LPM_DISABLED;
4665 /* The U1 timeout should be the maximum of the following values:
4666 * - For control endpoints, U1 system exit latency (SEL) * 3
4667 * - For bulk endpoints, U1 SEL * 5
4668 * - For interrupt endpoints:
4669 * - Notification EPs, U1 SEL * 3
4670 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4671 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4673 static unsigned long long xhci_calculate_intel_u1_timeout(
4674 struct usb_device *udev,
4675 struct usb_endpoint_descriptor *desc)
4677 unsigned long long timeout_ns;
4681 ep_type = usb_endpoint_type(desc);
4683 case USB_ENDPOINT_XFER_CONTROL:
4684 timeout_ns = udev->u1_params.sel * 3;
4686 case USB_ENDPOINT_XFER_BULK:
4687 timeout_ns = udev->u1_params.sel * 5;
4689 case USB_ENDPOINT_XFER_INT:
4690 intr_type = usb_endpoint_interrupt_type(desc);
4691 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4692 timeout_ns = udev->u1_params.sel * 3;
4695 /* Otherwise the calculation is the same as isoc eps */
4697 case USB_ENDPOINT_XFER_ISOC:
4698 timeout_ns = xhci_service_interval_to_ns(desc);
4699 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4700 if (timeout_ns < udev->u1_params.sel * 2)
4701 timeout_ns = udev->u1_params.sel * 2;
4710 /* Returns the hub-encoded U1 timeout value. */
4711 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4712 struct usb_device *udev,
4713 struct usb_endpoint_descriptor *desc)
4715 unsigned long long timeout_ns;
4717 /* Prevent U1 if service interval is shorter than U1 exit latency */
4718 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4719 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4720 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4721 return USB3_LPM_DISABLED;
4725 if (xhci->quirks & XHCI_INTEL_HOST)
4726 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4728 timeout_ns = udev->u1_params.sel;
4730 /* The U1 timeout is encoded in 1us intervals.
4731 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4733 if (timeout_ns == USB3_LPM_DISABLED)
4736 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4738 /* If the necessary timeout value is bigger than what we can set in the
4739 * USB 3.0 hub, we have to disable hub-initiated U1.
4741 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4743 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4744 "due to long timeout %llu ms\n", timeout_ns);
4745 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4748 /* The U2 timeout should be the maximum of:
4749 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4750 * - largest bInterval of any active periodic endpoint (to avoid going
4751 * into lower power link states between intervals).
4752 * - the U2 Exit Latency of the device
4754 static unsigned long long xhci_calculate_intel_u2_timeout(
4755 struct usb_device *udev,
4756 struct usb_endpoint_descriptor *desc)
4758 unsigned long long timeout_ns;
4759 unsigned long long u2_del_ns;
4761 timeout_ns = 10 * 1000 * 1000;
4763 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4764 (xhci_service_interval_to_ns(desc) > timeout_ns))
4765 timeout_ns = xhci_service_interval_to_ns(desc);
4767 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4768 if (u2_del_ns > timeout_ns)
4769 timeout_ns = u2_del_ns;
4774 /* Returns the hub-encoded U2 timeout value. */
4775 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4776 struct usb_device *udev,
4777 struct usb_endpoint_descriptor *desc)
4779 unsigned long long timeout_ns;
4781 /* Prevent U2 if service interval is shorter than U2 exit latency */
4782 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4783 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4784 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4785 return USB3_LPM_DISABLED;
4789 if (xhci->quirks & XHCI_INTEL_HOST)
4790 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4792 timeout_ns = udev->u2_params.sel;
4794 /* The U2 timeout is encoded in 256us intervals */
4795 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4796 /* If the necessary timeout value is bigger than what we can set in the
4797 * USB 3.0 hub, we have to disable hub-initiated U2.
4799 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4801 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4802 "due to long timeout %llu ms\n", timeout_ns);
4803 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4806 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4807 struct usb_device *udev,
4808 struct usb_endpoint_descriptor *desc,
4809 enum usb3_link_state state,
4812 if (state == USB3_LPM_U1)
4813 return xhci_calculate_u1_timeout(xhci, udev, desc);
4814 else if (state == USB3_LPM_U2)
4815 return xhci_calculate_u2_timeout(xhci, udev, desc);
4817 return USB3_LPM_DISABLED;
4820 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4821 struct usb_device *udev,
4822 struct usb_endpoint_descriptor *desc,
4823 enum usb3_link_state state,
4828 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4829 desc, state, timeout);
4831 /* If we found we can't enable hub-initiated LPM, and
4832 * the U1 or U2 exit latency was too high to allow
4833 * device-initiated LPM as well, then we will disable LPM
4834 * for this device, so stop searching any further.
4836 if (alt_timeout == USB3_LPM_DISABLED) {
4837 *timeout = alt_timeout;
4840 if (alt_timeout > *timeout)
4841 *timeout = alt_timeout;
4845 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4846 struct usb_device *udev,
4847 struct usb_host_interface *alt,
4848 enum usb3_link_state state,
4853 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4854 if (xhci_update_timeout_for_endpoint(xhci, udev,
4855 &alt->endpoint[j].desc, state, timeout))
4862 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4863 enum usb3_link_state state)
4865 struct usb_device *parent;
4866 unsigned int num_hubs;
4868 if (state == USB3_LPM_U2)
4871 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4872 for (parent = udev->parent, num_hubs = 0; parent->parent;
4873 parent = parent->parent)
4879 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4880 " below second-tier hub.\n");
4881 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4882 "to decrease power consumption.\n");
4886 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4887 struct usb_device *udev,
4888 enum usb3_link_state state)
4890 if (xhci->quirks & XHCI_INTEL_HOST)
4891 return xhci_check_intel_tier_policy(udev, state);
4896 /* Returns the U1 or U2 timeout that should be enabled.
4897 * If the tier check or timeout setting functions return with a non-zero exit
4898 * code, that means the timeout value has been finalized and we shouldn't look
4899 * at any more endpoints.
4901 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4902 struct usb_device *udev, enum usb3_link_state state)
4904 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4905 struct usb_host_config *config;
4908 u16 timeout = USB3_LPM_DISABLED;
4910 if (state == USB3_LPM_U1)
4912 else if (state == USB3_LPM_U2)
4915 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4920 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4923 /* Gather some information about the currently installed configuration
4924 * and alternate interface settings.
4926 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4930 config = udev->actconfig;
4934 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4935 struct usb_driver *driver;
4936 struct usb_interface *intf = config->interface[i];
4941 /* Check if any currently bound drivers want hub-initiated LPM
4944 if (intf->dev.driver) {
4945 driver = to_usb_driver(intf->dev.driver);
4946 if (driver && driver->disable_hub_initiated_lpm) {
4947 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4948 state_name, driver->name);
4949 timeout = xhci_get_timeout_no_hub_lpm(udev,
4951 if (timeout == USB3_LPM_DISABLED)
4956 /* Not sure how this could happen... */
4957 if (!intf->cur_altsetting)
4960 if (xhci_update_timeout_for_interface(xhci, udev,
4961 intf->cur_altsetting,
4968 static int calculate_max_exit_latency(struct usb_device *udev,
4969 enum usb3_link_state state_changed,
4970 u16 hub_encoded_timeout)
4972 unsigned long long u1_mel_us = 0;
4973 unsigned long long u2_mel_us = 0;
4974 unsigned long long mel_us = 0;
4980 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4981 hub_encoded_timeout == USB3_LPM_DISABLED);
4982 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4983 hub_encoded_timeout == USB3_LPM_DISABLED);
4985 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4986 hub_encoded_timeout != USB3_LPM_DISABLED);
4987 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4988 hub_encoded_timeout != USB3_LPM_DISABLED);
4990 /* If U1 was already enabled and we're not disabling it,
4991 * or we're going to enable U1, account for the U1 max exit latency.
4993 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4995 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4996 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4998 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
5000 if (u1_mel_us > u2_mel_us)
5004 /* xHCI host controller max exit latency field is only 16 bits wide. */
5005 if (mel_us > MAX_EXIT) {
5006 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5007 "is too big.\n", mel_us);
5013 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5014 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5015 struct usb_device *udev, enum usb3_link_state state)
5017 struct xhci_hcd *xhci;
5018 struct xhci_port *port;
5019 u16 hub_encoded_timeout;
5023 xhci = hcd_to_xhci(hcd);
5024 /* The LPM timeout values are pretty host-controller specific, so don't
5025 * enable hub-initiated timeouts unless the vendor has provided
5026 * information about their timeout algorithm.
5028 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5029 !xhci->devs[udev->slot_id])
5030 return USB3_LPM_DISABLED;
5032 /* If connected to root port then check port can handle lpm */
5033 if (udev->parent && !udev->parent->parent) {
5034 port = xhci->usb3_rhub.ports[udev->portnum - 1];
5035 if (port->lpm_incapable)
5036 return USB3_LPM_DISABLED;
5039 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5040 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5042 /* Max Exit Latency is too big, disable LPM. */
5043 hub_encoded_timeout = USB3_LPM_DISABLED;
5047 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5050 return hub_encoded_timeout;
5053 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5054 struct usb_device *udev, enum usb3_link_state state)
5056 struct xhci_hcd *xhci;
5059 xhci = hcd_to_xhci(hcd);
5060 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5061 !xhci->devs[udev->slot_id])
5064 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5065 return xhci_change_max_exit_latency(xhci, udev, mel);
5067 #else /* CONFIG_PM */
5069 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5070 struct usb_device *udev, int enable)
5075 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5080 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5081 struct usb_device *udev, enum usb3_link_state state)
5083 return USB3_LPM_DISABLED;
5086 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5087 struct usb_device *udev, enum usb3_link_state state)
5091 #endif /* CONFIG_PM */
5093 /*-------------------------------------------------------------------------*/
5095 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5096 * internal data structures for the device.
5098 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5099 struct usb_tt *tt, gfp_t mem_flags)
5101 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5102 struct xhci_virt_device *vdev;
5103 struct xhci_command *config_cmd;
5104 struct xhci_input_control_ctx *ctrl_ctx;
5105 struct xhci_slot_ctx *slot_ctx;
5106 unsigned long flags;
5107 unsigned think_time;
5110 /* Ignore root hubs */
5114 vdev = xhci->devs[hdev->slot_id];
5116 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5120 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5124 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5126 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5128 xhci_free_command(xhci, config_cmd);
5132 spin_lock_irqsave(&xhci->lock, flags);
5133 if (hdev->speed == USB_SPEED_HIGH &&
5134 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5135 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5136 xhci_free_command(xhci, config_cmd);
5137 spin_unlock_irqrestore(&xhci->lock, flags);
5141 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5142 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5143 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5144 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5146 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5147 * but it may be already set to 1 when setup an xHCI virtual
5148 * device, so clear it anyway.
5151 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5152 else if (hdev->speed == USB_SPEED_FULL)
5153 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5155 if (xhci->hci_version > 0x95) {
5156 xhci_dbg(xhci, "xHCI version %x needs hub "
5157 "TT think time and number of ports\n",
5158 (unsigned int) xhci->hci_version);
5159 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5160 /* Set TT think time - convert from ns to FS bit times.
5161 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5162 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5164 * xHCI 1.0: this field shall be 0 if the device is not a
5167 think_time = tt->think_time;
5168 if (think_time != 0)
5169 think_time = (think_time / 666) - 1;
5170 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5171 slot_ctx->tt_info |=
5172 cpu_to_le32(TT_THINK_TIME(think_time));
5174 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5175 "TT think time or number of ports\n",
5176 (unsigned int) xhci->hci_version);
5178 slot_ctx->dev_state = 0;
5179 spin_unlock_irqrestore(&xhci->lock, flags);
5181 xhci_dbg(xhci, "Set up %s for hub device.\n",
5182 (xhci->hci_version > 0x95) ?
5183 "configure endpoint" : "evaluate context");
5185 /* Issue and wait for the configure endpoint or
5186 * evaluate context command.
5188 if (xhci->hci_version > 0x95)
5189 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5192 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5195 xhci_free_command(xhci, config_cmd);
5198 EXPORT_SYMBOL_GPL(xhci_update_hub_device);
5200 static int xhci_get_frame(struct usb_hcd *hcd)
5202 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5203 /* EHCI mods by the periodic size. Why? */
5204 return readl(&xhci->run_regs->microframe_index) >> 3;
5207 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5209 struct xhci_hcd *xhci;
5211 * TODO: Check with DWC3 clients for sysdev according to
5214 struct device *dev = hcd->self.sysdev;
5215 unsigned int minor_rev;
5218 /* Accept arbitrarily long scatter-gather lists */
5219 hcd->self.sg_tablesize = ~0;
5221 /* support to build packet from discontinuous buffers */
5222 hcd->self.no_sg_constraint = 1;
5224 /* XHCI controllers don't stop the ep queue on short packets :| */
5225 hcd->self.no_stop_on_short = 1;
5227 xhci = hcd_to_xhci(hcd);
5229 if (usb_hcd_is_primary_hcd(hcd)) {
5230 xhci->main_hcd = hcd;
5231 xhci->usb2_rhub.hcd = hcd;
5232 /* Mark the first roothub as being USB 2.0.
5233 * The xHCI driver will register the USB 3.0 roothub.
5235 hcd->speed = HCD_USB2;
5236 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5238 * USB 2.0 roothub under xHCI has an integrated TT,
5239 * (rate matching hub) as opposed to having an OHCI/UHCI
5240 * companion controller.
5245 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5246 * should return 0x31 for sbrn, or that the minor revision
5247 * is a two digit BCD containig minor and sub-minor numbers.
5248 * This was later clarified in xHCI 1.2.
5250 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5251 * minor revision set to 0x1 instead of 0x10.
5253 if (xhci->usb3_rhub.min_rev == 0x1)
5256 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5258 switch (minor_rev) {
5260 hcd->speed = HCD_USB32;
5261 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5262 hcd->self.root_hub->rx_lanes = 2;
5263 hcd->self.root_hub->tx_lanes = 2;
5266 hcd->speed = HCD_USB31;
5267 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5270 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5272 minor_rev ? "Enhanced " : "");
5274 xhci->usb3_rhub.hcd = hcd;
5275 /* xHCI private pointer was set in xhci_pci_probe for the second
5276 * registered roothub.
5281 mutex_init(&xhci->mutex);
5282 xhci->cap_regs = hcd->regs;
5283 xhci->op_regs = hcd->regs +
5284 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5285 xhci->run_regs = hcd->regs +
5286 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5287 /* Cache read-only capability registers */
5288 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5289 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5290 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5291 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5292 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5293 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5294 if (xhci->hci_version > 0x100)
5295 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5297 xhci->quirks |= quirks;
5299 get_quirks(dev, xhci);
5301 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5302 * success event after a short transfer. This quirk will ignore such
5305 if (xhci->hci_version > 0x96)
5306 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5308 /* Make sure the HC is halted. */
5309 retval = xhci_halt(xhci);
5313 xhci_zero_64b_regs(xhci);
5315 xhci_dbg(xhci, "Resetting HCD\n");
5316 /* Reset the internal HC memory state and registers. */
5317 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5320 xhci_dbg(xhci, "Reset complete\n");
5323 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5324 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5325 * address memory pointers actually. So, this driver clears the AC64
5326 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5327 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5329 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5330 xhci->hcc_params &= ~BIT(0);
5332 /* Set dma_mask and coherent_dma_mask to 64-bits,
5333 * if xHC supports 64-bit addressing */
5334 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5335 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5336 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5337 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5340 * This is to avoid error in cases where a 32-bit USB
5341 * controller is used on a 64-bit capable system.
5343 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5346 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5347 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5350 xhci_dbg(xhci, "Calling HCD init\n");
5351 /* Initialize HCD and host controller data structures. */
5352 retval = xhci_init(hcd);
5355 xhci_dbg(xhci, "Called HCD init\n");
5357 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5358 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5362 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5364 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5365 struct usb_host_endpoint *ep)
5367 struct xhci_hcd *xhci;
5368 struct usb_device *udev;
5369 unsigned int slot_id;
5370 unsigned int ep_index;
5371 unsigned long flags;
5373 xhci = hcd_to_xhci(hcd);
5375 spin_lock_irqsave(&xhci->lock, flags);
5376 udev = (struct usb_device *)ep->hcpriv;
5377 slot_id = udev->slot_id;
5378 ep_index = xhci_get_endpoint_index(&ep->desc);
5380 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5381 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5382 spin_unlock_irqrestore(&xhci->lock, flags);
5385 static const struct hc_driver xhci_hc_driver = {
5386 .description = "xhci-hcd",
5387 .product_desc = "xHCI Host Controller",
5388 .hcd_priv_size = sizeof(struct xhci_hcd),
5391 * generic hardware linkage
5394 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5398 * basic lifecycle operations
5400 .reset = NULL, /* set in xhci_init_driver() */
5403 .shutdown = xhci_shutdown,
5406 * managing i/o requests and associated device resources
5408 .map_urb_for_dma = xhci_map_urb_for_dma,
5409 .urb_enqueue = xhci_urb_enqueue,
5410 .urb_dequeue = xhci_urb_dequeue,
5411 .alloc_dev = xhci_alloc_dev,
5412 .free_dev = xhci_free_dev,
5413 .alloc_streams = xhci_alloc_streams,
5414 .free_streams = xhci_free_streams,
5415 .add_endpoint = xhci_add_endpoint,
5416 .drop_endpoint = xhci_drop_endpoint,
5417 .endpoint_disable = xhci_endpoint_disable,
5418 .endpoint_reset = xhci_endpoint_reset,
5419 .check_bandwidth = xhci_check_bandwidth,
5420 .reset_bandwidth = xhci_reset_bandwidth,
5421 .address_device = xhci_address_device,
5422 .enable_device = xhci_enable_device,
5423 .update_hub_device = xhci_update_hub_device,
5424 .reset_device = xhci_discover_or_reset_device,
5427 * scheduling support
5429 .get_frame_number = xhci_get_frame,
5434 .hub_control = xhci_hub_control,
5435 .hub_status_data = xhci_hub_status_data,
5436 .bus_suspend = xhci_bus_suspend,
5437 .bus_resume = xhci_bus_resume,
5438 .get_resuming_ports = xhci_get_resuming_ports,
5441 * call back when device connected and addressed
5443 .update_device = xhci_update_device,
5444 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5445 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5446 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5447 .find_raw_port_number = xhci_find_raw_port_number,
5448 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5451 void xhci_init_driver(struct hc_driver *drv,
5452 const struct xhci_driver_overrides *over)
5456 /* Copy the generic table to drv then apply the overrides */
5457 *drv = xhci_hc_driver;
5460 drv->hcd_priv_size += over->extra_priv_size;
5462 drv->reset = over->reset;
5464 drv->start = over->start;
5465 if (over->check_bandwidth)
5466 drv->check_bandwidth = over->check_bandwidth;
5467 if (over->reset_bandwidth)
5468 drv->reset_bandwidth = over->reset_bandwidth;
5469 if (over->update_hub_device)
5470 drv->update_hub_device = over->update_hub_device;
5473 EXPORT_SYMBOL_GPL(xhci_init_driver);
5475 MODULE_DESCRIPTION(DRIVER_DESC);
5476 MODULE_AUTHOR(DRIVER_AUTHOR);
5477 MODULE_LICENSE("GPL");
5479 static int __init xhci_hcd_init(void)
5482 * Check the compiler generated sizes of structures that must be laid
5483 * out in specific ways for hardware access.
5485 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5486 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5487 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5488 /* xhci_device_control has eight fields, and also
5489 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5491 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5492 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5493 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5494 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5495 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5496 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5497 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5502 xhci_debugfs_create_root();
5508 * If an init function is provided, an exit function must also be provided
5509 * to allow module unload.
5511 static void __exit xhci_hcd_fini(void)
5513 xhci_debugfs_remove_root();
5516 module_init(xhci_hcd_init);
5517 module_exit(xhci_hcd_fini);