1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iommu.h>
13 #include <linux/iopoll.h>
14 #include <linux/irq.h>
15 #include <linux/log2.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/slab.h>
19 #include <linux/dmi.h>
20 #include <linux/dma-mapping.h>
23 #include "xhci-trace.h"
24 #include "xhci-debugfs.h"
25 #include "xhci-dbgcap.h"
27 #define DRIVER_AUTHOR "Sarah Sharp"
28 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
32 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
33 static int link_quirk;
34 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
35 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
37 static unsigned long long quirks;
38 module_param(quirks, ullong, S_IRUGO);
39 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
41 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
43 struct xhci_segment *seg = ring->first_seg;
45 if (!td || !td->start_seg)
48 if (seg == td->start_seg)
51 } while (seg && seg != ring->first_seg);
57 * xhci_handshake - spin reading hc until handshake completes or fails
58 * @ptr: address of hc register to be read
59 * @mask: bits to look at in result of read
60 * @done: value of those bits when handshake succeeds
61 * @usec: timeout in microseconds
63 * Returns negative errno, or zero on success
65 * Success happens when the "mask" bits have the specified value (hardware
66 * handshake done). There are two failure modes: "usec" have passed (major
67 * hardware flakeout), or the register reads as all-ones (hardware removed).
69 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
74 ret = readl_poll_timeout_atomic(ptr, result,
75 (result & mask) == done ||
78 if (result == U32_MAX) /* card removed */
85 * xhci_handshake_check_state - same as xhci_handshake but takes an additional
86 * exit_state parameter, and bails out with an error immediately when xhc_state
87 * has exit_state flag set.
89 int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr,
90 u32 mask, u32 done, int usec, unsigned int exit_state)
95 ret = readl_poll_timeout_atomic(ptr, result,
96 (result & mask) == done ||
98 xhci->xhc_state & exit_state,
101 if (result == U32_MAX || xhci->xhc_state & exit_state)
108 * Disable interrupts and begin the xHCI halting process.
110 void xhci_quiesce(struct xhci_hcd *xhci)
117 halted = readl(&xhci->op_regs->status) & STS_HALT;
121 cmd = readl(&xhci->op_regs->command);
123 writel(cmd, &xhci->op_regs->command);
127 * Force HC into halt state.
129 * Disable any IRQs and clear the run/stop bit.
130 * HC will complete any current and actively pipelined transactions, and
131 * should halt within 16 ms of the run/stop bit being cleared.
132 * Read HC Halted bit in the status register to see when the HC is finished.
134 int xhci_halt(struct xhci_hcd *xhci)
138 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
141 ret = xhci_handshake(&xhci->op_regs->status,
142 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
144 xhci_warn(xhci, "Host halt failed, %d\n", ret);
148 xhci->xhc_state |= XHCI_STATE_HALTED;
149 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
155 * Set the run bit and wait for the host to be running.
157 int xhci_start(struct xhci_hcd *xhci)
162 temp = readl(&xhci->op_regs->command);
164 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
166 writel(temp, &xhci->op_regs->command);
169 * Wait for the HCHalted Status bit to be 0 to indicate the host is
172 ret = xhci_handshake(&xhci->op_regs->status,
173 STS_HALT, 0, XHCI_MAX_HALT_USEC);
174 if (ret == -ETIMEDOUT)
175 xhci_err(xhci, "Host took too long to start, "
176 "waited %u microseconds.\n",
179 /* clear state flags. Including dying, halted or removing */
181 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
190 * This resets pipelines, timers, counters, state machines, etc.
191 * Transactions will be terminated immediately, and operational registers
192 * will be set to their defaults.
194 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
200 state = readl(&xhci->op_regs->status);
202 if (state == ~(u32)0) {
203 xhci_warn(xhci, "Host not accessible, reset failed.\n");
207 if ((state & STS_HALT) == 0) {
208 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
212 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
213 command = readl(&xhci->op_regs->command);
214 command |= CMD_RESET;
215 writel(command, &xhci->op_regs->command);
217 /* Existing Intel xHCI controllers require a delay of 1 mS,
218 * after setting the CMD_RESET bit, and before accessing any
219 * HC registers. This allows the HC to complete the
220 * reset operation and be ready for HC register access.
221 * Without this delay, the subsequent HC register access,
222 * may result in a system hang very rarely.
224 if (xhci->quirks & XHCI_INTEL_HOST)
227 ret = xhci_handshake_check_state(xhci, &xhci->op_regs->command,
228 CMD_RESET, 0, timeout_us, XHCI_STATE_REMOVING);
232 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
233 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
235 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
236 "Wait for controller to be ready for doorbell rings");
238 * xHCI cannot write to any doorbells or operational registers other
239 * than status until the "Controller Not Ready" flag is cleared.
241 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
243 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
244 xhci->usb2_rhub.bus_state.suspended_ports = 0;
245 xhci->usb2_rhub.bus_state.resuming_ports = 0;
246 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
247 xhci->usb3_rhub.bus_state.suspended_ports = 0;
248 xhci->usb3_rhub.bus_state.resuming_ports = 0;
253 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
255 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
256 struct iommu_domain *domain;
262 * Some Renesas controllers get into a weird state if they are
263 * reset while programmed with 64bit addresses (they will preserve
264 * the top half of the address in internal, non visible
265 * registers). You end up with half the address coming from the
266 * kernel, and the other half coming from the firmware. Also,
267 * changing the programming leads to extra accesses even if the
268 * controller is supposed to be halted. The controller ends up with
269 * a fatal fault, and is then ripe for being properly reset.
271 * Special care is taken to only apply this if the device is behind
272 * an iommu. Doing anything when there is no iommu is definitely
275 domain = iommu_get_domain_for_dev(dev);
276 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !domain ||
277 domain->type == IOMMU_DOMAIN_IDENTITY)
280 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
282 /* Clear HSEIE so that faults do not get signaled */
283 val = readl(&xhci->op_regs->command);
285 writel(val, &xhci->op_regs->command);
287 /* Clear HSE (aka FATAL) */
288 val = readl(&xhci->op_regs->status);
290 writel(val, &xhci->op_regs->status);
292 /* Now zero the registers, and brace for impact */
293 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
294 if (upper_32_bits(val))
295 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
296 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
297 if (upper_32_bits(val))
298 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
300 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
301 ARRAY_SIZE(xhci->run_regs->ir_set));
303 for (i = 0; i < intrs; i++) {
304 struct xhci_intr_reg __iomem *ir;
306 ir = &xhci->run_regs->ir_set[i];
307 val = xhci_read_64(xhci, &ir->erst_base);
308 if (upper_32_bits(val))
309 xhci_write_64(xhci, 0, &ir->erst_base);
310 val= xhci_read_64(xhci, &ir->erst_dequeue);
311 if (upper_32_bits(val))
312 xhci_write_64(xhci, 0, &ir->erst_dequeue);
315 /* Wait for the fault to appear. It will be cleared on reset */
316 err = xhci_handshake(&xhci->op_regs->status,
317 STS_FATAL, STS_FATAL,
320 xhci_info(xhci, "Fault detected\n");
323 static int xhci_enable_interrupter(struct xhci_interrupter *ir)
327 if (!ir || !ir->ir_set)
330 iman = readl(&ir->ir_set->irq_pending);
331 writel(ER_IRQ_ENABLE(iman), &ir->ir_set->irq_pending);
336 static int xhci_disable_interrupter(struct xhci_interrupter *ir)
340 if (!ir || !ir->ir_set)
343 iman = readl(&ir->ir_set->irq_pending);
344 writel(ER_IRQ_DISABLE(iman), &ir->ir_set->irq_pending);
349 static void compliance_mode_recovery(struct timer_list *t)
351 struct xhci_hcd *xhci;
353 struct xhci_hub *rhub;
357 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
358 rhub = &xhci->usb3_rhub;
364 for (i = 0; i < rhub->num_ports; i++) {
365 temp = readl(rhub->ports[i]->addr);
366 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
368 * Compliance Mode Detected. Letting USB Core
369 * handle the Warm Reset
371 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
372 "Compliance mode detected->port %d",
374 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
375 "Attempting compliance mode recovery");
377 if (hcd->state == HC_STATE_SUSPENDED)
378 usb_hcd_resume_root_hub(hcd);
380 usb_hcd_poll_rh_status(hcd);
384 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
385 mod_timer(&xhci->comp_mode_recovery_timer,
386 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
390 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
391 * that causes ports behind that hardware to enter compliance mode sometimes.
392 * The quirk creates a timer that polls every 2 seconds the link state of
393 * each host controller's port and recovers it by issuing a Warm reset
394 * if Compliance mode is detected, otherwise the port will become "dead" (no
395 * device connections or disconnections will be detected anymore). Becasue no
396 * status event is generated when entering compliance mode (per xhci spec),
397 * this quirk is needed on systems that have the failing hardware installed.
399 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
401 xhci->port_status_u0 = 0;
402 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
404 xhci->comp_mode_recovery_timer.expires = jiffies +
405 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
407 add_timer(&xhci->comp_mode_recovery_timer);
408 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
409 "Compliance mode recovery timer initialized");
413 * This function identifies the systems that have installed the SN65LVPE502CP
414 * USB3.0 re-driver and that need the Compliance Mode Quirk.
416 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
418 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
420 const char *dmi_product_name, *dmi_sys_vendor;
422 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
423 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
424 if (!dmi_product_name || !dmi_sys_vendor)
427 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
430 if (strstr(dmi_product_name, "Z420") ||
431 strstr(dmi_product_name, "Z620") ||
432 strstr(dmi_product_name, "Z820") ||
433 strstr(dmi_product_name, "Z1 Workstation"))
439 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
441 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
446 * Initialize memory for HCD and xHC (one-time init).
448 * Program the PAGESIZE register, initialize the device context array, create
449 * device contexts (?), set up a command ring segment (or two?), create event
450 * ring (one for now).
452 static int xhci_init(struct usb_hcd *hcd)
454 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
457 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
458 spin_lock_init(&xhci->lock);
459 if (xhci->hci_version == 0x95 && link_quirk) {
460 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
461 "QUIRK: Not clearing Link TRB chain bits.");
462 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
464 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
465 "xHCI doesn't need link TRB QUIRK");
467 retval = xhci_mem_init(xhci, GFP_KERNEL);
468 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
470 /* Initializing Compliance Mode Recovery Data If Needed */
471 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
472 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
473 compliance_mode_recovery_timer_init(xhci);
479 /*-------------------------------------------------------------------------*/
481 static int xhci_run_finished(struct xhci_hcd *xhci)
483 struct xhci_interrupter *ir = xhci->interrupter;
488 * Enable interrupts before starting the host (xhci 4.2 and 5.5.2).
489 * Protect the short window before host is running with a lock
491 spin_lock_irqsave(&xhci->lock, flags);
493 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable interrupts");
494 temp = readl(&xhci->op_regs->command);
496 writel(temp, &xhci->op_regs->command);
498 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable primary interrupter");
499 xhci_enable_interrupter(ir);
501 if (xhci_start(xhci)) {
503 spin_unlock_irqrestore(&xhci->lock, flags);
507 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
509 if (xhci->quirks & XHCI_NEC_HOST)
510 xhci_ring_cmd_db(xhci);
512 spin_unlock_irqrestore(&xhci->lock, flags);
518 * Start the HC after it was halted.
520 * This function is called by the USB core when the HC driver is added.
521 * Its opposite is xhci_stop().
523 * xhci_init() must be called once before this function can be called.
524 * Reset the HC, enable device slot contexts, program DCBAAP, and
525 * set command ring pointer and event ring pointer.
527 * Setup MSI-X vectors and enable interrupts.
529 int xhci_run(struct usb_hcd *hcd)
534 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
535 struct xhci_interrupter *ir = xhci->interrupter;
536 /* Start the xHCI host controller running only after the USB 2.0 roothub
540 hcd->uses_new_polling = 1;
541 if (!usb_hcd_is_primary_hcd(hcd))
542 return xhci_run_finished(xhci);
544 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
546 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
547 temp_64 &= ERST_PTR_MASK;
548 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
549 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
551 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
552 "// Set the interrupt modulation register");
553 temp = readl(&ir->ir_set->irq_control);
554 temp &= ~ER_IRQ_INTERVAL_MASK;
555 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
556 writel(temp, &ir->ir_set->irq_control);
558 if (xhci->quirks & XHCI_NEC_HOST) {
559 struct xhci_command *command;
561 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
565 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
566 TRB_TYPE(TRB_NEC_GET_FW));
568 xhci_free_command(xhci, command);
570 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
571 "Finished %s for main hcd", __func__);
573 xhci_create_dbc_dev(xhci);
575 xhci_debugfs_init(xhci);
577 if (xhci_has_one_roothub(xhci))
578 return xhci_run_finished(xhci);
580 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
584 EXPORT_SYMBOL_GPL(xhci_run);
589 * This function is called by the USB core when the HC driver is removed.
590 * Its opposite is xhci_run().
592 * Disable device contexts, disable IRQs, and quiesce the HC.
593 * Reset the HC, finish any completed transactions, and cleanup memory.
595 void xhci_stop(struct usb_hcd *hcd)
598 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
599 struct xhci_interrupter *ir = xhci->interrupter;
601 mutex_lock(&xhci->mutex);
603 /* Only halt host and free memory after both hcds are removed */
604 if (!usb_hcd_is_primary_hcd(hcd)) {
605 mutex_unlock(&xhci->mutex);
609 xhci_remove_dbc_dev(xhci);
611 spin_lock_irq(&xhci->lock);
612 xhci->xhc_state |= XHCI_STATE_HALTED;
613 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
615 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
616 spin_unlock_irq(&xhci->lock);
618 /* Deleting Compliance Mode Recovery Timer */
619 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
620 (!(xhci_all_ports_seen_u0(xhci)))) {
621 del_timer_sync(&xhci->comp_mode_recovery_timer);
622 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
623 "%s: compliance mode recovery timer deleted",
627 if (xhci->quirks & XHCI_AMD_PLL_FIX)
630 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
631 "// Disabling event ring interrupts");
632 temp = readl(&xhci->op_regs->status);
633 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
634 xhci_disable_interrupter(ir);
636 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
637 xhci_mem_cleanup(xhci);
638 xhci_debugfs_exit(xhci);
639 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
640 "xhci_stop completed - status = %x",
641 readl(&xhci->op_regs->status));
642 mutex_unlock(&xhci->mutex);
644 EXPORT_SYMBOL_GPL(xhci_stop);
647 * Shutdown HC (not bus-specific)
649 * This is called when the machine is rebooting or halting. We assume that the
650 * machine will be powered off, and the HC's internal state will be reset.
651 * Don't bother to free memory.
653 * This will only ever be called with the main usb_hcd (the USB3 roothub).
655 void xhci_shutdown(struct usb_hcd *hcd)
657 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
659 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
660 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
662 /* Don't poll the roothubs after shutdown. */
663 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
664 __func__, hcd->self.busnum);
665 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
666 del_timer_sync(&hcd->rh_timer);
668 if (xhci->shared_hcd) {
669 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
670 del_timer_sync(&xhci->shared_hcd->rh_timer);
673 spin_lock_irq(&xhci->lock);
677 * Workaround for spurious wakeps at shutdown with HSW, and for boot
678 * firmware delay in ADL-P PCH if port are left in U3 at shutdown
680 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
681 xhci->quirks & XHCI_RESET_TO_DEFAULT)
682 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
684 spin_unlock_irq(&xhci->lock);
686 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
687 "xhci_shutdown completed - status = %x",
688 readl(&xhci->op_regs->status));
690 EXPORT_SYMBOL_GPL(xhci_shutdown);
693 static void xhci_save_registers(struct xhci_hcd *xhci)
695 struct xhci_interrupter *ir = xhci->interrupter;
697 xhci->s3.command = readl(&xhci->op_regs->command);
698 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
699 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
700 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
705 ir->s3_erst_size = readl(&ir->ir_set->erst_size);
706 ir->s3_erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
707 ir->s3_erst_dequeue = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
708 ir->s3_irq_pending = readl(&ir->ir_set->irq_pending);
709 ir->s3_irq_control = readl(&ir->ir_set->irq_control);
712 static void xhci_restore_registers(struct xhci_hcd *xhci)
714 struct xhci_interrupter *ir = xhci->interrupter;
716 writel(xhci->s3.command, &xhci->op_regs->command);
717 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
718 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
719 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
720 writel(ir->s3_erst_size, &ir->ir_set->erst_size);
721 xhci_write_64(xhci, ir->s3_erst_base, &ir->ir_set->erst_base);
722 xhci_write_64(xhci, ir->s3_erst_dequeue, &ir->ir_set->erst_dequeue);
723 writel(ir->s3_irq_pending, &ir->ir_set->irq_pending);
724 writel(ir->s3_irq_control, &ir->ir_set->irq_control);
727 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
731 /* step 2: initialize command ring buffer */
732 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
733 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
734 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
735 xhci->cmd_ring->dequeue) &
736 (u64) ~CMD_RING_RSVD_BITS) |
737 xhci->cmd_ring->cycle_state;
738 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
739 "// Setting command ring address to 0x%llx",
740 (long unsigned long) val_64);
741 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
745 * The whole command ring must be cleared to zero when we suspend the host.
747 * The host doesn't save the command ring pointer in the suspend well, so we
748 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
749 * aligned, because of the reserved bits in the command ring dequeue pointer
750 * register. Therefore, we can't just set the dequeue pointer back in the
751 * middle of the ring (TRBs are 16-byte aligned).
753 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
755 struct xhci_ring *ring;
756 struct xhci_segment *seg;
758 ring = xhci->cmd_ring;
762 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
763 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
764 cpu_to_le32(~TRB_CYCLE);
766 } while (seg != ring->deq_seg);
768 /* Reset the software enqueue and dequeue pointers */
769 ring->deq_seg = ring->first_seg;
770 ring->dequeue = ring->first_seg->trbs;
771 ring->enq_seg = ring->deq_seg;
772 ring->enqueue = ring->dequeue;
774 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
776 * Ring is now zeroed, so the HW should look for change of ownership
777 * when the cycle bit is set to 1.
779 ring->cycle_state = 1;
782 * Reset the hardware dequeue pointer.
783 * Yes, this will need to be re-written after resume, but we're paranoid
784 * and want to make sure the hardware doesn't access bogus memory
785 * because, say, the BIOS or an SMI started the host without changing
786 * the command ring pointers.
788 xhci_set_cmd_ring_deq(xhci);
792 * Disable port wake bits if do_wakeup is not set.
794 * Also clear a possible internal port wake state left hanging for ports that
795 * detected termination but never successfully enumerated (trained to 0U).
796 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
797 * at enumeration clears this wake, force one here as well for unconnected ports
800 static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
801 struct xhci_hub *rhub,
808 spin_lock_irqsave(&xhci->lock, flags);
810 for (i = 0; i < rhub->num_ports; i++) {
811 portsc = readl(rhub->ports[i]->addr);
812 t1 = xhci_port_state_to_neutral(portsc);
815 /* clear wake bits if do_wake is not set */
817 t2 &= ~PORT_WAKE_BITS;
819 /* Don't touch csc bit if connected or connect change is set */
820 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
824 writel(t2, rhub->ports[i]->addr);
825 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
826 rhub->hcd->self.busnum, i + 1, portsc, t2);
829 spin_unlock_irqrestore(&xhci->lock, flags);
832 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
834 struct xhci_port **ports;
839 status = readl(&xhci->op_regs->status);
840 if (status & STS_EINT)
843 * Checking STS_EINT is not enough as there is a lag between a change
844 * bit being set and the Port Status Change Event that it generated
845 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
848 port_index = xhci->usb2_rhub.num_ports;
849 ports = xhci->usb2_rhub.ports;
850 while (port_index--) {
851 portsc = readl(ports[port_index]->addr);
852 if (portsc & PORT_CHANGE_MASK ||
853 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
856 port_index = xhci->usb3_rhub.num_ports;
857 ports = xhci->usb3_rhub.ports;
858 while (port_index--) {
859 portsc = readl(ports[port_index]->addr);
860 if (portsc & (PORT_CHANGE_MASK | PORT_CAS) ||
861 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
868 * Stop HC (not bus-specific)
870 * This is called when the machine transition into S3/S4 mode.
873 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
876 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
877 struct usb_hcd *hcd = xhci_to_hcd(xhci);
884 if (hcd->state != HC_STATE_SUSPENDED ||
885 (xhci->shared_hcd && xhci->shared_hcd->state != HC_STATE_SUSPENDED))
888 /* Clear root port wake on bits if wakeup not allowed. */
889 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
890 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
892 if (!HCD_HW_ACCESSIBLE(hcd))
895 xhci_dbc_suspend(xhci);
897 /* Don't poll the roothubs on bus suspend. */
898 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
899 __func__, hcd->self.busnum);
900 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
901 del_timer_sync(&hcd->rh_timer);
902 if (xhci->shared_hcd) {
903 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
904 del_timer_sync(&xhci->shared_hcd->rh_timer);
907 if (xhci->quirks & XHCI_SUSPEND_DELAY)
908 usleep_range(1000, 1500);
910 spin_lock_irq(&xhci->lock);
911 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
912 if (xhci->shared_hcd)
913 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
914 /* step 1: stop endpoint */
915 /* skipped assuming that port suspend has done */
917 /* step 2: clear Run/Stop bit */
918 command = readl(&xhci->op_regs->command);
920 writel(command, &xhci->op_regs->command);
922 /* Some chips from Fresco Logic need an extraordinary delay */
923 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
925 if (xhci_handshake(&xhci->op_regs->status,
926 STS_HALT, STS_HALT, delay)) {
927 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
928 spin_unlock_irq(&xhci->lock);
931 xhci_clear_command_ring(xhci);
933 /* step 3: save registers */
934 xhci_save_registers(xhci);
936 /* step 4: set CSS flag */
937 command = readl(&xhci->op_regs->command);
939 writel(command, &xhci->op_regs->command);
940 xhci->broken_suspend = 0;
941 if (xhci_handshake(&xhci->op_regs->status,
942 STS_SAVE, 0, 20 * 1000)) {
944 * AMD SNPS xHC 3.0 occasionally does not clear the
945 * SSS bit of USBSTS and when driver tries to poll
946 * to see if the xHC clears BIT(8) which never happens
947 * and driver assumes that controller is not responding
948 * and times out. To workaround this, its good to check
949 * if SRE and HCE bits are not set (as per xhci
950 * Section 5.4.2) and bypass the timeout.
952 res = readl(&xhci->op_regs->status);
953 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
954 (((res & STS_SRE) == 0) &&
955 ((res & STS_HCE) == 0))) {
956 xhci->broken_suspend = 1;
958 xhci_warn(xhci, "WARN: xHC save state timeout\n");
959 spin_unlock_irq(&xhci->lock);
963 spin_unlock_irq(&xhci->lock);
966 * Deleting Compliance Mode Recovery Timer because the xHCI Host
967 * is about to be suspended.
969 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
970 (!(xhci_all_ports_seen_u0(xhci)))) {
971 del_timer_sync(&xhci->comp_mode_recovery_timer);
972 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
973 "%s: compliance mode recovery timer deleted",
979 EXPORT_SYMBOL_GPL(xhci_suspend);
982 * start xHC (not bus-specific)
984 * This is called when the machine transition from S3/S4 mode.
987 int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg)
989 bool hibernated = (msg.event == PM_EVENT_RESTORE);
990 u32 command, temp = 0;
991 struct usb_hcd *hcd = xhci_to_hcd(xhci);
993 bool comp_timer_running = false;
994 bool pending_portevent = false;
995 bool suspended_usb3_devs = false;
996 bool reinit_xhc = false;
1001 /* Wait a bit if either of the roothubs need to settle from the
1002 * transition into bus suspend.
1005 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1006 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1009 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1010 if (xhci->shared_hcd)
1011 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1013 spin_lock_irq(&xhci->lock);
1015 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1020 * Some controllers might lose power during suspend, so wait
1021 * for controller not ready bit to clear, just as in xHC init.
1023 retval = xhci_handshake(&xhci->op_regs->status,
1024 STS_CNR, 0, 10 * 1000 * 1000);
1026 xhci_warn(xhci, "Controller not ready at resume %d\n",
1028 spin_unlock_irq(&xhci->lock);
1031 /* step 1: restore register */
1032 xhci_restore_registers(xhci);
1033 /* step 2: initialize command ring buffer */
1034 xhci_set_cmd_ring_deq(xhci);
1035 /* step 3: restore state and start state*/
1036 /* step 3: set CRS flag */
1037 command = readl(&xhci->op_regs->command);
1039 writel(command, &xhci->op_regs->command);
1041 * Some controllers take up to 55+ ms to complete the controller
1042 * restore so setting the timeout to 100ms. Xhci specification
1043 * doesn't mention any timeout value.
1045 if (xhci_handshake(&xhci->op_regs->status,
1046 STS_RESTORE, 0, 100 * 1000)) {
1047 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1048 spin_unlock_irq(&xhci->lock);
1053 temp = readl(&xhci->op_regs->status);
1055 /* re-initialize the HC on Restore Error, or Host Controller Error */
1056 if ((temp & (STS_SRE | STS_HCE)) &&
1057 !(xhci->xhc_state & XHCI_STATE_REMOVING)) {
1059 if (!xhci->broken_suspend)
1060 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1064 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1065 !(xhci_all_ports_seen_u0(xhci))) {
1066 del_timer_sync(&xhci->comp_mode_recovery_timer);
1067 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1068 "Compliance Mode Recovery Timer deleted!");
1071 /* Let the USB core know _both_ roothubs lost power. */
1072 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1073 if (xhci->shared_hcd)
1074 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1076 xhci_dbg(xhci, "Stop HCD\n");
1078 xhci_zero_64b_regs(xhci);
1079 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1080 spin_unlock_irq(&xhci->lock);
1084 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1085 temp = readl(&xhci->op_regs->status);
1086 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1087 xhci_disable_interrupter(xhci->interrupter);
1089 xhci_dbg(xhci, "cleaning up memory\n");
1090 xhci_mem_cleanup(xhci);
1091 xhci_debugfs_exit(xhci);
1092 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1093 readl(&xhci->op_regs->status));
1095 /* USB core calls the PCI reinit and start functions twice:
1096 * first with the primary HCD, and then with the secondary HCD.
1097 * If we don't do the same, the host will never be started.
1099 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1100 retval = xhci_init(hcd);
1103 comp_timer_running = true;
1105 xhci_dbg(xhci, "Start the primary HCD\n");
1106 retval = xhci_run(hcd);
1107 if (!retval && xhci->shared_hcd) {
1108 xhci_dbg(xhci, "Start the secondary HCD\n");
1109 retval = xhci_run(xhci->shared_hcd);
1112 hcd->state = HC_STATE_SUSPENDED;
1113 if (xhci->shared_hcd)
1114 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1118 /* step 4: set Run/Stop bit */
1119 command = readl(&xhci->op_regs->command);
1121 writel(command, &xhci->op_regs->command);
1122 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1125 /* step 5: walk topology and initialize portsc,
1126 * portpmsc and portli
1128 /* this is done in bus_resume */
1130 /* step 6: restart each of the previously
1131 * Running endpoints by ringing their doorbells
1134 spin_unlock_irq(&xhci->lock);
1136 xhci_dbc_resume(xhci);
1141 * Resume roothubs only if there are pending events.
1142 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1143 * the first wake signalling failed, give it that chance if
1144 * there are suspended USB 3 devices.
1146 if (xhci->usb3_rhub.bus_state.suspended_ports ||
1147 xhci->usb3_rhub.bus_state.bus_suspended)
1148 suspended_usb3_devs = true;
1150 pending_portevent = xhci_pending_portevent(xhci);
1152 if (suspended_usb3_devs && !pending_portevent &&
1153 msg.event == PM_EVENT_AUTO_RESUME) {
1155 pending_portevent = xhci_pending_portevent(xhci);
1158 if (pending_portevent) {
1159 if (xhci->shared_hcd)
1160 usb_hcd_resume_root_hub(xhci->shared_hcd);
1161 usb_hcd_resume_root_hub(hcd);
1165 * If system is subject to the Quirk, Compliance Mode Timer needs to
1166 * be re-initialized Always after a system resume. Ports are subject
1167 * to suffer the Compliance Mode issue again. It doesn't matter if
1168 * ports have entered previously to U0 before system's suspension.
1170 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1171 compliance_mode_recovery_timer_init(xhci);
1173 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1174 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1176 /* Re-enable port polling. */
1177 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1178 __func__, hcd->self.busnum);
1179 if (xhci->shared_hcd) {
1180 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1181 usb_hcd_poll_rh_status(xhci->shared_hcd);
1183 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1184 usb_hcd_poll_rh_status(hcd);
1188 EXPORT_SYMBOL_GPL(xhci_resume);
1189 #endif /* CONFIG_PM */
1191 /*-------------------------------------------------------------------------*/
1193 static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1197 unsigned int buf_len;
1198 enum dma_data_direction dir;
1200 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1201 buf_len = urb->transfer_buffer_length;
1203 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1204 dev_to_node(hcd->self.sysdev));
1206 if (usb_urb_dir_out(urb))
1207 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1210 urb->transfer_buffer = temp;
1211 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1212 urb->transfer_buffer,
1213 urb->transfer_buffer_length,
1216 if (dma_mapping_error(hcd->self.sysdev,
1217 urb->transfer_dma)) {
1221 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1227 static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1232 unsigned int len = 0;
1233 unsigned int trb_size;
1234 unsigned int max_pkt;
1235 struct scatterlist *sg;
1236 struct scatterlist *tail_sg;
1239 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1244 if (urb->dev->speed >= USB_SPEED_SUPER)
1245 trb_size = TRB_CACHE_SIZE_SS;
1247 trb_size = TRB_CACHE_SIZE_HS;
1249 if (urb->transfer_buffer_length != 0 &&
1250 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1251 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1252 len = len + sg->length;
1253 if (i > trb_size - 2) {
1254 len = len - tail_sg->length;
1255 if (len < max_pkt) {
1260 tail_sg = sg_next(tail_sg);
1267 static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1270 unsigned int buf_len;
1271 enum dma_data_direction dir;
1273 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1275 buf_len = urb->transfer_buffer_length;
1277 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1278 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1279 dma_unmap_single(hcd->self.sysdev,
1281 urb->transfer_buffer_length,
1284 if (usb_urb_dir_in(urb)) {
1285 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1286 urb->transfer_buffer,
1289 if (len != buf_len) {
1290 xhci_dbg(hcd_to_xhci(hcd),
1291 "Copy from tmp buf to urb sg list failed\n");
1292 urb->actual_length = len;
1295 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1296 kfree(urb->transfer_buffer);
1297 urb->transfer_buffer = NULL;
1301 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1302 * we'll copy the actual data into the TRB address register. This is limited to
1303 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1304 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1306 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1309 struct xhci_hcd *xhci;
1311 xhci = hcd_to_xhci(hcd);
1313 if (xhci_urb_suitable_for_idt(urb))
1316 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1317 if (xhci_urb_temp_buffer_required(hcd, urb))
1318 return xhci_map_temp_buffer(hcd, urb);
1320 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1323 static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1325 struct xhci_hcd *xhci;
1326 bool unmap_temp_buf = false;
1328 xhci = hcd_to_xhci(hcd);
1330 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1331 unmap_temp_buf = true;
1333 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1334 xhci_unmap_temp_buf(hcd, urb);
1336 usb_hcd_unmap_urb_for_dma(hcd, urb);
1340 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1341 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1342 * value to right shift 1 for the bitmask.
1344 * Index = (epnum * 2) + direction - 1,
1345 * where direction = 0 for OUT, 1 for IN.
1346 * For control endpoints, the IN index is used (OUT index is unused), so
1347 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1349 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1352 if (usb_endpoint_xfer_control(desc))
1353 index = (unsigned int) (usb_endpoint_num(desc)*2);
1355 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1356 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1359 EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1361 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1362 * address from the XHCI endpoint index.
1364 static unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1366 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1367 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1368 return direction | number;
1371 /* Find the flag for this endpoint (for use in the control context). Use the
1372 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1375 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1377 return 1 << (xhci_get_endpoint_index(desc) + 1);
1380 /* Compute the last valid endpoint context index. Basically, this is the
1381 * endpoint index plus one. For slot contexts with more than valid endpoint,
1382 * we find the most significant bit set in the added contexts flags.
1383 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1384 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1386 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1388 return fls(added_ctxs) - 1;
1391 /* Returns 1 if the arguments are OK;
1392 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1394 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1395 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1397 struct xhci_hcd *xhci;
1398 struct xhci_virt_device *virt_dev;
1400 if (!hcd || (check_ep && !ep) || !udev) {
1401 pr_debug("xHCI %s called with invalid args\n", func);
1404 if (!udev->parent) {
1405 pr_debug("xHCI %s called for root hub\n", func);
1409 xhci = hcd_to_xhci(hcd);
1410 if (check_virt_dev) {
1411 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1412 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1417 virt_dev = xhci->devs[udev->slot_id];
1418 if (virt_dev->udev != udev) {
1419 xhci_dbg(xhci, "xHCI %s called with udev and "
1420 "virt_dev does not match\n", func);
1425 if (xhci->xhc_state & XHCI_STATE_HALTED)
1431 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1432 struct usb_device *udev, struct xhci_command *command,
1433 bool ctx_change, bool must_succeed);
1436 * Full speed devices may have a max packet size greater than 8 bytes, but the
1437 * USB core doesn't know that until it reads the first 8 bytes of the
1438 * descriptor. If the usb_device's max packet size changes after that point,
1439 * we need to issue an evaluate context command and wait on it.
1441 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1442 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1444 struct xhci_container_ctx *out_ctx;
1445 struct xhci_input_control_ctx *ctrl_ctx;
1446 struct xhci_ep_ctx *ep_ctx;
1447 struct xhci_command *command;
1448 int max_packet_size;
1449 int hw_max_packet_size;
1452 out_ctx = xhci->devs[slot_id]->out_ctx;
1453 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1454 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1455 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1456 if (hw_max_packet_size != max_packet_size) {
1457 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1458 "Max Packet Size for ep 0 changed.");
1459 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1460 "Max packet size in usb_device = %d",
1462 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1463 "Max packet size in xHCI HW = %d",
1464 hw_max_packet_size);
1465 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1466 "Issuing evaluate context command.");
1468 /* Set up the input context flags for the command */
1469 /* FIXME: This won't work if a non-default control endpoint
1470 * changes max packet sizes.
1473 command = xhci_alloc_command(xhci, true, mem_flags);
1477 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1478 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1480 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1483 goto command_cleanup;
1485 /* Set up the modified control endpoint 0 */
1486 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1487 xhci->devs[slot_id]->out_ctx, ep_index);
1489 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1490 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1491 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1492 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1494 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1495 ctrl_ctx->drop_flags = 0;
1497 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1500 /* Clean up the input context for later use by bandwidth
1503 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1505 kfree(command->completion);
1512 * non-error returns are a promise to giveback() the urb later
1513 * we drop ownership so next owner (or urb unlink) can get it
1515 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1517 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1518 unsigned long flags;
1520 unsigned int slot_id, ep_index;
1521 unsigned int *ep_state;
1522 struct urb_priv *urb_priv;
1527 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1528 true, true, __func__);
1530 return ret ? ret : -EINVAL;
1532 slot_id = urb->dev->slot_id;
1533 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1534 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1536 if (!HCD_HW_ACCESSIBLE(hcd))
1539 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1540 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1544 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1545 num_tds = urb->number_of_packets;
1546 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1547 urb->transfer_buffer_length > 0 &&
1548 urb->transfer_flags & URB_ZERO_PACKET &&
1549 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1554 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1558 urb_priv->num_tds = num_tds;
1559 urb_priv->num_tds_done = 0;
1560 urb->hcpriv = urb_priv;
1562 trace_xhci_urb_enqueue(urb);
1564 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1565 /* Check to see if the max packet size for the default control
1566 * endpoint changed during FS device enumeration
1568 if (urb->dev->speed == USB_SPEED_FULL) {
1569 ret = xhci_check_maxpacket(xhci, slot_id,
1570 ep_index, urb, mem_flags);
1572 xhci_urb_free_priv(urb_priv);
1579 spin_lock_irqsave(&xhci->lock, flags);
1581 if (xhci->xhc_state & XHCI_STATE_DYING) {
1582 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1583 urb->ep->desc.bEndpointAddress, urb);
1587 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1588 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1593 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1594 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1599 switch (usb_endpoint_type(&urb->ep->desc)) {
1601 case USB_ENDPOINT_XFER_CONTROL:
1602 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1605 case USB_ENDPOINT_XFER_BULK:
1606 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1609 case USB_ENDPOINT_XFER_INT:
1610 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1613 case USB_ENDPOINT_XFER_ISOC:
1614 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1620 xhci_urb_free_priv(urb_priv);
1623 spin_unlock_irqrestore(&xhci->lock, flags);
1628 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1629 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1630 * should pick up where it left off in the TD, unless a Set Transfer Ring
1631 * Dequeue Pointer is issued.
1633 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1634 * the ring. Since the ring is a contiguous structure, they can't be physically
1635 * removed. Instead, there are two options:
1637 * 1) If the HC is in the middle of processing the URB to be canceled, we
1638 * simply move the ring's dequeue pointer past those TRBs using the Set
1639 * Transfer Ring Dequeue Pointer command. This will be the common case,
1640 * when drivers timeout on the last submitted URB and attempt to cancel.
1642 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1643 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1644 * HC will need to invalidate the any TRBs it has cached after the stop
1645 * endpoint command, as noted in the xHCI 0.95 errata.
1647 * 3) The TD may have completed by the time the Stop Endpoint Command
1648 * completes, so software needs to handle that case too.
1650 * This function should protect against the TD enqueueing code ringing the
1651 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1652 * It also needs to account for multiple cancellations on happening at the same
1653 * time for the same endpoint.
1655 * Note that this function can be called in any context, or so says
1656 * usb_hcd_unlink_urb()
1658 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1660 unsigned long flags;
1663 struct xhci_hcd *xhci;
1664 struct urb_priv *urb_priv;
1666 unsigned int ep_index;
1667 struct xhci_ring *ep_ring;
1668 struct xhci_virt_ep *ep;
1669 struct xhci_command *command;
1670 struct xhci_virt_device *vdev;
1672 xhci = hcd_to_xhci(hcd);
1673 spin_lock_irqsave(&xhci->lock, flags);
1675 trace_xhci_urb_dequeue(urb);
1677 /* Make sure the URB hasn't completed or been unlinked already */
1678 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1682 /* give back URB now if we can't queue it for cancel */
1683 vdev = xhci->devs[urb->dev->slot_id];
1684 urb_priv = urb->hcpriv;
1685 if (!vdev || !urb_priv)
1688 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1689 ep = &vdev->eps[ep_index];
1690 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1691 if (!ep || !ep_ring)
1694 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1695 temp = readl(&xhci->op_regs->status);
1696 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1702 * check ring is not re-allocated since URB was enqueued. If it is, then
1703 * make sure none of the ring related pointers in this URB private data
1704 * are touched, such as td_list, otherwise we overwrite freed data
1706 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1707 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1708 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1709 td = &urb_priv->td[i];
1710 if (!list_empty(&td->cancelled_td_list))
1711 list_del_init(&td->cancelled_td_list);
1716 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1717 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1718 "HC halted, freeing TD manually.");
1719 for (i = urb_priv->num_tds_done;
1720 i < urb_priv->num_tds;
1722 td = &urb_priv->td[i];
1723 if (!list_empty(&td->td_list))
1724 list_del_init(&td->td_list);
1725 if (!list_empty(&td->cancelled_td_list))
1726 list_del_init(&td->cancelled_td_list);
1731 i = urb_priv->num_tds_done;
1732 if (i < urb_priv->num_tds)
1733 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1734 "Cancel URB %p, dev %s, ep 0x%x, "
1735 "starting at offset 0x%llx",
1736 urb, urb->dev->devpath,
1737 urb->ep->desc.bEndpointAddress,
1738 (unsigned long long) xhci_trb_virt_to_dma(
1739 urb_priv->td[i].start_seg,
1740 urb_priv->td[i].first_trb));
1742 for (; i < urb_priv->num_tds; i++) {
1743 td = &urb_priv->td[i];
1744 /* TD can already be on cancelled list if ep halted on it */
1745 if (list_empty(&td->cancelled_td_list)) {
1746 td->cancel_status = TD_DIRTY;
1747 list_add_tail(&td->cancelled_td_list,
1748 &ep->cancelled_td_list);
1752 /* Queue a stop endpoint command, but only if this is
1753 * the first cancellation to be handled.
1755 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1756 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1761 ep->ep_state |= EP_STOP_CMD_PENDING;
1762 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1764 xhci_ring_cmd_db(xhci);
1767 spin_unlock_irqrestore(&xhci->lock, flags);
1772 xhci_urb_free_priv(urb_priv);
1773 usb_hcd_unlink_urb_from_ep(hcd, urb);
1774 spin_unlock_irqrestore(&xhci->lock, flags);
1775 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1779 /* Drop an endpoint from a new bandwidth configuration for this device.
1780 * Only one call to this function is allowed per endpoint before
1781 * check_bandwidth() or reset_bandwidth() must be called.
1782 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1783 * add the endpoint to the schedule with possibly new parameters denoted by a
1784 * different endpoint descriptor in usb_host_endpoint.
1785 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1788 * The USB core will not allow URBs to be queued to an endpoint that is being
1789 * disabled, so there's no need for mutual exclusion to protect
1790 * the xhci->devs[slot_id] structure.
1792 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1793 struct usb_host_endpoint *ep)
1795 struct xhci_hcd *xhci;
1796 struct xhci_container_ctx *in_ctx, *out_ctx;
1797 struct xhci_input_control_ctx *ctrl_ctx;
1798 unsigned int ep_index;
1799 struct xhci_ep_ctx *ep_ctx;
1801 u32 new_add_flags, new_drop_flags;
1804 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1807 xhci = hcd_to_xhci(hcd);
1808 if (xhci->xhc_state & XHCI_STATE_DYING)
1811 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1812 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1813 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1814 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1815 __func__, drop_flag);
1819 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1820 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1821 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1823 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1828 ep_index = xhci_get_endpoint_index(&ep->desc);
1829 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1830 /* If the HC already knows the endpoint is disabled,
1831 * or the HCD has noted it is disabled, ignore this request
1833 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1834 le32_to_cpu(ctrl_ctx->drop_flags) &
1835 xhci_get_endpoint_flag(&ep->desc)) {
1836 /* Do not warn when called after a usb_device_reset */
1837 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1838 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1843 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1844 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1846 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1847 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1849 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1851 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1853 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1854 (unsigned int) ep->desc.bEndpointAddress,
1856 (unsigned int) new_drop_flags,
1857 (unsigned int) new_add_flags);
1860 EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1862 /* Add an endpoint to a new possible bandwidth configuration for this device.
1863 * Only one call to this function is allowed per endpoint before
1864 * check_bandwidth() or reset_bandwidth() must be called.
1865 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1866 * add the endpoint to the schedule with possibly new parameters denoted by a
1867 * different endpoint descriptor in usb_host_endpoint.
1868 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1871 * The USB core will not allow URBs to be queued to an endpoint until the
1872 * configuration or alt setting is installed in the device, so there's no need
1873 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1875 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1876 struct usb_host_endpoint *ep)
1878 struct xhci_hcd *xhci;
1879 struct xhci_container_ctx *in_ctx;
1880 unsigned int ep_index;
1881 struct xhci_input_control_ctx *ctrl_ctx;
1882 struct xhci_ep_ctx *ep_ctx;
1884 u32 new_add_flags, new_drop_flags;
1885 struct xhci_virt_device *virt_dev;
1888 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1890 /* So we won't queue a reset ep command for a root hub */
1894 xhci = hcd_to_xhci(hcd);
1895 if (xhci->xhc_state & XHCI_STATE_DYING)
1898 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1899 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1900 /* FIXME when we have to issue an evaluate endpoint command to
1901 * deal with ep0 max packet size changing once we get the
1904 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1905 __func__, added_ctxs);
1909 virt_dev = xhci->devs[udev->slot_id];
1910 in_ctx = virt_dev->in_ctx;
1911 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1913 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1918 ep_index = xhci_get_endpoint_index(&ep->desc);
1919 /* If this endpoint is already in use, and the upper layers are trying
1920 * to add it again without dropping it, reject the addition.
1922 if (virt_dev->eps[ep_index].ring &&
1923 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1924 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1925 "without dropping it.\n",
1926 (unsigned int) ep->desc.bEndpointAddress);
1930 /* If the HCD has already noted the endpoint is enabled,
1931 * ignore this request.
1933 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1934 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1940 * Configuration and alternate setting changes must be done in
1941 * process context, not interrupt context (or so documenation
1942 * for usb_set_interface() and usb_set_configuration() claim).
1944 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1945 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1946 __func__, ep->desc.bEndpointAddress);
1950 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1951 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1953 /* If xhci_endpoint_disable() was called for this endpoint, but the
1954 * xHC hasn't been notified yet through the check_bandwidth() call,
1955 * this re-adds a new state for the endpoint from the new endpoint
1956 * descriptors. We must drop and re-add this endpoint, so we leave the
1959 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1961 /* Store the usb_device pointer for later use */
1964 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1965 trace_xhci_add_endpoint(ep_ctx);
1967 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1968 (unsigned int) ep->desc.bEndpointAddress,
1970 (unsigned int) new_drop_flags,
1971 (unsigned int) new_add_flags);
1974 EXPORT_SYMBOL_GPL(xhci_add_endpoint);
1976 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1978 struct xhci_input_control_ctx *ctrl_ctx;
1979 struct xhci_ep_ctx *ep_ctx;
1980 struct xhci_slot_ctx *slot_ctx;
1983 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1985 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1990 /* When a device's add flag and drop flag are zero, any subsequent
1991 * configure endpoint command will leave that endpoint's state
1992 * untouched. Make sure we don't leave any old state in the input
1993 * endpoint contexts.
1995 ctrl_ctx->drop_flags = 0;
1996 ctrl_ctx->add_flags = 0;
1997 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1998 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1999 /* Endpoint 0 is always valid */
2000 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2001 for (i = 1; i < 31; i++) {
2002 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2003 ep_ctx->ep_info = 0;
2004 ep_ctx->ep_info2 = 0;
2006 ep_ctx->tx_info = 0;
2010 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2011 struct usb_device *udev, u32 *cmd_status)
2015 switch (*cmd_status) {
2016 case COMP_COMMAND_ABORTED:
2017 case COMP_COMMAND_RING_STOPPED:
2018 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2021 case COMP_RESOURCE_ERROR:
2022 dev_warn(&udev->dev,
2023 "Not enough host controller resources for new device state.\n");
2025 /* FIXME: can we allocate more resources for the HC? */
2027 case COMP_BANDWIDTH_ERROR:
2028 case COMP_SECONDARY_BANDWIDTH_ERROR:
2029 dev_warn(&udev->dev,
2030 "Not enough bandwidth for new device state.\n");
2032 /* FIXME: can we go back to the old state? */
2034 case COMP_TRB_ERROR:
2035 /* the HCD set up something wrong */
2036 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2038 "and endpoint is not disabled.\n");
2041 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2042 dev_warn(&udev->dev,
2043 "ERROR: Incompatible device for endpoint configure command.\n");
2047 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2048 "Successful Endpoint Configure command");
2052 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2060 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2061 struct usb_device *udev, u32 *cmd_status)
2065 switch (*cmd_status) {
2066 case COMP_COMMAND_ABORTED:
2067 case COMP_COMMAND_RING_STOPPED:
2068 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2071 case COMP_PARAMETER_ERROR:
2072 dev_warn(&udev->dev,
2073 "WARN: xHCI driver setup invalid evaluate context command.\n");
2076 case COMP_SLOT_NOT_ENABLED_ERROR:
2077 dev_warn(&udev->dev,
2078 "WARN: slot not enabled for evaluate context command.\n");
2081 case COMP_CONTEXT_STATE_ERROR:
2082 dev_warn(&udev->dev,
2083 "WARN: invalid context state for evaluate context command.\n");
2086 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2087 dev_warn(&udev->dev,
2088 "ERROR: Incompatible device for evaluate context command.\n");
2091 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2092 /* Max Exit Latency too large error */
2093 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2097 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2098 "Successful evaluate context command");
2102 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2110 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2111 struct xhci_input_control_ctx *ctrl_ctx)
2113 u32 valid_add_flags;
2114 u32 valid_drop_flags;
2116 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2117 * (bit 1). The default control endpoint is added during the Address
2118 * Device command and is never removed until the slot is disabled.
2120 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2121 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2123 /* Use hweight32 to count the number of ones in the add flags, or
2124 * number of endpoints added. Don't count endpoints that are changed
2125 * (both added and dropped).
2127 return hweight32(valid_add_flags) -
2128 hweight32(valid_add_flags & valid_drop_flags);
2131 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2132 struct xhci_input_control_ctx *ctrl_ctx)
2134 u32 valid_add_flags;
2135 u32 valid_drop_flags;
2137 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2138 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2140 return hweight32(valid_drop_flags) -
2141 hweight32(valid_add_flags & valid_drop_flags);
2145 * We need to reserve the new number of endpoints before the configure endpoint
2146 * command completes. We can't subtract the dropped endpoints from the number
2147 * of active endpoints until the command completes because we can oversubscribe
2148 * the host in this case:
2150 * - the first configure endpoint command drops more endpoints than it adds
2151 * - a second configure endpoint command that adds more endpoints is queued
2152 * - the first configure endpoint command fails, so the config is unchanged
2153 * - the second command may succeed, even though there isn't enough resources
2155 * Must be called with xhci->lock held.
2157 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2158 struct xhci_input_control_ctx *ctrl_ctx)
2162 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2163 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2164 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2165 "Not enough ep ctxs: "
2166 "%u active, need to add %u, limit is %u.",
2167 xhci->num_active_eps, added_eps,
2168 xhci->limit_active_eps);
2171 xhci->num_active_eps += added_eps;
2172 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2173 "Adding %u ep ctxs, %u now active.", added_eps,
2174 xhci->num_active_eps);
2179 * The configure endpoint was failed by the xHC for some other reason, so we
2180 * need to revert the resources that failed configuration would have used.
2182 * Must be called with xhci->lock held.
2184 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2185 struct xhci_input_control_ctx *ctrl_ctx)
2189 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2190 xhci->num_active_eps -= num_failed_eps;
2191 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2192 "Removing %u failed ep ctxs, %u now active.",
2194 xhci->num_active_eps);
2198 * Now that the command has completed, clean up the active endpoint count by
2199 * subtracting out the endpoints that were dropped (but not changed).
2201 * Must be called with xhci->lock held.
2203 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2204 struct xhci_input_control_ctx *ctrl_ctx)
2206 u32 num_dropped_eps;
2208 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2209 xhci->num_active_eps -= num_dropped_eps;
2210 if (num_dropped_eps)
2211 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2212 "Removing %u dropped ep ctxs, %u now active.",
2214 xhci->num_active_eps);
2217 static unsigned int xhci_get_block_size(struct usb_device *udev)
2219 switch (udev->speed) {
2221 case USB_SPEED_FULL:
2223 case USB_SPEED_HIGH:
2225 case USB_SPEED_SUPER:
2226 case USB_SPEED_SUPER_PLUS:
2228 case USB_SPEED_UNKNOWN:
2230 /* Should never happen */
2236 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2238 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2240 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2245 /* If we are changing a LS/FS device under a HS hub,
2246 * make sure (if we are activating a new TT) that the HS bus has enough
2247 * bandwidth for this new TT.
2249 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2250 struct xhci_virt_device *virt_dev,
2253 struct xhci_interval_bw_table *bw_table;
2254 struct xhci_tt_bw_info *tt_info;
2256 /* Find the bandwidth table for the root port this TT is attached to. */
2257 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2258 tt_info = virt_dev->tt_info;
2259 /* If this TT already had active endpoints, the bandwidth for this TT
2260 * has already been added. Removing all periodic endpoints (and thus
2261 * making the TT enactive) will only decrease the bandwidth used.
2265 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2266 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2270 /* Not sure why we would have no new active endpoints...
2272 * Maybe because of an Evaluate Context change for a hub update or a
2273 * control endpoint 0 max packet size change?
2274 * FIXME: skip the bandwidth calculation in that case.
2279 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2280 struct xhci_virt_device *virt_dev)
2282 unsigned int bw_reserved;
2284 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2285 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2288 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2289 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2296 * This algorithm is a very conservative estimate of the worst-case scheduling
2297 * scenario for any one interval. The hardware dynamically schedules the
2298 * packets, so we can't tell which microframe could be the limiting factor in
2299 * the bandwidth scheduling. This only takes into account periodic endpoints.
2301 * Obviously, we can't solve an NP complete problem to find the minimum worst
2302 * case scenario. Instead, we come up with an estimate that is no less than
2303 * the worst case bandwidth used for any one microframe, but may be an
2306 * We walk the requirements for each endpoint by interval, starting with the
2307 * smallest interval, and place packets in the schedule where there is only one
2308 * possible way to schedule packets for that interval. In order to simplify
2309 * this algorithm, we record the largest max packet size for each interval, and
2310 * assume all packets will be that size.
2312 * For interval 0, we obviously must schedule all packets for each interval.
2313 * The bandwidth for interval 0 is just the amount of data to be transmitted
2314 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2315 * the number of packets).
2317 * For interval 1, we have two possible microframes to schedule those packets
2318 * in. For this algorithm, if we can schedule the same number of packets for
2319 * each possible scheduling opportunity (each microframe), we will do so. The
2320 * remaining number of packets will be saved to be transmitted in the gaps in
2321 * the next interval's scheduling sequence.
2323 * As we move those remaining packets to be scheduled with interval 2 packets,
2324 * we have to double the number of remaining packets to transmit. This is
2325 * because the intervals are actually powers of 2, and we would be transmitting
2326 * the previous interval's packets twice in this interval. We also have to be
2327 * sure that when we look at the largest max packet size for this interval, we
2328 * also look at the largest max packet size for the remaining packets and take
2329 * the greater of the two.
2331 * The algorithm continues to evenly distribute packets in each scheduling
2332 * opportunity, and push the remaining packets out, until we get to the last
2333 * interval. Then those packets and their associated overhead are just added
2334 * to the bandwidth used.
2336 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2337 struct xhci_virt_device *virt_dev,
2340 unsigned int bw_reserved;
2341 unsigned int max_bandwidth;
2342 unsigned int bw_used;
2343 unsigned int block_size;
2344 struct xhci_interval_bw_table *bw_table;
2345 unsigned int packet_size = 0;
2346 unsigned int overhead = 0;
2347 unsigned int packets_transmitted = 0;
2348 unsigned int packets_remaining = 0;
2351 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2352 return xhci_check_ss_bw(xhci, virt_dev);
2354 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2355 max_bandwidth = HS_BW_LIMIT;
2356 /* Convert percent of bus BW reserved to blocks reserved */
2357 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2359 max_bandwidth = FS_BW_LIMIT;
2360 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2363 bw_table = virt_dev->bw_table;
2364 /* We need to translate the max packet size and max ESIT payloads into
2365 * the units the hardware uses.
2367 block_size = xhci_get_block_size(virt_dev->udev);
2369 /* If we are manipulating a LS/FS device under a HS hub, double check
2370 * that the HS bus has enough bandwidth if we are activing a new TT.
2372 if (virt_dev->tt_info) {
2373 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2374 "Recalculating BW for rootport %u",
2375 virt_dev->real_port);
2376 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2377 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2378 "newly activated TT.\n");
2381 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2382 "Recalculating BW for TT slot %u port %u",
2383 virt_dev->tt_info->slot_id,
2384 virt_dev->tt_info->ttport);
2386 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2387 "Recalculating BW for rootport %u",
2388 virt_dev->real_port);
2391 /* Add in how much bandwidth will be used for interval zero, or the
2392 * rounded max ESIT payload + number of packets * largest overhead.
2394 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2395 bw_table->interval_bw[0].num_packets *
2396 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2398 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2399 unsigned int bw_added;
2400 unsigned int largest_mps;
2401 unsigned int interval_overhead;
2404 * How many packets could we transmit in this interval?
2405 * If packets didn't fit in the previous interval, we will need
2406 * to transmit that many packets twice within this interval.
2408 packets_remaining = 2 * packets_remaining +
2409 bw_table->interval_bw[i].num_packets;
2411 /* Find the largest max packet size of this or the previous
2414 if (list_empty(&bw_table->interval_bw[i].endpoints))
2417 struct xhci_virt_ep *virt_ep;
2418 struct list_head *ep_entry;
2420 ep_entry = bw_table->interval_bw[i].endpoints.next;
2421 virt_ep = list_entry(ep_entry,
2422 struct xhci_virt_ep, bw_endpoint_list);
2423 /* Convert to blocks, rounding up */
2424 largest_mps = DIV_ROUND_UP(
2425 virt_ep->bw_info.max_packet_size,
2428 if (largest_mps > packet_size)
2429 packet_size = largest_mps;
2431 /* Use the larger overhead of this or the previous interval. */
2432 interval_overhead = xhci_get_largest_overhead(
2433 &bw_table->interval_bw[i]);
2434 if (interval_overhead > overhead)
2435 overhead = interval_overhead;
2437 /* How many packets can we evenly distribute across
2438 * (1 << (i + 1)) possible scheduling opportunities?
2440 packets_transmitted = packets_remaining >> (i + 1);
2442 /* Add in the bandwidth used for those scheduled packets */
2443 bw_added = packets_transmitted * (overhead + packet_size);
2445 /* How many packets do we have remaining to transmit? */
2446 packets_remaining = packets_remaining % (1 << (i + 1));
2448 /* What largest max packet size should those packets have? */
2449 /* If we've transmitted all packets, don't carry over the
2450 * largest packet size.
2452 if (packets_remaining == 0) {
2455 } else if (packets_transmitted > 0) {
2456 /* Otherwise if we do have remaining packets, and we've
2457 * scheduled some packets in this interval, take the
2458 * largest max packet size from endpoints with this
2461 packet_size = largest_mps;
2462 overhead = interval_overhead;
2464 /* Otherwise carry over packet_size and overhead from the last
2465 * time we had a remainder.
2467 bw_used += bw_added;
2468 if (bw_used > max_bandwidth) {
2469 xhci_warn(xhci, "Not enough bandwidth. "
2470 "Proposed: %u, Max: %u\n",
2471 bw_used, max_bandwidth);
2476 * Ok, we know we have some packets left over after even-handedly
2477 * scheduling interval 15. We don't know which microframes they will
2478 * fit into, so we over-schedule and say they will be scheduled every
2481 if (packets_remaining > 0)
2482 bw_used += overhead + packet_size;
2484 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2485 unsigned int port_index = virt_dev->real_port - 1;
2487 /* OK, we're manipulating a HS device attached to a
2488 * root port bandwidth domain. Include the number of active TTs
2489 * in the bandwidth used.
2491 bw_used += TT_HS_OVERHEAD *
2492 xhci->rh_bw[port_index].num_active_tts;
2495 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2496 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2497 "Available: %u " "percent",
2498 bw_used, max_bandwidth, bw_reserved,
2499 (max_bandwidth - bw_used - bw_reserved) * 100 /
2502 bw_used += bw_reserved;
2503 if (bw_used > max_bandwidth) {
2504 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2505 bw_used, max_bandwidth);
2509 bw_table->bw_used = bw_used;
2513 static bool xhci_is_async_ep(unsigned int ep_type)
2515 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2516 ep_type != ISOC_IN_EP &&
2517 ep_type != INT_IN_EP);
2520 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2522 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2525 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2527 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2529 if (ep_bw->ep_interval == 0)
2530 return SS_OVERHEAD_BURST +
2531 (ep_bw->mult * ep_bw->num_packets *
2532 (SS_OVERHEAD + mps));
2533 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2534 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2535 1 << ep_bw->ep_interval);
2539 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2540 struct xhci_bw_info *ep_bw,
2541 struct xhci_interval_bw_table *bw_table,
2542 struct usb_device *udev,
2543 struct xhci_virt_ep *virt_ep,
2544 struct xhci_tt_bw_info *tt_info)
2546 struct xhci_interval_bw *interval_bw;
2547 int normalized_interval;
2549 if (xhci_is_async_ep(ep_bw->type))
2552 if (udev->speed >= USB_SPEED_SUPER) {
2553 if (xhci_is_sync_in_ep(ep_bw->type))
2554 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2555 xhci_get_ss_bw_consumed(ep_bw);
2557 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2558 xhci_get_ss_bw_consumed(ep_bw);
2562 /* SuperSpeed endpoints never get added to intervals in the table, so
2563 * this check is only valid for HS/FS/LS devices.
2565 if (list_empty(&virt_ep->bw_endpoint_list))
2567 /* For LS/FS devices, we need to translate the interval expressed in
2568 * microframes to frames.
2570 if (udev->speed == USB_SPEED_HIGH)
2571 normalized_interval = ep_bw->ep_interval;
2573 normalized_interval = ep_bw->ep_interval - 3;
2575 if (normalized_interval == 0)
2576 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2577 interval_bw = &bw_table->interval_bw[normalized_interval];
2578 interval_bw->num_packets -= ep_bw->num_packets;
2579 switch (udev->speed) {
2581 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2583 case USB_SPEED_FULL:
2584 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2586 case USB_SPEED_HIGH:
2587 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2590 /* Should never happen because only LS/FS/HS endpoints will get
2591 * added to the endpoint list.
2596 tt_info->active_eps -= 1;
2597 list_del_init(&virt_ep->bw_endpoint_list);
2600 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2601 struct xhci_bw_info *ep_bw,
2602 struct xhci_interval_bw_table *bw_table,
2603 struct usb_device *udev,
2604 struct xhci_virt_ep *virt_ep,
2605 struct xhci_tt_bw_info *tt_info)
2607 struct xhci_interval_bw *interval_bw;
2608 struct xhci_virt_ep *smaller_ep;
2609 int normalized_interval;
2611 if (xhci_is_async_ep(ep_bw->type))
2614 if (udev->speed == USB_SPEED_SUPER) {
2615 if (xhci_is_sync_in_ep(ep_bw->type))
2616 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2617 xhci_get_ss_bw_consumed(ep_bw);
2619 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2620 xhci_get_ss_bw_consumed(ep_bw);
2624 /* For LS/FS devices, we need to translate the interval expressed in
2625 * microframes to frames.
2627 if (udev->speed == USB_SPEED_HIGH)
2628 normalized_interval = ep_bw->ep_interval;
2630 normalized_interval = ep_bw->ep_interval - 3;
2632 if (normalized_interval == 0)
2633 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2634 interval_bw = &bw_table->interval_bw[normalized_interval];
2635 interval_bw->num_packets += ep_bw->num_packets;
2636 switch (udev->speed) {
2638 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2640 case USB_SPEED_FULL:
2641 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2643 case USB_SPEED_HIGH:
2644 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2647 /* Should never happen because only LS/FS/HS endpoints will get
2648 * added to the endpoint list.
2654 tt_info->active_eps += 1;
2655 /* Insert the endpoint into the list, largest max packet size first. */
2656 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2658 if (ep_bw->max_packet_size >=
2659 smaller_ep->bw_info.max_packet_size) {
2660 /* Add the new ep before the smaller endpoint */
2661 list_add_tail(&virt_ep->bw_endpoint_list,
2662 &smaller_ep->bw_endpoint_list);
2666 /* Add the new endpoint at the end of the list. */
2667 list_add_tail(&virt_ep->bw_endpoint_list,
2668 &interval_bw->endpoints);
2671 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2672 struct xhci_virt_device *virt_dev,
2675 struct xhci_root_port_bw_info *rh_bw_info;
2676 if (!virt_dev->tt_info)
2679 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2680 if (old_active_eps == 0 &&
2681 virt_dev->tt_info->active_eps != 0) {
2682 rh_bw_info->num_active_tts += 1;
2683 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2684 } else if (old_active_eps != 0 &&
2685 virt_dev->tt_info->active_eps == 0) {
2686 rh_bw_info->num_active_tts -= 1;
2687 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2691 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2692 struct xhci_virt_device *virt_dev,
2693 struct xhci_container_ctx *in_ctx)
2695 struct xhci_bw_info ep_bw_info[31];
2697 struct xhci_input_control_ctx *ctrl_ctx;
2698 int old_active_eps = 0;
2700 if (virt_dev->tt_info)
2701 old_active_eps = virt_dev->tt_info->active_eps;
2703 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2705 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2710 for (i = 0; i < 31; i++) {
2711 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2714 /* Make a copy of the BW info in case we need to revert this */
2715 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2716 sizeof(ep_bw_info[i]));
2717 /* Drop the endpoint from the interval table if the endpoint is
2718 * being dropped or changed.
2720 if (EP_IS_DROPPED(ctrl_ctx, i))
2721 xhci_drop_ep_from_interval_table(xhci,
2722 &virt_dev->eps[i].bw_info,
2728 /* Overwrite the information stored in the endpoints' bw_info */
2729 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2730 for (i = 0; i < 31; i++) {
2731 /* Add any changed or added endpoints to the interval table */
2732 if (EP_IS_ADDED(ctrl_ctx, i))
2733 xhci_add_ep_to_interval_table(xhci,
2734 &virt_dev->eps[i].bw_info,
2741 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2742 /* Ok, this fits in the bandwidth we have.
2743 * Update the number of active TTs.
2745 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2749 /* We don't have enough bandwidth for this, revert the stored info. */
2750 for (i = 0; i < 31; i++) {
2751 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2754 /* Drop the new copies of any added or changed endpoints from
2755 * the interval table.
2757 if (EP_IS_ADDED(ctrl_ctx, i)) {
2758 xhci_drop_ep_from_interval_table(xhci,
2759 &virt_dev->eps[i].bw_info,
2765 /* Revert the endpoint back to its old information */
2766 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2767 sizeof(ep_bw_info[i]));
2768 /* Add any changed or dropped endpoints back into the table */
2769 if (EP_IS_DROPPED(ctrl_ctx, i))
2770 xhci_add_ep_to_interval_table(xhci,
2771 &virt_dev->eps[i].bw_info,
2781 /* Issue a configure endpoint command or evaluate context command
2782 * and wait for it to finish.
2784 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2785 struct usb_device *udev,
2786 struct xhci_command *command,
2787 bool ctx_change, bool must_succeed)
2790 unsigned long flags;
2791 struct xhci_input_control_ctx *ctrl_ctx;
2792 struct xhci_virt_device *virt_dev;
2793 struct xhci_slot_ctx *slot_ctx;
2798 spin_lock_irqsave(&xhci->lock, flags);
2800 if (xhci->xhc_state & XHCI_STATE_DYING) {
2801 spin_unlock_irqrestore(&xhci->lock, flags);
2805 virt_dev = xhci->devs[udev->slot_id];
2807 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2809 spin_unlock_irqrestore(&xhci->lock, flags);
2810 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2815 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2816 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2817 spin_unlock_irqrestore(&xhci->lock, flags);
2818 xhci_warn(xhci, "Not enough host resources, "
2819 "active endpoint contexts = %u\n",
2820 xhci->num_active_eps);
2823 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2824 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2825 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2826 xhci_free_host_resources(xhci, ctrl_ctx);
2827 spin_unlock_irqrestore(&xhci->lock, flags);
2828 xhci_warn(xhci, "Not enough bandwidth\n");
2832 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2834 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2835 trace_xhci_configure_endpoint(slot_ctx);
2838 ret = xhci_queue_configure_endpoint(xhci, command,
2839 command->in_ctx->dma,
2840 udev->slot_id, must_succeed);
2842 ret = xhci_queue_evaluate_context(xhci, command,
2843 command->in_ctx->dma,
2844 udev->slot_id, must_succeed);
2846 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2847 xhci_free_host_resources(xhci, ctrl_ctx);
2848 spin_unlock_irqrestore(&xhci->lock, flags);
2849 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2850 "FIXME allocate a new ring segment");
2853 xhci_ring_cmd_db(xhci);
2854 spin_unlock_irqrestore(&xhci->lock, flags);
2856 /* Wait for the configure endpoint command to complete */
2857 wait_for_completion(command->completion);
2860 ret = xhci_configure_endpoint_result(xhci, udev,
2863 ret = xhci_evaluate_context_result(xhci, udev,
2866 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2867 spin_lock_irqsave(&xhci->lock, flags);
2868 /* If the command failed, remove the reserved resources.
2869 * Otherwise, clean up the estimate to include dropped eps.
2872 xhci_free_host_resources(xhci, ctrl_ctx);
2874 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2875 spin_unlock_irqrestore(&xhci->lock, flags);
2880 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2881 struct xhci_virt_device *vdev, int i)
2883 struct xhci_virt_ep *ep = &vdev->eps[i];
2885 if (ep->ep_state & EP_HAS_STREAMS) {
2886 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2887 xhci_get_endpoint_address(i));
2888 xhci_free_stream_info(xhci, ep->stream_info);
2889 ep->stream_info = NULL;
2890 ep->ep_state &= ~EP_HAS_STREAMS;
2894 /* Called after one or more calls to xhci_add_endpoint() or
2895 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2896 * to call xhci_reset_bandwidth().
2898 * Since we are in the middle of changing either configuration or
2899 * installing a new alt setting, the USB core won't allow URBs to be
2900 * enqueued for any endpoint on the old config or interface. Nothing
2901 * else should be touching the xhci->devs[slot_id] structure, so we
2902 * don't need to take the xhci->lock for manipulating that.
2904 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2908 struct xhci_hcd *xhci;
2909 struct xhci_virt_device *virt_dev;
2910 struct xhci_input_control_ctx *ctrl_ctx;
2911 struct xhci_slot_ctx *slot_ctx;
2912 struct xhci_command *command;
2914 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2917 xhci = hcd_to_xhci(hcd);
2918 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2919 (xhci->xhc_state & XHCI_STATE_REMOVING))
2922 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2923 virt_dev = xhci->devs[udev->slot_id];
2925 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2929 command->in_ctx = virt_dev->in_ctx;
2931 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2932 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2934 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2937 goto command_cleanup;
2939 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2940 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2941 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2943 /* Don't issue the command if there's no endpoints to update. */
2944 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2945 ctrl_ctx->drop_flags == 0) {
2947 goto command_cleanup;
2949 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2950 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2951 for (i = 31; i >= 1; i--) {
2952 __le32 le32 = cpu_to_le32(BIT(i));
2954 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2955 || (ctrl_ctx->add_flags & le32) || i == 1) {
2956 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2957 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2962 ret = xhci_configure_endpoint(xhci, udev, command,
2965 /* Callee should call reset_bandwidth() */
2966 goto command_cleanup;
2968 /* Free any rings that were dropped, but not changed. */
2969 for (i = 1; i < 31; i++) {
2970 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2971 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2972 xhci_free_endpoint_ring(xhci, virt_dev, i);
2973 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2976 xhci_zero_in_ctx(xhci, virt_dev);
2978 * Install any rings for completely new endpoints or changed endpoints,
2979 * and free any old rings from changed endpoints.
2981 for (i = 1; i < 31; i++) {
2982 if (!virt_dev->eps[i].new_ring)
2984 /* Only free the old ring if it exists.
2985 * It may not if this is the first add of an endpoint.
2987 if (virt_dev->eps[i].ring) {
2988 xhci_free_endpoint_ring(xhci, virt_dev, i);
2990 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2991 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2992 virt_dev->eps[i].new_ring = NULL;
2993 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
2996 kfree(command->completion);
3001 EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3003 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3005 struct xhci_hcd *xhci;
3006 struct xhci_virt_device *virt_dev;
3009 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3012 xhci = hcd_to_xhci(hcd);
3014 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3015 virt_dev = xhci->devs[udev->slot_id];
3016 /* Free any rings allocated for added endpoints */
3017 for (i = 0; i < 31; i++) {
3018 if (virt_dev->eps[i].new_ring) {
3019 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3020 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3021 virt_dev->eps[i].new_ring = NULL;
3024 xhci_zero_in_ctx(xhci, virt_dev);
3026 EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3028 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3029 struct xhci_container_ctx *in_ctx,
3030 struct xhci_container_ctx *out_ctx,
3031 struct xhci_input_control_ctx *ctrl_ctx,
3032 u32 add_flags, u32 drop_flags)
3034 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3035 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3036 xhci_slot_copy(xhci, in_ctx, out_ctx);
3037 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3040 static void xhci_endpoint_disable(struct usb_hcd *hcd,
3041 struct usb_host_endpoint *host_ep)
3043 struct xhci_hcd *xhci;
3044 struct xhci_virt_device *vdev;
3045 struct xhci_virt_ep *ep;
3046 struct usb_device *udev;
3047 unsigned long flags;
3048 unsigned int ep_index;
3050 xhci = hcd_to_xhci(hcd);
3052 spin_lock_irqsave(&xhci->lock, flags);
3054 udev = (struct usb_device *)host_ep->hcpriv;
3055 if (!udev || !udev->slot_id)
3058 vdev = xhci->devs[udev->slot_id];
3062 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3063 ep = &vdev->eps[ep_index];
3065 /* wait for hub_tt_work to finish clearing hub TT */
3066 if (ep->ep_state & EP_CLEARING_TT) {
3067 spin_unlock_irqrestore(&xhci->lock, flags);
3068 schedule_timeout_uninterruptible(1);
3073 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3076 host_ep->hcpriv = NULL;
3077 spin_unlock_irqrestore(&xhci->lock, flags);
3081 * Called after usb core issues a clear halt control message.
3082 * The host side of the halt should already be cleared by a reset endpoint
3083 * command issued when the STALL event was received.
3085 * The reset endpoint command may only be issued to endpoints in the halted
3086 * state. For software that wishes to reset the data toggle or sequence number
3087 * of an endpoint that isn't in the halted state this function will issue a
3088 * configure endpoint command with the Drop and Add bits set for the target
3089 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3092 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3093 struct usb_host_endpoint *host_ep)
3095 struct xhci_hcd *xhci;
3096 struct usb_device *udev;
3097 struct xhci_virt_device *vdev;
3098 struct xhci_virt_ep *ep;
3099 struct xhci_input_control_ctx *ctrl_ctx;
3100 struct xhci_command *stop_cmd, *cfg_cmd;
3101 unsigned int ep_index;
3102 unsigned long flags;
3106 xhci = hcd_to_xhci(hcd);
3107 if (!host_ep->hcpriv)
3109 udev = (struct usb_device *) host_ep->hcpriv;
3110 vdev = xhci->devs[udev->slot_id];
3113 * vdev may be lost due to xHC restore error and re-initialization
3114 * during S3/S4 resume. A new vdev will be allocated later by
3115 * xhci_discover_or_reset_device()
3117 if (!udev->slot_id || !vdev)
3119 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3120 ep = &vdev->eps[ep_index];
3122 /* Bail out if toggle is already being cleared by a endpoint reset */
3123 spin_lock_irqsave(&xhci->lock, flags);
3124 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3125 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3126 spin_unlock_irqrestore(&xhci->lock, flags);
3129 spin_unlock_irqrestore(&xhci->lock, flags);
3130 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3131 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3132 usb_endpoint_xfer_isoc(&host_ep->desc))
3135 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3137 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3140 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3144 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3148 spin_lock_irqsave(&xhci->lock, flags);
3150 /* block queuing new trbs and ringing ep doorbell */
3151 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3154 * Make sure endpoint ring is empty before resetting the toggle/seq.
3155 * Driver is required to synchronously cancel all transfer request.
3156 * Stop the endpoint to force xHC to update the output context
3159 if (!list_empty(&ep->ring->td_list)) {
3160 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3161 spin_unlock_irqrestore(&xhci->lock, flags);
3162 xhci_free_command(xhci, cfg_cmd);
3166 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3169 spin_unlock_irqrestore(&xhci->lock, flags);
3170 xhci_free_command(xhci, cfg_cmd);
3171 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3176 xhci_ring_cmd_db(xhci);
3177 spin_unlock_irqrestore(&xhci->lock, flags);
3179 wait_for_completion(stop_cmd->completion);
3181 spin_lock_irqsave(&xhci->lock, flags);
3183 /* config ep command clears toggle if add and drop ep flags are set */
3184 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3186 spin_unlock_irqrestore(&xhci->lock, flags);
3187 xhci_free_command(xhci, cfg_cmd);
3188 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3193 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3194 ctrl_ctx, ep_flag, ep_flag);
3195 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3197 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3198 udev->slot_id, false);
3200 spin_unlock_irqrestore(&xhci->lock, flags);
3201 xhci_free_command(xhci, cfg_cmd);
3202 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3207 xhci_ring_cmd_db(xhci);
3208 spin_unlock_irqrestore(&xhci->lock, flags);
3210 wait_for_completion(cfg_cmd->completion);
3212 xhci_free_command(xhci, cfg_cmd);
3214 xhci_free_command(xhci, stop_cmd);
3215 spin_lock_irqsave(&xhci->lock, flags);
3216 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3217 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3218 spin_unlock_irqrestore(&xhci->lock, flags);
3221 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3222 struct usb_device *udev, struct usb_host_endpoint *ep,
3223 unsigned int slot_id)
3226 unsigned int ep_index;
3227 unsigned int ep_state;
3231 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3233 return ret ? ret : -EINVAL;
3234 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3235 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3236 " descriptor for ep 0x%x does not support streams\n",
3237 ep->desc.bEndpointAddress);
3241 ep_index = xhci_get_endpoint_index(&ep->desc);
3242 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3243 if (ep_state & EP_HAS_STREAMS ||
3244 ep_state & EP_GETTING_STREAMS) {
3245 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3246 "already has streams set up.\n",
3247 ep->desc.bEndpointAddress);
3248 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3249 "dynamic stream context array reallocation.\n");
3252 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3253 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3254 "endpoint 0x%x; URBs are pending.\n",
3255 ep->desc.bEndpointAddress);
3261 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3262 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3264 unsigned int max_streams;
3266 /* The stream context array size must be a power of two */
3267 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3269 * Find out how many primary stream array entries the host controller
3270 * supports. Later we may use secondary stream arrays (similar to 2nd
3271 * level page entries), but that's an optional feature for xHCI host
3272 * controllers. xHCs must support at least 4 stream IDs.
3274 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3275 if (*num_stream_ctxs > max_streams) {
3276 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3278 *num_stream_ctxs = max_streams;
3279 *num_streams = max_streams;
3283 /* Returns an error code if one of the endpoint already has streams.
3284 * This does not change any data structures, it only checks and gathers
3287 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3288 struct usb_device *udev,
3289 struct usb_host_endpoint **eps, unsigned int num_eps,
3290 unsigned int *num_streams, u32 *changed_ep_bitmask)
3292 unsigned int max_streams;
3293 unsigned int endpoint_flag;
3297 for (i = 0; i < num_eps; i++) {
3298 ret = xhci_check_streams_endpoint(xhci, udev,
3299 eps[i], udev->slot_id);
3303 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3304 if (max_streams < (*num_streams - 1)) {
3305 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3306 eps[i]->desc.bEndpointAddress,
3308 *num_streams = max_streams+1;
3311 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3312 if (*changed_ep_bitmask & endpoint_flag)
3314 *changed_ep_bitmask |= endpoint_flag;
3319 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3320 struct usb_device *udev,
3321 struct usb_host_endpoint **eps, unsigned int num_eps)
3323 u32 changed_ep_bitmask = 0;
3324 unsigned int slot_id;
3325 unsigned int ep_index;
3326 unsigned int ep_state;
3329 slot_id = udev->slot_id;
3330 if (!xhci->devs[slot_id])
3333 for (i = 0; i < num_eps; i++) {
3334 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3335 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3336 /* Are streams already being freed for the endpoint? */
3337 if (ep_state & EP_GETTING_NO_STREAMS) {
3338 xhci_warn(xhci, "WARN Can't disable streams for "
3340 "streams are being disabled already\n",
3341 eps[i]->desc.bEndpointAddress);
3344 /* Are there actually any streams to free? */
3345 if (!(ep_state & EP_HAS_STREAMS) &&
3346 !(ep_state & EP_GETTING_STREAMS)) {
3347 xhci_warn(xhci, "WARN Can't disable streams for "
3349 "streams are already disabled!\n",
3350 eps[i]->desc.bEndpointAddress);
3351 xhci_warn(xhci, "WARN xhci_free_streams() called "
3352 "with non-streams endpoint\n");
3355 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3357 return changed_ep_bitmask;
3361 * The USB device drivers use this function (through the HCD interface in USB
3362 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3363 * coordinate mass storage command queueing across multiple endpoints (basically
3364 * a stream ID == a task ID).
3366 * Setting up streams involves allocating the same size stream context array
3367 * for each endpoint and issuing a configure endpoint command for all endpoints.
3369 * Don't allow the call to succeed if one endpoint only supports one stream
3370 * (which means it doesn't support streams at all).
3372 * Drivers may get less stream IDs than they asked for, if the host controller
3373 * hardware or endpoints claim they can't support the number of requested
3376 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3377 struct usb_host_endpoint **eps, unsigned int num_eps,
3378 unsigned int num_streams, gfp_t mem_flags)
3381 struct xhci_hcd *xhci;
3382 struct xhci_virt_device *vdev;
3383 struct xhci_command *config_cmd;
3384 struct xhci_input_control_ctx *ctrl_ctx;
3385 unsigned int ep_index;
3386 unsigned int num_stream_ctxs;
3387 unsigned int max_packet;
3388 unsigned long flags;
3389 u32 changed_ep_bitmask = 0;
3394 /* Add one to the number of streams requested to account for
3395 * stream 0 that is reserved for xHCI usage.
3398 xhci = hcd_to_xhci(hcd);
3399 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3402 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3403 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3404 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3405 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3409 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3413 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3415 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3417 xhci_free_command(xhci, config_cmd);
3421 /* Check to make sure all endpoints are not already configured for
3422 * streams. While we're at it, find the maximum number of streams that
3423 * all the endpoints will support and check for duplicate endpoints.
3425 spin_lock_irqsave(&xhci->lock, flags);
3426 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3427 num_eps, &num_streams, &changed_ep_bitmask);
3429 xhci_free_command(xhci, config_cmd);
3430 spin_unlock_irqrestore(&xhci->lock, flags);
3433 if (num_streams <= 1) {
3434 xhci_warn(xhci, "WARN: endpoints can't handle "
3435 "more than one stream.\n");
3436 xhci_free_command(xhci, config_cmd);
3437 spin_unlock_irqrestore(&xhci->lock, flags);
3440 vdev = xhci->devs[udev->slot_id];
3441 /* Mark each endpoint as being in transition, so
3442 * xhci_urb_enqueue() will reject all URBs.
3444 for (i = 0; i < num_eps; i++) {
3445 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3446 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3448 spin_unlock_irqrestore(&xhci->lock, flags);
3450 /* Setup internal data structures and allocate HW data structures for
3451 * streams (but don't install the HW structures in the input context
3452 * until we're sure all memory allocation succeeded).
3454 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3455 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3456 num_stream_ctxs, num_streams);
3458 for (i = 0; i < num_eps; i++) {
3459 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3460 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3461 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3464 max_packet, mem_flags);
3465 if (!vdev->eps[ep_index].stream_info)
3467 /* Set maxPstreams in endpoint context and update deq ptr to
3468 * point to stream context array. FIXME
3472 /* Set up the input context for a configure endpoint command. */
3473 for (i = 0; i < num_eps; i++) {
3474 struct xhci_ep_ctx *ep_ctx;
3476 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3477 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3479 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3480 vdev->out_ctx, ep_index);
3481 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3482 vdev->eps[ep_index].stream_info);
3484 /* Tell the HW to drop its old copy of the endpoint context info
3485 * and add the updated copy from the input context.
3487 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3488 vdev->out_ctx, ctrl_ctx,
3489 changed_ep_bitmask, changed_ep_bitmask);
3491 /* Issue and wait for the configure endpoint command */
3492 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3495 /* xHC rejected the configure endpoint command for some reason, so we
3496 * leave the old ring intact and free our internal streams data
3502 spin_lock_irqsave(&xhci->lock, flags);
3503 for (i = 0; i < num_eps; i++) {
3504 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3505 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3506 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3507 udev->slot_id, ep_index);
3508 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3510 xhci_free_command(xhci, config_cmd);
3511 spin_unlock_irqrestore(&xhci->lock, flags);
3513 for (i = 0; i < num_eps; i++) {
3514 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3515 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3517 /* Subtract 1 for stream 0, which drivers can't use */
3518 return num_streams - 1;
3521 /* If it didn't work, free the streams! */
3522 for (i = 0; i < num_eps; i++) {
3523 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3524 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3525 vdev->eps[ep_index].stream_info = NULL;
3526 /* FIXME Unset maxPstreams in endpoint context and
3527 * update deq ptr to point to normal string ring.
3529 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3530 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3531 xhci_endpoint_zero(xhci, vdev, eps[i]);
3533 xhci_free_command(xhci, config_cmd);
3537 /* Transition the endpoint from using streams to being a "normal" endpoint
3540 * Modify the endpoint context state, submit a configure endpoint command,
3541 * and free all endpoint rings for streams if that completes successfully.
3543 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3544 struct usb_host_endpoint **eps, unsigned int num_eps,
3548 struct xhci_hcd *xhci;
3549 struct xhci_virt_device *vdev;
3550 struct xhci_command *command;
3551 struct xhci_input_control_ctx *ctrl_ctx;
3552 unsigned int ep_index;
3553 unsigned long flags;
3554 u32 changed_ep_bitmask;
3556 xhci = hcd_to_xhci(hcd);
3557 vdev = xhci->devs[udev->slot_id];
3559 /* Set up a configure endpoint command to remove the streams rings */
3560 spin_lock_irqsave(&xhci->lock, flags);
3561 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3562 udev, eps, num_eps);
3563 if (changed_ep_bitmask == 0) {
3564 spin_unlock_irqrestore(&xhci->lock, flags);
3568 /* Use the xhci_command structure from the first endpoint. We may have
3569 * allocated too many, but the driver may call xhci_free_streams() for
3570 * each endpoint it grouped into one call to xhci_alloc_streams().
3572 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3573 command = vdev->eps[ep_index].stream_info->free_streams_command;
3574 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3576 spin_unlock_irqrestore(&xhci->lock, flags);
3577 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3582 for (i = 0; i < num_eps; i++) {
3583 struct xhci_ep_ctx *ep_ctx;
3585 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3586 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3587 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3588 EP_GETTING_NO_STREAMS;
3590 xhci_endpoint_copy(xhci, command->in_ctx,
3591 vdev->out_ctx, ep_index);
3592 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3593 &vdev->eps[ep_index]);
3595 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3596 vdev->out_ctx, ctrl_ctx,
3597 changed_ep_bitmask, changed_ep_bitmask);
3598 spin_unlock_irqrestore(&xhci->lock, flags);
3600 /* Issue and wait for the configure endpoint command,
3601 * which must succeed.
3603 ret = xhci_configure_endpoint(xhci, udev, command,
3606 /* xHC rejected the configure endpoint command for some reason, so we
3607 * leave the streams rings intact.
3612 spin_lock_irqsave(&xhci->lock, flags);
3613 for (i = 0; i < num_eps; i++) {
3614 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3615 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3616 vdev->eps[ep_index].stream_info = NULL;
3617 /* FIXME Unset maxPstreams in endpoint context and
3618 * update deq ptr to point to normal string ring.
3620 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3621 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3623 spin_unlock_irqrestore(&xhci->lock, flags);
3629 * Deletes endpoint resources for endpoints that were active before a Reset
3630 * Device command, or a Disable Slot command. The Reset Device command leaves
3631 * the control endpoint intact, whereas the Disable Slot command deletes it.
3633 * Must be called with xhci->lock held.
3635 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3636 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3639 unsigned int num_dropped_eps = 0;
3640 unsigned int drop_flags = 0;
3642 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3643 if (virt_dev->eps[i].ring) {
3644 drop_flags |= 1 << i;
3648 xhci->num_active_eps -= num_dropped_eps;
3649 if (num_dropped_eps)
3650 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3651 "Dropped %u ep ctxs, flags = 0x%x, "
3653 num_dropped_eps, drop_flags,
3654 xhci->num_active_eps);
3658 * This submits a Reset Device Command, which will set the device state to 0,
3659 * set the device address to 0, and disable all the endpoints except the default
3660 * control endpoint. The USB core should come back and call
3661 * xhci_address_device(), and then re-set up the configuration. If this is
3662 * called because of a usb_reset_and_verify_device(), then the old alternate
3663 * settings will be re-installed through the normal bandwidth allocation
3666 * Wait for the Reset Device command to finish. Remove all structures
3667 * associated with the endpoints that were disabled. Clear the input device
3668 * structure? Reset the control endpoint 0 max packet size?
3670 * If the virt_dev to be reset does not exist or does not match the udev,
3671 * it means the device is lost, possibly due to the xHC restore error and
3672 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3673 * re-allocate the device.
3675 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3676 struct usb_device *udev)
3679 unsigned long flags;
3680 struct xhci_hcd *xhci;
3681 unsigned int slot_id;
3682 struct xhci_virt_device *virt_dev;
3683 struct xhci_command *reset_device_cmd;
3684 struct xhci_slot_ctx *slot_ctx;
3685 int old_active_eps = 0;
3687 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3690 xhci = hcd_to_xhci(hcd);
3691 slot_id = udev->slot_id;
3692 virt_dev = xhci->devs[slot_id];
3694 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3695 "not exist. Re-allocate the device\n", slot_id);
3696 ret = xhci_alloc_dev(hcd, udev);
3703 if (virt_dev->tt_info)
3704 old_active_eps = virt_dev->tt_info->active_eps;
3706 if (virt_dev->udev != udev) {
3707 /* If the virt_dev and the udev does not match, this virt_dev
3708 * may belong to another udev.
3709 * Re-allocate the device.
3711 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3712 "not match the udev. Re-allocate the device\n",
3714 ret = xhci_alloc_dev(hcd, udev);
3721 /* If device is not setup, there is no point in resetting it */
3722 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3723 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3724 SLOT_STATE_DISABLED)
3727 trace_xhci_discover_or_reset_device(slot_ctx);
3729 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3730 /* Allocate the command structure that holds the struct completion.
3731 * Assume we're in process context, since the normal device reset
3732 * process has to wait for the device anyway. Storage devices are
3733 * reset as part of error handling, so use GFP_NOIO instead of
3736 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3737 if (!reset_device_cmd) {
3738 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3742 /* Attempt to submit the Reset Device command to the command ring */
3743 spin_lock_irqsave(&xhci->lock, flags);
3745 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3747 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3748 spin_unlock_irqrestore(&xhci->lock, flags);
3749 goto command_cleanup;
3751 xhci_ring_cmd_db(xhci);
3752 spin_unlock_irqrestore(&xhci->lock, flags);
3754 /* Wait for the Reset Device command to finish */
3755 wait_for_completion(reset_device_cmd->completion);
3757 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3758 * unless we tried to reset a slot ID that wasn't enabled,
3759 * or the device wasn't in the addressed or configured state.
3761 ret = reset_device_cmd->status;
3763 case COMP_COMMAND_ABORTED:
3764 case COMP_COMMAND_RING_STOPPED:
3765 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3767 goto command_cleanup;
3768 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3769 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3770 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3772 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3773 xhci_dbg(xhci, "Not freeing device rings.\n");
3774 /* Don't treat this as an error. May change my mind later. */
3776 goto command_cleanup;
3778 xhci_dbg(xhci, "Successful reset device command.\n");
3781 if (xhci_is_vendor_info_code(xhci, ret))
3783 xhci_warn(xhci, "Unknown completion code %u for "
3784 "reset device command.\n", ret);
3786 goto command_cleanup;
3789 /* Free up host controller endpoint resources */
3790 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3791 spin_lock_irqsave(&xhci->lock, flags);
3792 /* Don't delete the default control endpoint resources */
3793 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3794 spin_unlock_irqrestore(&xhci->lock, flags);
3797 /* Everything but endpoint 0 is disabled, so free the rings. */
3798 for (i = 1; i < 31; i++) {
3799 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3801 if (ep->ep_state & EP_HAS_STREAMS) {
3802 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3803 xhci_get_endpoint_address(i));
3804 xhci_free_stream_info(xhci, ep->stream_info);
3805 ep->stream_info = NULL;
3806 ep->ep_state &= ~EP_HAS_STREAMS;
3810 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3811 xhci_free_endpoint_ring(xhci, virt_dev, i);
3813 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3814 xhci_drop_ep_from_interval_table(xhci,
3815 &virt_dev->eps[i].bw_info,
3820 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3822 /* If necessary, update the number of active TTs on this root port */
3823 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3824 virt_dev->flags = 0;
3828 xhci_free_command(xhci, reset_device_cmd);
3833 * At this point, the struct usb_device is about to go away, the device has
3834 * disconnected, and all traffic has been stopped and the endpoints have been
3835 * disabled. Free any HC data structures associated with that device.
3837 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3839 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3840 struct xhci_virt_device *virt_dev;
3841 struct xhci_slot_ctx *slot_ctx;
3842 unsigned long flags;
3846 * We called pm_runtime_get_noresume when the device was attached.
3847 * Decrement the counter here to allow controller to runtime suspend
3848 * if no devices remain.
3850 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3851 pm_runtime_put_noidle(hcd->self.controller);
3853 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3854 /* If the host is halted due to driver unload, we still need to free the
3857 if (ret <= 0 && ret != -ENODEV)
3860 virt_dev = xhci->devs[udev->slot_id];
3861 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3862 trace_xhci_free_dev(slot_ctx);
3864 /* Stop any wayward timer functions (which may grab the lock) */
3865 for (i = 0; i < 31; i++)
3866 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3867 virt_dev->udev = NULL;
3868 xhci_disable_slot(xhci, udev->slot_id);
3870 spin_lock_irqsave(&xhci->lock, flags);
3871 xhci_free_virt_device(xhci, udev->slot_id);
3872 spin_unlock_irqrestore(&xhci->lock, flags);
3876 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3878 struct xhci_command *command;
3879 unsigned long flags;
3883 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3887 xhci_debugfs_remove_slot(xhci, slot_id);
3889 spin_lock_irqsave(&xhci->lock, flags);
3890 /* Don't disable the slot if the host controller is dead. */
3891 state = readl(&xhci->op_regs->status);
3892 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3893 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3894 spin_unlock_irqrestore(&xhci->lock, flags);
3899 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3902 spin_unlock_irqrestore(&xhci->lock, flags);
3906 xhci_ring_cmd_db(xhci);
3907 spin_unlock_irqrestore(&xhci->lock, flags);
3909 wait_for_completion(command->completion);
3911 if (command->status != COMP_SUCCESS)
3912 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
3913 slot_id, command->status);
3915 xhci_free_command(xhci, command);
3921 * Checks if we have enough host controller resources for the default control
3924 * Must be called with xhci->lock held.
3926 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3928 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3929 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3930 "Not enough ep ctxs: "
3931 "%u active, need to add 1, limit is %u.",
3932 xhci->num_active_eps, xhci->limit_active_eps);
3935 xhci->num_active_eps += 1;
3936 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3937 "Adding 1 ep ctx, %u now active.",
3938 xhci->num_active_eps);
3944 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3945 * timed out, or allocating memory failed. Returns 1 on success.
3947 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3949 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3950 struct xhci_virt_device *vdev;
3951 struct xhci_slot_ctx *slot_ctx;
3952 unsigned long flags;
3954 struct xhci_command *command;
3956 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3960 spin_lock_irqsave(&xhci->lock, flags);
3961 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3963 spin_unlock_irqrestore(&xhci->lock, flags);
3964 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3965 xhci_free_command(xhci, command);
3968 xhci_ring_cmd_db(xhci);
3969 spin_unlock_irqrestore(&xhci->lock, flags);
3971 wait_for_completion(command->completion);
3972 slot_id = command->slot_id;
3974 if (!slot_id || command->status != COMP_SUCCESS) {
3975 xhci_err(xhci, "Error while assigning device slot ID: %s\n",
3976 xhci_trb_comp_code_string(command->status));
3977 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3979 readl(&xhci->cap_regs->hcs_params1)));
3980 xhci_free_command(xhci, command);
3984 xhci_free_command(xhci, command);
3986 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3987 spin_lock_irqsave(&xhci->lock, flags);
3988 ret = xhci_reserve_host_control_ep_resources(xhci);
3990 spin_unlock_irqrestore(&xhci->lock, flags);
3991 xhci_warn(xhci, "Not enough host resources, "
3992 "active endpoint contexts = %u\n",
3993 xhci->num_active_eps);
3996 spin_unlock_irqrestore(&xhci->lock, flags);
3998 /* Use GFP_NOIO, since this function can be called from
3999 * xhci_discover_or_reset_device(), which may be called as part of
4000 * mass storage driver error handling.
4002 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4003 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4006 vdev = xhci->devs[slot_id];
4007 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4008 trace_xhci_alloc_dev(slot_ctx);
4010 udev->slot_id = slot_id;
4012 xhci_debugfs_create_slot(xhci, slot_id);
4015 * If resetting upon resume, we can't put the controller into runtime
4016 * suspend if there is a device attached.
4018 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4019 pm_runtime_get_noresume(hcd->self.controller);
4021 /* Is this a LS or FS device under a HS hub? */
4022 /* Hub or peripherial? */
4026 xhci_disable_slot(xhci, udev->slot_id);
4027 xhci_free_virt_device(xhci, udev->slot_id);
4033 * Issue an Address Device command and optionally send a corresponding
4034 * SetAddress request to the device.
4036 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4037 enum xhci_setup_dev setup)
4039 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4040 unsigned long flags;
4041 struct xhci_virt_device *virt_dev;
4043 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4044 struct xhci_slot_ctx *slot_ctx;
4045 struct xhci_input_control_ctx *ctrl_ctx;
4047 struct xhci_command *command = NULL;
4049 mutex_lock(&xhci->mutex);
4051 if (xhci->xhc_state) { /* dying, removing or halted */
4056 if (!udev->slot_id) {
4057 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4058 "Bad Slot ID %d", udev->slot_id);
4063 virt_dev = xhci->devs[udev->slot_id];
4065 if (WARN_ON(!virt_dev)) {
4067 * In plug/unplug torture test with an NEC controller,
4068 * a zero-dereference was observed once due to virt_dev = 0.
4069 * Print useful debug rather than crash if it is observed again!
4071 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4076 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4077 trace_xhci_setup_device_slot(slot_ctx);
4079 if (setup == SETUP_CONTEXT_ONLY) {
4080 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4081 SLOT_STATE_DEFAULT) {
4082 xhci_dbg(xhci, "Slot already in default state\n");
4087 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4093 command->in_ctx = virt_dev->in_ctx;
4095 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4096 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4098 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4104 * If this is the first Set Address since device plug-in or
4105 * virt_device realloaction after a resume with an xHCI power loss,
4106 * then set up the slot context.
4108 if (!slot_ctx->dev_info)
4109 xhci_setup_addressable_virt_dev(xhci, udev);
4110 /* Otherwise, update the control endpoint ring enqueue pointer. */
4112 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4113 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4114 ctrl_ctx->drop_flags = 0;
4116 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4117 le32_to_cpu(slot_ctx->dev_info) >> 27);
4119 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4120 spin_lock_irqsave(&xhci->lock, flags);
4121 trace_xhci_setup_device(virt_dev);
4122 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4123 udev->slot_id, setup);
4125 spin_unlock_irqrestore(&xhci->lock, flags);
4126 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4127 "FIXME: allocate a command ring segment");
4130 xhci_ring_cmd_db(xhci);
4131 spin_unlock_irqrestore(&xhci->lock, flags);
4133 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4134 wait_for_completion(command->completion);
4136 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4137 * the SetAddress() "recovery interval" required by USB and aborting the
4138 * command on a timeout.
4140 switch (command->status) {
4141 case COMP_COMMAND_ABORTED:
4142 case COMP_COMMAND_RING_STOPPED:
4143 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4146 case COMP_CONTEXT_STATE_ERROR:
4147 case COMP_SLOT_NOT_ENABLED_ERROR:
4148 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4149 act, udev->slot_id);
4152 case COMP_USB_TRANSACTION_ERROR:
4153 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4155 mutex_unlock(&xhci->mutex);
4156 ret = xhci_disable_slot(xhci, udev->slot_id);
4157 xhci_free_virt_device(xhci, udev->slot_id);
4159 xhci_alloc_dev(hcd, udev);
4160 kfree(command->completion);
4163 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4164 dev_warn(&udev->dev,
4165 "ERROR: Incompatible device for setup %s command\n", act);
4169 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4170 "Successful setup %s command", act);
4174 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4175 act, command->status);
4176 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4182 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4183 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4184 "Op regs DCBAA ptr = %#016llx", temp_64);
4185 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4186 "Slot ID %d dcbaa entry @%p = %#016llx",
4188 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4189 (unsigned long long)
4190 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4191 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4192 "Output Context DMA address = %#08llx",
4193 (unsigned long long)virt_dev->out_ctx->dma);
4194 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4195 le32_to_cpu(slot_ctx->dev_info) >> 27);
4197 * USB core uses address 1 for the roothubs, so we add one to the
4198 * address given back to us by the HC.
4200 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4201 le32_to_cpu(slot_ctx->dev_info) >> 27);
4202 /* Zero the input context control for later use */
4203 ctrl_ctx->add_flags = 0;
4204 ctrl_ctx->drop_flags = 0;
4205 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4206 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4208 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4209 "Internal device address = %d",
4210 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4212 mutex_unlock(&xhci->mutex);
4214 kfree(command->completion);
4220 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4222 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4225 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4227 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4231 * Transfer the port index into real index in the HW port status
4232 * registers. Caculate offset between the port's PORTSC register
4233 * and port status base. Divide the number of per port register
4234 * to get the real index. The raw port number bases 1.
4236 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4238 struct xhci_hub *rhub;
4240 rhub = xhci_get_rhub(hcd);
4241 return rhub->ports[port1 - 1]->hw_portnum + 1;
4245 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4246 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4248 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4249 struct usb_device *udev, u16 max_exit_latency)
4251 struct xhci_virt_device *virt_dev;
4252 struct xhci_command *command;
4253 struct xhci_input_control_ctx *ctrl_ctx;
4254 struct xhci_slot_ctx *slot_ctx;
4255 unsigned long flags;
4258 command = xhci_alloc_command_with_ctx(xhci, true, GFP_KERNEL);
4262 spin_lock_irqsave(&xhci->lock, flags);
4264 virt_dev = xhci->devs[udev->slot_id];
4267 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4268 * xHC was re-initialized. Exit latency will be set later after
4269 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4272 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4273 spin_unlock_irqrestore(&xhci->lock, flags);
4274 xhci_free_command(xhci, command);
4278 /* Attempt to issue an Evaluate Context command to change the MEL. */
4279 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4281 spin_unlock_irqrestore(&xhci->lock, flags);
4282 xhci_free_command(xhci, command);
4283 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4288 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4289 spin_unlock_irqrestore(&xhci->lock, flags);
4291 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4292 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4293 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4294 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4295 slot_ctx->dev_state = 0;
4297 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4298 "Set up evaluate context for LPM MEL change.");
4300 /* Issue and wait for the evaluate context command. */
4301 ret = xhci_configure_endpoint(xhci, udev, command,
4305 spin_lock_irqsave(&xhci->lock, flags);
4306 virt_dev->current_mel = max_exit_latency;
4307 spin_unlock_irqrestore(&xhci->lock, flags);
4310 xhci_free_command(xhci, command);
4317 /* BESL to HIRD Encoding array for USB2 LPM */
4318 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4319 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4321 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4322 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4323 struct usb_device *udev)
4325 int u2del, besl, besl_host;
4326 int besl_device = 0;
4329 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4330 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4332 if (field & USB_BESL_SUPPORT) {
4333 for (besl_host = 0; besl_host < 16; besl_host++) {
4334 if (xhci_besl_encoding[besl_host] >= u2del)
4337 /* Use baseline BESL value as default */
4338 if (field & USB_BESL_BASELINE_VALID)
4339 besl_device = USB_GET_BESL_BASELINE(field);
4340 else if (field & USB_BESL_DEEP_VALID)
4341 besl_device = USB_GET_BESL_DEEP(field);
4346 besl_host = (u2del - 51) / 75 + 1;
4349 besl = besl_host + besl_device;
4356 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4357 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4364 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4366 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4367 l1 = udev->l1_params.timeout / 256;
4369 /* device has preferred BESLD */
4370 if (field & USB_BESL_DEEP_VALID) {
4371 besld = USB_GET_BESL_DEEP(field);
4375 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4378 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4379 struct usb_device *udev, int enable)
4381 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4382 struct xhci_port **ports;
4383 __le32 __iomem *pm_addr, *hlpm_addr;
4384 u32 pm_val, hlpm_val, field;
4385 unsigned int port_num;
4386 unsigned long flags;
4387 int hird, exit_latency;
4390 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4393 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4397 if (!udev->parent || udev->parent->parent ||
4398 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4401 if (udev->usb2_hw_lpm_capable != 1)
4404 spin_lock_irqsave(&xhci->lock, flags);
4406 ports = xhci->usb2_rhub.ports;
4407 port_num = udev->portnum - 1;
4408 pm_addr = ports[port_num]->addr + PORTPMSC;
4409 pm_val = readl(pm_addr);
4410 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4412 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4413 enable ? "enable" : "disable", port_num + 1);
4416 /* Host supports BESL timeout instead of HIRD */
4417 if (udev->usb2_hw_lpm_besl_capable) {
4418 /* if device doesn't have a preferred BESL value use a
4419 * default one which works with mixed HIRD and BESL
4420 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4422 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4423 if ((field & USB_BESL_SUPPORT) &&
4424 (field & USB_BESL_BASELINE_VALID))
4425 hird = USB_GET_BESL_BASELINE(field);
4427 hird = udev->l1_params.besl;
4429 exit_latency = xhci_besl_encoding[hird];
4430 spin_unlock_irqrestore(&xhci->lock, flags);
4432 ret = xhci_change_max_exit_latency(xhci, udev,
4436 spin_lock_irqsave(&xhci->lock, flags);
4438 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4439 writel(hlpm_val, hlpm_addr);
4443 hird = xhci_calculate_hird_besl(xhci, udev);
4446 pm_val &= ~PORT_HIRD_MASK;
4447 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4448 writel(pm_val, pm_addr);
4449 pm_val = readl(pm_addr);
4451 writel(pm_val, pm_addr);
4455 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4456 writel(pm_val, pm_addr);
4459 if (udev->usb2_hw_lpm_besl_capable) {
4460 spin_unlock_irqrestore(&xhci->lock, flags);
4461 xhci_change_max_exit_latency(xhci, udev, 0);
4462 readl_poll_timeout(ports[port_num]->addr, pm_val,
4463 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4469 spin_unlock_irqrestore(&xhci->lock, flags);
4473 /* check if a usb2 port supports a given extened capability protocol
4474 * only USB2 ports extended protocol capability values are cached.
4475 * Return 1 if capability is supported
4477 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4478 unsigned capability)
4480 u32 port_offset, port_count;
4483 for (i = 0; i < xhci->num_ext_caps; i++) {
4484 if (xhci->ext_caps[i] & capability) {
4485 /* port offsets starts at 1 */
4486 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4487 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4488 if (port >= port_offset &&
4489 port < port_offset + port_count)
4496 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4498 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4499 int portnum = udev->portnum - 1;
4501 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4504 /* we only support lpm for non-hub device connected to root hub yet */
4505 if (!udev->parent || udev->parent->parent ||
4506 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4509 if (xhci->hw_lpm_support == 1 &&
4510 xhci_check_usb2_port_capability(
4511 xhci, portnum, XHCI_HLC)) {
4512 udev->usb2_hw_lpm_capable = 1;
4513 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4514 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4515 if (xhci_check_usb2_port_capability(xhci, portnum,
4517 udev->usb2_hw_lpm_besl_capable = 1;
4523 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4525 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4526 static unsigned long long xhci_service_interval_to_ns(
4527 struct usb_endpoint_descriptor *desc)
4529 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4532 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4533 enum usb3_link_state state)
4535 unsigned long long sel;
4536 unsigned long long pel;
4537 unsigned int max_sel_pel;
4542 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4543 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4544 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4545 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4549 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4550 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4551 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4555 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4557 return USB3_LPM_DISABLED;
4560 if (sel <= max_sel_pel && pel <= max_sel_pel)
4561 return USB3_LPM_DEVICE_INITIATED;
4563 if (sel > max_sel_pel)
4564 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4565 "due to long SEL %llu ms\n",
4568 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4569 "due to long PEL %llu ms\n",
4571 return USB3_LPM_DISABLED;
4574 /* The U1 timeout should be the maximum of the following values:
4575 * - For control endpoints, U1 system exit latency (SEL) * 3
4576 * - For bulk endpoints, U1 SEL * 5
4577 * - For interrupt endpoints:
4578 * - Notification EPs, U1 SEL * 3
4579 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4580 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4582 static unsigned long long xhci_calculate_intel_u1_timeout(
4583 struct usb_device *udev,
4584 struct usb_endpoint_descriptor *desc)
4586 unsigned long long timeout_ns;
4590 ep_type = usb_endpoint_type(desc);
4592 case USB_ENDPOINT_XFER_CONTROL:
4593 timeout_ns = udev->u1_params.sel * 3;
4595 case USB_ENDPOINT_XFER_BULK:
4596 timeout_ns = udev->u1_params.sel * 5;
4598 case USB_ENDPOINT_XFER_INT:
4599 intr_type = usb_endpoint_interrupt_type(desc);
4600 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4601 timeout_ns = udev->u1_params.sel * 3;
4604 /* Otherwise the calculation is the same as isoc eps */
4606 case USB_ENDPOINT_XFER_ISOC:
4607 timeout_ns = xhci_service_interval_to_ns(desc);
4608 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4609 if (timeout_ns < udev->u1_params.sel * 2)
4610 timeout_ns = udev->u1_params.sel * 2;
4619 /* Returns the hub-encoded U1 timeout value. */
4620 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4621 struct usb_device *udev,
4622 struct usb_endpoint_descriptor *desc)
4624 unsigned long long timeout_ns;
4626 /* Prevent U1 if service interval is shorter than U1 exit latency */
4627 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4628 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4629 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4630 return USB3_LPM_DISABLED;
4634 if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
4635 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4637 timeout_ns = udev->u1_params.sel;
4639 /* The U1 timeout is encoded in 1us intervals.
4640 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4642 if (timeout_ns == USB3_LPM_DISABLED)
4645 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4647 /* If the necessary timeout value is bigger than what we can set in the
4648 * USB 3.0 hub, we have to disable hub-initiated U1.
4650 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4652 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4653 "due to long timeout %llu ms\n", timeout_ns);
4654 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4657 /* The U2 timeout should be the maximum of:
4658 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4659 * - largest bInterval of any active periodic endpoint (to avoid going
4660 * into lower power link states between intervals).
4661 * - the U2 Exit Latency of the device
4663 static unsigned long long xhci_calculate_intel_u2_timeout(
4664 struct usb_device *udev,
4665 struct usb_endpoint_descriptor *desc)
4667 unsigned long long timeout_ns;
4668 unsigned long long u2_del_ns;
4670 timeout_ns = 10 * 1000 * 1000;
4672 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4673 (xhci_service_interval_to_ns(desc) > timeout_ns))
4674 timeout_ns = xhci_service_interval_to_ns(desc);
4676 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4677 if (u2_del_ns > timeout_ns)
4678 timeout_ns = u2_del_ns;
4683 /* Returns the hub-encoded U2 timeout value. */
4684 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4685 struct usb_device *udev,
4686 struct usb_endpoint_descriptor *desc)
4688 unsigned long long timeout_ns;
4690 /* Prevent U2 if service interval is shorter than U2 exit latency */
4691 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4692 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4693 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4694 return USB3_LPM_DISABLED;
4698 if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
4699 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4701 timeout_ns = udev->u2_params.sel;
4703 /* The U2 timeout is encoded in 256us intervals */
4704 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4705 /* If the necessary timeout value is bigger than what we can set in the
4706 * USB 3.0 hub, we have to disable hub-initiated U2.
4708 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4710 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4711 "due to long timeout %llu ms\n", timeout_ns);
4712 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4715 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4716 struct usb_device *udev,
4717 struct usb_endpoint_descriptor *desc,
4718 enum usb3_link_state state,
4721 if (state == USB3_LPM_U1)
4722 return xhci_calculate_u1_timeout(xhci, udev, desc);
4723 else if (state == USB3_LPM_U2)
4724 return xhci_calculate_u2_timeout(xhci, udev, desc);
4726 return USB3_LPM_DISABLED;
4729 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4730 struct usb_device *udev,
4731 struct usb_endpoint_descriptor *desc,
4732 enum usb3_link_state state,
4737 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4738 desc, state, timeout);
4740 /* If we found we can't enable hub-initiated LPM, and
4741 * the U1 or U2 exit latency was too high to allow
4742 * device-initiated LPM as well, then we will disable LPM
4743 * for this device, so stop searching any further.
4745 if (alt_timeout == USB3_LPM_DISABLED) {
4746 *timeout = alt_timeout;
4749 if (alt_timeout > *timeout)
4750 *timeout = alt_timeout;
4754 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4755 struct usb_device *udev,
4756 struct usb_host_interface *alt,
4757 enum usb3_link_state state,
4762 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4763 if (xhci_update_timeout_for_endpoint(xhci, udev,
4764 &alt->endpoint[j].desc, state, timeout))
4770 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4771 struct usb_device *udev,
4772 enum usb3_link_state state)
4774 struct usb_device *parent = udev->parent;
4775 int tier = 1; /* roothub is tier1 */
4778 parent = parent->parent;
4782 if (xhci->quirks & XHCI_INTEL_HOST && tier > 3)
4784 if (xhci->quirks & XHCI_ZHAOXIN_HOST && tier > 2)
4789 dev_dbg(&udev->dev, "Tier policy prevents U1/U2 LPM states for devices at tier %d\n",
4794 /* Returns the U1 or U2 timeout that should be enabled.
4795 * If the tier check or timeout setting functions return with a non-zero exit
4796 * code, that means the timeout value has been finalized and we shouldn't look
4797 * at any more endpoints.
4799 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4800 struct usb_device *udev, enum usb3_link_state state)
4802 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4803 struct usb_host_config *config;
4806 u16 timeout = USB3_LPM_DISABLED;
4808 if (state == USB3_LPM_U1)
4810 else if (state == USB3_LPM_U2)
4813 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4818 /* Gather some information about the currently installed configuration
4819 * and alternate interface settings.
4821 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4825 config = udev->actconfig;
4829 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4830 struct usb_driver *driver;
4831 struct usb_interface *intf = config->interface[i];
4836 /* Check if any currently bound drivers want hub-initiated LPM
4839 if (intf->dev.driver) {
4840 driver = to_usb_driver(intf->dev.driver);
4841 if (driver && driver->disable_hub_initiated_lpm) {
4842 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4843 state_name, driver->name);
4844 timeout = xhci_get_timeout_no_hub_lpm(udev,
4846 if (timeout == USB3_LPM_DISABLED)
4851 /* Not sure how this could happen... */
4852 if (!intf->cur_altsetting)
4855 if (xhci_update_timeout_for_interface(xhci, udev,
4856 intf->cur_altsetting,
4863 static int calculate_max_exit_latency(struct usb_device *udev,
4864 enum usb3_link_state state_changed,
4865 u16 hub_encoded_timeout)
4867 unsigned long long u1_mel_us = 0;
4868 unsigned long long u2_mel_us = 0;
4869 unsigned long long mel_us = 0;
4875 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4876 hub_encoded_timeout == USB3_LPM_DISABLED);
4877 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4878 hub_encoded_timeout == USB3_LPM_DISABLED);
4880 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4881 hub_encoded_timeout != USB3_LPM_DISABLED);
4882 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4883 hub_encoded_timeout != USB3_LPM_DISABLED);
4885 /* If U1 was already enabled and we're not disabling it,
4886 * or we're going to enable U1, account for the U1 max exit latency.
4888 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4890 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4891 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4893 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4895 mel_us = max(u1_mel_us, u2_mel_us);
4897 /* xHCI host controller max exit latency field is only 16 bits wide. */
4898 if (mel_us > MAX_EXIT) {
4899 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4900 "is too big.\n", mel_us);
4906 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4907 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4908 struct usb_device *udev, enum usb3_link_state state)
4910 struct xhci_hcd *xhci;
4911 struct xhci_port *port;
4912 u16 hub_encoded_timeout;
4916 xhci = hcd_to_xhci(hcd);
4917 /* The LPM timeout values are pretty host-controller specific, so don't
4918 * enable hub-initiated timeouts unless the vendor has provided
4919 * information about their timeout algorithm.
4921 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4922 !xhci->devs[udev->slot_id])
4923 return USB3_LPM_DISABLED;
4925 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4926 return USB3_LPM_DISABLED;
4928 /* If connected to root port then check port can handle lpm */
4929 if (udev->parent && !udev->parent->parent) {
4930 port = xhci->usb3_rhub.ports[udev->portnum - 1];
4931 if (port->lpm_incapable)
4932 return USB3_LPM_DISABLED;
4935 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4936 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4938 /* Max Exit Latency is too big, disable LPM. */
4939 hub_encoded_timeout = USB3_LPM_DISABLED;
4943 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4946 return hub_encoded_timeout;
4949 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4950 struct usb_device *udev, enum usb3_link_state state)
4952 struct xhci_hcd *xhci;
4955 xhci = hcd_to_xhci(hcd);
4956 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4957 !xhci->devs[udev->slot_id])
4960 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4961 return xhci_change_max_exit_latency(xhci, udev, mel);
4963 #else /* CONFIG_PM */
4965 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4966 struct usb_device *udev, int enable)
4971 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4976 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4977 struct usb_device *udev, enum usb3_link_state state)
4979 return USB3_LPM_DISABLED;
4982 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4983 struct usb_device *udev, enum usb3_link_state state)
4987 #endif /* CONFIG_PM */
4989 /*-------------------------------------------------------------------------*/
4991 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4992 * internal data structures for the device.
4994 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4995 struct usb_tt *tt, gfp_t mem_flags)
4997 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4998 struct xhci_virt_device *vdev;
4999 struct xhci_command *config_cmd;
5000 struct xhci_input_control_ctx *ctrl_ctx;
5001 struct xhci_slot_ctx *slot_ctx;
5002 unsigned long flags;
5003 unsigned think_time;
5006 /* Ignore root hubs */
5010 vdev = xhci->devs[hdev->slot_id];
5012 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5016 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5020 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5022 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5024 xhci_free_command(xhci, config_cmd);
5028 spin_lock_irqsave(&xhci->lock, flags);
5029 if (hdev->speed == USB_SPEED_HIGH &&
5030 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5031 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5032 xhci_free_command(xhci, config_cmd);
5033 spin_unlock_irqrestore(&xhci->lock, flags);
5037 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5038 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5039 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5040 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5042 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5043 * but it may be already set to 1 when setup an xHCI virtual
5044 * device, so clear it anyway.
5047 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5048 else if (hdev->speed == USB_SPEED_FULL)
5049 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5051 if (xhci->hci_version > 0x95) {
5052 xhci_dbg(xhci, "xHCI version %x needs hub "
5053 "TT think time and number of ports\n",
5054 (unsigned int) xhci->hci_version);
5055 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5056 /* Set TT think time - convert from ns to FS bit times.
5057 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5058 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5060 * xHCI 1.0: this field shall be 0 if the device is not a
5063 think_time = tt->think_time;
5064 if (think_time != 0)
5065 think_time = (think_time / 666) - 1;
5066 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5067 slot_ctx->tt_info |=
5068 cpu_to_le32(TT_THINK_TIME(think_time));
5070 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5071 "TT think time or number of ports\n",
5072 (unsigned int) xhci->hci_version);
5074 slot_ctx->dev_state = 0;
5075 spin_unlock_irqrestore(&xhci->lock, flags);
5077 xhci_dbg(xhci, "Set up %s for hub device.\n",
5078 (xhci->hci_version > 0x95) ?
5079 "configure endpoint" : "evaluate context");
5081 /* Issue and wait for the configure endpoint or
5082 * evaluate context command.
5084 if (xhci->hci_version > 0x95)
5085 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5088 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5091 xhci_free_command(xhci, config_cmd);
5094 EXPORT_SYMBOL_GPL(xhci_update_hub_device);
5096 static int xhci_get_frame(struct usb_hcd *hcd)
5098 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5099 /* EHCI mods by the periodic size. Why? */
5100 return readl(&xhci->run_regs->microframe_index) >> 3;
5103 static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5105 xhci->usb2_rhub.hcd = hcd;
5106 hcd->speed = HCD_USB2;
5107 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5109 * USB 2.0 roothub under xHCI has an integrated TT,
5110 * (rate matching hub) as opposed to having an OHCI/UHCI
5111 * companion controller.
5116 static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5118 unsigned int minor_rev;
5121 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5122 * should return 0x31 for sbrn, or that the minor revision
5123 * is a two digit BCD containig minor and sub-minor numbers.
5124 * This was later clarified in xHCI 1.2.
5126 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5127 * minor revision set to 0x1 instead of 0x10.
5129 if (xhci->usb3_rhub.min_rev == 0x1)
5132 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5134 switch (minor_rev) {
5136 hcd->speed = HCD_USB32;
5137 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5138 hcd->self.root_hub->rx_lanes = 2;
5139 hcd->self.root_hub->tx_lanes = 2;
5140 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5143 hcd->speed = HCD_USB31;
5144 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5145 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5148 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5149 minor_rev, minor_rev ? "Enhanced " : "");
5151 xhci->usb3_rhub.hcd = hcd;
5154 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5156 struct xhci_hcd *xhci;
5158 * TODO: Check with DWC3 clients for sysdev according to
5161 struct device *dev = hcd->self.sysdev;
5164 /* Accept arbitrarily long scatter-gather lists */
5165 hcd->self.sg_tablesize = ~0;
5167 /* support to build packet from discontinuous buffers */
5168 hcd->self.no_sg_constraint = 1;
5170 /* XHCI controllers don't stop the ep queue on short packets :| */
5171 hcd->self.no_stop_on_short = 1;
5173 xhci = hcd_to_xhci(hcd);
5175 if (!usb_hcd_is_primary_hcd(hcd)) {
5176 xhci_hcd_init_usb3_data(xhci, hcd);
5180 mutex_init(&xhci->mutex);
5181 xhci->main_hcd = hcd;
5182 xhci->cap_regs = hcd->regs;
5183 xhci->op_regs = hcd->regs +
5184 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5185 xhci->run_regs = hcd->regs +
5186 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5187 /* Cache read-only capability registers */
5188 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5189 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5190 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5191 xhci->hci_version = HC_VERSION(readl(&xhci->cap_regs->hc_capbase));
5192 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5193 if (xhci->hci_version > 0x100)
5194 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5196 /* xhci-plat or xhci-pci might have set max_interrupters already */
5197 if ((!xhci->max_interrupters) ||
5198 xhci->max_interrupters > HCS_MAX_INTRS(xhci->hcs_params1))
5199 xhci->max_interrupters = HCS_MAX_INTRS(xhci->hcs_params1);
5201 xhci->quirks |= quirks;
5204 get_quirks(dev, xhci);
5206 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5207 * success event after a short transfer. This quirk will ignore such
5210 if (xhci->hci_version > 0x96)
5211 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5213 /* Make sure the HC is halted. */
5214 retval = xhci_halt(xhci);
5218 xhci_zero_64b_regs(xhci);
5220 xhci_dbg(xhci, "Resetting HCD\n");
5221 /* Reset the internal HC memory state and registers. */
5222 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5225 xhci_dbg(xhci, "Reset complete\n");
5228 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5229 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5230 * address memory pointers actually. So, this driver clears the AC64
5231 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5232 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5234 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5235 xhci->hcc_params &= ~BIT(0);
5237 /* Set dma_mask and coherent_dma_mask to 64-bits,
5238 * if xHC supports 64-bit addressing */
5239 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5240 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5241 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5242 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5245 * This is to avoid error in cases where a 32-bit USB
5246 * controller is used on a 64-bit capable system.
5248 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5251 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5252 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5255 xhci_dbg(xhci, "Calling HCD init\n");
5256 /* Initialize HCD and host controller data structures. */
5257 retval = xhci_init(hcd);
5260 xhci_dbg(xhci, "Called HCD init\n");
5262 if (xhci_hcd_is_usb3(hcd))
5263 xhci_hcd_init_usb3_data(xhci, hcd);
5265 xhci_hcd_init_usb2_data(xhci, hcd);
5267 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5268 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5272 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5274 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5275 struct usb_host_endpoint *ep)
5277 struct xhci_hcd *xhci;
5278 struct usb_device *udev;
5279 unsigned int slot_id;
5280 unsigned int ep_index;
5281 unsigned long flags;
5283 xhci = hcd_to_xhci(hcd);
5285 spin_lock_irqsave(&xhci->lock, flags);
5286 udev = (struct usb_device *)ep->hcpriv;
5287 slot_id = udev->slot_id;
5288 ep_index = xhci_get_endpoint_index(&ep->desc);
5290 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5291 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5292 spin_unlock_irqrestore(&xhci->lock, flags);
5295 static const struct hc_driver xhci_hc_driver = {
5296 .description = "xhci-hcd",
5297 .product_desc = "xHCI Host Controller",
5298 .hcd_priv_size = sizeof(struct xhci_hcd),
5301 * generic hardware linkage
5304 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5308 * basic lifecycle operations
5310 .reset = NULL, /* set in xhci_init_driver() */
5313 .shutdown = xhci_shutdown,
5316 * managing i/o requests and associated device resources
5318 .map_urb_for_dma = xhci_map_urb_for_dma,
5319 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5320 .urb_enqueue = xhci_urb_enqueue,
5321 .urb_dequeue = xhci_urb_dequeue,
5322 .alloc_dev = xhci_alloc_dev,
5323 .free_dev = xhci_free_dev,
5324 .alloc_streams = xhci_alloc_streams,
5325 .free_streams = xhci_free_streams,
5326 .add_endpoint = xhci_add_endpoint,
5327 .drop_endpoint = xhci_drop_endpoint,
5328 .endpoint_disable = xhci_endpoint_disable,
5329 .endpoint_reset = xhci_endpoint_reset,
5330 .check_bandwidth = xhci_check_bandwidth,
5331 .reset_bandwidth = xhci_reset_bandwidth,
5332 .address_device = xhci_address_device,
5333 .enable_device = xhci_enable_device,
5334 .update_hub_device = xhci_update_hub_device,
5335 .reset_device = xhci_discover_or_reset_device,
5338 * scheduling support
5340 .get_frame_number = xhci_get_frame,
5345 .hub_control = xhci_hub_control,
5346 .hub_status_data = xhci_hub_status_data,
5347 .bus_suspend = xhci_bus_suspend,
5348 .bus_resume = xhci_bus_resume,
5349 .get_resuming_ports = xhci_get_resuming_ports,
5352 * call back when device connected and addressed
5354 .update_device = xhci_update_device,
5355 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5356 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5357 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5358 .find_raw_port_number = xhci_find_raw_port_number,
5359 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5362 void xhci_init_driver(struct hc_driver *drv,
5363 const struct xhci_driver_overrides *over)
5367 /* Copy the generic table to drv then apply the overrides */
5368 *drv = xhci_hc_driver;
5371 drv->hcd_priv_size += over->extra_priv_size;
5373 drv->reset = over->reset;
5375 drv->start = over->start;
5376 if (over->add_endpoint)
5377 drv->add_endpoint = over->add_endpoint;
5378 if (over->drop_endpoint)
5379 drv->drop_endpoint = over->drop_endpoint;
5380 if (over->check_bandwidth)
5381 drv->check_bandwidth = over->check_bandwidth;
5382 if (over->reset_bandwidth)
5383 drv->reset_bandwidth = over->reset_bandwidth;
5384 if (over->update_hub_device)
5385 drv->update_hub_device = over->update_hub_device;
5386 if (over->hub_control)
5387 drv->hub_control = over->hub_control;
5390 EXPORT_SYMBOL_GPL(xhci_init_driver);
5392 MODULE_DESCRIPTION(DRIVER_DESC);
5393 MODULE_AUTHOR(DRIVER_AUTHOR);
5394 MODULE_LICENSE("GPL");
5396 static int __init xhci_hcd_init(void)
5399 * Check the compiler generated sizes of structures that must be laid
5400 * out in specific ways for hardware access.
5402 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5403 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5404 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5405 /* xhci_device_control has eight fields, and also
5406 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5408 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5409 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5410 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5411 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5412 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5413 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5414 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5419 xhci_debugfs_create_root();
5426 * If an init function is provided, an exit function must also be provided
5427 * to allow module unload.
5429 static void __exit xhci_hcd_fini(void)
5431 xhci_debugfs_remove_root();
5435 module_init(xhci_hcd_init);
5436 module_exit(xhci_hcd_fini);