2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/iopoll.h>
25 #include <linux/irq.h>
26 #include <linux/log2.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/slab.h>
30 #include <linux/dmi.h>
31 #include <linux/dma-mapping.h>
34 #include "xhci-trace.h"
37 #define DRIVER_AUTHOR "Sarah Sharp"
38 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
40 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
42 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
43 static int link_quirk;
44 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
45 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
47 static unsigned int quirks;
48 module_param(quirks, uint, S_IRUGO);
49 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
52 * xhci_handshake - spin reading hc until handshake completes or fails
53 * @ptr: address of hc register to be read
54 * @mask: bits to look at in result of read
55 * @done: value of those bits when handshake succeeds
56 * @usec: timeout in microseconds
58 * Returns negative errno, or zero on success
60 * Success happens when the "mask" bits have the specified value (hardware
61 * handshake done). There are two failure modes: "usec" have passed (major
62 * hardware flakeout), or the register reads as all-ones (hardware removed).
64 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
69 ret = readl_poll_timeout_atomic(ptr, result,
70 (result & mask) == done ||
73 if (result == U32_MAX) /* card removed */
80 * Disable interrupts and begin the xHCI halting process.
82 void xhci_quiesce(struct xhci_hcd *xhci)
89 halted = readl(&xhci->op_regs->status) & STS_HALT;
93 cmd = readl(&xhci->op_regs->command);
95 writel(cmd, &xhci->op_regs->command);
99 * Force HC into halt state.
101 * Disable any IRQs and clear the run/stop bit.
102 * HC will complete any current and actively pipelined transactions, and
103 * should halt within 16 ms of the run/stop bit being cleared.
104 * Read HC Halted bit in the status register to see when the HC is finished.
106 int xhci_halt(struct xhci_hcd *xhci)
109 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
112 ret = xhci_handshake(&xhci->op_regs->status,
113 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
115 xhci->xhc_state |= XHCI_STATE_HALTED;
116 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
118 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
124 * Set the run bit and wait for the host to be running.
126 static int xhci_start(struct xhci_hcd *xhci)
131 temp = readl(&xhci->op_regs->command);
133 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
135 writel(temp, &xhci->op_regs->command);
138 * Wait for the HCHalted Status bit to be 0 to indicate the host is
141 ret = xhci_handshake(&xhci->op_regs->status,
142 STS_HALT, 0, XHCI_MAX_HALT_USEC);
143 if (ret == -ETIMEDOUT)
144 xhci_err(xhci, "Host took too long to start, "
145 "waited %u microseconds.\n",
148 /* clear state flags. Including dying, halted or removing */
157 * This resets pipelines, timers, counters, state machines, etc.
158 * Transactions will be terminated immediately, and operational registers
159 * will be set to their defaults.
161 int xhci_reset(struct xhci_hcd *xhci)
167 state = readl(&xhci->op_regs->status);
168 if ((state & STS_HALT) == 0) {
169 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
173 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
174 command = readl(&xhci->op_regs->command);
175 command |= CMD_RESET;
176 writel(command, &xhci->op_regs->command);
178 /* Existing Intel xHCI controllers require a delay of 1 mS,
179 * after setting the CMD_RESET bit, and before accessing any
180 * HC registers. This allows the HC to complete the
181 * reset operation and be ready for HC register access.
182 * Without this delay, the subsequent HC register access,
183 * may result in a system hang very rarely.
185 if (xhci->quirks & XHCI_INTEL_HOST)
188 ret = xhci_handshake(&xhci->op_regs->command,
189 CMD_RESET, 0, 10 * 1000 * 1000);
193 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
194 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
196 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
197 "Wait for controller to be ready for doorbell rings");
199 * xHCI cannot write to any doorbells or operational registers other
200 * than status until the "Controller Not Ready" flag is cleared.
202 ret = xhci_handshake(&xhci->op_regs->status,
203 STS_CNR, 0, 10 * 1000 * 1000);
205 for (i = 0; i < 2; ++i) {
206 xhci->bus_state[i].port_c_suspend = 0;
207 xhci->bus_state[i].suspended_ports = 0;
208 xhci->bus_state[i].resuming_ports = 0;
215 static int xhci_free_msi(struct xhci_hcd *xhci)
219 if (!xhci->msix_entries)
222 for (i = 0; i < xhci->msix_count; i++)
223 if (xhci->msix_entries[i].vector)
224 free_irq(xhci->msix_entries[i].vector,
232 static int xhci_setup_msi(struct xhci_hcd *xhci)
235 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
237 ret = pci_enable_msi(pdev);
239 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
240 "failed to allocate MSI entry");
244 ret = request_irq(pdev->irq, xhci_msi_irq,
245 0, "xhci_hcd", xhci_to_hcd(xhci));
247 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
248 "disable MSI interrupt");
249 pci_disable_msi(pdev);
257 * free all IRQs request
259 static void xhci_free_irq(struct xhci_hcd *xhci)
261 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
264 /* return if using legacy interrupt */
265 if (xhci_to_hcd(xhci)->irq > 0)
268 ret = xhci_free_msi(xhci);
272 free_irq(pdev->irq, xhci_to_hcd(xhci));
280 static int xhci_setup_msix(struct xhci_hcd *xhci)
283 struct usb_hcd *hcd = xhci_to_hcd(xhci);
284 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
287 * calculate number of msi-x vectors supported.
288 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
289 * with max number of interrupters based on the xhci HCSPARAMS1.
290 * - num_online_cpus: maximum msi-x vectors per CPUs core.
291 * Add additional 1 vector to ensure always available interrupt.
293 xhci->msix_count = min(num_online_cpus() + 1,
294 HCS_MAX_INTRS(xhci->hcs_params1));
297 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
299 if (!xhci->msix_entries)
302 for (i = 0; i < xhci->msix_count; i++) {
303 xhci->msix_entries[i].entry = i;
304 xhci->msix_entries[i].vector = 0;
307 ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count);
309 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
310 "Failed to enable MSI-X");
314 for (i = 0; i < xhci->msix_count; i++) {
315 ret = request_irq(xhci->msix_entries[i].vector,
317 0, "xhci_hcd", xhci_to_hcd(xhci));
322 hcd->msix_enabled = 1;
326 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
328 pci_disable_msix(pdev);
330 kfree(xhci->msix_entries);
331 xhci->msix_entries = NULL;
335 /* Free any IRQs and disable MSI-X */
336 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
338 struct usb_hcd *hcd = xhci_to_hcd(xhci);
339 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
341 if (xhci->quirks & XHCI_PLAT)
346 if (xhci->msix_entries) {
347 pci_disable_msix(pdev);
348 kfree(xhci->msix_entries);
349 xhci->msix_entries = NULL;
351 pci_disable_msi(pdev);
354 hcd->msix_enabled = 0;
358 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
362 if (xhci->msix_entries) {
363 for (i = 0; i < xhci->msix_count; i++)
364 synchronize_irq(xhci->msix_entries[i].vector);
368 static int xhci_try_enable_msi(struct usb_hcd *hcd)
370 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
371 struct pci_dev *pdev;
374 /* The xhci platform device has set up IRQs through usb_add_hcd. */
375 if (xhci->quirks & XHCI_PLAT)
378 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
380 * Some Fresco Logic host controllers advertise MSI, but fail to
381 * generate interrupts. Don't even try to enable MSI.
383 if (xhci->quirks & XHCI_BROKEN_MSI)
386 /* unregister the legacy interrupt */
388 free_irq(hcd->irq, hcd);
391 ret = xhci_setup_msix(xhci);
393 /* fall back to msi*/
394 ret = xhci_setup_msi(xhci);
397 /* hcd->irq is 0, we have MSI */
401 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
406 if (!strlen(hcd->irq_descr))
407 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
408 hcd->driver->description, hcd->self.busnum);
410 /* fall back to legacy interrupt*/
411 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
412 hcd->irq_descr, hcd);
414 xhci_err(xhci, "request interrupt %d failed\n",
418 hcd->irq = pdev->irq;
424 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
429 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
433 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
439 static void compliance_mode_recovery(unsigned long arg)
441 struct xhci_hcd *xhci;
446 xhci = (struct xhci_hcd *)arg;
448 for (i = 0; i < xhci->num_usb3_ports; i++) {
449 temp = readl(xhci->usb3_ports[i]);
450 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
452 * Compliance Mode Detected. Letting USB Core
453 * handle the Warm Reset
455 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
456 "Compliance mode detected->port %d",
458 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
459 "Attempting compliance mode recovery");
460 hcd = xhci->shared_hcd;
462 if (hcd->state == HC_STATE_SUSPENDED)
463 usb_hcd_resume_root_hub(hcd);
465 usb_hcd_poll_rh_status(hcd);
469 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
470 mod_timer(&xhci->comp_mode_recovery_timer,
471 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
475 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
476 * that causes ports behind that hardware to enter compliance mode sometimes.
477 * The quirk creates a timer that polls every 2 seconds the link state of
478 * each host controller's port and recovers it by issuing a Warm reset
479 * if Compliance mode is detected, otherwise the port will become "dead" (no
480 * device connections or disconnections will be detected anymore). Becasue no
481 * status event is generated when entering compliance mode (per xhci spec),
482 * this quirk is needed on systems that have the failing hardware installed.
484 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
486 xhci->port_status_u0 = 0;
487 setup_timer(&xhci->comp_mode_recovery_timer,
488 compliance_mode_recovery, (unsigned long)xhci);
489 xhci->comp_mode_recovery_timer.expires = jiffies +
490 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
492 add_timer(&xhci->comp_mode_recovery_timer);
493 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
494 "Compliance mode recovery timer initialized");
498 * This function identifies the systems that have installed the SN65LVPE502CP
499 * USB3.0 re-driver and that need the Compliance Mode Quirk.
501 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
503 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
505 const char *dmi_product_name, *dmi_sys_vendor;
507 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
508 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
509 if (!dmi_product_name || !dmi_sys_vendor)
512 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
515 if (strstr(dmi_product_name, "Z420") ||
516 strstr(dmi_product_name, "Z620") ||
517 strstr(dmi_product_name, "Z820") ||
518 strstr(dmi_product_name, "Z1 Workstation"))
524 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
526 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
531 * Initialize memory for HCD and xHC (one-time init).
533 * Program the PAGESIZE register, initialize the device context array, create
534 * device contexts (?), set up a command ring segment (or two?), create event
535 * ring (one for now).
537 int xhci_init(struct usb_hcd *hcd)
539 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
542 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
543 spin_lock_init(&xhci->lock);
544 if (xhci->hci_version == 0x95 && link_quirk) {
545 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
546 "QUIRK: Not clearing Link TRB chain bits.");
547 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
549 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
550 "xHCI doesn't need link TRB QUIRK");
552 retval = xhci_mem_init(xhci, GFP_KERNEL);
553 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
555 /* Initializing Compliance Mode Recovery Data If Needed */
556 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
557 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
558 compliance_mode_recovery_timer_init(xhci);
564 /*-------------------------------------------------------------------------*/
567 static int xhci_run_finished(struct xhci_hcd *xhci)
569 if (xhci_start(xhci)) {
573 xhci->shared_hcd->state = HC_STATE_RUNNING;
574 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
576 if (xhci->quirks & XHCI_NEC_HOST)
577 xhci_ring_cmd_db(xhci);
579 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
580 "Finished xhci_run for USB3 roothub");
585 * Start the HC after it was halted.
587 * This function is called by the USB core when the HC driver is added.
588 * Its opposite is xhci_stop().
590 * xhci_init() must be called once before this function can be called.
591 * Reset the HC, enable device slot contexts, program DCBAAP, and
592 * set command ring pointer and event ring pointer.
594 * Setup MSI-X vectors and enable interrupts.
596 int xhci_run(struct usb_hcd *hcd)
601 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
603 /* Start the xHCI host controller running only after the USB 2.0 roothub
607 hcd->uses_new_polling = 1;
608 if (!usb_hcd_is_primary_hcd(hcd))
609 return xhci_run_finished(xhci);
611 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
613 ret = xhci_try_enable_msi(hcd);
617 xhci_dbg(xhci, "Command ring memory map follows:\n");
618 xhci_debug_ring(xhci, xhci->cmd_ring);
619 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
620 xhci_dbg_cmd_ptrs(xhci);
622 xhci_dbg(xhci, "ERST memory map follows:\n");
623 xhci_dbg_erst(xhci, &xhci->erst);
624 xhci_dbg(xhci, "Event ring:\n");
625 xhci_debug_ring(xhci, xhci->event_ring);
626 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
627 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
628 temp_64 &= ~ERST_PTR_MASK;
629 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
630 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
632 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
633 "// Set the interrupt modulation register");
634 temp = readl(&xhci->ir_set->irq_control);
635 temp &= ~ER_IRQ_INTERVAL_MASK;
637 * the increment interval is 8 times as much as that defined
638 * in xHCI spec on MTK's controller
640 temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
641 writel(temp, &xhci->ir_set->irq_control);
643 /* Set the HCD state before we enable the irqs */
644 temp = readl(&xhci->op_regs->command);
646 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
647 "// Enable interrupts, cmd = 0x%x.", temp);
648 writel(temp, &xhci->op_regs->command);
650 temp = readl(&xhci->ir_set->irq_pending);
651 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
652 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
653 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
654 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
655 xhci_print_ir_set(xhci, 0);
657 if (xhci->quirks & XHCI_NEC_HOST) {
658 struct xhci_command *command;
659 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
662 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
663 TRB_TYPE(TRB_NEC_GET_FW));
665 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
666 "Finished xhci_run for USB2 roothub");
669 EXPORT_SYMBOL_GPL(xhci_run);
674 * This function is called by the USB core when the HC driver is removed.
675 * Its opposite is xhci_run().
677 * Disable device contexts, disable IRQs, and quiesce the HC.
678 * Reset the HC, finish any completed transactions, and cleanup memory.
680 void xhci_stop(struct usb_hcd *hcd)
683 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
685 mutex_lock(&xhci->mutex);
687 if (!(xhci->xhc_state & XHCI_STATE_HALTED)) {
688 spin_lock_irq(&xhci->lock);
690 xhci->xhc_state |= XHCI_STATE_HALTED;
691 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
695 spin_unlock_irq(&xhci->lock);
698 if (!usb_hcd_is_primary_hcd(hcd)) {
699 mutex_unlock(&xhci->mutex);
703 xhci_cleanup_msix(xhci);
705 /* Deleting Compliance Mode Recovery Timer */
706 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
707 (!(xhci_all_ports_seen_u0(xhci)))) {
708 del_timer_sync(&xhci->comp_mode_recovery_timer);
709 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
710 "%s: compliance mode recovery timer deleted",
714 if (xhci->quirks & XHCI_AMD_PLL_FIX)
717 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
718 "// Disabling event ring interrupts");
719 temp = readl(&xhci->op_regs->status);
720 writel(temp & ~STS_EINT, &xhci->op_regs->status);
721 temp = readl(&xhci->ir_set->irq_pending);
722 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
723 xhci_print_ir_set(xhci, 0);
725 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
726 xhci_mem_cleanup(xhci);
727 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
728 "xhci_stop completed - status = %x",
729 readl(&xhci->op_regs->status));
730 mutex_unlock(&xhci->mutex);
734 * Shutdown HC (not bus-specific)
736 * This is called when the machine is rebooting or halting. We assume that the
737 * machine will be powered off, and the HC's internal state will be reset.
738 * Don't bother to free memory.
740 * This will only ever be called with the main usb_hcd (the USB3 roothub).
742 void xhci_shutdown(struct usb_hcd *hcd)
744 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
746 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
747 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
749 spin_lock_irq(&xhci->lock);
751 /* Workaround for spurious wakeups at shutdown with HSW */
752 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
754 spin_unlock_irq(&xhci->lock);
756 xhci_cleanup_msix(xhci);
758 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
759 "xhci_shutdown completed - status = %x",
760 readl(&xhci->op_regs->status));
762 EXPORT_SYMBOL_GPL(xhci_shutdown);
765 static void xhci_save_registers(struct xhci_hcd *xhci)
767 xhci->s3.command = readl(&xhci->op_regs->command);
768 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
769 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
770 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
771 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
772 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
773 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
774 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
775 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
778 static void xhci_restore_registers(struct xhci_hcd *xhci)
780 writel(xhci->s3.command, &xhci->op_regs->command);
781 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
782 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
783 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
784 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
785 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
786 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
787 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
788 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
791 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
795 /* step 2: initialize command ring buffer */
796 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
797 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
798 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
799 xhci->cmd_ring->dequeue) &
800 (u64) ~CMD_RING_RSVD_BITS) |
801 xhci->cmd_ring->cycle_state;
802 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
803 "// Setting command ring address to 0x%llx",
804 (long unsigned long) val_64);
805 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
809 * The whole command ring must be cleared to zero when we suspend the host.
811 * The host doesn't save the command ring pointer in the suspend well, so we
812 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
813 * aligned, because of the reserved bits in the command ring dequeue pointer
814 * register. Therefore, we can't just set the dequeue pointer back in the
815 * middle of the ring (TRBs are 16-byte aligned).
817 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
819 struct xhci_ring *ring;
820 struct xhci_segment *seg;
822 ring = xhci->cmd_ring;
826 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
827 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
828 cpu_to_le32(~TRB_CYCLE);
830 } while (seg != ring->deq_seg);
832 /* Reset the software enqueue and dequeue pointers */
833 ring->deq_seg = ring->first_seg;
834 ring->dequeue = ring->first_seg->trbs;
835 ring->enq_seg = ring->deq_seg;
836 ring->enqueue = ring->dequeue;
838 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
840 * Ring is now zeroed, so the HW should look for change of ownership
841 * when the cycle bit is set to 1.
843 ring->cycle_state = 1;
846 * Reset the hardware dequeue pointer.
847 * Yes, this will need to be re-written after resume, but we're paranoid
848 * and want to make sure the hardware doesn't access bogus memory
849 * because, say, the BIOS or an SMI started the host without changing
850 * the command ring pointers.
852 xhci_set_cmd_ring_deq(xhci);
855 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
858 __le32 __iomem **port_array;
862 spin_lock_irqsave(&xhci->lock, flags);
864 /* disble usb3 ports Wake bits*/
865 port_index = xhci->num_usb3_ports;
866 port_array = xhci->usb3_ports;
867 while (port_index--) {
868 t1 = readl(port_array[port_index]);
869 t1 = xhci_port_state_to_neutral(t1);
870 t2 = t1 & ~PORT_WAKE_BITS;
872 writel(t2, port_array[port_index]);
875 /* disble usb2 ports Wake bits*/
876 port_index = xhci->num_usb2_ports;
877 port_array = xhci->usb2_ports;
878 while (port_index--) {
879 t1 = readl(port_array[port_index]);
880 t1 = xhci_port_state_to_neutral(t1);
881 t2 = t1 & ~PORT_WAKE_BITS;
883 writel(t2, port_array[port_index]);
886 spin_unlock_irqrestore(&xhci->lock, flags);
889 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
891 __le32 __iomem **port_array;
896 status = readl(&xhci->op_regs->status);
897 if (status & STS_EINT)
900 * Checking STS_EINT is not enough as there is a lag between a change
901 * bit being set and the Port Status Change Event that it generated
902 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
905 port_index = xhci->num_usb2_ports;
906 port_array = xhci->usb2_ports;
907 while (port_index--) {
908 portsc = readl(port_array[port_index]);
909 if (portsc & PORT_CHANGE_MASK ||
910 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
913 port_index = xhci->num_usb3_ports;
914 port_array = xhci->usb3_ports;
915 while (port_index--) {
916 portsc = readl(port_array[port_index]);
917 if (portsc & PORT_CHANGE_MASK ||
918 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
925 * Stop HC (not bus-specific)
927 * This is called when the machine transition into S3/S4 mode.
930 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
933 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
934 struct usb_hcd *hcd = xhci_to_hcd(xhci);
940 if (hcd->state != HC_STATE_SUSPENDED ||
941 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
944 /* Clear root port wake on bits if wakeup not allowed. */
946 xhci_disable_port_wake_on_bits(xhci);
948 /* Don't poll the roothubs on bus suspend. */
949 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
950 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
951 del_timer_sync(&hcd->rh_timer);
952 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
953 del_timer_sync(&xhci->shared_hcd->rh_timer);
955 spin_lock_irq(&xhci->lock);
956 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
957 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
958 /* step 1: stop endpoint */
959 /* skipped assuming that port suspend has done */
961 /* step 2: clear Run/Stop bit */
962 command = readl(&xhci->op_regs->command);
964 writel(command, &xhci->op_regs->command);
966 /* Some chips from Fresco Logic need an extraordinary delay */
967 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
969 if (xhci_handshake(&xhci->op_regs->status,
970 STS_HALT, STS_HALT, delay)) {
971 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
972 spin_unlock_irq(&xhci->lock);
975 xhci_clear_command_ring(xhci);
977 /* step 3: save registers */
978 xhci_save_registers(xhci);
980 /* step 4: set CSS flag */
981 command = readl(&xhci->op_regs->command);
983 writel(command, &xhci->op_regs->command);
984 if (xhci_handshake(&xhci->op_regs->status,
985 STS_SAVE, 0, 20 * 1000)) {
986 xhci_warn(xhci, "WARN: xHC save state timeout\n");
987 spin_unlock_irq(&xhci->lock);
990 spin_unlock_irq(&xhci->lock);
993 * Deleting Compliance Mode Recovery Timer because the xHCI Host
994 * is about to be suspended.
996 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
997 (!(xhci_all_ports_seen_u0(xhci)))) {
998 del_timer_sync(&xhci->comp_mode_recovery_timer);
999 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1000 "%s: compliance mode recovery timer deleted",
1004 /* step 5: remove core well power */
1005 /* synchronize irq when using MSI-X */
1006 xhci_msix_sync_irqs(xhci);
1010 EXPORT_SYMBOL_GPL(xhci_suspend);
1013 * start xHC (not bus-specific)
1015 * This is called when the machine transition from S3/S4 mode.
1018 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1020 u32 command, temp = 0;
1021 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1022 struct usb_hcd *secondary_hcd;
1024 bool comp_timer_running = false;
1025 bool pending_portevent = false;
1030 /* Wait a bit if either of the roothubs need to settle from the
1031 * transition into bus suspend.
1033 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1034 time_before(jiffies,
1035 xhci->bus_state[1].next_statechange))
1038 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1039 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1041 spin_lock_irq(&xhci->lock);
1042 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1047 * Some controllers might lose power during suspend, so wait
1048 * for controller not ready bit to clear, just as in xHC init.
1050 retval = xhci_handshake(&xhci->op_regs->status,
1051 STS_CNR, 0, 10 * 1000 * 1000);
1053 xhci_warn(xhci, "Controller not ready at resume %d\n",
1055 spin_unlock_irq(&xhci->lock);
1058 /* step 1: restore register */
1059 xhci_restore_registers(xhci);
1060 /* step 2: initialize command ring buffer */
1061 xhci_set_cmd_ring_deq(xhci);
1062 /* step 3: restore state and start state*/
1063 /* step 3: set CRS flag */
1064 command = readl(&xhci->op_regs->command);
1066 writel(command, &xhci->op_regs->command);
1068 * Some controllers take up to 55+ ms to complete the controller
1069 * restore so setting the timeout to 100ms. Xhci specification
1070 * doesn't mention any timeout value.
1072 if (xhci_handshake(&xhci->op_regs->status,
1073 STS_RESTORE, 0, 100 * 1000)) {
1074 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1075 spin_unlock_irq(&xhci->lock);
1078 temp = readl(&xhci->op_regs->status);
1081 /* If restore operation fails, re-initialize the HC during resume */
1082 if ((temp & STS_SRE) || hibernated) {
1084 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1085 !(xhci_all_ports_seen_u0(xhci))) {
1086 del_timer_sync(&xhci->comp_mode_recovery_timer);
1087 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1088 "Compliance Mode Recovery Timer deleted!");
1091 /* Let the USB core know _both_ roothubs lost power. */
1092 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1093 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1095 xhci_dbg(xhci, "Stop HCD\n");
1098 spin_unlock_irq(&xhci->lock);
1099 xhci_cleanup_msix(xhci);
1101 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1102 temp = readl(&xhci->op_regs->status);
1103 writel(temp & ~STS_EINT, &xhci->op_regs->status);
1104 temp = readl(&xhci->ir_set->irq_pending);
1105 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1106 xhci_print_ir_set(xhci, 0);
1108 xhci_dbg(xhci, "cleaning up memory\n");
1109 xhci_mem_cleanup(xhci);
1110 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1111 readl(&xhci->op_regs->status));
1113 /* USB core calls the PCI reinit and start functions twice:
1114 * first with the primary HCD, and then with the secondary HCD.
1115 * If we don't do the same, the host will never be started.
1117 if (!usb_hcd_is_primary_hcd(hcd))
1118 secondary_hcd = hcd;
1120 secondary_hcd = xhci->shared_hcd;
1122 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1123 retval = xhci_init(hcd->primary_hcd);
1126 comp_timer_running = true;
1128 xhci_dbg(xhci, "Start the primary HCD\n");
1129 retval = xhci_run(hcd->primary_hcd);
1131 xhci_dbg(xhci, "Start the secondary HCD\n");
1132 retval = xhci_run(secondary_hcd);
1134 hcd->state = HC_STATE_SUSPENDED;
1135 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1139 /* step 4: set Run/Stop bit */
1140 command = readl(&xhci->op_regs->command);
1142 writel(command, &xhci->op_regs->command);
1143 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1146 /* step 5: walk topology and initialize portsc,
1147 * portpmsc and portli
1149 /* this is done in bus_resume */
1151 /* step 6: restart each of the previously
1152 * Running endpoints by ringing their doorbells
1155 spin_unlock_irq(&xhci->lock);
1160 * Resume roothubs only if there are pending events.
1161 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1162 * the first wake signalling failed, give it that chance.
1164 pending_portevent = xhci_pending_portevent(xhci);
1165 if (!pending_portevent) {
1167 pending_portevent = xhci_pending_portevent(xhci);
1170 if (pending_portevent) {
1171 usb_hcd_resume_root_hub(xhci->shared_hcd);
1172 usb_hcd_resume_root_hub(hcd);
1176 * If system is subject to the Quirk, Compliance Mode Timer needs to
1177 * be re-initialized Always after a system resume. Ports are subject
1178 * to suffer the Compliance Mode issue again. It doesn't matter if
1179 * ports have entered previously to U0 before system's suspension.
1181 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1182 compliance_mode_recovery_timer_init(xhci);
1184 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1185 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1187 /* Re-enable port polling. */
1188 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1189 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1190 usb_hcd_poll_rh_status(xhci->shared_hcd);
1191 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1192 usb_hcd_poll_rh_status(hcd);
1196 EXPORT_SYMBOL_GPL(xhci_resume);
1197 #endif /* CONFIG_PM */
1199 /*-------------------------------------------------------------------------*/
1202 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1203 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1204 * value to right shift 1 for the bitmask.
1206 * Index = (epnum * 2) + direction - 1,
1207 * where direction = 0 for OUT, 1 for IN.
1208 * For control endpoints, the IN index is used (OUT index is unused), so
1209 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1211 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1214 if (usb_endpoint_xfer_control(desc))
1215 index = (unsigned int) (usb_endpoint_num(desc)*2);
1217 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1218 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1222 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1223 * address from the XHCI endpoint index.
1225 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1227 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1228 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1229 return direction | number;
1232 /* Find the flag for this endpoint (for use in the control context). Use the
1233 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1236 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1238 return 1 << (xhci_get_endpoint_index(desc) + 1);
1241 /* Find the flag for this endpoint (for use in the control context). Use the
1242 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1245 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1247 return 1 << (ep_index + 1);
1250 /* Compute the last valid endpoint context index. Basically, this is the
1251 * endpoint index plus one. For slot contexts with more than valid endpoint,
1252 * we find the most significant bit set in the added contexts flags.
1253 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1254 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1256 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1258 return fls(added_ctxs) - 1;
1261 /* Returns 1 if the arguments are OK;
1262 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1264 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1265 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1267 struct xhci_hcd *xhci;
1268 struct xhci_virt_device *virt_dev;
1270 if (!hcd || (check_ep && !ep) || !udev) {
1271 pr_debug("xHCI %s called with invalid args\n", func);
1274 if (!udev->parent) {
1275 pr_debug("xHCI %s called for root hub\n", func);
1279 xhci = hcd_to_xhci(hcd);
1280 if (check_virt_dev) {
1281 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1282 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1287 virt_dev = xhci->devs[udev->slot_id];
1288 if (virt_dev->udev != udev) {
1289 xhci_dbg(xhci, "xHCI %s called with udev and "
1290 "virt_dev does not match\n", func);
1295 if (xhci->xhc_state & XHCI_STATE_HALTED)
1301 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1302 struct usb_device *udev, struct xhci_command *command,
1303 bool ctx_change, bool must_succeed);
1306 * Full speed devices may have a max packet size greater than 8 bytes, but the
1307 * USB core doesn't know that until it reads the first 8 bytes of the
1308 * descriptor. If the usb_device's max packet size changes after that point,
1309 * we need to issue an evaluate context command and wait on it.
1311 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1312 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1314 struct xhci_container_ctx *out_ctx;
1315 struct xhci_input_control_ctx *ctrl_ctx;
1316 struct xhci_ep_ctx *ep_ctx;
1317 struct xhci_command *command;
1318 int max_packet_size;
1319 int hw_max_packet_size;
1322 out_ctx = xhci->devs[slot_id]->out_ctx;
1323 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1324 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1325 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1326 if (hw_max_packet_size != max_packet_size) {
1327 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1328 "Max Packet Size for ep 0 changed.");
1329 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1330 "Max packet size in usb_device = %d",
1332 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1333 "Max packet size in xHCI HW = %d",
1334 hw_max_packet_size);
1335 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1336 "Issuing evaluate context command.");
1338 /* Set up the input context flags for the command */
1339 /* FIXME: This won't work if a non-default control endpoint
1340 * changes max packet sizes.
1343 command = xhci_alloc_command(xhci, false, true, mem_flags);
1347 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1348 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1350 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1353 goto command_cleanup;
1355 /* Set up the modified control endpoint 0 */
1356 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1357 xhci->devs[slot_id]->out_ctx, ep_index);
1359 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1360 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1361 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1362 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1364 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1365 ctrl_ctx->drop_flags = 0;
1367 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1368 xhci_dbg_ctx(xhci, command->in_ctx, ep_index);
1369 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1370 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1372 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1375 /* Clean up the input context for later use by bandwidth
1378 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1380 kfree(command->completion);
1387 * non-error returns are a promise to giveback() the urb later
1388 * we drop ownership so next owner (or urb unlink) can get it
1390 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1392 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1393 struct xhci_td *buffer;
1394 unsigned long flags;
1396 unsigned int slot_id, ep_index;
1397 struct urb_priv *urb_priv;
1400 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1401 true, true, __func__) <= 0)
1404 slot_id = urb->dev->slot_id;
1405 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1407 if (!HCD_HW_ACCESSIBLE(hcd)) {
1408 if (!in_interrupt())
1409 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1414 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1415 size = urb->number_of_packets;
1416 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1417 urb->transfer_buffer_length > 0 &&
1418 urb->transfer_flags & URB_ZERO_PACKET &&
1419 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1424 urb_priv = kzalloc(sizeof(struct urb_priv) +
1425 size * sizeof(struct xhci_td *), mem_flags);
1429 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1435 for (i = 0; i < size; i++) {
1436 urb_priv->td[i] = buffer;
1440 urb_priv->length = size;
1441 urb_priv->td_cnt = 0;
1442 urb->hcpriv = urb_priv;
1444 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1445 /* Check to see if the max packet size for the default control
1446 * endpoint changed during FS device enumeration
1448 if (urb->dev->speed == USB_SPEED_FULL) {
1449 ret = xhci_check_maxpacket(xhci, slot_id,
1450 ep_index, urb, mem_flags);
1452 xhci_urb_free_priv(urb_priv);
1458 /* We have a spinlock and interrupts disabled, so we must pass
1459 * atomic context to this function, which may allocate memory.
1461 spin_lock_irqsave(&xhci->lock, flags);
1462 if (xhci->xhc_state & XHCI_STATE_DYING)
1464 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1468 spin_unlock_irqrestore(&xhci->lock, flags);
1469 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1470 spin_lock_irqsave(&xhci->lock, flags);
1471 if (xhci->xhc_state & XHCI_STATE_DYING)
1473 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1474 EP_GETTING_STREAMS) {
1475 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1476 "is transitioning to using streams.\n");
1478 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1479 EP_GETTING_NO_STREAMS) {
1480 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1481 "is transitioning to "
1482 "not having streams.\n");
1485 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1490 spin_unlock_irqrestore(&xhci->lock, flags);
1491 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1492 spin_lock_irqsave(&xhci->lock, flags);
1493 if (xhci->xhc_state & XHCI_STATE_DYING)
1495 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1499 spin_unlock_irqrestore(&xhci->lock, flags);
1501 spin_lock_irqsave(&xhci->lock, flags);
1502 if (xhci->xhc_state & XHCI_STATE_DYING)
1504 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1508 spin_unlock_irqrestore(&xhci->lock, flags);
1513 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1514 "non-responsive xHCI host.\n",
1515 urb->ep->desc.bEndpointAddress, urb);
1518 xhci_urb_free_priv(urb_priv);
1520 spin_unlock_irqrestore(&xhci->lock, flags);
1525 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1526 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1527 * should pick up where it left off in the TD, unless a Set Transfer Ring
1528 * Dequeue Pointer is issued.
1530 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1531 * the ring. Since the ring is a contiguous structure, they can't be physically
1532 * removed. Instead, there are two options:
1534 * 1) If the HC is in the middle of processing the URB to be canceled, we
1535 * simply move the ring's dequeue pointer past those TRBs using the Set
1536 * Transfer Ring Dequeue Pointer command. This will be the common case,
1537 * when drivers timeout on the last submitted URB and attempt to cancel.
1539 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1540 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1541 * HC will need to invalidate the any TRBs it has cached after the stop
1542 * endpoint command, as noted in the xHCI 0.95 errata.
1544 * 3) The TD may have completed by the time the Stop Endpoint Command
1545 * completes, so software needs to handle that case too.
1547 * This function should protect against the TD enqueueing code ringing the
1548 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1549 * It also needs to account for multiple cancellations on happening at the same
1550 * time for the same endpoint.
1552 * Note that this function can be called in any context, or so says
1553 * usb_hcd_unlink_urb()
1555 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1557 unsigned long flags;
1560 struct xhci_hcd *xhci;
1561 struct urb_priv *urb_priv;
1563 unsigned int ep_index;
1564 struct xhci_ring *ep_ring;
1565 struct xhci_virt_ep *ep;
1566 struct xhci_command *command;
1568 xhci = hcd_to_xhci(hcd);
1569 spin_lock_irqsave(&xhci->lock, flags);
1570 /* Make sure the URB hasn't completed or been unlinked already */
1571 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1572 if (ret || !urb->hcpriv)
1574 temp = readl(&xhci->op_regs->status);
1575 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1576 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1577 "HW died, freeing TD.");
1578 urb_priv = urb->hcpriv;
1579 for (i = urb_priv->td_cnt;
1580 i < urb_priv->length && xhci->devs[urb->dev->slot_id];
1582 td = urb_priv->td[i];
1583 if (!list_empty(&td->td_list))
1584 list_del_init(&td->td_list);
1585 if (!list_empty(&td->cancelled_td_list))
1586 list_del_init(&td->cancelled_td_list);
1589 usb_hcd_unlink_urb_from_ep(hcd, urb);
1590 spin_unlock_irqrestore(&xhci->lock, flags);
1591 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1592 xhci_urb_free_priv(urb_priv);
1596 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1597 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1598 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1604 urb_priv = urb->hcpriv;
1605 i = urb_priv->td_cnt;
1606 if (i < urb_priv->length)
1607 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1608 "Cancel URB %p, dev %s, ep 0x%x, "
1609 "starting at offset 0x%llx",
1610 urb, urb->dev->devpath,
1611 urb->ep->desc.bEndpointAddress,
1612 (unsigned long long) xhci_trb_virt_to_dma(
1613 urb_priv->td[i]->start_seg,
1614 urb_priv->td[i]->first_trb));
1616 for (; i < urb_priv->length; i++) {
1617 td = urb_priv->td[i];
1618 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1621 /* Queue a stop endpoint command, but only if this is
1622 * the first cancellation to be handled.
1624 if (!(ep->ep_state & EP_HALT_PENDING)) {
1625 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1630 ep->ep_state |= EP_HALT_PENDING;
1631 ep->stop_cmds_pending++;
1632 ep->stop_cmd_timer.expires = jiffies +
1633 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1634 add_timer(&ep->stop_cmd_timer);
1635 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1637 xhci_ring_cmd_db(xhci);
1640 spin_unlock_irqrestore(&xhci->lock, flags);
1644 /* Drop an endpoint from a new bandwidth configuration for this device.
1645 * Only one call to this function is allowed per endpoint before
1646 * check_bandwidth() or reset_bandwidth() must be called.
1647 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1648 * add the endpoint to the schedule with possibly new parameters denoted by a
1649 * different endpoint descriptor in usb_host_endpoint.
1650 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1653 * The USB core will not allow URBs to be queued to an endpoint that is being
1654 * disabled, so there's no need for mutual exclusion to protect
1655 * the xhci->devs[slot_id] structure.
1657 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1658 struct usb_host_endpoint *ep)
1660 struct xhci_hcd *xhci;
1661 struct xhci_container_ctx *in_ctx, *out_ctx;
1662 struct xhci_input_control_ctx *ctrl_ctx;
1663 unsigned int ep_index;
1664 struct xhci_ep_ctx *ep_ctx;
1666 u32 new_add_flags, new_drop_flags;
1669 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1672 xhci = hcd_to_xhci(hcd);
1673 if (xhci->xhc_state & XHCI_STATE_DYING)
1676 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1677 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1678 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1679 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1680 __func__, drop_flag);
1684 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1685 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1686 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1688 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1693 ep_index = xhci_get_endpoint_index(&ep->desc);
1694 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1695 /* If the HC already knows the endpoint is disabled,
1696 * or the HCD has noted it is disabled, ignore this request
1698 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1699 cpu_to_le32(EP_STATE_DISABLED)) ||
1700 le32_to_cpu(ctrl_ctx->drop_flags) &
1701 xhci_get_endpoint_flag(&ep->desc)) {
1702 /* Do not warn when called after a usb_device_reset */
1703 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1704 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1709 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1710 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1712 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1713 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1715 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1717 if (xhci->quirks & XHCI_MTK_HOST)
1718 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1720 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1721 (unsigned int) ep->desc.bEndpointAddress,
1723 (unsigned int) new_drop_flags,
1724 (unsigned int) new_add_flags);
1728 /* Add an endpoint to a new possible bandwidth configuration for this device.
1729 * Only one call to this function is allowed per endpoint before
1730 * check_bandwidth() or reset_bandwidth() must be called.
1731 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1732 * add the endpoint to the schedule with possibly new parameters denoted by a
1733 * different endpoint descriptor in usb_host_endpoint.
1734 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1737 * The USB core will not allow URBs to be queued to an endpoint until the
1738 * configuration or alt setting is installed in the device, so there's no need
1739 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1741 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1742 struct usb_host_endpoint *ep)
1744 struct xhci_hcd *xhci;
1745 struct xhci_container_ctx *in_ctx;
1746 unsigned int ep_index;
1747 struct xhci_input_control_ctx *ctrl_ctx;
1749 u32 new_add_flags, new_drop_flags;
1750 struct xhci_virt_device *virt_dev;
1753 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1755 /* So we won't queue a reset ep command for a root hub */
1759 xhci = hcd_to_xhci(hcd);
1760 if (xhci->xhc_state & XHCI_STATE_DYING)
1763 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1764 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1765 /* FIXME when we have to issue an evaluate endpoint command to
1766 * deal with ep0 max packet size changing once we get the
1769 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1770 __func__, added_ctxs);
1774 virt_dev = xhci->devs[udev->slot_id];
1775 in_ctx = virt_dev->in_ctx;
1776 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1778 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1783 ep_index = xhci_get_endpoint_index(&ep->desc);
1784 /* If this endpoint is already in use, and the upper layers are trying
1785 * to add it again without dropping it, reject the addition.
1787 if (virt_dev->eps[ep_index].ring &&
1788 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1789 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1790 "without dropping it.\n",
1791 (unsigned int) ep->desc.bEndpointAddress);
1795 /* If the HCD has already noted the endpoint is enabled,
1796 * ignore this request.
1798 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1799 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1805 * Configuration and alternate setting changes must be done in
1806 * process context, not interrupt context (or so documenation
1807 * for usb_set_interface() and usb_set_configuration() claim).
1809 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1810 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1811 __func__, ep->desc.bEndpointAddress);
1815 if (xhci->quirks & XHCI_MTK_HOST) {
1816 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1818 xhci_free_or_cache_endpoint_ring(xhci,
1819 virt_dev, ep_index);
1824 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1825 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1827 /* If xhci_endpoint_disable() was called for this endpoint, but the
1828 * xHC hasn't been notified yet through the check_bandwidth() call,
1829 * this re-adds a new state for the endpoint from the new endpoint
1830 * descriptors. We must drop and re-add this endpoint, so we leave the
1833 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1835 /* Store the usb_device pointer for later use */
1838 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1839 (unsigned int) ep->desc.bEndpointAddress,
1841 (unsigned int) new_drop_flags,
1842 (unsigned int) new_add_flags);
1846 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1848 struct xhci_input_control_ctx *ctrl_ctx;
1849 struct xhci_ep_ctx *ep_ctx;
1850 struct xhci_slot_ctx *slot_ctx;
1853 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1855 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1860 /* When a device's add flag and drop flag are zero, any subsequent
1861 * configure endpoint command will leave that endpoint's state
1862 * untouched. Make sure we don't leave any old state in the input
1863 * endpoint contexts.
1865 ctrl_ctx->drop_flags = 0;
1866 ctrl_ctx->add_flags = 0;
1867 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1868 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1869 /* Endpoint 0 is always valid */
1870 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1871 for (i = 1; i < 31; ++i) {
1872 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1873 ep_ctx->ep_info = 0;
1874 ep_ctx->ep_info2 = 0;
1876 ep_ctx->tx_info = 0;
1880 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1881 struct usb_device *udev, u32 *cmd_status)
1885 switch (*cmd_status) {
1886 case COMP_CMD_ABORT:
1888 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1892 dev_warn(&udev->dev,
1893 "Not enough host controller resources for new device state.\n");
1895 /* FIXME: can we allocate more resources for the HC? */
1898 case COMP_2ND_BW_ERR:
1899 dev_warn(&udev->dev,
1900 "Not enough bandwidth for new device state.\n");
1902 /* FIXME: can we go back to the old state? */
1905 /* the HCD set up something wrong */
1906 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1908 "and endpoint is not disabled.\n");
1912 dev_warn(&udev->dev,
1913 "ERROR: Incompatible device for endpoint configure command.\n");
1917 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1918 "Successful Endpoint Configure command");
1922 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1930 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1931 struct usb_device *udev, u32 *cmd_status)
1934 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1936 switch (*cmd_status) {
1937 case COMP_CMD_ABORT:
1939 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1943 dev_warn(&udev->dev,
1944 "WARN: xHCI driver setup invalid evaluate context command.\n");
1948 dev_warn(&udev->dev,
1949 "WARN: slot not enabled for evaluate context command.\n");
1952 case COMP_CTX_STATE:
1953 dev_warn(&udev->dev,
1954 "WARN: invalid context state for evaluate context command.\n");
1955 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1959 dev_warn(&udev->dev,
1960 "ERROR: Incompatible device for evaluate context command.\n");
1964 /* Max Exit Latency too large error */
1965 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1969 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1970 "Successful evaluate context command");
1974 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1982 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1983 struct xhci_input_control_ctx *ctrl_ctx)
1985 u32 valid_add_flags;
1986 u32 valid_drop_flags;
1988 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1989 * (bit 1). The default control endpoint is added during the Address
1990 * Device command and is never removed until the slot is disabled.
1992 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1993 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1995 /* Use hweight32 to count the number of ones in the add flags, or
1996 * number of endpoints added. Don't count endpoints that are changed
1997 * (both added and dropped).
1999 return hweight32(valid_add_flags) -
2000 hweight32(valid_add_flags & valid_drop_flags);
2003 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2004 struct xhci_input_control_ctx *ctrl_ctx)
2006 u32 valid_add_flags;
2007 u32 valid_drop_flags;
2009 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2010 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2012 return hweight32(valid_drop_flags) -
2013 hweight32(valid_add_flags & valid_drop_flags);
2017 * We need to reserve the new number of endpoints before the configure endpoint
2018 * command completes. We can't subtract the dropped endpoints from the number
2019 * of active endpoints until the command completes because we can oversubscribe
2020 * the host in this case:
2022 * - the first configure endpoint command drops more endpoints than it adds
2023 * - a second configure endpoint command that adds more endpoints is queued
2024 * - the first configure endpoint command fails, so the config is unchanged
2025 * - the second command may succeed, even though there isn't enough resources
2027 * Must be called with xhci->lock held.
2029 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2030 struct xhci_input_control_ctx *ctrl_ctx)
2034 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2035 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2036 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2037 "Not enough ep ctxs: "
2038 "%u active, need to add %u, limit is %u.",
2039 xhci->num_active_eps, added_eps,
2040 xhci->limit_active_eps);
2043 xhci->num_active_eps += added_eps;
2044 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2045 "Adding %u ep ctxs, %u now active.", added_eps,
2046 xhci->num_active_eps);
2051 * The configure endpoint was failed by the xHC for some other reason, so we
2052 * need to revert the resources that failed configuration would have used.
2054 * Must be called with xhci->lock held.
2056 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2057 struct xhci_input_control_ctx *ctrl_ctx)
2061 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2062 xhci->num_active_eps -= num_failed_eps;
2063 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2064 "Removing %u failed ep ctxs, %u now active.",
2066 xhci->num_active_eps);
2070 * Now that the command has completed, clean up the active endpoint count by
2071 * subtracting out the endpoints that were dropped (but not changed).
2073 * Must be called with xhci->lock held.
2075 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2076 struct xhci_input_control_ctx *ctrl_ctx)
2078 u32 num_dropped_eps;
2080 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2081 xhci->num_active_eps -= num_dropped_eps;
2082 if (num_dropped_eps)
2083 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2084 "Removing %u dropped ep ctxs, %u now active.",
2086 xhci->num_active_eps);
2089 static unsigned int xhci_get_block_size(struct usb_device *udev)
2091 switch (udev->speed) {
2093 case USB_SPEED_FULL:
2095 case USB_SPEED_HIGH:
2097 case USB_SPEED_SUPER:
2098 case USB_SPEED_SUPER_PLUS:
2100 case USB_SPEED_UNKNOWN:
2101 case USB_SPEED_WIRELESS:
2103 /* Should never happen */
2109 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2111 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2113 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2118 /* If we are changing a LS/FS device under a HS hub,
2119 * make sure (if we are activating a new TT) that the HS bus has enough
2120 * bandwidth for this new TT.
2122 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2123 struct xhci_virt_device *virt_dev,
2126 struct xhci_interval_bw_table *bw_table;
2127 struct xhci_tt_bw_info *tt_info;
2129 /* Find the bandwidth table for the root port this TT is attached to. */
2130 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2131 tt_info = virt_dev->tt_info;
2132 /* If this TT already had active endpoints, the bandwidth for this TT
2133 * has already been added. Removing all periodic endpoints (and thus
2134 * making the TT enactive) will only decrease the bandwidth used.
2138 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2139 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2143 /* Not sure why we would have no new active endpoints...
2145 * Maybe because of an Evaluate Context change for a hub update or a
2146 * control endpoint 0 max packet size change?
2147 * FIXME: skip the bandwidth calculation in that case.
2152 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2153 struct xhci_virt_device *virt_dev)
2155 unsigned int bw_reserved;
2157 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2158 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2161 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2162 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2169 * This algorithm is a very conservative estimate of the worst-case scheduling
2170 * scenario for any one interval. The hardware dynamically schedules the
2171 * packets, so we can't tell which microframe could be the limiting factor in
2172 * the bandwidth scheduling. This only takes into account periodic endpoints.
2174 * Obviously, we can't solve an NP complete problem to find the minimum worst
2175 * case scenario. Instead, we come up with an estimate that is no less than
2176 * the worst case bandwidth used for any one microframe, but may be an
2179 * We walk the requirements for each endpoint by interval, starting with the
2180 * smallest interval, and place packets in the schedule where there is only one
2181 * possible way to schedule packets for that interval. In order to simplify
2182 * this algorithm, we record the largest max packet size for each interval, and
2183 * assume all packets will be that size.
2185 * For interval 0, we obviously must schedule all packets for each interval.
2186 * The bandwidth for interval 0 is just the amount of data to be transmitted
2187 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2188 * the number of packets).
2190 * For interval 1, we have two possible microframes to schedule those packets
2191 * in. For this algorithm, if we can schedule the same number of packets for
2192 * each possible scheduling opportunity (each microframe), we will do so. The
2193 * remaining number of packets will be saved to be transmitted in the gaps in
2194 * the next interval's scheduling sequence.
2196 * As we move those remaining packets to be scheduled with interval 2 packets,
2197 * we have to double the number of remaining packets to transmit. This is
2198 * because the intervals are actually powers of 2, and we would be transmitting
2199 * the previous interval's packets twice in this interval. We also have to be
2200 * sure that when we look at the largest max packet size for this interval, we
2201 * also look at the largest max packet size for the remaining packets and take
2202 * the greater of the two.
2204 * The algorithm continues to evenly distribute packets in each scheduling
2205 * opportunity, and push the remaining packets out, until we get to the last
2206 * interval. Then those packets and their associated overhead are just added
2207 * to the bandwidth used.
2209 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2210 struct xhci_virt_device *virt_dev,
2213 unsigned int bw_reserved;
2214 unsigned int max_bandwidth;
2215 unsigned int bw_used;
2216 unsigned int block_size;
2217 struct xhci_interval_bw_table *bw_table;
2218 unsigned int packet_size = 0;
2219 unsigned int overhead = 0;
2220 unsigned int packets_transmitted = 0;
2221 unsigned int packets_remaining = 0;
2224 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2225 return xhci_check_ss_bw(xhci, virt_dev);
2227 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2228 max_bandwidth = HS_BW_LIMIT;
2229 /* Convert percent of bus BW reserved to blocks reserved */
2230 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2232 max_bandwidth = FS_BW_LIMIT;
2233 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2236 bw_table = virt_dev->bw_table;
2237 /* We need to translate the max packet size and max ESIT payloads into
2238 * the units the hardware uses.
2240 block_size = xhci_get_block_size(virt_dev->udev);
2242 /* If we are manipulating a LS/FS device under a HS hub, double check
2243 * that the HS bus has enough bandwidth if we are activing a new TT.
2245 if (virt_dev->tt_info) {
2246 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2247 "Recalculating BW for rootport %u",
2248 virt_dev->real_port);
2249 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2250 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2251 "newly activated TT.\n");
2254 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2255 "Recalculating BW for TT slot %u port %u",
2256 virt_dev->tt_info->slot_id,
2257 virt_dev->tt_info->ttport);
2259 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2260 "Recalculating BW for rootport %u",
2261 virt_dev->real_port);
2264 /* Add in how much bandwidth will be used for interval zero, or the
2265 * rounded max ESIT payload + number of packets * largest overhead.
2267 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2268 bw_table->interval_bw[0].num_packets *
2269 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2271 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2272 unsigned int bw_added;
2273 unsigned int largest_mps;
2274 unsigned int interval_overhead;
2277 * How many packets could we transmit in this interval?
2278 * If packets didn't fit in the previous interval, we will need
2279 * to transmit that many packets twice within this interval.
2281 packets_remaining = 2 * packets_remaining +
2282 bw_table->interval_bw[i].num_packets;
2284 /* Find the largest max packet size of this or the previous
2287 if (list_empty(&bw_table->interval_bw[i].endpoints))
2290 struct xhci_virt_ep *virt_ep;
2291 struct list_head *ep_entry;
2293 ep_entry = bw_table->interval_bw[i].endpoints.next;
2294 virt_ep = list_entry(ep_entry,
2295 struct xhci_virt_ep, bw_endpoint_list);
2296 /* Convert to blocks, rounding up */
2297 largest_mps = DIV_ROUND_UP(
2298 virt_ep->bw_info.max_packet_size,
2301 if (largest_mps > packet_size)
2302 packet_size = largest_mps;
2304 /* Use the larger overhead of this or the previous interval. */
2305 interval_overhead = xhci_get_largest_overhead(
2306 &bw_table->interval_bw[i]);
2307 if (interval_overhead > overhead)
2308 overhead = interval_overhead;
2310 /* How many packets can we evenly distribute across
2311 * (1 << (i + 1)) possible scheduling opportunities?
2313 packets_transmitted = packets_remaining >> (i + 1);
2315 /* Add in the bandwidth used for those scheduled packets */
2316 bw_added = packets_transmitted * (overhead + packet_size);
2318 /* How many packets do we have remaining to transmit? */
2319 packets_remaining = packets_remaining % (1 << (i + 1));
2321 /* What largest max packet size should those packets have? */
2322 /* If we've transmitted all packets, don't carry over the
2323 * largest packet size.
2325 if (packets_remaining == 0) {
2328 } else if (packets_transmitted > 0) {
2329 /* Otherwise if we do have remaining packets, and we've
2330 * scheduled some packets in this interval, take the
2331 * largest max packet size from endpoints with this
2334 packet_size = largest_mps;
2335 overhead = interval_overhead;
2337 /* Otherwise carry over packet_size and overhead from the last
2338 * time we had a remainder.
2340 bw_used += bw_added;
2341 if (bw_used > max_bandwidth) {
2342 xhci_warn(xhci, "Not enough bandwidth. "
2343 "Proposed: %u, Max: %u\n",
2344 bw_used, max_bandwidth);
2349 * Ok, we know we have some packets left over after even-handedly
2350 * scheduling interval 15. We don't know which microframes they will
2351 * fit into, so we over-schedule and say they will be scheduled every
2354 if (packets_remaining > 0)
2355 bw_used += overhead + packet_size;
2357 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2358 unsigned int port_index = virt_dev->real_port - 1;
2360 /* OK, we're manipulating a HS device attached to a
2361 * root port bandwidth domain. Include the number of active TTs
2362 * in the bandwidth used.
2364 bw_used += TT_HS_OVERHEAD *
2365 xhci->rh_bw[port_index].num_active_tts;
2368 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2369 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2370 "Available: %u " "percent",
2371 bw_used, max_bandwidth, bw_reserved,
2372 (max_bandwidth - bw_used - bw_reserved) * 100 /
2375 bw_used += bw_reserved;
2376 if (bw_used > max_bandwidth) {
2377 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2378 bw_used, max_bandwidth);
2382 bw_table->bw_used = bw_used;
2386 static bool xhci_is_async_ep(unsigned int ep_type)
2388 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2389 ep_type != ISOC_IN_EP &&
2390 ep_type != INT_IN_EP);
2393 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2395 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2398 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2400 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2402 if (ep_bw->ep_interval == 0)
2403 return SS_OVERHEAD_BURST +
2404 (ep_bw->mult * ep_bw->num_packets *
2405 (SS_OVERHEAD + mps));
2406 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2407 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2408 1 << ep_bw->ep_interval);
2412 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2413 struct xhci_bw_info *ep_bw,
2414 struct xhci_interval_bw_table *bw_table,
2415 struct usb_device *udev,
2416 struct xhci_virt_ep *virt_ep,
2417 struct xhci_tt_bw_info *tt_info)
2419 struct xhci_interval_bw *interval_bw;
2420 int normalized_interval;
2422 if (xhci_is_async_ep(ep_bw->type))
2425 if (udev->speed >= USB_SPEED_SUPER) {
2426 if (xhci_is_sync_in_ep(ep_bw->type))
2427 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2428 xhci_get_ss_bw_consumed(ep_bw);
2430 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2431 xhci_get_ss_bw_consumed(ep_bw);
2435 /* SuperSpeed endpoints never get added to intervals in the table, so
2436 * this check is only valid for HS/FS/LS devices.
2438 if (list_empty(&virt_ep->bw_endpoint_list))
2440 /* For LS/FS devices, we need to translate the interval expressed in
2441 * microframes to frames.
2443 if (udev->speed == USB_SPEED_HIGH)
2444 normalized_interval = ep_bw->ep_interval;
2446 normalized_interval = ep_bw->ep_interval - 3;
2448 if (normalized_interval == 0)
2449 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2450 interval_bw = &bw_table->interval_bw[normalized_interval];
2451 interval_bw->num_packets -= ep_bw->num_packets;
2452 switch (udev->speed) {
2454 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2456 case USB_SPEED_FULL:
2457 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2459 case USB_SPEED_HIGH:
2460 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2462 case USB_SPEED_SUPER:
2463 case USB_SPEED_SUPER_PLUS:
2464 case USB_SPEED_UNKNOWN:
2465 case USB_SPEED_WIRELESS:
2466 /* Should never happen because only LS/FS/HS endpoints will get
2467 * added to the endpoint list.
2472 tt_info->active_eps -= 1;
2473 list_del_init(&virt_ep->bw_endpoint_list);
2476 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2477 struct xhci_bw_info *ep_bw,
2478 struct xhci_interval_bw_table *bw_table,
2479 struct usb_device *udev,
2480 struct xhci_virt_ep *virt_ep,
2481 struct xhci_tt_bw_info *tt_info)
2483 struct xhci_interval_bw *interval_bw;
2484 struct xhci_virt_ep *smaller_ep;
2485 int normalized_interval;
2487 if (xhci_is_async_ep(ep_bw->type))
2490 if (udev->speed == USB_SPEED_SUPER) {
2491 if (xhci_is_sync_in_ep(ep_bw->type))
2492 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2493 xhci_get_ss_bw_consumed(ep_bw);
2495 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2496 xhci_get_ss_bw_consumed(ep_bw);
2500 /* For LS/FS devices, we need to translate the interval expressed in
2501 * microframes to frames.
2503 if (udev->speed == USB_SPEED_HIGH)
2504 normalized_interval = ep_bw->ep_interval;
2506 normalized_interval = ep_bw->ep_interval - 3;
2508 if (normalized_interval == 0)
2509 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2510 interval_bw = &bw_table->interval_bw[normalized_interval];
2511 interval_bw->num_packets += ep_bw->num_packets;
2512 switch (udev->speed) {
2514 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2516 case USB_SPEED_FULL:
2517 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2519 case USB_SPEED_HIGH:
2520 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2522 case USB_SPEED_SUPER:
2523 case USB_SPEED_SUPER_PLUS:
2524 case USB_SPEED_UNKNOWN:
2525 case USB_SPEED_WIRELESS:
2526 /* Should never happen because only LS/FS/HS endpoints will get
2527 * added to the endpoint list.
2533 tt_info->active_eps += 1;
2534 /* Insert the endpoint into the list, largest max packet size first. */
2535 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2537 if (ep_bw->max_packet_size >=
2538 smaller_ep->bw_info.max_packet_size) {
2539 /* Add the new ep before the smaller endpoint */
2540 list_add_tail(&virt_ep->bw_endpoint_list,
2541 &smaller_ep->bw_endpoint_list);
2545 /* Add the new endpoint at the end of the list. */
2546 list_add_tail(&virt_ep->bw_endpoint_list,
2547 &interval_bw->endpoints);
2550 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2551 struct xhci_virt_device *virt_dev,
2554 struct xhci_root_port_bw_info *rh_bw_info;
2555 if (!virt_dev->tt_info)
2558 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2559 if (old_active_eps == 0 &&
2560 virt_dev->tt_info->active_eps != 0) {
2561 rh_bw_info->num_active_tts += 1;
2562 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2563 } else if (old_active_eps != 0 &&
2564 virt_dev->tt_info->active_eps == 0) {
2565 rh_bw_info->num_active_tts -= 1;
2566 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2570 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2571 struct xhci_virt_device *virt_dev,
2572 struct xhci_container_ctx *in_ctx)
2574 struct xhci_bw_info ep_bw_info[31];
2576 struct xhci_input_control_ctx *ctrl_ctx;
2577 int old_active_eps = 0;
2579 if (virt_dev->tt_info)
2580 old_active_eps = virt_dev->tt_info->active_eps;
2582 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2584 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2589 for (i = 0; i < 31; i++) {
2590 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2593 /* Make a copy of the BW info in case we need to revert this */
2594 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2595 sizeof(ep_bw_info[i]));
2596 /* Drop the endpoint from the interval table if the endpoint is
2597 * being dropped or changed.
2599 if (EP_IS_DROPPED(ctrl_ctx, i))
2600 xhci_drop_ep_from_interval_table(xhci,
2601 &virt_dev->eps[i].bw_info,
2607 /* Overwrite the information stored in the endpoints' bw_info */
2608 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2609 for (i = 0; i < 31; i++) {
2610 /* Add any changed or added endpoints to the interval table */
2611 if (EP_IS_ADDED(ctrl_ctx, i))
2612 xhci_add_ep_to_interval_table(xhci,
2613 &virt_dev->eps[i].bw_info,
2620 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2621 /* Ok, this fits in the bandwidth we have.
2622 * Update the number of active TTs.
2624 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2628 /* We don't have enough bandwidth for this, revert the stored info. */
2629 for (i = 0; i < 31; i++) {
2630 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2633 /* Drop the new copies of any added or changed endpoints from
2634 * the interval table.
2636 if (EP_IS_ADDED(ctrl_ctx, i)) {
2637 xhci_drop_ep_from_interval_table(xhci,
2638 &virt_dev->eps[i].bw_info,
2644 /* Revert the endpoint back to its old information */
2645 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2646 sizeof(ep_bw_info[i]));
2647 /* Add any changed or dropped endpoints back into the table */
2648 if (EP_IS_DROPPED(ctrl_ctx, i))
2649 xhci_add_ep_to_interval_table(xhci,
2650 &virt_dev->eps[i].bw_info,
2660 /* Issue a configure endpoint command or evaluate context command
2661 * and wait for it to finish.
2663 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2664 struct usb_device *udev,
2665 struct xhci_command *command,
2666 bool ctx_change, bool must_succeed)
2669 unsigned long flags;
2670 struct xhci_input_control_ctx *ctrl_ctx;
2671 struct xhci_virt_device *virt_dev;
2676 spin_lock_irqsave(&xhci->lock, flags);
2677 virt_dev = xhci->devs[udev->slot_id];
2679 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2681 spin_unlock_irqrestore(&xhci->lock, flags);
2682 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2687 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2688 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2689 spin_unlock_irqrestore(&xhci->lock, flags);
2690 xhci_warn(xhci, "Not enough host resources, "
2691 "active endpoint contexts = %u\n",
2692 xhci->num_active_eps);
2695 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2696 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2697 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2698 xhci_free_host_resources(xhci, ctrl_ctx);
2699 spin_unlock_irqrestore(&xhci->lock, flags);
2700 xhci_warn(xhci, "Not enough bandwidth\n");
2705 ret = xhci_queue_configure_endpoint(xhci, command,
2706 command->in_ctx->dma,
2707 udev->slot_id, must_succeed);
2709 ret = xhci_queue_evaluate_context(xhci, command,
2710 command->in_ctx->dma,
2711 udev->slot_id, must_succeed);
2713 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2714 xhci_free_host_resources(xhci, ctrl_ctx);
2715 spin_unlock_irqrestore(&xhci->lock, flags);
2716 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2717 "FIXME allocate a new ring segment");
2720 xhci_ring_cmd_db(xhci);
2721 spin_unlock_irqrestore(&xhci->lock, flags);
2723 /* Wait for the configure endpoint command to complete */
2724 wait_for_completion(command->completion);
2727 ret = xhci_configure_endpoint_result(xhci, udev,
2730 ret = xhci_evaluate_context_result(xhci, udev,
2733 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2734 spin_lock_irqsave(&xhci->lock, flags);
2735 /* If the command failed, remove the reserved resources.
2736 * Otherwise, clean up the estimate to include dropped eps.
2739 xhci_free_host_resources(xhci, ctrl_ctx);
2741 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2742 spin_unlock_irqrestore(&xhci->lock, flags);
2747 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2748 struct xhci_virt_device *vdev, int i)
2750 struct xhci_virt_ep *ep = &vdev->eps[i];
2752 if (ep->ep_state & EP_HAS_STREAMS) {
2753 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2754 xhci_get_endpoint_address(i));
2755 xhci_free_stream_info(xhci, ep->stream_info);
2756 ep->stream_info = NULL;
2757 ep->ep_state &= ~EP_HAS_STREAMS;
2761 /* Called after one or more calls to xhci_add_endpoint() or
2762 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2763 * to call xhci_reset_bandwidth().
2765 * Since we are in the middle of changing either configuration or
2766 * installing a new alt setting, the USB core won't allow URBs to be
2767 * enqueued for any endpoint on the old config or interface. Nothing
2768 * else should be touching the xhci->devs[slot_id] structure, so we
2769 * don't need to take the xhci->lock for manipulating that.
2771 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2775 struct xhci_hcd *xhci;
2776 struct xhci_virt_device *virt_dev;
2777 struct xhci_input_control_ctx *ctrl_ctx;
2778 struct xhci_slot_ctx *slot_ctx;
2779 struct xhci_command *command;
2781 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2784 xhci = hcd_to_xhci(hcd);
2785 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2786 (xhci->xhc_state & XHCI_STATE_REMOVING))
2789 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2790 virt_dev = xhci->devs[udev->slot_id];
2792 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2796 command->in_ctx = virt_dev->in_ctx;
2798 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2799 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2801 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2804 goto command_cleanup;
2806 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2807 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2808 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2810 /* Don't issue the command if there's no endpoints to update. */
2811 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2812 ctrl_ctx->drop_flags == 0) {
2814 goto command_cleanup;
2816 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2817 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2818 for (i = 31; i >= 1; i--) {
2819 __le32 le32 = cpu_to_le32(BIT(i));
2821 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2822 || (ctrl_ctx->add_flags & le32) || i == 1) {
2823 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2824 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2828 xhci_dbg(xhci, "New Input Control Context:\n");
2829 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2830 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2832 ret = xhci_configure_endpoint(xhci, udev, command,
2835 /* Callee should call reset_bandwidth() */
2836 goto command_cleanup;
2838 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2839 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2840 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2842 /* Free any rings that were dropped, but not changed. */
2843 for (i = 1; i < 31; ++i) {
2844 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2845 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2846 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2847 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2850 xhci_zero_in_ctx(xhci, virt_dev);
2852 * Install any rings for completely new endpoints or changed endpoints,
2853 * and free or cache any old rings from changed endpoints.
2855 for (i = 1; i < 31; ++i) {
2856 if (!virt_dev->eps[i].new_ring)
2858 /* Only cache or free the old ring if it exists.
2859 * It may not if this is the first add of an endpoint.
2861 if (virt_dev->eps[i].ring) {
2862 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2864 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2865 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2866 virt_dev->eps[i].new_ring = NULL;
2869 kfree(command->completion);
2875 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2877 struct xhci_hcd *xhci;
2878 struct xhci_virt_device *virt_dev;
2881 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2884 xhci = hcd_to_xhci(hcd);
2886 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2887 virt_dev = xhci->devs[udev->slot_id];
2888 /* Free any rings allocated for added endpoints */
2889 for (i = 0; i < 31; ++i) {
2890 if (virt_dev->eps[i].new_ring) {
2891 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2892 virt_dev->eps[i].new_ring = NULL;
2895 xhci_zero_in_ctx(xhci, virt_dev);
2898 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2899 struct xhci_container_ctx *in_ctx,
2900 struct xhci_container_ctx *out_ctx,
2901 struct xhci_input_control_ctx *ctrl_ctx,
2902 u32 add_flags, u32 drop_flags)
2904 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2905 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2906 xhci_slot_copy(xhci, in_ctx, out_ctx);
2907 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2909 xhci_dbg(xhci, "Input Context:\n");
2910 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2913 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2914 unsigned int slot_id, unsigned int ep_index,
2915 struct xhci_dequeue_state *deq_state)
2917 struct xhci_input_control_ctx *ctrl_ctx;
2918 struct xhci_container_ctx *in_ctx;
2919 struct xhci_ep_ctx *ep_ctx;
2923 in_ctx = xhci->devs[slot_id]->in_ctx;
2924 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2926 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2931 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2932 xhci->devs[slot_id]->out_ctx, ep_index);
2933 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2934 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2935 deq_state->new_deq_ptr);
2937 xhci_warn(xhci, "WARN Cannot submit config ep after "
2938 "reset ep command\n");
2939 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2940 deq_state->new_deq_seg,
2941 deq_state->new_deq_ptr);
2944 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2946 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2947 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2948 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2949 added_ctxs, added_ctxs);
2952 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2953 unsigned int ep_index, struct xhci_td *td)
2955 struct xhci_dequeue_state deq_state;
2956 struct xhci_virt_ep *ep;
2957 struct usb_device *udev = td->urb->dev;
2959 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2960 "Cleaning up stalled endpoint ring");
2961 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2962 /* We need to move the HW's dequeue pointer past this TD,
2963 * or it will attempt to resend it on the next doorbell ring.
2965 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2966 ep_index, ep->stopped_stream, td, &deq_state);
2968 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2971 /* HW with the reset endpoint quirk will use the saved dequeue state to
2972 * issue a configure endpoint command later.
2974 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2975 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2976 "Queueing new dequeue state");
2977 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2978 ep_index, ep->stopped_stream, &deq_state);
2980 /* Better hope no one uses the input context between now and the
2981 * reset endpoint completion!
2982 * XXX: No idea how this hardware will react when stream rings
2985 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2986 "Setting up input context for "
2987 "configure endpoint command");
2988 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2989 ep_index, &deq_state);
2993 /* Called when clearing halted device. The core should have sent the control
2994 * message to clear the device halt condition. The host side of the halt should
2995 * already be cleared with a reset endpoint command issued when the STALL tx
2996 * event was received.
2998 * Context: in_interrupt
3001 void xhci_endpoint_reset(struct usb_hcd *hcd,
3002 struct usb_host_endpoint *ep)
3004 struct xhci_hcd *xhci;
3006 xhci = hcd_to_xhci(hcd);
3009 * We might need to implement the config ep cmd in xhci 4.8.1 note:
3010 * The Reset Endpoint Command may only be issued to endpoints in the
3011 * Halted state. If software wishes reset the Data Toggle or Sequence
3012 * Number of an endpoint that isn't in the Halted state, then software
3013 * may issue a Configure Endpoint Command with the Drop and Add bits set
3014 * for the target endpoint. that is in the Stopped state.
3017 /* For now just print debug to follow the situation */
3018 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
3019 ep->desc.bEndpointAddress);
3022 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3023 struct usb_device *udev, struct usb_host_endpoint *ep,
3024 unsigned int slot_id)
3027 unsigned int ep_index;
3028 unsigned int ep_state;
3032 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3035 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3036 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3037 " descriptor for ep 0x%x does not support streams\n",
3038 ep->desc.bEndpointAddress);
3042 ep_index = xhci_get_endpoint_index(&ep->desc);
3043 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3044 if (ep_state & EP_HAS_STREAMS ||
3045 ep_state & EP_GETTING_STREAMS) {
3046 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3047 "already has streams set up.\n",
3048 ep->desc.bEndpointAddress);
3049 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3050 "dynamic stream context array reallocation.\n");
3053 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3054 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3055 "endpoint 0x%x; URBs are pending.\n",
3056 ep->desc.bEndpointAddress);
3062 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3063 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3065 unsigned int max_streams;
3067 /* The stream context array size must be a power of two */
3068 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3070 * Find out how many primary stream array entries the host controller
3071 * supports. Later we may use secondary stream arrays (similar to 2nd
3072 * level page entries), but that's an optional feature for xHCI host
3073 * controllers. xHCs must support at least 4 stream IDs.
3075 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3076 if (*num_stream_ctxs > max_streams) {
3077 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3079 *num_stream_ctxs = max_streams;
3080 *num_streams = max_streams;
3084 /* Returns an error code if one of the endpoint already has streams.
3085 * This does not change any data structures, it only checks and gathers
3088 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3089 struct usb_device *udev,
3090 struct usb_host_endpoint **eps, unsigned int num_eps,
3091 unsigned int *num_streams, u32 *changed_ep_bitmask)
3093 unsigned int max_streams;
3094 unsigned int endpoint_flag;
3098 for (i = 0; i < num_eps; i++) {
3099 ret = xhci_check_streams_endpoint(xhci, udev,
3100 eps[i], udev->slot_id);
3104 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3105 if (max_streams < (*num_streams - 1)) {
3106 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3107 eps[i]->desc.bEndpointAddress,
3109 *num_streams = max_streams+1;
3112 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3113 if (*changed_ep_bitmask & endpoint_flag)
3115 *changed_ep_bitmask |= endpoint_flag;
3120 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3121 struct usb_device *udev,
3122 struct usb_host_endpoint **eps, unsigned int num_eps)
3124 u32 changed_ep_bitmask = 0;
3125 unsigned int slot_id;
3126 unsigned int ep_index;
3127 unsigned int ep_state;
3130 slot_id = udev->slot_id;
3131 if (!xhci->devs[slot_id])
3134 for (i = 0; i < num_eps; i++) {
3135 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3136 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3137 /* Are streams already being freed for the endpoint? */
3138 if (ep_state & EP_GETTING_NO_STREAMS) {
3139 xhci_warn(xhci, "WARN Can't disable streams for "
3141 "streams are being disabled already\n",
3142 eps[i]->desc.bEndpointAddress);
3145 /* Are there actually any streams to free? */
3146 if (!(ep_state & EP_HAS_STREAMS) &&
3147 !(ep_state & EP_GETTING_STREAMS)) {
3148 xhci_warn(xhci, "WARN Can't disable streams for "
3150 "streams are already disabled!\n",
3151 eps[i]->desc.bEndpointAddress);
3152 xhci_warn(xhci, "WARN xhci_free_streams() called "
3153 "with non-streams endpoint\n");
3156 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3158 return changed_ep_bitmask;
3162 * The USB device drivers use this function (through the HCD interface in USB
3163 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3164 * coordinate mass storage command queueing across multiple endpoints (basically
3165 * a stream ID == a task ID).
3167 * Setting up streams involves allocating the same size stream context array
3168 * for each endpoint and issuing a configure endpoint command for all endpoints.
3170 * Don't allow the call to succeed if one endpoint only supports one stream
3171 * (which means it doesn't support streams at all).
3173 * Drivers may get less stream IDs than they asked for, if the host controller
3174 * hardware or endpoints claim they can't support the number of requested
3177 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3178 struct usb_host_endpoint **eps, unsigned int num_eps,
3179 unsigned int num_streams, gfp_t mem_flags)
3182 struct xhci_hcd *xhci;
3183 struct xhci_virt_device *vdev;
3184 struct xhci_command *config_cmd;
3185 struct xhci_input_control_ctx *ctrl_ctx;
3186 unsigned int ep_index;
3187 unsigned int num_stream_ctxs;
3188 unsigned int max_packet;
3189 unsigned long flags;
3190 u32 changed_ep_bitmask = 0;
3195 /* Add one to the number of streams requested to account for
3196 * stream 0 that is reserved for xHCI usage.
3199 xhci = hcd_to_xhci(hcd);
3200 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3203 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3204 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3205 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3206 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3210 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3212 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3215 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3217 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3219 xhci_free_command(xhci, config_cmd);
3223 /* Check to make sure all endpoints are not already configured for
3224 * streams. While we're at it, find the maximum number of streams that
3225 * all the endpoints will support and check for duplicate endpoints.
3227 spin_lock_irqsave(&xhci->lock, flags);
3228 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3229 num_eps, &num_streams, &changed_ep_bitmask);
3231 xhci_free_command(xhci, config_cmd);
3232 spin_unlock_irqrestore(&xhci->lock, flags);
3235 if (num_streams <= 1) {
3236 xhci_warn(xhci, "WARN: endpoints can't handle "
3237 "more than one stream.\n");
3238 xhci_free_command(xhci, config_cmd);
3239 spin_unlock_irqrestore(&xhci->lock, flags);
3242 vdev = xhci->devs[udev->slot_id];
3243 /* Mark each endpoint as being in transition, so
3244 * xhci_urb_enqueue() will reject all URBs.
3246 for (i = 0; i < num_eps; i++) {
3247 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3248 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3250 spin_unlock_irqrestore(&xhci->lock, flags);
3252 /* Setup internal data structures and allocate HW data structures for
3253 * streams (but don't install the HW structures in the input context
3254 * until we're sure all memory allocation succeeded).
3256 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3257 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3258 num_stream_ctxs, num_streams);
3260 for (i = 0; i < num_eps; i++) {
3261 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3262 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&eps[i]->desc));
3263 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3266 max_packet, mem_flags);
3267 if (!vdev->eps[ep_index].stream_info)
3269 /* Set maxPstreams in endpoint context and update deq ptr to
3270 * point to stream context array. FIXME
3274 /* Set up the input context for a configure endpoint command. */
3275 for (i = 0; i < num_eps; i++) {
3276 struct xhci_ep_ctx *ep_ctx;
3278 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3279 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3281 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3282 vdev->out_ctx, ep_index);
3283 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3284 vdev->eps[ep_index].stream_info);
3286 /* Tell the HW to drop its old copy of the endpoint context info
3287 * and add the updated copy from the input context.
3289 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3290 vdev->out_ctx, ctrl_ctx,
3291 changed_ep_bitmask, changed_ep_bitmask);
3293 /* Issue and wait for the configure endpoint command */
3294 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3297 /* xHC rejected the configure endpoint command for some reason, so we
3298 * leave the old ring intact and free our internal streams data
3304 spin_lock_irqsave(&xhci->lock, flags);
3305 for (i = 0; i < num_eps; i++) {
3306 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3307 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3308 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3309 udev->slot_id, ep_index);
3310 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3312 xhci_free_command(xhci, config_cmd);
3313 spin_unlock_irqrestore(&xhci->lock, flags);
3315 /* Subtract 1 for stream 0, which drivers can't use */
3316 return num_streams - 1;
3319 /* If it didn't work, free the streams! */
3320 for (i = 0; i < num_eps; i++) {
3321 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3322 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3323 vdev->eps[ep_index].stream_info = NULL;
3324 /* FIXME Unset maxPstreams in endpoint context and
3325 * update deq ptr to point to normal string ring.
3327 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3328 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3329 xhci_endpoint_zero(xhci, vdev, eps[i]);
3331 xhci_free_command(xhci, config_cmd);
3335 /* Transition the endpoint from using streams to being a "normal" endpoint
3338 * Modify the endpoint context state, submit a configure endpoint command,
3339 * and free all endpoint rings for streams if that completes successfully.
3341 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3342 struct usb_host_endpoint **eps, unsigned int num_eps,
3346 struct xhci_hcd *xhci;
3347 struct xhci_virt_device *vdev;
3348 struct xhci_command *command;
3349 struct xhci_input_control_ctx *ctrl_ctx;
3350 unsigned int ep_index;
3351 unsigned long flags;
3352 u32 changed_ep_bitmask;
3354 xhci = hcd_to_xhci(hcd);
3355 vdev = xhci->devs[udev->slot_id];
3357 /* Set up a configure endpoint command to remove the streams rings */
3358 spin_lock_irqsave(&xhci->lock, flags);
3359 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3360 udev, eps, num_eps);
3361 if (changed_ep_bitmask == 0) {
3362 spin_unlock_irqrestore(&xhci->lock, flags);
3366 /* Use the xhci_command structure from the first endpoint. We may have
3367 * allocated too many, but the driver may call xhci_free_streams() for
3368 * each endpoint it grouped into one call to xhci_alloc_streams().
3370 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3371 command = vdev->eps[ep_index].stream_info->free_streams_command;
3372 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3374 spin_unlock_irqrestore(&xhci->lock, flags);
3375 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3380 for (i = 0; i < num_eps; i++) {
3381 struct xhci_ep_ctx *ep_ctx;
3383 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3384 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3385 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3386 EP_GETTING_NO_STREAMS;
3388 xhci_endpoint_copy(xhci, command->in_ctx,
3389 vdev->out_ctx, ep_index);
3390 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3391 &vdev->eps[ep_index]);
3393 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3394 vdev->out_ctx, ctrl_ctx,
3395 changed_ep_bitmask, changed_ep_bitmask);
3396 spin_unlock_irqrestore(&xhci->lock, flags);
3398 /* Issue and wait for the configure endpoint command,
3399 * which must succeed.
3401 ret = xhci_configure_endpoint(xhci, udev, command,
3404 /* xHC rejected the configure endpoint command for some reason, so we
3405 * leave the streams rings intact.
3410 spin_lock_irqsave(&xhci->lock, flags);
3411 for (i = 0; i < num_eps; i++) {
3412 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3413 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3414 vdev->eps[ep_index].stream_info = NULL;
3415 /* FIXME Unset maxPstreams in endpoint context and
3416 * update deq ptr to point to normal string ring.
3418 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3419 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3421 spin_unlock_irqrestore(&xhci->lock, flags);
3427 * Deletes endpoint resources for endpoints that were active before a Reset
3428 * Device command, or a Disable Slot command. The Reset Device command leaves
3429 * the control endpoint intact, whereas the Disable Slot command deletes it.
3431 * Must be called with xhci->lock held.
3433 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3434 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3437 unsigned int num_dropped_eps = 0;
3438 unsigned int drop_flags = 0;
3440 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3441 if (virt_dev->eps[i].ring) {
3442 drop_flags |= 1 << i;
3446 xhci->num_active_eps -= num_dropped_eps;
3447 if (num_dropped_eps)
3448 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3449 "Dropped %u ep ctxs, flags = 0x%x, "
3451 num_dropped_eps, drop_flags,
3452 xhci->num_active_eps);
3456 * This submits a Reset Device Command, which will set the device state to 0,
3457 * set the device address to 0, and disable all the endpoints except the default
3458 * control endpoint. The USB core should come back and call
3459 * xhci_address_device(), and then re-set up the configuration. If this is
3460 * called because of a usb_reset_and_verify_device(), then the old alternate
3461 * settings will be re-installed through the normal bandwidth allocation
3464 * Wait for the Reset Device command to finish. Remove all structures
3465 * associated with the endpoints that were disabled. Clear the input device
3466 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3468 * If the virt_dev to be reset does not exist or does not match the udev,
3469 * it means the device is lost, possibly due to the xHC restore error and
3470 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3471 * re-allocate the device.
3473 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3476 unsigned long flags;
3477 struct xhci_hcd *xhci;
3478 unsigned int slot_id;
3479 struct xhci_virt_device *virt_dev;
3480 struct xhci_command *reset_device_cmd;
3481 int last_freed_endpoint;
3482 struct xhci_slot_ctx *slot_ctx;
3483 int old_active_eps = 0;
3485 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3488 xhci = hcd_to_xhci(hcd);
3489 slot_id = udev->slot_id;
3490 virt_dev = xhci->devs[slot_id];
3492 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3493 "not exist. Re-allocate the device\n", slot_id);
3494 ret = xhci_alloc_dev(hcd, udev);
3501 if (virt_dev->tt_info)
3502 old_active_eps = virt_dev->tt_info->active_eps;
3504 if (virt_dev->udev != udev) {
3505 /* If the virt_dev and the udev does not match, this virt_dev
3506 * may belong to another udev.
3507 * Re-allocate the device.
3509 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3510 "not match the udev. Re-allocate the device\n",
3512 ret = xhci_alloc_dev(hcd, udev);
3519 /* If device is not setup, there is no point in resetting it */
3520 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3521 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3522 SLOT_STATE_DISABLED)
3525 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3526 /* Allocate the command structure that holds the struct completion.
3527 * Assume we're in process context, since the normal device reset
3528 * process has to wait for the device anyway. Storage devices are
3529 * reset as part of error handling, so use GFP_NOIO instead of
3532 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3533 if (!reset_device_cmd) {
3534 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3538 /* Attempt to submit the Reset Device command to the command ring */
3539 spin_lock_irqsave(&xhci->lock, flags);
3541 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3543 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3544 spin_unlock_irqrestore(&xhci->lock, flags);
3545 goto command_cleanup;
3547 xhci_ring_cmd_db(xhci);
3548 spin_unlock_irqrestore(&xhci->lock, flags);
3550 /* Wait for the Reset Device command to finish */
3551 wait_for_completion(reset_device_cmd->completion);
3553 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3554 * unless we tried to reset a slot ID that wasn't enabled,
3555 * or the device wasn't in the addressed or configured state.
3557 ret = reset_device_cmd->status;
3559 case COMP_CMD_ABORT:
3561 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3563 goto command_cleanup;
3564 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3565 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3566 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3568 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3569 xhci_dbg(xhci, "Not freeing device rings.\n");
3570 /* Don't treat this as an error. May change my mind later. */
3572 goto command_cleanup;
3574 xhci_dbg(xhci, "Successful reset device command.\n");
3577 if (xhci_is_vendor_info_code(xhci, ret))
3579 xhci_warn(xhci, "Unknown completion code %u for "
3580 "reset device command.\n", ret);
3582 goto command_cleanup;
3585 /* Free up host controller endpoint resources */
3586 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3587 spin_lock_irqsave(&xhci->lock, flags);
3588 /* Don't delete the default control endpoint resources */
3589 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3590 spin_unlock_irqrestore(&xhci->lock, flags);
3593 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3594 last_freed_endpoint = 1;
3595 for (i = 1; i < 31; ++i) {
3596 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3598 if (ep->ep_state & EP_HAS_STREAMS) {
3599 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3600 xhci_get_endpoint_address(i));
3601 xhci_free_stream_info(xhci, ep->stream_info);
3602 ep->stream_info = NULL;
3603 ep->ep_state &= ~EP_HAS_STREAMS;
3607 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3608 last_freed_endpoint = i;
3610 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3611 xhci_drop_ep_from_interval_table(xhci,
3612 &virt_dev->eps[i].bw_info,
3617 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3619 /* If necessary, update the number of active TTs on this root port */
3620 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3622 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3623 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3627 xhci_free_command(xhci, reset_device_cmd);
3632 * At this point, the struct usb_device is about to go away, the device has
3633 * disconnected, and all traffic has been stopped and the endpoints have been
3634 * disabled. Free any HC data structures associated with that device.
3636 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3638 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3639 struct xhci_virt_device *virt_dev;
3640 unsigned long flags;
3643 struct xhci_command *command;
3645 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3649 #ifndef CONFIG_USB_DEFAULT_PERSIST
3651 * We called pm_runtime_get_noresume when the device was attached.
3652 * Decrement the counter here to allow controller to runtime suspend
3653 * if no devices remain.
3655 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3656 pm_runtime_put_noidle(hcd->self.controller);
3659 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3660 /* If the host is halted due to driver unload, we still need to free the
3663 if (ret <= 0 && ret != -ENODEV) {
3668 virt_dev = xhci->devs[udev->slot_id];
3670 /* Stop any wayward timer functions (which may grab the lock) */
3671 for (i = 0; i < 31; ++i) {
3672 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3673 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3676 spin_lock_irqsave(&xhci->lock, flags);
3678 virt_dev->udev = NULL;
3680 /* Don't disable the slot if the host controller is dead. */
3681 state = readl(&xhci->op_regs->status);
3682 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3683 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3684 xhci_free_virt_device(xhci, udev->slot_id);
3685 spin_unlock_irqrestore(&xhci->lock, flags);
3690 if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3692 spin_unlock_irqrestore(&xhci->lock, flags);
3693 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3696 xhci_ring_cmd_db(xhci);
3697 spin_unlock_irqrestore(&xhci->lock, flags);
3700 * Event command completion handler will free any data structures
3701 * associated with the slot. XXX Can free sleep?
3706 * Checks if we have enough host controller resources for the default control
3709 * Must be called with xhci->lock held.
3711 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3713 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3714 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3715 "Not enough ep ctxs: "
3716 "%u active, need to add 1, limit is %u.",
3717 xhci->num_active_eps, xhci->limit_active_eps);
3720 xhci->num_active_eps += 1;
3721 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3722 "Adding 1 ep ctx, %u now active.",
3723 xhci->num_active_eps);
3729 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3730 * timed out, or allocating memory failed. Returns 1 on success.
3732 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3734 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3735 unsigned long flags;
3737 struct xhci_command *command;
3739 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3743 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3744 mutex_lock(&xhci->mutex);
3745 spin_lock_irqsave(&xhci->lock, flags);
3746 command->completion = &xhci->addr_dev;
3747 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3749 spin_unlock_irqrestore(&xhci->lock, flags);
3750 mutex_unlock(&xhci->mutex);
3751 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3755 xhci_ring_cmd_db(xhci);
3756 spin_unlock_irqrestore(&xhci->lock, flags);
3758 wait_for_completion(command->completion);
3759 slot_id = xhci->slot_id;
3760 mutex_unlock(&xhci->mutex);
3762 if (!slot_id || command->status != COMP_SUCCESS) {
3763 xhci_err(xhci, "Error while assigning device slot ID\n");
3764 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3766 readl(&xhci->cap_regs->hcs_params1)));
3771 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3772 spin_lock_irqsave(&xhci->lock, flags);
3773 ret = xhci_reserve_host_control_ep_resources(xhci);
3775 spin_unlock_irqrestore(&xhci->lock, flags);
3776 xhci_warn(xhci, "Not enough host resources, "
3777 "active endpoint contexts = %u\n",
3778 xhci->num_active_eps);
3781 spin_unlock_irqrestore(&xhci->lock, flags);
3783 /* Use GFP_NOIO, since this function can be called from
3784 * xhci_discover_or_reset_device(), which may be called as part of
3785 * mass storage driver error handling.
3787 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3788 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3791 udev->slot_id = slot_id;
3793 #ifndef CONFIG_USB_DEFAULT_PERSIST
3795 * If resetting upon resume, we can't put the controller into runtime
3796 * suspend if there is a device attached.
3798 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3799 pm_runtime_get_noresume(hcd->self.controller);
3804 /* Is this a LS or FS device under a HS hub? */
3805 /* Hub or peripherial? */
3809 /* Disable slot, if we can do it without mem alloc */
3810 spin_lock_irqsave(&xhci->lock, flags);
3811 command->completion = NULL;
3812 command->status = 0;
3813 if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3815 xhci_ring_cmd_db(xhci);
3816 spin_unlock_irqrestore(&xhci->lock, flags);
3821 * Issue an Address Device command and optionally send a corresponding
3822 * SetAddress request to the device.
3824 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3825 enum xhci_setup_dev setup)
3827 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3828 unsigned long flags;
3829 struct xhci_virt_device *virt_dev;
3831 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3832 struct xhci_slot_ctx *slot_ctx;
3833 struct xhci_input_control_ctx *ctrl_ctx;
3835 struct xhci_command *command = NULL;
3837 mutex_lock(&xhci->mutex);
3839 if (xhci->xhc_state) { /* dying, removing or halted */
3844 if (!udev->slot_id) {
3845 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3846 "Bad Slot ID %d", udev->slot_id);
3851 virt_dev = xhci->devs[udev->slot_id];
3853 if (WARN_ON(!virt_dev)) {
3855 * In plug/unplug torture test with an NEC controller,
3856 * a zero-dereference was observed once due to virt_dev = 0.
3857 * Print useful debug rather than crash if it is observed again!
3859 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3865 if (setup == SETUP_CONTEXT_ONLY) {
3866 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3867 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3868 SLOT_STATE_DEFAULT) {
3869 xhci_dbg(xhci, "Slot already in default state\n");
3874 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3880 command->in_ctx = virt_dev->in_ctx;
3881 command->completion = &xhci->addr_dev;
3883 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3884 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3886 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3892 * If this is the first Set Address since device plug-in or
3893 * virt_device realloaction after a resume with an xHCI power loss,
3894 * then set up the slot context.
3896 if (!slot_ctx->dev_info)
3897 xhci_setup_addressable_virt_dev(xhci, udev);
3898 /* Otherwise, update the control endpoint ring enqueue pointer. */
3900 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3901 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3902 ctrl_ctx->drop_flags = 0;
3904 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3905 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3906 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3907 le32_to_cpu(slot_ctx->dev_info) >> 27);
3909 spin_lock_irqsave(&xhci->lock, flags);
3910 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3911 udev->slot_id, setup);
3913 spin_unlock_irqrestore(&xhci->lock, flags);
3914 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3915 "FIXME: allocate a command ring segment");
3918 xhci_ring_cmd_db(xhci);
3919 spin_unlock_irqrestore(&xhci->lock, flags);
3921 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3922 wait_for_completion(command->completion);
3924 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3925 * the SetAddress() "recovery interval" required by USB and aborting the
3926 * command on a timeout.
3928 switch (command->status) {
3929 case COMP_CMD_ABORT:
3931 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3934 case COMP_CTX_STATE:
3936 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3937 act, udev->slot_id);
3941 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3945 dev_warn(&udev->dev,
3946 "ERROR: Incompatible device for setup %s command\n", act);
3950 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3951 "Successful setup %s command", act);
3955 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3956 act, command->status);
3957 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3958 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3959 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3965 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3966 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3967 "Op regs DCBAA ptr = %#016llx", temp_64);
3968 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3969 "Slot ID %d dcbaa entry @%p = %#016llx",
3971 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3972 (unsigned long long)
3973 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3974 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3975 "Output Context DMA address = %#08llx",
3976 (unsigned long long)virt_dev->out_ctx->dma);
3977 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3978 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3979 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3980 le32_to_cpu(slot_ctx->dev_info) >> 27);
3981 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3982 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3984 * USB core uses address 1 for the roothubs, so we add one to the
3985 * address given back to us by the HC.
3987 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3988 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3989 le32_to_cpu(slot_ctx->dev_info) >> 27);
3990 /* Zero the input context control for later use */
3991 ctrl_ctx->add_flags = 0;
3992 ctrl_ctx->drop_flags = 0;
3994 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3995 "Internal device address = %d",
3996 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
3998 mutex_unlock(&xhci->mutex);
4003 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4005 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4008 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4010 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4014 * Transfer the port index into real index in the HW port status
4015 * registers. Caculate offset between the port's PORTSC register
4016 * and port status base. Divide the number of per port register
4017 * to get the real index. The raw port number bases 1.
4019 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4021 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4022 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
4023 __le32 __iomem *addr;
4026 if (hcd->speed < HCD_USB3)
4027 addr = xhci->usb2_ports[port1 - 1];
4029 addr = xhci->usb3_ports[port1 - 1];
4031 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
4036 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4037 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4039 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4040 struct usb_device *udev, u16 max_exit_latency)
4042 struct xhci_virt_device *virt_dev;
4043 struct xhci_command *command;
4044 struct xhci_input_control_ctx *ctrl_ctx;
4045 struct xhci_slot_ctx *slot_ctx;
4046 unsigned long flags;
4049 spin_lock_irqsave(&xhci->lock, flags);
4051 virt_dev = xhci->devs[udev->slot_id];
4054 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4055 * xHC was re-initialized. Exit latency will be set later after
4056 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4059 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4060 spin_unlock_irqrestore(&xhci->lock, flags);
4064 /* Attempt to issue an Evaluate Context command to change the MEL. */
4065 command = xhci->lpm_command;
4066 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4068 spin_unlock_irqrestore(&xhci->lock, flags);
4069 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4074 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4075 spin_unlock_irqrestore(&xhci->lock, flags);
4077 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4078 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4079 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4080 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4081 slot_ctx->dev_state = 0;
4083 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4084 "Set up evaluate context for LPM MEL change.");
4085 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4086 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4088 /* Issue and wait for the evaluate context command. */
4089 ret = xhci_configure_endpoint(xhci, udev, command,
4091 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4092 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4095 spin_lock_irqsave(&xhci->lock, flags);
4096 virt_dev->current_mel = max_exit_latency;
4097 spin_unlock_irqrestore(&xhci->lock, flags);
4104 /* BESL to HIRD Encoding array for USB2 LPM */
4105 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4106 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4108 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4109 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4110 struct usb_device *udev)
4112 int u2del, besl, besl_host;
4113 int besl_device = 0;
4116 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4117 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4119 if (field & USB_BESL_SUPPORT) {
4120 for (besl_host = 0; besl_host < 16; besl_host++) {
4121 if (xhci_besl_encoding[besl_host] >= u2del)
4124 /* Use baseline BESL value as default */
4125 if (field & USB_BESL_BASELINE_VALID)
4126 besl_device = USB_GET_BESL_BASELINE(field);
4127 else if (field & USB_BESL_DEEP_VALID)
4128 besl_device = USB_GET_BESL_DEEP(field);
4133 besl_host = (u2del - 51) / 75 + 1;
4136 besl = besl_host + besl_device;
4143 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4144 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4151 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4153 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4154 l1 = udev->l1_params.timeout / 256;
4156 /* device has preferred BESLD */
4157 if (field & USB_BESL_DEEP_VALID) {
4158 besld = USB_GET_BESL_DEEP(field);
4162 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4165 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4166 struct usb_device *udev, int enable)
4168 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4169 __le32 __iomem **port_array;
4170 __le32 __iomem *pm_addr, *hlpm_addr;
4171 u32 pm_val, hlpm_val, field;
4172 unsigned int port_num;
4173 unsigned long flags;
4174 int hird, exit_latency;
4177 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4181 if (!udev->parent || udev->parent->parent ||
4182 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4185 if (udev->usb2_hw_lpm_capable != 1)
4188 spin_lock_irqsave(&xhci->lock, flags);
4190 port_array = xhci->usb2_ports;
4191 port_num = udev->portnum - 1;
4192 pm_addr = port_array[port_num] + PORTPMSC;
4193 pm_val = readl(pm_addr);
4194 hlpm_addr = port_array[port_num] + PORTHLPMC;
4196 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4197 enable ? "enable" : "disable", port_num + 1);
4200 /* Host supports BESL timeout instead of HIRD */
4201 if (udev->usb2_hw_lpm_besl_capable) {
4202 /* if device doesn't have a preferred BESL value use a
4203 * default one which works with mixed HIRD and BESL
4204 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4206 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4207 if ((field & USB_BESL_SUPPORT) &&
4208 (field & USB_BESL_BASELINE_VALID))
4209 hird = USB_GET_BESL_BASELINE(field);
4211 hird = udev->l1_params.besl;
4213 exit_latency = xhci_besl_encoding[hird];
4214 spin_unlock_irqrestore(&xhci->lock, flags);
4216 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4217 * input context for link powermanagement evaluate
4218 * context commands. It is protected by hcd->bandwidth
4219 * mutex and is shared by all devices. We need to set
4220 * the max ext latency in USB 2 BESL LPM as well, so
4221 * use the same mutex and xhci_change_max_exit_latency()
4223 mutex_lock(hcd->bandwidth_mutex);
4224 ret = xhci_change_max_exit_latency(xhci, udev,
4226 mutex_unlock(hcd->bandwidth_mutex);
4230 spin_lock_irqsave(&xhci->lock, flags);
4232 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4233 writel(hlpm_val, hlpm_addr);
4237 hird = xhci_calculate_hird_besl(xhci, udev);
4240 pm_val &= ~PORT_HIRD_MASK;
4241 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4242 writel(pm_val, pm_addr);
4243 pm_val = readl(pm_addr);
4245 writel(pm_val, pm_addr);
4249 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4250 writel(pm_val, pm_addr);
4253 if (udev->usb2_hw_lpm_besl_capable) {
4254 spin_unlock_irqrestore(&xhci->lock, flags);
4255 mutex_lock(hcd->bandwidth_mutex);
4256 xhci_change_max_exit_latency(xhci, udev, 0);
4257 mutex_unlock(hcd->bandwidth_mutex);
4258 readl_poll_timeout(port_array[port_num], pm_val,
4259 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4265 spin_unlock_irqrestore(&xhci->lock, flags);
4269 /* check if a usb2 port supports a given extened capability protocol
4270 * only USB2 ports extended protocol capability values are cached.
4271 * Return 1 if capability is supported
4273 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4274 unsigned capability)
4276 u32 port_offset, port_count;
4279 for (i = 0; i < xhci->num_ext_caps; i++) {
4280 if (xhci->ext_caps[i] & capability) {
4281 /* port offsets starts at 1 */
4282 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4283 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4284 if (port >= port_offset &&
4285 port < port_offset + port_count)
4292 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4294 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4295 int portnum = udev->portnum - 1;
4297 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4301 /* we only support lpm for non-hub device connected to root hub yet */
4302 if (!udev->parent || udev->parent->parent ||
4303 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4306 if (xhci->hw_lpm_support == 1 &&
4307 xhci_check_usb2_port_capability(
4308 xhci, portnum, XHCI_HLC)) {
4309 udev->usb2_hw_lpm_capable = 1;
4310 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4311 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4312 if (xhci_check_usb2_port_capability(xhci, portnum,
4314 udev->usb2_hw_lpm_besl_capable = 1;
4320 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4322 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4323 static unsigned long long xhci_service_interval_to_ns(
4324 struct usb_endpoint_descriptor *desc)
4326 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4329 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4330 enum usb3_link_state state)
4332 unsigned long long sel;
4333 unsigned long long pel;
4334 unsigned int max_sel_pel;
4339 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4340 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4341 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4342 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4346 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4347 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4348 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4352 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4354 return USB3_LPM_DISABLED;
4357 if (sel <= max_sel_pel && pel <= max_sel_pel)
4358 return USB3_LPM_DEVICE_INITIATED;
4360 if (sel > max_sel_pel)
4361 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4362 "due to long SEL %llu ms\n",
4365 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4366 "due to long PEL %llu ms\n",
4368 return USB3_LPM_DISABLED;
4371 /* The U1 timeout should be the maximum of the following values:
4372 * - For control endpoints, U1 system exit latency (SEL) * 3
4373 * - For bulk endpoints, U1 SEL * 5
4374 * - For interrupt endpoints:
4375 * - Notification EPs, U1 SEL * 3
4376 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4377 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4379 static unsigned long long xhci_calculate_intel_u1_timeout(
4380 struct usb_device *udev,
4381 struct usb_endpoint_descriptor *desc)
4383 unsigned long long timeout_ns;
4387 ep_type = usb_endpoint_type(desc);
4389 case USB_ENDPOINT_XFER_CONTROL:
4390 timeout_ns = udev->u1_params.sel * 3;
4392 case USB_ENDPOINT_XFER_BULK:
4393 timeout_ns = udev->u1_params.sel * 5;
4395 case USB_ENDPOINT_XFER_INT:
4396 intr_type = usb_endpoint_interrupt_type(desc);
4397 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4398 timeout_ns = udev->u1_params.sel * 3;
4401 /* Otherwise the calculation is the same as isoc eps */
4402 case USB_ENDPOINT_XFER_ISOC:
4403 timeout_ns = xhci_service_interval_to_ns(desc);
4404 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4405 if (timeout_ns < udev->u1_params.sel * 2)
4406 timeout_ns = udev->u1_params.sel * 2;
4415 /* Returns the hub-encoded U1 timeout value. */
4416 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4417 struct usb_device *udev,
4418 struct usb_endpoint_descriptor *desc)
4420 unsigned long long timeout_ns;
4422 /* Prevent U1 if service interval is shorter than U1 exit latency */
4423 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4424 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4425 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4426 return USB3_LPM_DISABLED;
4430 if (xhci->quirks & XHCI_INTEL_HOST)
4431 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4433 timeout_ns = udev->u1_params.sel;
4435 /* The U1 timeout is encoded in 1us intervals.
4436 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4438 if (timeout_ns == USB3_LPM_DISABLED)
4441 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4443 /* If the necessary timeout value is bigger than what we can set in the
4444 * USB 3.0 hub, we have to disable hub-initiated U1.
4446 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4448 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4449 "due to long timeout %llu ms\n", timeout_ns);
4450 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4453 /* The U2 timeout should be the maximum of:
4454 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4455 * - largest bInterval of any active periodic endpoint (to avoid going
4456 * into lower power link states between intervals).
4457 * - the U2 Exit Latency of the device
4459 static unsigned long long xhci_calculate_intel_u2_timeout(
4460 struct usb_device *udev,
4461 struct usb_endpoint_descriptor *desc)
4463 unsigned long long timeout_ns;
4464 unsigned long long u2_del_ns;
4466 timeout_ns = 10 * 1000 * 1000;
4468 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4469 (xhci_service_interval_to_ns(desc) > timeout_ns))
4470 timeout_ns = xhci_service_interval_to_ns(desc);
4472 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4473 if (u2_del_ns > timeout_ns)
4474 timeout_ns = u2_del_ns;
4479 /* Returns the hub-encoded U2 timeout value. */
4480 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4481 struct usb_device *udev,
4482 struct usb_endpoint_descriptor *desc)
4484 unsigned long long timeout_ns;
4486 /* Prevent U2 if service interval is shorter than U2 exit latency */
4487 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4488 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4489 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4490 return USB3_LPM_DISABLED;
4494 if (xhci->quirks & XHCI_INTEL_HOST)
4495 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4497 timeout_ns = udev->u2_params.sel;
4499 /* The U2 timeout is encoded in 256us intervals */
4500 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4501 /* If the necessary timeout value is bigger than what we can set in the
4502 * USB 3.0 hub, we have to disable hub-initiated U2.
4504 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4506 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4507 "due to long timeout %llu ms\n", timeout_ns);
4508 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4511 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4512 struct usb_device *udev,
4513 struct usb_endpoint_descriptor *desc,
4514 enum usb3_link_state state,
4517 if (state == USB3_LPM_U1)
4518 return xhci_calculate_u1_timeout(xhci, udev, desc);
4519 else if (state == USB3_LPM_U2)
4520 return xhci_calculate_u2_timeout(xhci, udev, desc);
4522 return USB3_LPM_DISABLED;
4525 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4526 struct usb_device *udev,
4527 struct usb_endpoint_descriptor *desc,
4528 enum usb3_link_state state,
4533 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4534 desc, state, timeout);
4536 /* If we found we can't enable hub-initiated LPM, and
4537 * the U1 or U2 exit latency was too high to allow
4538 * device-initiated LPM as well, then we will disable LPM
4539 * for this device, so stop searching any further.
4541 if (alt_timeout == USB3_LPM_DISABLED) {
4542 *timeout = alt_timeout;
4545 if (alt_timeout > *timeout)
4546 *timeout = alt_timeout;
4550 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4551 struct usb_device *udev,
4552 struct usb_host_interface *alt,
4553 enum usb3_link_state state,
4558 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4559 if (xhci_update_timeout_for_endpoint(xhci, udev,
4560 &alt->endpoint[j].desc, state, timeout))
4567 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4568 enum usb3_link_state state)
4570 struct usb_device *parent;
4571 unsigned int num_hubs;
4573 if (state == USB3_LPM_U2)
4576 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4577 for (parent = udev->parent, num_hubs = 0; parent->parent;
4578 parent = parent->parent)
4584 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4585 " below second-tier hub.\n");
4586 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4587 "to decrease power consumption.\n");
4591 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4592 struct usb_device *udev,
4593 enum usb3_link_state state)
4595 if (xhci->quirks & XHCI_INTEL_HOST)
4596 return xhci_check_intel_tier_policy(udev, state);
4601 /* Returns the U1 or U2 timeout that should be enabled.
4602 * If the tier check or timeout setting functions return with a non-zero exit
4603 * code, that means the timeout value has been finalized and we shouldn't look
4604 * at any more endpoints.
4606 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4607 struct usb_device *udev, enum usb3_link_state state)
4609 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4610 struct usb_host_config *config;
4613 u16 timeout = USB3_LPM_DISABLED;
4615 if (state == USB3_LPM_U1)
4617 else if (state == USB3_LPM_U2)
4620 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4625 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4628 /* Gather some information about the currently installed configuration
4629 * and alternate interface settings.
4631 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4635 config = udev->actconfig;
4639 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4640 struct usb_driver *driver;
4641 struct usb_interface *intf = config->interface[i];
4646 /* Check if any currently bound drivers want hub-initiated LPM
4649 if (intf->dev.driver) {
4650 driver = to_usb_driver(intf->dev.driver);
4651 if (driver && driver->disable_hub_initiated_lpm) {
4652 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4653 state_name, driver->name);
4654 timeout = xhci_get_timeout_no_hub_lpm(udev,
4656 if (timeout == USB3_LPM_DISABLED)
4661 /* Not sure how this could happen... */
4662 if (!intf->cur_altsetting)
4665 if (xhci_update_timeout_for_interface(xhci, udev,
4666 intf->cur_altsetting,
4673 static int calculate_max_exit_latency(struct usb_device *udev,
4674 enum usb3_link_state state_changed,
4675 u16 hub_encoded_timeout)
4677 unsigned long long u1_mel_us = 0;
4678 unsigned long long u2_mel_us = 0;
4679 unsigned long long mel_us = 0;
4685 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4686 hub_encoded_timeout == USB3_LPM_DISABLED);
4687 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4688 hub_encoded_timeout == USB3_LPM_DISABLED);
4690 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4691 hub_encoded_timeout != USB3_LPM_DISABLED);
4692 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4693 hub_encoded_timeout != USB3_LPM_DISABLED);
4695 /* If U1 was already enabled and we're not disabling it,
4696 * or we're going to enable U1, account for the U1 max exit latency.
4698 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4700 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4701 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4703 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4705 if (u1_mel_us > u2_mel_us)
4709 /* xHCI host controller max exit latency field is only 16 bits wide. */
4710 if (mel_us > MAX_EXIT) {
4711 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4712 "is too big.\n", mel_us);
4718 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4719 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4720 struct usb_device *udev, enum usb3_link_state state)
4722 struct xhci_hcd *xhci;
4723 u16 hub_encoded_timeout;
4727 xhci = hcd_to_xhci(hcd);
4728 /* The LPM timeout values are pretty host-controller specific, so don't
4729 * enable hub-initiated timeouts unless the vendor has provided
4730 * information about their timeout algorithm.
4732 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4733 !xhci->devs[udev->slot_id])
4734 return USB3_LPM_DISABLED;
4736 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4737 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4739 /* Max Exit Latency is too big, disable LPM. */
4740 hub_encoded_timeout = USB3_LPM_DISABLED;
4744 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4747 return hub_encoded_timeout;
4750 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4751 struct usb_device *udev, enum usb3_link_state state)
4753 struct xhci_hcd *xhci;
4756 xhci = hcd_to_xhci(hcd);
4757 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4758 !xhci->devs[udev->slot_id])
4761 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4762 return xhci_change_max_exit_latency(xhci, udev, mel);
4764 #else /* CONFIG_PM */
4766 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4767 struct usb_device *udev, int enable)
4772 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4777 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4778 struct usb_device *udev, enum usb3_link_state state)
4780 return USB3_LPM_DISABLED;
4783 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4784 struct usb_device *udev, enum usb3_link_state state)
4788 #endif /* CONFIG_PM */
4790 /*-------------------------------------------------------------------------*/
4792 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4793 * internal data structures for the device.
4795 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4796 struct usb_tt *tt, gfp_t mem_flags)
4798 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4799 struct xhci_virt_device *vdev;
4800 struct xhci_command *config_cmd;
4801 struct xhci_input_control_ctx *ctrl_ctx;
4802 struct xhci_slot_ctx *slot_ctx;
4803 unsigned long flags;
4804 unsigned think_time;
4807 /* Ignore root hubs */
4811 vdev = xhci->devs[hdev->slot_id];
4813 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4816 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4818 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4821 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4823 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4825 xhci_free_command(xhci, config_cmd);
4829 spin_lock_irqsave(&xhci->lock, flags);
4830 if (hdev->speed == USB_SPEED_HIGH &&
4831 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4832 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4833 xhci_free_command(xhci, config_cmd);
4834 spin_unlock_irqrestore(&xhci->lock, flags);
4838 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4839 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4840 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4841 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4843 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4844 * but it may be already set to 1 when setup an xHCI virtual
4845 * device, so clear it anyway.
4848 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4849 else if (hdev->speed == USB_SPEED_FULL)
4850 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4852 if (xhci->hci_version > 0x95) {
4853 xhci_dbg(xhci, "xHCI version %x needs hub "
4854 "TT think time and number of ports\n",
4855 (unsigned int) xhci->hci_version);
4856 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4857 /* Set TT think time - convert from ns to FS bit times.
4858 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4859 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4861 * xHCI 1.0: this field shall be 0 if the device is not a
4864 think_time = tt->think_time;
4865 if (think_time != 0)
4866 think_time = (think_time / 666) - 1;
4867 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4868 slot_ctx->tt_info |=
4869 cpu_to_le32(TT_THINK_TIME(think_time));
4871 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4872 "TT think time or number of ports\n",
4873 (unsigned int) xhci->hci_version);
4875 slot_ctx->dev_state = 0;
4876 spin_unlock_irqrestore(&xhci->lock, flags);
4878 xhci_dbg(xhci, "Set up %s for hub device.\n",
4879 (xhci->hci_version > 0x95) ?
4880 "configure endpoint" : "evaluate context");
4881 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4882 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4884 /* Issue and wait for the configure endpoint or
4885 * evaluate context command.
4887 if (xhci->hci_version > 0x95)
4888 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4891 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4894 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4895 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4897 xhci_free_command(xhci, config_cmd);
4901 int xhci_get_frame(struct usb_hcd *hcd)
4903 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4904 /* EHCI mods by the periodic size. Why? */
4905 return readl(&xhci->run_regs->microframe_index) >> 3;
4908 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4910 struct xhci_hcd *xhci;
4911 struct device *dev = hcd->self.controller;
4914 /* Accept arbitrarily long scatter-gather lists */
4915 hcd->self.sg_tablesize = ~0;
4917 /* support to build packet from discontinuous buffers */
4918 hcd->self.no_sg_constraint = 1;
4920 /* XHCI controllers don't stop the ep queue on short packets :| */
4921 hcd->self.no_stop_on_short = 1;
4923 xhci = hcd_to_xhci(hcd);
4925 if (usb_hcd_is_primary_hcd(hcd)) {
4926 xhci->main_hcd = hcd;
4927 /* Mark the first roothub as being USB 2.0.
4928 * The xHCI driver will register the USB 3.0 roothub.
4930 hcd->speed = HCD_USB2;
4931 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4933 * USB 2.0 roothub under xHCI has an integrated TT,
4934 * (rate matching hub) as opposed to having an OHCI/UHCI
4935 * companion controller.
4939 /* Some 3.1 hosts return sbrn 0x30, can't rely on sbrn alone */
4940 if (xhci->sbrn == 0x31 || xhci->usb3_rhub.min_rev >= 1) {
4941 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4942 hcd->speed = HCD_USB31;
4943 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
4945 /* xHCI private pointer was set in xhci_pci_probe for the second
4946 * registered roothub.
4951 mutex_init(&xhci->mutex);
4952 xhci->cap_regs = hcd->regs;
4953 xhci->op_regs = hcd->regs +
4954 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4955 xhci->run_regs = hcd->regs +
4956 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4957 /* Cache read-only capability registers */
4958 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4959 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4960 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4961 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4962 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4963 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4964 if (xhci->hci_version > 0x100)
4965 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4966 xhci_print_registers(xhci);
4968 xhci->quirks |= quirks;
4970 get_quirks(dev, xhci);
4972 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4973 * success event after a short transfer. This quirk will ignore such
4976 if (xhci->hci_version > 0x96)
4977 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4979 /* Make sure the HC is halted. */
4980 retval = xhci_halt(xhci);
4984 xhci_dbg(xhci, "Resetting HCD\n");
4985 /* Reset the internal HC memory state and registers. */
4986 retval = xhci_reset(xhci);
4989 xhci_dbg(xhci, "Reset complete\n");
4992 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
4993 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
4994 * address memory pointers actually. So, this driver clears the AC64
4995 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
4996 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
4998 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
4999 xhci->hcc_params &= ~BIT(0);
5001 /* Set dma_mask and coherent_dma_mask to 64-bits,
5002 * if xHC supports 64-bit addressing */
5003 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5004 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5005 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5006 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5009 * This is to avoid error in cases where a 32-bit USB
5010 * controller is used on a 64-bit capable system.
5012 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5015 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5016 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5019 xhci_dbg(xhci, "Calling HCD init\n");
5020 /* Initialize HCD and host controller data structures. */
5021 retval = xhci_init(hcd);
5024 xhci_dbg(xhci, "Called HCD init\n");
5026 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
5027 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5031 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5033 static const struct hc_driver xhci_hc_driver = {
5034 .description = "xhci-hcd",
5035 .product_desc = "xHCI Host Controller",
5036 .hcd_priv_size = sizeof(struct xhci_hcd),
5039 * generic hardware linkage
5042 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
5045 * basic lifecycle operations
5047 .reset = NULL, /* set in xhci_init_driver() */
5050 .shutdown = xhci_shutdown,
5053 * managing i/o requests and associated device resources
5055 .urb_enqueue = xhci_urb_enqueue,
5056 .urb_dequeue = xhci_urb_dequeue,
5057 .alloc_dev = xhci_alloc_dev,
5058 .free_dev = xhci_free_dev,
5059 .alloc_streams = xhci_alloc_streams,
5060 .free_streams = xhci_free_streams,
5061 .add_endpoint = xhci_add_endpoint,
5062 .drop_endpoint = xhci_drop_endpoint,
5063 .endpoint_reset = xhci_endpoint_reset,
5064 .check_bandwidth = xhci_check_bandwidth,
5065 .reset_bandwidth = xhci_reset_bandwidth,
5066 .address_device = xhci_address_device,
5067 .enable_device = xhci_enable_device,
5068 .update_hub_device = xhci_update_hub_device,
5069 .reset_device = xhci_discover_or_reset_device,
5072 * scheduling support
5074 .get_frame_number = xhci_get_frame,
5079 .hub_control = xhci_hub_control,
5080 .hub_status_data = xhci_hub_status_data,
5081 .bus_suspend = xhci_bus_suspend,
5082 .bus_resume = xhci_bus_resume,
5085 * call back when device connected and addressed
5087 .update_device = xhci_update_device,
5088 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5089 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5090 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5091 .find_raw_port_number = xhci_find_raw_port_number,
5094 void xhci_init_driver(struct hc_driver *drv,
5095 const struct xhci_driver_overrides *over)
5099 /* Copy the generic table to drv then apply the overrides */
5100 *drv = xhci_hc_driver;
5103 drv->hcd_priv_size += over->extra_priv_size;
5105 drv->reset = over->reset;
5107 drv->start = over->start;
5110 EXPORT_SYMBOL_GPL(xhci_init_driver);
5112 MODULE_DESCRIPTION(DRIVER_DESC);
5113 MODULE_AUTHOR(DRIVER_AUTHOR);
5114 MODULE_LICENSE("GPL");
5116 static int __init xhci_hcd_init(void)
5119 * Check the compiler generated sizes of structures that must be laid
5120 * out in specific ways for hardware access.
5122 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5123 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5124 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5125 /* xhci_device_control has eight fields, and also
5126 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5128 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5129 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5130 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5131 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5132 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5133 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5134 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5143 * If an init function is provided, an exit function must also be provided
5144 * to allow module unload.
5146 static void __exit xhci_hcd_fini(void) { }
5148 module_init(xhci_hcd_init);
5149 module_exit(xhci_hcd_fini);