2 * NVIDIA Tegra xHCI host controller driver
4 * Copyright (C) 2014 NVIDIA Corporation
5 * Copyright (C) 2014 Google, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/firmware.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/phy/phy.h>
21 #include <linux/phy/tegra/xusb.h>
22 #include <linux/platform_device.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/reset.h>
26 #include <linux/slab.h>
30 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
31 #define TEGRA_XHCI_SS_LOW_SPEED 12000000
33 /* FPCI CFG registers */
34 #define XUSB_CFG_1 0x004
35 #define XUSB_IO_SPACE_EN BIT(0)
36 #define XUSB_MEM_SPACE_EN BIT(1)
37 #define XUSB_BUS_MASTER_EN BIT(2)
38 #define XUSB_CFG_4 0x010
39 #define XUSB_BASE_ADDR_SHIFT 15
40 #define XUSB_BASE_ADDR_MASK 0x1ffff
41 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c
42 #define XUSB_CFG_CSB_BASE_ADDR 0x800
44 /* FPCI mailbox registers */
45 #define XUSB_CFG_ARU_MBOX_CMD 0x0e4
46 #define MBOX_DEST_FALC BIT(27)
47 #define MBOX_DEST_PME BIT(28)
48 #define MBOX_DEST_SMI BIT(29)
49 #define MBOX_DEST_XHCI BIT(30)
50 #define MBOX_INT_EN BIT(31)
51 #define XUSB_CFG_ARU_MBOX_DATA_IN 0x0e8
52 #define CMD_DATA_SHIFT 0
53 #define CMD_DATA_MASK 0xffffff
54 #define CMD_TYPE_SHIFT 24
55 #define CMD_TYPE_MASK 0xff
56 #define XUSB_CFG_ARU_MBOX_DATA_OUT 0x0ec
57 #define XUSB_CFG_ARU_MBOX_OWNER 0x0f0
58 #define MBOX_OWNER_NONE 0
59 #define MBOX_OWNER_FW 1
60 #define MBOX_OWNER_SW 2
61 #define XUSB_CFG_ARU_SMI_INTR 0x428
62 #define MBOX_SMI_INTR_FW_HANG BIT(1)
63 #define MBOX_SMI_INTR_EN BIT(3)
66 #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180
67 #define IPFS_EN_FPCI BIT(0)
68 #define IPFS_XUSB_HOST_INTR_MASK_0 0x188
69 #define IPFS_IP_INT_MASK BIT(16)
70 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc
72 #define CSB_PAGE_SELECT_MASK 0x7fffff
73 #define CSB_PAGE_SELECT_SHIFT 9
74 #define CSB_PAGE_OFFSET_MASK 0x1ff
75 #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \
77 #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK)
79 /* Falcon CSB registers */
80 #define XUSB_FALC_CPUCTL 0x100
81 #define CPUCTL_STARTCPU BIT(1)
82 #define CPUCTL_STATE_HALTED BIT(4)
83 #define CPUCTL_STATE_STOPPED BIT(5)
84 #define XUSB_FALC_BOOTVEC 0x104
85 #define XUSB_FALC_DMACTL 0x10c
86 #define XUSB_FALC_IMFILLRNG1 0x154
87 #define IMFILLRNG1_TAG_MASK 0xffff
88 #define IMFILLRNG1_TAG_LO_SHIFT 0
89 #define IMFILLRNG1_TAG_HI_SHIFT 16
90 #define XUSB_FALC_IMFILLCTL 0x158
92 /* MP CSB registers */
93 #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00
94 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04
95 #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08
96 #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10
97 #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8
98 #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff
99 #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24
100 #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff
101 #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14
102 #define L2IMEMOP_ACTION_SHIFT 24
103 #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT)
104 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT)
105 #define XUSB_CSB_MP_APMAP 0x10181c
106 #define APMAP_BOOTPATH BIT(31)
108 #define IMEM_BLOCK_SIZE 256
110 struct tegra_xusb_fw_header {
111 u32 boot_loadaddr_in_imem;
112 u32 boot_codedfi_offset;
117 u16 alloc_phys_memsize;
118 u32 rodata_img_offset;
119 u32 rodata_section_start;
120 u32 rodata_section_end;
123 u32 fwimg_created_time;
124 u32 imem_resident_start;
125 u32 imem_resident_end;
133 u32 phys_addr_log_buffer;
134 u32 total_log_entries;
139 u32 ss_low_power_entry_timeout;
141 u8 padding[139]; /* Pad to 256 bytes */
144 struct tegra_xusb_phy_type {
149 struct tegra_xusb_soc {
150 const char *firmware;
151 const char * const *supply_names;
152 unsigned int num_supplies;
153 const struct tegra_xusb_phy_type *phy_types;
154 unsigned int num_types;
160 } usb2, ulpi, hsic, usb3;
176 void __iomem *ipfs_base;
177 void __iomem *fpci_base;
179 const struct tegra_xusb_soc *soc;
181 struct regulator_bulk_data *supplies;
183 struct tegra_xusb_padctl *padctl;
185 struct clk *host_clk;
186 struct clk *falcon_clk;
188 struct clk *ss_src_clk;
189 struct clk *hs_src_clk;
190 struct clk *fs_src_clk;
191 struct clk *pll_u_480m;
195 struct reset_control *host_rst;
196 struct reset_control *ss_rst;
199 unsigned int num_phys;
201 /* Firmware loading related */
209 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
211 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
213 return readl(tegra->fpci_base + offset);
216 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
219 writel(value, tegra->fpci_base + offset);
222 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
224 return readl(tegra->ipfs_base + offset);
227 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
230 writel(value, tegra->ipfs_base + offset);
233 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
235 u32 page = CSB_PAGE_SELECT(offset);
236 u32 ofs = CSB_PAGE_OFFSET(offset);
238 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
240 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
243 static void csb_writel(struct tegra_xusb *tegra, u32 value,
246 u32 page = CSB_PAGE_SELECT(offset);
247 u32 ofs = CSB_PAGE_OFFSET(offset);
249 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
250 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
253 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
256 unsigned long new_parent_rate, old_parent_rate;
257 struct clk *clk = tegra->ss_src_clk;
261 if (clk_get_rate(clk) == rate)
265 case TEGRA_XHCI_SS_HIGH_SPEED:
267 * Reparent to PLLU_480M. Set divider first to avoid
270 old_parent_rate = clk_get_rate(clk_get_parent(clk));
271 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
272 div = new_parent_rate / rate;
274 err = clk_set_rate(clk, old_parent_rate / div);
278 err = clk_set_parent(clk, tegra->pll_u_480m);
283 * The rate should already be correct, but set it again just
286 err = clk_set_rate(clk, rate);
292 case TEGRA_XHCI_SS_LOW_SPEED:
293 /* Reparent to CLK_M */
294 err = clk_set_parent(clk, tegra->clk_m);
298 err = clk_set_rate(clk, rate);
305 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
309 if (clk_get_rate(clk) != rate) {
310 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
317 static unsigned long extract_field(u32 value, unsigned int start,
320 return (value >> start) & ((1 << count) - 1);
323 /* Command requests from the firmware */
324 enum tegra_xusb_mbox_cmd {
325 MBOX_CMD_MSG_ENABLED = 1,
326 MBOX_CMD_INC_FALC_CLOCK,
327 MBOX_CMD_DEC_FALC_CLOCK,
328 MBOX_CMD_INC_SSPI_CLOCK,
329 MBOX_CMD_DEC_SSPI_CLOCK,
330 MBOX_CMD_SET_BW, /* no ACK/NAK required */
331 MBOX_CMD_SET_SS_PWR_GATING,
332 MBOX_CMD_SET_SS_PWR_UNGATING,
333 MBOX_CMD_SAVE_DFE_CTLE_CTX,
334 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
335 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
336 MBOX_CMD_START_HSIC_IDLE,
337 MBOX_CMD_STOP_HSIC_IDLE,
338 MBOX_CMD_DBC_WAKE_STACK, /* unused */
339 MBOX_CMD_HSIC_PRETEND_CONNECT,
341 MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
342 MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
346 /* Response message to above commands */
351 static const char * const mbox_cmd_name[] = {
353 [ 2] = "INC_FALCON_CLOCK",
354 [ 3] = "DEC_FALCON_CLOCK",
355 [ 4] = "INC_SSPI_CLOCK",
356 [ 5] = "DEC_SSPI_CLOCK",
358 [ 7] = "SET_SS_PWR_GATING",
359 [ 8] = "SET_SS_PWR_UNGATING",
360 [ 9] = "SAVE_DFE_CTLE_CTX",
361 [ 10] = "AIRPLANE_MODE_ENABLED",
362 [ 11] = "AIRPLANE_MODE_DISABLED",
363 [ 12] = "START_HSIC_IDLE",
364 [ 13] = "STOP_HSIC_IDLE",
365 [ 14] = "DBC_WAKE_STACK",
366 [ 15] = "HSIC_PRETEND_CONNECT",
367 [ 16] = "RESET_SSPI",
368 [ 17] = "DISABLE_SS_LFPS_DETECTION",
369 [ 18] = "ENABLE_SS_LFPS_DETECTION",
374 struct tegra_xusb_mbox_msg {
379 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
381 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
382 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
384 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
387 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
388 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
391 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
394 case MBOX_CMD_SET_BW:
404 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
405 const struct tegra_xusb_mbox_msg *msg)
407 bool wait_for_idle = false;
411 * Acquire the mailbox. The firmware still owns the mailbox for
414 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
415 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
416 if (value != MBOX_OWNER_NONE) {
417 dev_err(tegra->dev, "mailbox is busy\n");
421 fpci_writel(tegra, MBOX_OWNER_SW, XUSB_CFG_ARU_MBOX_OWNER);
423 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
424 if (value != MBOX_OWNER_SW) {
425 dev_err(tegra->dev, "failed to acquire mailbox\n");
429 wait_for_idle = true;
432 value = tegra_xusb_mbox_pack(msg);
433 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_DATA_IN);
435 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
436 value |= MBOX_INT_EN | MBOX_DEST_FALC;
437 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
440 unsigned long timeout = jiffies + msecs_to_jiffies(250);
442 while (time_before(jiffies, timeout)) {
443 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
444 if (value == MBOX_OWNER_NONE)
447 usleep_range(10, 20);
450 if (time_after(jiffies, timeout))
451 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
453 if (value != MBOX_OWNER_NONE)
460 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
462 struct tegra_xusb *tegra = data;
465 /* clear mailbox interrupts */
466 value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
467 fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
469 if (value & MBOX_SMI_INTR_FW_HANG)
470 dev_err(tegra->dev, "controller firmware hang\n");
472 return IRQ_WAKE_THREAD;
475 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
476 const struct tegra_xusb_mbox_msg *msg)
478 struct tegra_xusb_padctl *padctl = tegra->padctl;
479 const struct tegra_xusb_soc *soc = tegra->soc;
480 struct device *dev = tegra->dev;
481 struct tegra_xusb_mbox_msg rsp;
487 memset(&rsp, 0, sizeof(rsp));
490 case MBOX_CMD_INC_FALC_CLOCK:
491 case MBOX_CMD_DEC_FALC_CLOCK:
492 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
493 if (rsp.data != msg->data)
494 rsp.cmd = MBOX_CMD_NAK;
496 rsp.cmd = MBOX_CMD_ACK;
500 case MBOX_CMD_INC_SSPI_CLOCK:
501 case MBOX_CMD_DEC_SSPI_CLOCK:
502 if (tegra->soc->scale_ss_clock) {
503 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
505 rsp.cmd = MBOX_CMD_NAK;
507 rsp.cmd = MBOX_CMD_ACK;
509 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
511 rsp.cmd = MBOX_CMD_ACK;
512 rsp.data = msg->data;
517 case MBOX_CMD_SET_BW:
519 * TODO: Request bandwidth once EMC scaling is supported.
520 * Ignore for now since ACK/NAK is not required for SET_BW
525 case MBOX_CMD_SAVE_DFE_CTLE_CTX:
526 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
528 dev_err(dev, "failed to save context for USB3#%u: %d\n",
530 rsp.cmd = MBOX_CMD_NAK;
532 rsp.cmd = MBOX_CMD_ACK;
535 rsp.data = msg->data;
538 case MBOX_CMD_START_HSIC_IDLE:
539 case MBOX_CMD_STOP_HSIC_IDLE:
540 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
545 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
546 soc->ports.hsic.count);
548 for_each_set_bit(port, &mask, 32) {
549 err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
556 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
557 idle ? "idle" : "busy", err);
558 rsp.cmd = MBOX_CMD_NAK;
560 rsp.cmd = MBOX_CMD_ACK;
563 rsp.data = msg->data;
566 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
567 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
568 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
573 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
574 soc->ports.usb3.count);
576 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
577 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
584 * wait 500us for LFPS detector to be disabled before
588 usleep_range(500, 1000);
593 "failed to %s LFPS detection on USB3#%u: %d\n",
594 enable ? "enable" : "disable", port, err);
595 rsp.cmd = MBOX_CMD_NAK;
597 rsp.cmd = MBOX_CMD_ACK;
600 rsp.data = msg->data;
604 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
609 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
611 err = tegra_xusb_mbox_send(tegra, &rsp);
613 dev_err(dev, "failed to send %s: %d\n", cmd, err);
617 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
619 struct tegra_xusb *tegra = data;
620 struct tegra_xusb_mbox_msg msg;
623 mutex_lock(&tegra->lock);
625 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_DATA_OUT);
626 tegra_xusb_mbox_unpack(&msg, value);
628 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
629 value &= ~MBOX_DEST_SMI;
630 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
632 /* clear mailbox owner if no ACK/NAK is required */
633 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
634 fpci_writel(tegra, MBOX_OWNER_NONE, XUSB_CFG_ARU_MBOX_OWNER);
636 tegra_xusb_mbox_handle(tegra, &msg);
638 mutex_unlock(&tegra->lock);
642 static void tegra_xusb_ipfs_config(struct tegra_xusb *tegra,
643 struct resource *regs)
647 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
648 value |= IPFS_EN_FPCI;
649 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
651 usleep_range(10, 20);
653 /* Program BAR0 space */
654 value = fpci_readl(tegra, XUSB_CFG_4);
655 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
656 value |= regs->start & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
657 fpci_writel(tegra, value, XUSB_CFG_4);
659 usleep_range(100, 200);
661 /* Enable bus master */
662 value = fpci_readl(tegra, XUSB_CFG_1);
663 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
664 fpci_writel(tegra, value, XUSB_CFG_1);
666 /* Enable interrupt assertion */
667 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
668 value |= IPFS_IP_INT_MASK;
669 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
672 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
675 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
679 err = clk_prepare_enable(tegra->pll_e);
683 err = clk_prepare_enable(tegra->host_clk);
687 err = clk_prepare_enable(tegra->ss_clk);
691 err = clk_prepare_enable(tegra->falcon_clk);
695 err = clk_prepare_enable(tegra->fs_src_clk);
699 err = clk_prepare_enable(tegra->hs_src_clk);
703 if (tegra->soc->scale_ss_clock) {
704 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
712 clk_disable_unprepare(tegra->hs_src_clk);
714 clk_disable_unprepare(tegra->fs_src_clk);
716 clk_disable_unprepare(tegra->falcon_clk);
718 clk_disable_unprepare(tegra->ss_clk);
720 clk_disable_unprepare(tegra->host_clk);
722 clk_disable_unprepare(tegra->pll_e);
726 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
728 clk_disable_unprepare(tegra->pll_e);
729 clk_disable_unprepare(tegra->host_clk);
730 clk_disable_unprepare(tegra->ss_clk);
731 clk_disable_unprepare(tegra->falcon_clk);
732 clk_disable_unprepare(tegra->fs_src_clk);
733 clk_disable_unprepare(tegra->hs_src_clk);
736 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
741 for (i = 0; i < tegra->num_phys; i++) {
742 err = phy_init(tegra->phys[i]);
746 err = phy_power_on(tegra->phys[i]);
748 phy_exit(tegra->phys[i]);
757 phy_power_off(tegra->phys[i]);
758 phy_exit(tegra->phys[i]);
764 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
768 for (i = 0; i < tegra->num_phys; i++) {
769 phy_power_off(tegra->phys[i]);
770 phy_exit(tegra->phys[i]);
774 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
776 unsigned int code_tag_blocks, code_size_blocks, code_blocks;
777 struct tegra_xusb_fw_header *header;
778 struct device *dev = tegra->dev;
779 const struct firmware *fw;
780 unsigned long timeout;
787 err = reject_firmware(&fw, tegra->soc->firmware, tegra->dev);
789 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
793 /* Load Falcon controller with its firmware. */
794 header = (struct tegra_xusb_fw_header *)fw->data;
795 tegra->fw.size = le32_to_cpu(header->fwimg_len);
797 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
798 &tegra->fw.phys, GFP_KERNEL);
799 if (!tegra->fw.virt) {
800 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
801 release_firmware(fw);
805 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
806 memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
807 release_firmware(fw);
809 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
810 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
811 csb_readl(tegra, XUSB_FALC_CPUCTL));
815 /* Program the size of DFI into ILOAD_ATTR. */
816 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
819 * Boot code of the firmware reads the ILOAD_BASE registers
820 * to get to the start of the DFI in system memory.
822 address = tegra->fw.phys + sizeof(*header);
823 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
824 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
826 /* Set BOOTPATH to 1 in APMAP. */
827 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
829 /* Invalidate L2IMEM. */
830 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
833 * Initiate fetch of bootcode from system memory into L2IMEM.
834 * Program bootcode location and size in system memory.
836 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
838 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
840 code_blocks = code_tag_blocks + code_size_blocks;
842 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
843 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
844 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
845 L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
846 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
848 /* Trigger L2IMEM load operation. */
849 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
850 XUSB_CSB_MP_L2IMEMOP_TRIG);
852 /* Setup Falcon auto-fill. */
853 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
855 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
856 IMFILLRNG1_TAG_LO_SHIFT) |
857 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
858 IMFILLRNG1_TAG_HI_SHIFT);
859 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
861 csb_writel(tegra, 0, XUSB_FALC_DMACTL);
865 csb_writel(tegra, le32_to_cpu(header->boot_codetag),
868 /* Boot Falcon CPU and wait for it to enter the STOPPED (idle) state. */
869 timeout = jiffies + msecs_to_jiffies(5);
871 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
873 while (time_before(jiffies, timeout)) {
874 if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED)
877 usleep_range(100, 200);
880 if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) {
881 dev_err(dev, "Falcon failed to start, state: %#x\n",
882 csb_readl(tegra, XUSB_FALC_CPUCTL));
886 timestamp = le32_to_cpu(header->fwimg_created_time);
887 time_to_tm(timestamp, 0, &time);
889 dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
890 time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
891 time.tm_hour, time.tm_min, time.tm_sec);
896 static int tegra_xusb_probe(struct platform_device *pdev)
898 struct tegra_xusb_mbox_msg msg;
899 struct resource *res, *regs;
900 struct tegra_xusb *tegra;
901 struct xhci_hcd *xhci;
902 unsigned int i, j, k;
906 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
908 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
912 tegra->soc = of_device_get_match_data(&pdev->dev);
913 mutex_init(&tegra->lock);
914 tegra->dev = &pdev->dev;
916 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
917 tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
918 if (IS_ERR(tegra->regs))
919 return PTR_ERR(tegra->regs);
921 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
922 tegra->fpci_base = devm_ioremap_resource(&pdev->dev, res);
923 if (IS_ERR(tegra->fpci_base))
924 return PTR_ERR(tegra->fpci_base);
926 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
927 tegra->ipfs_base = devm_ioremap_resource(&pdev->dev, res);
928 if (IS_ERR(tegra->ipfs_base))
929 return PTR_ERR(tegra->ipfs_base);
931 tegra->xhci_irq = platform_get_irq(pdev, 0);
932 if (tegra->xhci_irq < 0)
933 return tegra->xhci_irq;
935 tegra->mbox_irq = platform_get_irq(pdev, 1);
936 if (tegra->mbox_irq < 0)
937 return tegra->mbox_irq;
939 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
940 if (IS_ERR(tegra->padctl))
941 return PTR_ERR(tegra->padctl);
943 tegra->host_rst = devm_reset_control_get(&pdev->dev, "xusb_host");
944 if (IS_ERR(tegra->host_rst)) {
945 err = PTR_ERR(tegra->host_rst);
946 dev_err(&pdev->dev, "failed to get xusb_host reset: %d\n", err);
950 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
951 if (IS_ERR(tegra->ss_rst)) {
952 err = PTR_ERR(tegra->ss_rst);
953 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", err);
957 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
958 if (IS_ERR(tegra->host_clk)) {
959 err = PTR_ERR(tegra->host_clk);
960 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
964 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
965 if (IS_ERR(tegra->falcon_clk)) {
966 err = PTR_ERR(tegra->falcon_clk);
967 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
971 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
972 if (IS_ERR(tegra->ss_clk)) {
973 err = PTR_ERR(tegra->ss_clk);
974 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
978 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
979 if (IS_ERR(tegra->ss_src_clk)) {
980 err = PTR_ERR(tegra->ss_src_clk);
981 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
985 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
986 if (IS_ERR(tegra->hs_src_clk)) {
987 err = PTR_ERR(tegra->hs_src_clk);
988 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
992 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
993 if (IS_ERR(tegra->fs_src_clk)) {
994 err = PTR_ERR(tegra->fs_src_clk);
995 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
999 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1000 if (IS_ERR(tegra->pll_u_480m)) {
1001 err = PTR_ERR(tegra->pll_u_480m);
1002 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1006 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1007 if (IS_ERR(tegra->clk_m)) {
1008 err = PTR_ERR(tegra->clk_m);
1009 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1013 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1014 if (IS_ERR(tegra->pll_e)) {
1015 err = PTR_ERR(tegra->pll_e);
1016 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1020 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1021 sizeof(*tegra->supplies), GFP_KERNEL);
1022 if (!tegra->supplies) {
1027 for (i = 0; i < tegra->soc->num_supplies; i++)
1028 tegra->supplies[i].supply = tegra->soc->supply_names[i];
1030 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1033 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1037 for (i = 0; i < tegra->soc->num_types; i++)
1038 tegra->num_phys += tegra->soc->phy_types[i].num;
1040 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1041 sizeof(*tegra->phys), GFP_KERNEL);
1047 for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1050 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1051 snprintf(prop, sizeof(prop), "%s-%d",
1052 tegra->soc->phy_types[i].name, j);
1054 phy = devm_phy_optional_get(&pdev->dev, prop);
1057 "failed to get PHY %s: %ld\n", prop,
1063 tegra->phys[k++] = phy;
1067 err = tegra_xusb_clk_enable(tegra);
1069 dev_err(&pdev->dev, "failed to enable clocks: %d\n", err);
1073 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
1075 dev_err(&pdev->dev, "failed to enable regulators: %d\n", err);
1079 err = tegra_xusb_phy_enable(tegra);
1081 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1082 goto disable_regulator;
1085 tegra_xusb_ipfs_config(tegra, regs);
1087 err = tegra_xusb_load_firmware(tegra);
1089 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1093 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1094 dev_name(&pdev->dev));
1101 * This must happen after usb_create_hcd(), because usb_create_hcd()
1102 * will overwrite the drvdata of the device with the hcd it creates.
1104 platform_set_drvdata(pdev, tegra);
1106 tegra->hcd->regs = tegra->regs;
1107 tegra->hcd->rsrc_start = regs->start;
1108 tegra->hcd->rsrc_len = resource_size(regs);
1110 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1112 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1116 device_wakeup_enable(tegra->hcd->self.controller);
1118 xhci = hcd_to_xhci(tegra->hcd);
1120 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1122 dev_name(&pdev->dev),
1124 if (!xhci->shared_hcd) {
1125 dev_err(&pdev->dev, "failed to create shared HCD\n");
1130 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1132 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1136 mutex_lock(&tegra->lock);
1138 /* Enable firmware messages from controller. */
1139 msg.cmd = MBOX_CMD_MSG_ENABLED;
1142 err = tegra_xusb_mbox_send(tegra, &msg);
1144 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1145 mutex_unlock(&tegra->lock);
1149 mutex_unlock(&tegra->lock);
1151 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1152 tegra_xusb_mbox_irq,
1153 tegra_xusb_mbox_thread, 0,
1154 dev_name(&pdev->dev), tegra);
1156 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1163 usb_remove_hcd(xhci->shared_hcd);
1165 usb_put_hcd(xhci->shared_hcd);
1167 usb_remove_hcd(tegra->hcd);
1169 usb_put_hcd(tegra->hcd);
1171 tegra_xusb_phy_disable(tegra);
1173 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1175 tegra_xusb_clk_disable(tegra);
1177 tegra_xusb_padctl_put(tegra->padctl);
1181 static int tegra_xusb_remove(struct platform_device *pdev)
1183 struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1184 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1186 usb_remove_hcd(xhci->shared_hcd);
1187 usb_put_hcd(xhci->shared_hcd);
1188 usb_remove_hcd(tegra->hcd);
1189 usb_put_hcd(tegra->hcd);
1191 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1194 tegra_xusb_phy_disable(tegra);
1195 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1196 tegra_xusb_clk_disable(tegra);
1198 tegra_xusb_padctl_put(tegra->padctl);
1203 #ifdef CONFIG_PM_SLEEP
1204 static int tegra_xusb_suspend(struct device *dev)
1206 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1207 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1208 bool wakeup = device_may_wakeup(dev);
1210 /* TODO: Powergate controller across suspend/resume. */
1211 return xhci_suspend(xhci, wakeup);
1214 static int tegra_xusb_resume(struct device *dev)
1216 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1217 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1219 return xhci_resume(xhci, 0);
1223 static const struct dev_pm_ops tegra_xusb_pm_ops = {
1224 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
1227 static const char * const tegra124_supply_names[] = {
1235 "hvdd-usb-ss-pll-e",
1238 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
1239 { .name = "usb3", .num = 2, },
1240 { .name = "usb2", .num = 3, },
1241 { .name = "hsic", .num = 2, },
1244 static const struct tegra_xusb_soc tegra124_soc = {
1245 .firmware = "/*(DEBLOBBED)*/",
1246 .supply_names = tegra124_supply_names,
1247 .num_supplies = ARRAY_SIZE(tegra124_supply_names),
1248 .phy_types = tegra124_phy_types,
1249 .num_types = ARRAY_SIZE(tegra124_phy_types),
1251 .usb2 = { .offset = 4, .count = 4, },
1252 .hsic = { .offset = 6, .count = 2, },
1253 .usb3 = { .offset = 0, .count = 2, },
1255 .scale_ss_clock = true,
1259 static const char * const tegra210_supply_names[] = {
1269 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
1270 { .name = "usb3", .num = 4, },
1271 { .name = "usb2", .num = 4, },
1272 { .name = "hsic", .num = 1, },
1275 static const struct tegra_xusb_soc tegra210_soc = {
1276 .firmware = "/*(DEBLOBBED)*/",
1277 .supply_names = tegra210_supply_names,
1278 .num_supplies = ARRAY_SIZE(tegra210_supply_names),
1279 .phy_types = tegra210_phy_types,
1280 .num_types = ARRAY_SIZE(tegra210_phy_types),
1282 .usb2 = { .offset = 4, .count = 4, },
1283 .hsic = { .offset = 8, .count = 1, },
1284 .usb3 = { .offset = 0, .count = 4, },
1286 .scale_ss_clock = false,
1290 static const struct of_device_id tegra_xusb_of_match[] = {
1291 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
1292 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
1295 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
1297 static struct platform_driver tegra_xusb_driver = {
1298 .probe = tegra_xusb_probe,
1299 .remove = tegra_xusb_remove,
1301 .name = "tegra-xusb",
1302 .pm = &tegra_xusb_pm_ops,
1303 .of_match_table = tegra_xusb_of_match,
1307 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
1309 xhci->quirks |= XHCI_PLAT;
1312 static int tegra_xhci_setup(struct usb_hcd *hcd)
1314 return xhci_gen_setup(hcd, tegra_xhci_quirks);
1317 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
1318 .extra_priv_size = sizeof(struct xhci_hcd),
1319 .reset = tegra_xhci_setup,
1322 static int __init tegra_xusb_init(void)
1324 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
1326 return platform_driver_register(&tegra_xusb_driver);
1328 module_init(tegra_xusb_init);
1330 static void __exit tegra_xusb_exit(void)
1332 platform_driver_unregister(&tegra_xusb_driver);
1334 module_exit(tegra_xusb_exit);
1336 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
1337 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
1338 MODULE_LICENSE("GPL v2");