1 // SPDX-License-Identifier: GPL-2.0
3 * NVIDIA Tegra xHCI host controller driver
5 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
6 * Copyright (C) 2014 Google, Inc.
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/firmware.h>
13 #include <linux/interrupt.h>
14 #include <linux/iopoll.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/phy/phy.h>
20 #include <linux/phy/tegra/xusb.h>
21 #include <linux/platform_device.h>
22 #include <linux/usb/ch9.h>
24 #include <linux/pm_domain.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/reset.h>
28 #include <linux/slab.h>
29 #include <linux/usb/otg.h>
30 #include <linux/usb/phy.h>
31 #include <linux/usb/role.h>
32 #include <soc/tegra/pmc.h>
36 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
37 #define TEGRA_XHCI_SS_LOW_SPEED 12000000
39 /* FPCI CFG registers */
40 #define XUSB_CFG_1 0x004
41 #define XUSB_IO_SPACE_EN BIT(0)
42 #define XUSB_MEM_SPACE_EN BIT(1)
43 #define XUSB_BUS_MASTER_EN BIT(2)
44 #define XUSB_CFG_4 0x010
45 #define XUSB_BASE_ADDR_SHIFT 15
46 #define XUSB_BASE_ADDR_MASK 0x1ffff
47 #define XUSB_CFG_16 0x040
48 #define XUSB_CFG_24 0x060
49 #define XUSB_CFG_AXI_CFG 0x0f8
50 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c
51 #define XUSB_CFG_ARU_CONTEXT 0x43c
52 #define XUSB_CFG_ARU_CONTEXT_HS_PLS 0x478
53 #define XUSB_CFG_ARU_CONTEXT_FS_PLS 0x47c
54 #define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED 0x480
55 #define XUSB_CFG_ARU_CONTEXT_HSFS_PP 0x484
56 #define XUSB_CFG_CSB_BASE_ADDR 0x800
58 /* FPCI mailbox registers */
59 /* XUSB_CFG_ARU_MBOX_CMD */
60 #define MBOX_DEST_FALC BIT(27)
61 #define MBOX_DEST_PME BIT(28)
62 #define MBOX_DEST_SMI BIT(29)
63 #define MBOX_DEST_XHCI BIT(30)
64 #define MBOX_INT_EN BIT(31)
65 /* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */
66 #define CMD_DATA_SHIFT 0
67 #define CMD_DATA_MASK 0xffffff
68 #define CMD_TYPE_SHIFT 24
69 #define CMD_TYPE_MASK 0xff
70 /* XUSB_CFG_ARU_MBOX_OWNER */
71 #define MBOX_OWNER_NONE 0
72 #define MBOX_OWNER_FW 1
73 #define MBOX_OWNER_SW 2
74 #define XUSB_CFG_ARU_SMI_INTR 0x428
75 #define MBOX_SMI_INTR_FW_HANG BIT(1)
76 #define MBOX_SMI_INTR_EN BIT(3)
79 #define IPFS_XUSB_HOST_MSI_BAR_SZ_0 0x0c0
80 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0 0x0c4
81 #define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0 0x0c8
82 #define IPFS_XUSB_HOST_MSI_VEC0_0 0x100
83 #define IPFS_XUSB_HOST_MSI_EN_VEC0_0 0x140
84 #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180
85 #define IPFS_EN_FPCI BIT(0)
86 #define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0 0x184
87 #define IPFS_XUSB_HOST_INTR_MASK_0 0x188
88 #define IPFS_IP_INT_MASK BIT(16)
89 #define IPFS_XUSB_HOST_INTR_ENABLE_0 0x198
90 #define IPFS_XUSB_HOST_UFPCI_CONFIG_0 0x19c
91 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc
92 #define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0 0x1dc
94 #define CSB_PAGE_SELECT_MASK 0x7fffff
95 #define CSB_PAGE_SELECT_SHIFT 9
96 #define CSB_PAGE_OFFSET_MASK 0x1ff
97 #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \
99 #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK)
101 /* Falcon CSB registers */
102 #define XUSB_FALC_CPUCTL 0x100
103 #define CPUCTL_STARTCPU BIT(1)
104 #define CPUCTL_STATE_HALTED BIT(4)
105 #define CPUCTL_STATE_STOPPED BIT(5)
106 #define XUSB_FALC_BOOTVEC 0x104
107 #define XUSB_FALC_DMACTL 0x10c
108 #define XUSB_FALC_IMFILLRNG1 0x154
109 #define IMFILLRNG1_TAG_MASK 0xffff
110 #define IMFILLRNG1_TAG_LO_SHIFT 0
111 #define IMFILLRNG1_TAG_HI_SHIFT 16
112 #define XUSB_FALC_IMFILLCTL 0x158
114 /* MP CSB registers */
115 #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00
116 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04
117 #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08
118 #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10
119 #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8
120 #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff
121 #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24
122 #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff
123 #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14
124 #define L2IMEMOP_ACTION_SHIFT 24
125 #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT)
126 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT)
127 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101a18
128 #define L2IMEMOP_RESULT_VLD BIT(31)
129 #define XUSB_CSB_MP_APMAP 0x10181c
130 #define APMAP_BOOTPATH BIT(31)
132 #define IMEM_BLOCK_SIZE 256
134 struct tegra_xusb_fw_header {
135 __le32 boot_loadaddr_in_imem;
136 __le32 boot_codedfi_offset;
138 __le32 boot_codesize;
140 __le16 reqphys_memsize;
141 __le16 alloc_phys_memsize;
142 __le32 rodata_img_offset;
143 __le32 rodata_section_start;
144 __le32 rodata_section_end;
147 __le32 fwimg_created_time;
148 __le32 imem_resident_start;
149 __le32 imem_resident_end;
150 __le32 idirect_start;
152 __le32 l2_imem_start;
157 __le32 phys_addr_log_buffer;
158 __le32 total_log_entries;
163 __le32 ss_low_power_entry_timeout;
165 u8 padding[139]; /* Pad to 256 bytes */
168 struct tegra_xusb_phy_type {
173 struct tegra_xusb_mbox_regs {
180 struct tegra_xusb_context_soc {
182 const unsigned int *offsets;
183 unsigned int num_offsets;
187 const unsigned int *offsets;
188 unsigned int num_offsets;
192 struct tegra_xusb_soc {
193 const char *firmware;
194 const char * const *supply_names;
195 unsigned int num_supplies;
196 const struct tegra_xusb_phy_type *phy_types;
197 unsigned int num_types;
198 const struct tegra_xusb_context_soc *context;
204 } usb2, ulpi, hsic, usb3;
207 struct tegra_xusb_mbox_regs mbox;
215 struct tegra_xusb_context {
231 void __iomem *ipfs_base;
232 void __iomem *fpci_base;
234 const struct tegra_xusb_soc *soc;
236 struct regulator_bulk_data *supplies;
238 struct tegra_xusb_padctl *padctl;
240 struct clk *host_clk;
241 struct clk *falcon_clk;
243 struct clk *ss_src_clk;
244 struct clk *hs_src_clk;
245 struct clk *fs_src_clk;
246 struct clk *pll_u_480m;
250 struct reset_control *host_rst;
251 struct reset_control *ss_rst;
253 struct device *genpd_dev_host;
254 struct device *genpd_dev_ss;
258 unsigned int num_phys;
260 struct usb_phy **usbphy;
261 unsigned int num_usb_phys;
265 struct notifier_block id_nb;
266 struct work_struct id_work;
268 /* Firmware loading related */
276 struct tegra_xusb_context context;
279 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
281 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
283 return readl(tegra->fpci_base + offset);
286 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
289 writel(value, tegra->fpci_base + offset);
292 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
294 return readl(tegra->ipfs_base + offset);
297 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
300 writel(value, tegra->ipfs_base + offset);
303 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
305 u32 page = CSB_PAGE_SELECT(offset);
306 u32 ofs = CSB_PAGE_OFFSET(offset);
308 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
310 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
313 static void csb_writel(struct tegra_xusb *tegra, u32 value,
316 u32 page = CSB_PAGE_SELECT(offset);
317 u32 ofs = CSB_PAGE_OFFSET(offset);
319 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
320 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
323 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
326 unsigned long new_parent_rate, old_parent_rate;
327 struct clk *clk = tegra->ss_src_clk;
331 if (clk_get_rate(clk) == rate)
335 case TEGRA_XHCI_SS_HIGH_SPEED:
337 * Reparent to PLLU_480M. Set divider first to avoid
340 old_parent_rate = clk_get_rate(clk_get_parent(clk));
341 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
342 div = new_parent_rate / rate;
344 err = clk_set_rate(clk, old_parent_rate / div);
348 err = clk_set_parent(clk, tegra->pll_u_480m);
353 * The rate should already be correct, but set it again just
356 err = clk_set_rate(clk, rate);
362 case TEGRA_XHCI_SS_LOW_SPEED:
363 /* Reparent to CLK_M */
364 err = clk_set_parent(clk, tegra->clk_m);
368 err = clk_set_rate(clk, rate);
375 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
379 if (clk_get_rate(clk) != rate) {
380 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
387 static unsigned long extract_field(u32 value, unsigned int start,
390 return (value >> start) & ((1 << count) - 1);
393 /* Command requests from the firmware */
394 enum tegra_xusb_mbox_cmd {
395 MBOX_CMD_MSG_ENABLED = 1,
396 MBOX_CMD_INC_FALC_CLOCK,
397 MBOX_CMD_DEC_FALC_CLOCK,
398 MBOX_CMD_INC_SSPI_CLOCK,
399 MBOX_CMD_DEC_SSPI_CLOCK,
400 MBOX_CMD_SET_BW, /* no ACK/NAK required */
401 MBOX_CMD_SET_SS_PWR_GATING,
402 MBOX_CMD_SET_SS_PWR_UNGATING,
403 MBOX_CMD_SAVE_DFE_CTLE_CTX,
404 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
405 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
406 MBOX_CMD_START_HSIC_IDLE,
407 MBOX_CMD_STOP_HSIC_IDLE,
408 MBOX_CMD_DBC_WAKE_STACK, /* unused */
409 MBOX_CMD_HSIC_PRETEND_CONNECT,
411 MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
412 MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
416 /* Response message to above commands */
421 struct tegra_xusb_mbox_msg {
426 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
428 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
429 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
431 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
434 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
435 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
438 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
441 case MBOX_CMD_SET_BW:
451 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
452 const struct tegra_xusb_mbox_msg *msg)
454 bool wait_for_idle = false;
458 * Acquire the mailbox. The firmware still owns the mailbox for
461 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
462 value = fpci_readl(tegra, tegra->soc->mbox.owner);
463 if (value != MBOX_OWNER_NONE) {
464 dev_err(tegra->dev, "mailbox is busy\n");
468 fpci_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner);
470 value = fpci_readl(tegra, tegra->soc->mbox.owner);
471 if (value != MBOX_OWNER_SW) {
472 dev_err(tegra->dev, "failed to acquire mailbox\n");
476 wait_for_idle = true;
479 value = tegra_xusb_mbox_pack(msg);
480 fpci_writel(tegra, value, tegra->soc->mbox.data_in);
482 value = fpci_readl(tegra, tegra->soc->mbox.cmd);
483 value |= MBOX_INT_EN | MBOX_DEST_FALC;
484 fpci_writel(tegra, value, tegra->soc->mbox.cmd);
487 unsigned long timeout = jiffies + msecs_to_jiffies(250);
489 while (time_before(jiffies, timeout)) {
490 value = fpci_readl(tegra, tegra->soc->mbox.owner);
491 if (value == MBOX_OWNER_NONE)
494 usleep_range(10, 20);
497 if (time_after(jiffies, timeout))
498 value = fpci_readl(tegra, tegra->soc->mbox.owner);
500 if (value != MBOX_OWNER_NONE)
507 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
509 struct tegra_xusb *tegra = data;
512 /* clear mailbox interrupts */
513 value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
514 fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
516 if (value & MBOX_SMI_INTR_FW_HANG)
517 dev_err(tegra->dev, "controller firmware hang\n");
519 return IRQ_WAKE_THREAD;
522 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
523 const struct tegra_xusb_mbox_msg *msg)
525 struct tegra_xusb_padctl *padctl = tegra->padctl;
526 const struct tegra_xusb_soc *soc = tegra->soc;
527 struct device *dev = tegra->dev;
528 struct tegra_xusb_mbox_msg rsp;
534 memset(&rsp, 0, sizeof(rsp));
537 case MBOX_CMD_INC_FALC_CLOCK:
538 case MBOX_CMD_DEC_FALC_CLOCK:
539 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
540 if (rsp.data != msg->data)
541 rsp.cmd = MBOX_CMD_NAK;
543 rsp.cmd = MBOX_CMD_ACK;
547 case MBOX_CMD_INC_SSPI_CLOCK:
548 case MBOX_CMD_DEC_SSPI_CLOCK:
549 if (tegra->soc->scale_ss_clock) {
550 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
552 rsp.cmd = MBOX_CMD_NAK;
554 rsp.cmd = MBOX_CMD_ACK;
556 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
558 rsp.cmd = MBOX_CMD_ACK;
559 rsp.data = msg->data;
564 case MBOX_CMD_SET_BW:
566 * TODO: Request bandwidth once EMC scaling is supported.
567 * Ignore for now since ACK/NAK is not required for SET_BW
572 case MBOX_CMD_SAVE_DFE_CTLE_CTX:
573 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
575 dev_err(dev, "failed to save context for USB3#%u: %d\n",
577 rsp.cmd = MBOX_CMD_NAK;
579 rsp.cmd = MBOX_CMD_ACK;
582 rsp.data = msg->data;
585 case MBOX_CMD_START_HSIC_IDLE:
586 case MBOX_CMD_STOP_HSIC_IDLE:
587 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
592 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
593 soc->ports.hsic.count);
595 for_each_set_bit(port, &mask, 32) {
596 err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
603 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
604 idle ? "idle" : "busy", err);
605 rsp.cmd = MBOX_CMD_NAK;
607 rsp.cmd = MBOX_CMD_ACK;
610 rsp.data = msg->data;
613 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
614 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
615 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
620 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
621 soc->ports.usb3.count);
623 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
624 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
631 * wait 500us for LFPS detector to be disabled before
635 usleep_range(500, 1000);
640 "failed to %s LFPS detection on USB3#%u: %d\n",
641 enable ? "enable" : "disable", port, err);
642 rsp.cmd = MBOX_CMD_NAK;
644 rsp.cmd = MBOX_CMD_ACK;
647 rsp.data = msg->data;
651 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
656 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
658 err = tegra_xusb_mbox_send(tegra, &rsp);
660 dev_err(dev, "failed to send %s: %d\n", cmd, err);
664 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
666 struct tegra_xusb *tegra = data;
667 struct tegra_xusb_mbox_msg msg;
670 mutex_lock(&tegra->lock);
672 if (pm_runtime_suspended(tegra->dev) || tegra->suspended)
675 value = fpci_readl(tegra, tegra->soc->mbox.data_out);
676 tegra_xusb_mbox_unpack(&msg, value);
678 value = fpci_readl(tegra, tegra->soc->mbox.cmd);
679 value &= ~MBOX_DEST_SMI;
680 fpci_writel(tegra, value, tegra->soc->mbox.cmd);
682 /* clear mailbox owner if no ACK/NAK is required */
683 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
684 fpci_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner);
686 tegra_xusb_mbox_handle(tegra, &msg);
689 mutex_unlock(&tegra->lock);
693 static void tegra_xusb_config(struct tegra_xusb *tegra)
695 u32 regs = tegra->hcd->rsrc_start;
698 if (tegra->soc->has_ipfs) {
699 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
700 value |= IPFS_EN_FPCI;
701 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
703 usleep_range(10, 20);
706 /* Program BAR0 space */
707 value = fpci_readl(tegra, XUSB_CFG_4);
708 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
709 value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
710 fpci_writel(tegra, value, XUSB_CFG_4);
712 usleep_range(100, 200);
714 /* Enable bus master */
715 value = fpci_readl(tegra, XUSB_CFG_1);
716 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
717 fpci_writel(tegra, value, XUSB_CFG_1);
719 if (tegra->soc->has_ipfs) {
720 /* Enable interrupt assertion */
721 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
722 value |= IPFS_IP_INT_MASK;
723 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
726 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
730 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
734 err = clk_prepare_enable(tegra->pll_e);
738 err = clk_prepare_enable(tegra->host_clk);
742 err = clk_prepare_enable(tegra->ss_clk);
746 err = clk_prepare_enable(tegra->falcon_clk);
750 err = clk_prepare_enable(tegra->fs_src_clk);
754 err = clk_prepare_enable(tegra->hs_src_clk);
758 if (tegra->soc->scale_ss_clock) {
759 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
767 clk_disable_unprepare(tegra->hs_src_clk);
769 clk_disable_unprepare(tegra->fs_src_clk);
771 clk_disable_unprepare(tegra->falcon_clk);
773 clk_disable_unprepare(tegra->ss_clk);
775 clk_disable_unprepare(tegra->host_clk);
777 clk_disable_unprepare(tegra->pll_e);
781 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
783 clk_disable_unprepare(tegra->pll_e);
784 clk_disable_unprepare(tegra->host_clk);
785 clk_disable_unprepare(tegra->ss_clk);
786 clk_disable_unprepare(tegra->falcon_clk);
787 clk_disable_unprepare(tegra->fs_src_clk);
788 clk_disable_unprepare(tegra->hs_src_clk);
791 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
796 for (i = 0; i < tegra->num_phys; i++) {
797 err = phy_init(tegra->phys[i]);
801 err = phy_power_on(tegra->phys[i]);
803 phy_exit(tegra->phys[i]);
812 phy_power_off(tegra->phys[i]);
813 phy_exit(tegra->phys[i]);
819 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
823 for (i = 0; i < tegra->num_phys; i++) {
824 phy_power_off(tegra->phys[i]);
825 phy_exit(tegra->phys[i]);
829 #ifdef CONFIG_PM_SLEEP
830 static int tegra_xusb_init_context(struct tegra_xusb *tegra)
832 const struct tegra_xusb_context_soc *soc = tegra->soc->context;
834 tegra->context.ipfs = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets,
835 sizeof(u32), GFP_KERNEL);
836 if (!tegra->context.ipfs)
839 tegra->context.fpci = devm_kcalloc(tegra->dev, soc->fpci.num_offsets,
840 sizeof(u32), GFP_KERNEL);
841 if (!tegra->context.fpci)
847 static inline int tegra_xusb_init_context(struct tegra_xusb *tegra)
853 static int tegra_xusb_request_firmware(struct tegra_xusb *tegra)
855 struct tegra_xusb_fw_header *header;
856 const struct firmware *fw;
859 err = reject_firmware(&fw, tegra->soc->firmware, tegra->dev);
861 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
865 /* Load Falcon controller with its firmware. */
866 header = (struct tegra_xusb_fw_header *)fw->data;
867 tegra->fw.size = le32_to_cpu(header->fwimg_len);
869 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
870 &tegra->fw.phys, GFP_KERNEL);
871 if (!tegra->fw.virt) {
872 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
873 release_firmware(fw);
877 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
878 memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
879 release_firmware(fw);
884 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
886 unsigned int code_tag_blocks, code_size_blocks, code_blocks;
887 struct xhci_cap_regs __iomem *cap = tegra->regs;
888 struct tegra_xusb_fw_header *header;
889 struct device *dev = tegra->dev;
890 struct xhci_op_regs __iomem *op;
891 unsigned long timeout;
897 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
898 op = tegra->regs + HC_LENGTH(readl(&cap->hc_capbase));
900 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
901 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
902 csb_readl(tegra, XUSB_FALC_CPUCTL));
906 /* Program the size of DFI into ILOAD_ATTR. */
907 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
910 * Boot code of the firmware reads the ILOAD_BASE registers
911 * to get to the start of the DFI in system memory.
913 address = tegra->fw.phys + sizeof(*header);
914 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
915 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
917 /* Set BOOTPATH to 1 in APMAP. */
918 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
920 /* Invalidate L2IMEM. */
921 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
924 * Initiate fetch of bootcode from system memory into L2IMEM.
925 * Program bootcode location and size in system memory.
927 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
929 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
931 code_blocks = code_tag_blocks + code_size_blocks;
933 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
934 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
935 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
936 L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
937 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
939 /* Trigger L2IMEM load operation. */
940 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
941 XUSB_CSB_MP_L2IMEMOP_TRIG);
943 /* Setup Falcon auto-fill. */
944 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
946 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
947 IMFILLRNG1_TAG_LO_SHIFT) |
948 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
949 IMFILLRNG1_TAG_HI_SHIFT);
950 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
952 csb_writel(tegra, 0, XUSB_FALC_DMACTL);
954 /* wait for RESULT_VLD to get set */
955 #define tegra_csb_readl(offset) csb_readl(tegra, offset)
956 err = readx_poll_timeout(tegra_csb_readl,
957 XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value,
958 value & L2IMEMOP_RESULT_VLD, 100, 10000);
960 dev_err(dev, "DMA controller not ready %#010x\n", value);
963 #undef tegra_csb_readl
965 csb_writel(tegra, le32_to_cpu(header->boot_codetag),
968 /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */
969 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
971 timeout = jiffies + msecs_to_jiffies(200);
974 value = readl(&op->status);
975 if ((value & STS_CNR) == 0)
978 usleep_range(1000, 2000);
979 } while (time_is_after_jiffies(timeout));
981 value = readl(&op->status);
982 if (value & STS_CNR) {
983 value = csb_readl(tegra, XUSB_FALC_CPUCTL);
984 dev_err(dev, "XHCI controller not read: %#010x\n", value);
988 timestamp = le32_to_cpu(header->fwimg_created_time);
990 dev_info(dev, "Firmware timestamp: %ptTs UTC\n", ×tamp);
995 static void tegra_xusb_powerdomain_remove(struct device *dev,
996 struct tegra_xusb *tegra)
998 if (!tegra->use_genpd)
1001 if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss))
1002 dev_pm_domain_detach(tegra->genpd_dev_ss, true);
1003 if (!IS_ERR_OR_NULL(tegra->genpd_dev_host))
1004 dev_pm_domain_detach(tegra->genpd_dev_host, true);
1007 static int tegra_xusb_powerdomain_init(struct device *dev,
1008 struct tegra_xusb *tegra)
1012 tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host");
1013 if (IS_ERR(tegra->genpd_dev_host)) {
1014 err = PTR_ERR(tegra->genpd_dev_host);
1015 dev_err(dev, "failed to get host pm-domain: %d\n", err);
1019 tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss");
1020 if (IS_ERR(tegra->genpd_dev_ss)) {
1021 err = PTR_ERR(tegra->genpd_dev_ss);
1022 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err);
1026 tegra->use_genpd = true;
1031 static int tegra_xusb_unpowergate_partitions(struct tegra_xusb *tegra)
1033 struct device *dev = tegra->dev;
1036 if (tegra->use_genpd) {
1037 rc = pm_runtime_resume_and_get(tegra->genpd_dev_ss);
1039 dev_err(dev, "failed to enable XUSB SS partition\n");
1043 rc = pm_runtime_resume_and_get(tegra->genpd_dev_host);
1045 dev_err(dev, "failed to enable XUSB Host partition\n");
1046 pm_runtime_put_sync(tegra->genpd_dev_ss);
1050 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
1054 dev_err(dev, "failed to enable XUSB SS partition\n");
1058 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1062 dev_err(dev, "failed to enable XUSB Host partition\n");
1063 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1071 static int tegra_xusb_powergate_partitions(struct tegra_xusb *tegra)
1073 struct device *dev = tegra->dev;
1076 if (tegra->use_genpd) {
1077 rc = pm_runtime_put_sync(tegra->genpd_dev_host);
1079 dev_err(dev, "failed to disable XUSB Host partition\n");
1083 rc = pm_runtime_put_sync(tegra->genpd_dev_ss);
1085 dev_err(dev, "failed to disable XUSB SS partition\n");
1086 pm_runtime_get_sync(tegra->genpd_dev_host);
1090 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1092 dev_err(dev, "failed to disable XUSB Host partition\n");
1096 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1098 dev_err(dev, "failed to disable XUSB SS partition\n");
1099 tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1109 static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1111 struct tegra_xusb_mbox_msg msg;
1114 /* Enable firmware messages from controller. */
1115 msg.cmd = MBOX_CMD_MSG_ENABLED;
1118 err = tegra_xusb_mbox_send(tegra, &msg);
1120 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
1125 static irqreturn_t tegra_xusb_padctl_irq(int irq, void *data)
1127 struct tegra_xusb *tegra = data;
1129 mutex_lock(&tegra->lock);
1131 if (tegra->suspended) {
1132 mutex_unlock(&tegra->lock);
1136 mutex_unlock(&tegra->lock);
1138 pm_runtime_resume(tegra->dev);
1143 static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1147 mutex_lock(&tegra->lock);
1148 err = __tegra_xusb_enable_firmware_messages(tegra);
1149 mutex_unlock(&tegra->lock);
1154 static void tegra_xhci_set_port_power(struct tegra_xusb *tegra, bool main,
1157 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1158 struct usb_hcd *hcd = main ? xhci->main_hcd : xhci->shared_hcd;
1159 unsigned int wait = (!main && !set) ? 1000 : 10;
1160 u16 typeReq = set ? SetPortFeature : ClearPortFeature;
1161 u16 wIndex = main ? tegra->otg_usb2_port + 1 : tegra->otg_usb3_port + 1;
1163 u32 stat_power = main ? USB_PORT_STAT_POWER : USB_SS_PORT_STAT_POWER;
1164 u32 status_val = set ? stat_power : 0;
1166 dev_dbg(tegra->dev, "%s():%s %s port power\n", __func__,
1167 set ? "set" : "clear", main ? "HS" : "SS");
1169 hcd->driver->hub_control(hcd, typeReq, USB_PORT_FEAT_POWER, wIndex,
1173 tegra_xhci_hc_driver.hub_control(hcd, GetPortStatus, 0, wIndex,
1174 (char *) &status, sizeof(status));
1175 if (status_val == (status & stat_power))
1179 usleep_range(600, 700);
1181 usleep_range(10, 20);
1182 } while (--wait > 0);
1184 if (status_val != (status & stat_power))
1185 dev_info(tegra->dev, "failed to %s %s PP %d\n",
1186 set ? "set" : "clear",
1187 main ? "HS" : "SS", status);
1190 static struct phy *tegra_xusb_get_phy(struct tegra_xusb *tegra, char *name,
1193 unsigned int i, phy_count = 0;
1195 for (i = 0; i < tegra->soc->num_types; i++) {
1196 if (!strncmp(tegra->soc->phy_types[i].name, name,
1198 return tegra->phys[phy_count+port];
1200 phy_count += tegra->soc->phy_types[i].num;
1206 static void tegra_xhci_id_work(struct work_struct *work)
1208 struct tegra_xusb *tegra = container_of(work, struct tegra_xusb,
1210 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1211 struct tegra_xusb_mbox_msg msg;
1212 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2",
1213 tegra->otg_usb2_port);
1217 dev_dbg(tegra->dev, "host mode %s\n", tegra->host_mode ? "on" : "off");
1219 mutex_lock(&tegra->lock);
1221 if (tegra->host_mode)
1222 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_HOST);
1224 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_NONE);
1226 mutex_unlock(&tegra->lock);
1228 if (tegra->host_mode) {
1229 /* switch to host mode */
1230 if (tegra->otg_usb3_port >= 0) {
1231 if (tegra->soc->otg_reset_sspi) {
1233 tegra_xhci_hc_driver.hub_control(
1234 xhci->shared_hcd, GetPortStatus,
1235 0, tegra->otg_usb3_port+1,
1236 (char *) &status, sizeof(status));
1237 if (status & USB_SS_PORT_STAT_POWER)
1238 tegra_xhci_set_port_power(tegra, false,
1241 /* reset OTG port SSPI */
1242 msg.cmd = MBOX_CMD_RESET_SSPI;
1243 msg.data = tegra->otg_usb3_port+1;
1245 ret = tegra_xusb_mbox_send(tegra, &msg);
1247 dev_info(tegra->dev,
1248 "failed to RESET_SSPI %d\n",
1253 tegra_xhci_set_port_power(tegra, false, true);
1256 tegra_xhci_set_port_power(tegra, true, true);
1259 if (tegra->otg_usb3_port >= 0)
1260 tegra_xhci_set_port_power(tegra, false, false);
1262 tegra_xhci_set_port_power(tegra, true, false);
1266 #if IS_ENABLED(CONFIG_PM) || IS_ENABLED(CONFIG_PM_SLEEP)
1267 static bool is_usb2_otg_phy(struct tegra_xusb *tegra, unsigned int index)
1269 return (tegra->usbphy[index] != NULL);
1272 static bool is_usb3_otg_phy(struct tegra_xusb *tegra, unsigned int index)
1274 struct tegra_xusb_padctl *padctl = tegra->padctl;
1278 for (i = 0; i < tegra->num_usb_phys; i++) {
1279 if (is_usb2_otg_phy(tegra, i)) {
1280 port = tegra_xusb_padctl_get_usb3_companion(padctl, i);
1281 if ((port >= 0) && (index == (unsigned int)port))
1289 static bool is_host_mode_phy(struct tegra_xusb *tegra, unsigned int phy_type, unsigned int index)
1291 if (strcmp(tegra->soc->phy_types[phy_type].name, "hsic") == 0)
1294 if (strcmp(tegra->soc->phy_types[phy_type].name, "usb2") == 0) {
1295 if (is_usb2_otg_phy(tegra, index))
1296 return ((index == tegra->otg_usb2_port) && tegra->host_mode);
1301 if (strcmp(tegra->soc->phy_types[phy_type].name, "usb3") == 0) {
1302 if (is_usb3_otg_phy(tegra, index))
1303 return ((index == tegra->otg_usb3_port) && tegra->host_mode);
1312 static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra,
1313 struct usb_phy *usbphy)
1317 for (i = 0; i < tegra->num_usb_phys; i++) {
1318 if (tegra->usbphy[i] && usbphy == tegra->usbphy[i])
1325 static int tegra_xhci_id_notify(struct notifier_block *nb,
1326 unsigned long action, void *data)
1328 struct tegra_xusb *tegra = container_of(nb, struct tegra_xusb,
1330 struct usb_phy *usbphy = (struct usb_phy *)data;
1332 dev_dbg(tegra->dev, "%s(): action is %d", __func__, usbphy->last_event);
1334 if ((tegra->host_mode && usbphy->last_event == USB_EVENT_ID) ||
1335 (!tegra->host_mode && usbphy->last_event != USB_EVENT_ID)) {
1336 dev_dbg(tegra->dev, "Same role(%d) received. Ignore",
1341 tegra->otg_usb2_port = tegra_xusb_get_usb2_port(tegra, usbphy);
1342 tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion(
1344 tegra->otg_usb2_port);
1346 tegra->host_mode = (usbphy->last_event == USB_EVENT_ID) ? true : false;
1348 schedule_work(&tegra->id_work);
1353 static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra)
1357 tegra->usbphy = devm_kcalloc(tegra->dev, tegra->num_usb_phys,
1358 sizeof(*tegra->usbphy), GFP_KERNEL);
1362 INIT_WORK(&tegra->id_work, tegra_xhci_id_work);
1363 tegra->id_nb.notifier_call = tegra_xhci_id_notify;
1364 tegra->otg_usb2_port = -EINVAL;
1365 tegra->otg_usb3_port = -EINVAL;
1367 for (i = 0; i < tegra->num_usb_phys; i++) {
1368 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i);
1373 tegra->usbphy[i] = devm_usb_get_phy_by_node(tegra->dev,
1376 if (!IS_ERR(tegra->usbphy[i])) {
1377 dev_dbg(tegra->dev, "usbphy-%d registered", i);
1378 otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self);
1381 * usb-phy is optional, continue if its not available.
1383 tegra->usbphy[i] = NULL;
1390 static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra)
1394 cancel_work_sync(&tegra->id_work);
1396 for (i = 0; i < tegra->num_usb_phys; i++)
1397 if (tegra->usbphy[i])
1398 otg_set_host(tegra->usbphy[i]->otg, NULL);
1401 static int tegra_xusb_probe(struct platform_device *pdev)
1403 struct of_phandle_args args;
1404 struct tegra_xusb *tegra;
1405 struct device_node *np;
1406 struct resource *regs;
1407 struct xhci_hcd *xhci;
1408 unsigned int i, j, k;
1412 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
1414 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
1418 tegra->soc = of_device_get_match_data(&pdev->dev);
1419 mutex_init(&tegra->lock);
1420 tegra->dev = &pdev->dev;
1422 err = tegra_xusb_init_context(tegra);
1426 tegra->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
1427 if (IS_ERR(tegra->regs))
1428 return PTR_ERR(tegra->regs);
1430 tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1);
1431 if (IS_ERR(tegra->fpci_base))
1432 return PTR_ERR(tegra->fpci_base);
1434 if (tegra->soc->has_ipfs) {
1435 tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2);
1436 if (IS_ERR(tegra->ipfs_base))
1437 return PTR_ERR(tegra->ipfs_base);
1440 tegra->xhci_irq = platform_get_irq(pdev, 0);
1441 if (tegra->xhci_irq < 0)
1442 return tegra->xhci_irq;
1444 tegra->mbox_irq = platform_get_irq(pdev, 1);
1445 if (tegra->mbox_irq < 0)
1446 return tegra->mbox_irq;
1448 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
1449 if (IS_ERR(tegra->padctl))
1450 return PTR_ERR(tegra->padctl);
1452 np = of_parse_phandle(pdev->dev.of_node, "nvidia,xusb-padctl", 0);
1458 /* Older device-trees don't have padctrl interrupt */
1459 err = of_irq_parse_one(np, 0, &args);
1461 tegra->padctl_irq = of_irq_get(np, 0);
1462 if (tegra->padctl_irq <= 0) {
1463 err = (tegra->padctl_irq == 0) ? -ENODEV : tegra->padctl_irq;
1468 "%pOF is missing an interrupt, disabling PM support\n", np);
1471 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
1472 if (IS_ERR(tegra->host_clk)) {
1473 err = PTR_ERR(tegra->host_clk);
1474 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
1478 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
1479 if (IS_ERR(tegra->falcon_clk)) {
1480 err = PTR_ERR(tegra->falcon_clk);
1481 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
1485 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
1486 if (IS_ERR(tegra->ss_clk)) {
1487 err = PTR_ERR(tegra->ss_clk);
1488 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
1492 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
1493 if (IS_ERR(tegra->ss_src_clk)) {
1494 err = PTR_ERR(tegra->ss_src_clk);
1495 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
1499 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
1500 if (IS_ERR(tegra->hs_src_clk)) {
1501 err = PTR_ERR(tegra->hs_src_clk);
1502 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
1506 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
1507 if (IS_ERR(tegra->fs_src_clk)) {
1508 err = PTR_ERR(tegra->fs_src_clk);
1509 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
1513 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1514 if (IS_ERR(tegra->pll_u_480m)) {
1515 err = PTR_ERR(tegra->pll_u_480m);
1516 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1520 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1521 if (IS_ERR(tegra->clk_m)) {
1522 err = PTR_ERR(tegra->clk_m);
1523 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1527 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1528 if (IS_ERR(tegra->pll_e)) {
1529 err = PTR_ERR(tegra->pll_e);
1530 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1534 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1535 tegra->host_rst = devm_reset_control_get(&pdev->dev,
1537 if (IS_ERR(tegra->host_rst)) {
1538 err = PTR_ERR(tegra->host_rst);
1540 "failed to get xusb_host reset: %d\n", err);
1544 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
1545 if (IS_ERR(tegra->ss_rst)) {
1546 err = PTR_ERR(tegra->ss_rst);
1547 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
1552 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra);
1554 goto put_powerdomains;
1557 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1558 sizeof(*tegra->supplies), GFP_KERNEL);
1559 if (!tegra->supplies) {
1561 goto put_powerdomains;
1564 regulator_bulk_set_supply_names(tegra->supplies,
1565 tegra->soc->supply_names,
1566 tegra->soc->num_supplies);
1568 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1571 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1572 goto put_powerdomains;
1575 for (i = 0; i < tegra->soc->num_types; i++) {
1576 if (!strncmp(tegra->soc->phy_types[i].name, "usb2", 4))
1577 tegra->num_usb_phys = tegra->soc->phy_types[i].num;
1578 tegra->num_phys += tegra->soc->phy_types[i].num;
1581 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1582 sizeof(*tegra->phys), GFP_KERNEL);
1585 goto put_powerdomains;
1588 for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1591 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1592 snprintf(prop, sizeof(prop), "%s-%d",
1593 tegra->soc->phy_types[i].name, j);
1595 phy = devm_phy_optional_get(&pdev->dev, prop);
1598 "failed to get PHY %s: %ld\n", prop,
1601 goto put_powerdomains;
1604 tegra->phys[k++] = phy;
1608 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1609 dev_name(&pdev->dev));
1612 goto put_powerdomains;
1615 tegra->hcd->skip_phy_initialization = 1;
1616 tegra->hcd->regs = tegra->regs;
1617 tegra->hcd->rsrc_start = regs->start;
1618 tegra->hcd->rsrc_len = resource_size(regs);
1621 * This must happen after usb_create_hcd(), because usb_create_hcd()
1622 * will overwrite the drvdata of the device with the hcd it creates.
1624 platform_set_drvdata(pdev, tegra);
1626 err = tegra_xusb_clk_enable(tegra);
1628 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
1632 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
1634 dev_err(tegra->dev, "failed to enable regulators: %d\n", err);
1638 err = tegra_xusb_phy_enable(tegra);
1640 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1641 goto disable_regulator;
1645 * The XUSB Falcon microcontroller can only address 40 bits, so set
1646 * the DMA mask accordingly.
1648 err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40));
1650 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
1654 err = tegra_xusb_request_firmware(tegra);
1656 dev_err(&pdev->dev, "failed to request firmware: %d\n", err);
1660 err = tegra_xusb_unpowergate_partitions(tegra);
1664 tegra_xusb_config(tegra);
1666 err = tegra_xusb_load_firmware(tegra);
1668 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1672 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1674 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1678 device_wakeup_enable(tegra->hcd->self.controller);
1680 xhci = hcd_to_xhci(tegra->hcd);
1682 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1684 dev_name(&pdev->dev),
1686 if (!xhci->shared_hcd) {
1687 dev_err(&pdev->dev, "failed to create shared HCD\n");
1692 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1694 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1698 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1699 tegra_xusb_mbox_irq,
1700 tegra_xusb_mbox_thread, 0,
1701 dev_name(&pdev->dev), tegra);
1703 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1707 if (tegra->padctl_irq) {
1708 err = devm_request_threaded_irq(&pdev->dev, tegra->padctl_irq,
1709 NULL, tegra_xusb_padctl_irq,
1710 IRQF_ONESHOT, dev_name(&pdev->dev),
1713 dev_err(&pdev->dev, "failed to request padctl IRQ: %d\n", err);
1718 err = tegra_xusb_enable_firmware_messages(tegra);
1720 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1724 err = tegra_xusb_init_usb_phy(tegra);
1726 dev_err(&pdev->dev, "failed to init USB PHY: %d\n", err);
1730 /* Enable wake for both USB 2.0 and USB 3.0 roothubs */
1731 device_init_wakeup(&tegra->hcd->self.root_hub->dev, true);
1732 device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, true);
1734 pm_runtime_use_autosuspend(tegra->dev);
1735 pm_runtime_set_autosuspend_delay(tegra->dev, 2000);
1736 pm_runtime_mark_last_busy(tegra->dev);
1737 pm_runtime_set_active(tegra->dev);
1739 if (tegra->padctl_irq) {
1740 device_init_wakeup(tegra->dev, true);
1741 pm_runtime_enable(tegra->dev);
1747 usb_remove_hcd(xhci->shared_hcd);
1749 usb_put_hcd(xhci->shared_hcd);
1751 usb_remove_hcd(tegra->hcd);
1753 tegra_xusb_powergate_partitions(tegra);
1755 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1758 tegra_xusb_phy_disable(tegra);
1760 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1762 tegra_xusb_clk_disable(tegra);
1764 usb_put_hcd(tegra->hcd);
1766 tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1769 tegra_xusb_padctl_put(tegra->padctl);
1773 static int tegra_xusb_remove(struct platform_device *pdev)
1775 struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1776 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1778 tegra_xusb_deinit_usb_phy(tegra);
1780 pm_runtime_get_sync(&pdev->dev);
1781 usb_remove_hcd(xhci->shared_hcd);
1782 usb_put_hcd(xhci->shared_hcd);
1783 xhci->shared_hcd = NULL;
1784 usb_remove_hcd(tegra->hcd);
1785 usb_put_hcd(tegra->hcd);
1787 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1790 if (tegra->padctl_irq)
1791 pm_runtime_disable(&pdev->dev);
1793 pm_runtime_put(&pdev->dev);
1795 tegra_xusb_powergate_partitions(tegra);
1797 tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1799 tegra_xusb_phy_disable(tegra);
1800 tegra_xusb_clk_disable(tegra);
1801 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1802 tegra_xusb_padctl_put(tegra->padctl);
1807 static bool xhci_hub_ports_suspended(struct xhci_hub *hub)
1809 struct device *dev = hub->hcd->self.controller;
1814 for (i = 0; i < hub->num_ports; i++) {
1815 value = readl(hub->ports[i]->addr);
1816 if ((value & PORT_PE) == 0)
1819 if ((value & PORT_PLS_MASK) != XDEV_U3) {
1820 dev_info(dev, "%u-%u isn't suspended: %#010x\n",
1821 hub->hcd->self.busnum, i + 1, value);
1829 static int tegra_xusb_check_ports(struct tegra_xusb *tegra)
1831 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1832 struct xhci_bus_state *bus_state = &xhci->usb2_rhub.bus_state;
1833 unsigned long flags;
1836 if (bus_state->bus_suspended) {
1837 /* xusb_hub_suspend() has just directed one or more USB2 port(s)
1838 * to U3 state, it takes 3ms to enter U3.
1840 usleep_range(3000, 4000);
1843 spin_lock_irqsave(&xhci->lock, flags);
1845 if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) ||
1846 !xhci_hub_ports_suspended(&xhci->usb3_rhub))
1849 spin_unlock_irqrestore(&xhci->lock, flags);
1854 static void tegra_xusb_save_context(struct tegra_xusb *tegra)
1856 const struct tegra_xusb_context_soc *soc = tegra->soc->context;
1857 struct tegra_xusb_context *ctx = &tegra->context;
1860 if (soc->ipfs.num_offsets > 0) {
1861 for (i = 0; i < soc->ipfs.num_offsets; i++)
1862 ctx->ipfs[i] = ipfs_readl(tegra, soc->ipfs.offsets[i]);
1865 if (soc->fpci.num_offsets > 0) {
1866 for (i = 0; i < soc->fpci.num_offsets; i++)
1867 ctx->fpci[i] = fpci_readl(tegra, soc->fpci.offsets[i]);
1871 static void tegra_xusb_restore_context(struct tegra_xusb *tegra)
1873 const struct tegra_xusb_context_soc *soc = tegra->soc->context;
1874 struct tegra_xusb_context *ctx = &tegra->context;
1877 if (soc->fpci.num_offsets > 0) {
1878 for (i = 0; i < soc->fpci.num_offsets; i++)
1879 fpci_writel(tegra, ctx->fpci[i], soc->fpci.offsets[i]);
1882 if (soc->ipfs.num_offsets > 0) {
1883 for (i = 0; i < soc->ipfs.num_offsets; i++)
1884 ipfs_writel(tegra, ctx->ipfs[i], soc->ipfs.offsets[i]);
1888 static enum usb_device_speed tegra_xhci_portsc_to_speed(struct tegra_xusb *tegra, u32 portsc)
1890 if (DEV_LOWSPEED(portsc))
1891 return USB_SPEED_LOW;
1893 if (DEV_HIGHSPEED(portsc))
1894 return USB_SPEED_HIGH;
1896 if (DEV_FULLSPEED(portsc))
1897 return USB_SPEED_FULL;
1899 if (DEV_SUPERSPEED_ANY(portsc))
1900 return USB_SPEED_SUPER;
1902 return USB_SPEED_UNKNOWN;
1905 static void tegra_xhci_enable_phy_sleepwalk_wake(struct tegra_xusb *tegra)
1907 struct tegra_xusb_padctl *padctl = tegra->padctl;
1908 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1909 enum usb_device_speed speed;
1911 unsigned int index, offset;
1912 unsigned int i, j, k;
1913 struct xhci_hub *rhub;
1916 for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1917 if (strcmp(tegra->soc->phy_types[i].name, "usb3") == 0)
1918 rhub = &xhci->usb3_rhub;
1920 rhub = &xhci->usb2_rhub;
1922 if (strcmp(tegra->soc->phy_types[i].name, "hsic") == 0)
1923 offset = tegra->soc->ports.usb2.count;
1927 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1928 phy = tegra->phys[k++];
1935 if (index >= rhub->num_ports)
1938 if (!is_host_mode_phy(tegra, i, j))
1941 portsc = readl(rhub->ports[index]->addr);
1942 speed = tegra_xhci_portsc_to_speed(tegra, portsc);
1943 tegra_xusb_padctl_enable_phy_sleepwalk(padctl, phy, speed);
1944 tegra_xusb_padctl_enable_phy_wake(padctl, phy);
1949 static void tegra_xhci_disable_phy_wake(struct tegra_xusb *tegra)
1951 struct tegra_xusb_padctl *padctl = tegra->padctl;
1954 for (i = 0; i < tegra->num_phys; i++) {
1955 if (!tegra->phys[i])
1958 tegra_xusb_padctl_disable_phy_wake(padctl, tegra->phys[i]);
1962 static void tegra_xhci_disable_phy_sleepwalk(struct tegra_xusb *tegra)
1964 struct tegra_xusb_padctl *padctl = tegra->padctl;
1967 for (i = 0; i < tegra->num_phys; i++) {
1968 if (!tegra->phys[i])
1971 tegra_xusb_padctl_disable_phy_sleepwalk(padctl, tegra->phys[i]);
1975 static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool runtime)
1977 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1978 struct device *dev = tegra->dev;
1979 bool wakeup = runtime ? true : device_may_wakeup(dev);
1984 dev_dbg(dev, "entering ELPG\n");
1986 usbcmd = readl(&xhci->op_regs->command);
1988 writel(usbcmd, &xhci->op_regs->command);
1990 err = tegra_xusb_check_ports(tegra);
1992 dev_err(tegra->dev, "not all ports suspended: %d\n", err);
1996 err = xhci_suspend(xhci, wakeup);
1998 dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err);
2002 tegra_xusb_save_context(tegra);
2005 tegra_xhci_enable_phy_sleepwalk_wake(tegra);
2007 tegra_xusb_powergate_partitions(tegra);
2009 for (i = 0; i < tegra->num_phys; i++) {
2010 if (!tegra->phys[i])
2013 phy_power_off(tegra->phys[i]);
2015 phy_exit(tegra->phys[i]);
2018 tegra_xusb_clk_disable(tegra);
2022 dev_dbg(tegra->dev, "entering ELPG done\n");
2024 usbcmd = readl(&xhci->op_regs->command);
2026 writel(usbcmd, &xhci->op_regs->command);
2028 dev_dbg(tegra->dev, "entering ELPG failed\n");
2029 pm_runtime_mark_last_busy(tegra->dev);
2035 static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool runtime)
2037 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
2038 struct device *dev = tegra->dev;
2039 bool wakeup = runtime ? true : device_may_wakeup(dev);
2044 dev_dbg(dev, "exiting ELPG\n");
2045 pm_runtime_mark_last_busy(tegra->dev);
2047 err = tegra_xusb_clk_enable(tegra);
2049 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
2053 err = tegra_xusb_unpowergate_partitions(tegra);
2058 tegra_xhci_disable_phy_wake(tegra);
2060 for (i = 0; i < tegra->num_phys; i++) {
2061 if (!tegra->phys[i])
2065 phy_init(tegra->phys[i]);
2067 phy_power_on(tegra->phys[i]);
2070 tegra_xusb_config(tegra);
2071 tegra_xusb_restore_context(tegra);
2073 err = tegra_xusb_load_firmware(tegra);
2075 dev_err(tegra->dev, "failed to load firmware: %d\n", err);
2079 err = __tegra_xusb_enable_firmware_messages(tegra);
2081 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
2086 tegra_xhci_disable_phy_sleepwalk(tegra);
2088 err = xhci_resume(xhci, 0);
2090 dev_err(tegra->dev, "failed to resume XHCI: %d\n", err);
2094 usbcmd = readl(&xhci->op_regs->command);
2096 writel(usbcmd, &xhci->op_regs->command);
2101 for (i = 0; i < tegra->num_phys; i++) {
2102 if (!tegra->phys[i])
2105 phy_power_off(tegra->phys[i]);
2107 phy_exit(tegra->phys[i]);
2109 tegra_xusb_powergate_partitions(tegra);
2111 tegra_xusb_clk_disable(tegra);
2114 dev_dbg(dev, "exiting ELPG done\n");
2116 dev_dbg(dev, "exiting ELPG failed\n");
2121 static __maybe_unused int tegra_xusb_suspend(struct device *dev)
2123 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2126 synchronize_irq(tegra->mbox_irq);
2128 mutex_lock(&tegra->lock);
2130 if (pm_runtime_suspended(dev)) {
2131 err = tegra_xusb_exit_elpg(tegra, true);
2136 err = tegra_xusb_enter_elpg(tegra, false);
2138 if (pm_runtime_suspended(dev)) {
2139 pm_runtime_disable(dev);
2140 pm_runtime_set_active(dev);
2141 pm_runtime_enable(dev);
2149 tegra->suspended = true;
2150 pm_runtime_disable(dev);
2152 if (device_may_wakeup(dev)) {
2153 if (enable_irq_wake(tegra->padctl_irq))
2154 dev_err(dev, "failed to enable padctl wakes\n");
2158 mutex_unlock(&tegra->lock);
2163 static __maybe_unused int tegra_xusb_resume(struct device *dev)
2165 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2168 mutex_lock(&tegra->lock);
2170 if (!tegra->suspended) {
2171 mutex_unlock(&tegra->lock);
2175 err = tegra_xusb_exit_elpg(tegra, false);
2177 mutex_unlock(&tegra->lock);
2181 if (device_may_wakeup(dev)) {
2182 if (disable_irq_wake(tegra->padctl_irq))
2183 dev_err(dev, "failed to disable padctl wakes\n");
2185 tegra->suspended = false;
2186 mutex_unlock(&tegra->lock);
2188 pm_runtime_set_active(dev);
2189 pm_runtime_enable(dev);
2194 static __maybe_unused int tegra_xusb_runtime_suspend(struct device *dev)
2196 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2199 synchronize_irq(tegra->mbox_irq);
2200 mutex_lock(&tegra->lock);
2201 ret = tegra_xusb_enter_elpg(tegra, true);
2202 mutex_unlock(&tegra->lock);
2207 static __maybe_unused int tegra_xusb_runtime_resume(struct device *dev)
2209 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2212 mutex_lock(&tegra->lock);
2213 err = tegra_xusb_exit_elpg(tegra, true);
2214 mutex_unlock(&tegra->lock);
2219 static const struct dev_pm_ops tegra_xusb_pm_ops = {
2220 SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
2221 tegra_xusb_runtime_resume, NULL)
2222 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
2225 static const char * const tegra124_supply_names[] = {
2232 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
2233 { .name = "usb3", .num = 2, },
2234 { .name = "usb2", .num = 3, },
2235 { .name = "hsic", .num = 2, },
2238 static const unsigned int tegra124_xusb_context_ipfs[] = {
2239 IPFS_XUSB_HOST_MSI_BAR_SZ_0,
2240 IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0,
2241 IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0,
2242 IPFS_XUSB_HOST_MSI_VEC0_0,
2243 IPFS_XUSB_HOST_MSI_EN_VEC0_0,
2244 IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0,
2245 IPFS_XUSB_HOST_INTR_MASK_0,
2246 IPFS_XUSB_HOST_INTR_ENABLE_0,
2247 IPFS_XUSB_HOST_UFPCI_CONFIG_0,
2248 IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0,
2249 IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0,
2252 static const unsigned int tegra124_xusb_context_fpci[] = {
2253 XUSB_CFG_ARU_CONTEXT_HS_PLS,
2254 XUSB_CFG_ARU_CONTEXT_FS_PLS,
2255 XUSB_CFG_ARU_CONTEXT_HSFS_SPEED,
2256 XUSB_CFG_ARU_CONTEXT_HSFS_PP,
2257 XUSB_CFG_ARU_CONTEXT,
2263 static const struct tegra_xusb_context_soc tegra124_xusb_context = {
2265 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs),
2266 .offsets = tegra124_xusb_context_ipfs,
2269 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
2270 .offsets = tegra124_xusb_context_fpci,
2274 static const struct tegra_xusb_soc tegra124_soc = {
2275 .firmware = "/*(DEBLOBBED)*/",
2276 .supply_names = tegra124_supply_names,
2277 .num_supplies = ARRAY_SIZE(tegra124_supply_names),
2278 .phy_types = tegra124_phy_types,
2279 .num_types = ARRAY_SIZE(tegra124_phy_types),
2280 .context = &tegra124_xusb_context,
2282 .usb2 = { .offset = 4, .count = 4, },
2283 .hsic = { .offset = 6, .count = 2, },
2284 .usb3 = { .offset = 0, .count = 2, },
2286 .scale_ss_clock = true,
2288 .otg_reset_sspi = false,
2298 static const char * const tegra210_supply_names[] = {
2304 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
2305 { .name = "usb3", .num = 4, },
2306 { .name = "usb2", .num = 4, },
2307 { .name = "hsic", .num = 1, },
2310 static const struct tegra_xusb_soc tegra210_soc = {
2311 .firmware = "/*(DEBLOBBED)*/",
2312 .supply_names = tegra210_supply_names,
2313 .num_supplies = ARRAY_SIZE(tegra210_supply_names),
2314 .phy_types = tegra210_phy_types,
2315 .num_types = ARRAY_SIZE(tegra210_phy_types),
2316 .context = &tegra124_xusb_context,
2318 .usb2 = { .offset = 4, .count = 4, },
2319 .hsic = { .offset = 8, .count = 1, },
2320 .usb3 = { .offset = 0, .count = 4, },
2322 .scale_ss_clock = false,
2324 .otg_reset_sspi = true,
2334 static const char * const tegra186_supply_names[] = {
2338 static const struct tegra_xusb_phy_type tegra186_phy_types[] = {
2339 { .name = "usb3", .num = 3, },
2340 { .name = "usb2", .num = 3, },
2341 { .name = "hsic", .num = 1, },
2344 static const struct tegra_xusb_context_soc tegra186_xusb_context = {
2346 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
2347 .offsets = tegra124_xusb_context_fpci,
2351 static const struct tegra_xusb_soc tegra186_soc = {
2352 .firmware = "/*(DEBLOBBED)*/",
2353 .supply_names = tegra186_supply_names,
2354 .num_supplies = ARRAY_SIZE(tegra186_supply_names),
2355 .phy_types = tegra186_phy_types,
2356 .num_types = ARRAY_SIZE(tegra186_phy_types),
2357 .context = &tegra186_xusb_context,
2359 .usb3 = { .offset = 0, .count = 3, },
2360 .usb2 = { .offset = 3, .count = 3, },
2361 .hsic = { .offset = 6, .count = 1, },
2363 .scale_ss_clock = false,
2365 .otg_reset_sspi = false,
2372 .lpm_support = true,
2375 static const char * const tegra194_supply_names[] = {
2378 static const struct tegra_xusb_phy_type tegra194_phy_types[] = {
2379 { .name = "usb3", .num = 4, },
2380 { .name = "usb2", .num = 4, },
2383 static const struct tegra_xusb_soc tegra194_soc = {
2384 .firmware = "/*(DEBLOBBED)*/",
2385 .supply_names = tegra194_supply_names,
2386 .num_supplies = ARRAY_SIZE(tegra194_supply_names),
2387 .phy_types = tegra194_phy_types,
2388 .num_types = ARRAY_SIZE(tegra194_phy_types),
2389 .context = &tegra186_xusb_context,
2391 .usb3 = { .offset = 0, .count = 4, },
2392 .usb2 = { .offset = 4, .count = 4, },
2394 .scale_ss_clock = false,
2396 .otg_reset_sspi = false,
2403 .lpm_support = true,
2407 static const struct of_device_id tegra_xusb_of_match[] = {
2408 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
2409 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
2410 { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc },
2411 { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc },
2414 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
2416 static struct platform_driver tegra_xusb_driver = {
2417 .probe = tegra_xusb_probe,
2418 .remove = tegra_xusb_remove,
2420 .name = "tegra-xusb",
2421 .pm = &tegra_xusb_pm_ops,
2422 .of_match_table = tegra_xusb_of_match,
2426 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
2428 struct tegra_xusb *tegra = dev_get_drvdata(dev);
2430 xhci->quirks |= XHCI_PLAT;
2431 if (tegra && tegra->soc->lpm_support)
2432 xhci->quirks |= XHCI_LPM_SUPPORT;
2435 static int tegra_xhci_setup(struct usb_hcd *hcd)
2437 return xhci_gen_setup(hcd, tegra_xhci_quirks);
2440 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
2441 .reset = tegra_xhci_setup,
2444 static int __init tegra_xusb_init(void)
2446 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
2448 return platform_driver_register(&tegra_xusb_driver);
2450 module_init(tegra_xusb_init);
2452 static void __exit tegra_xusb_exit(void)
2454 platform_driver_unregister(&tegra_xusb_driver);
2456 module_exit(tegra_xusb_exit);
2458 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
2459 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
2460 MODULE_LICENSE("GPL v2");