drivers/usb/host/xhci-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVIDIA Tegra xHCI host controller driver
   4  *
   5  * Copyright (C) 2014 NVIDIA Corporation
   6  * Copyright (C) 2014 Google, Inc.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/firmware.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/of_device.h>
  18 #include <linux/phy/phy.h>
  19 #include <linux/phy/tegra/xusb.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm.h>
  22 #include <linux/pm_domain.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/reset.h>
  26 #include <linux/slab.h>
  27 #include <linux/usb/otg.h>
  28 #include <linux/usb/phy.h>
  29 #include <linux/usb/role.h>
  30 #include <soc/tegra/pmc.h>
  31
  32 #include "xhci.h"
  33
  34 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
  35 #define TEGRA_XHCI_SS_LOW_SPEED   12000000
  36
  37 /* FPCI CFG registers */
  38 #define XUSB_CFG_1                              0x004
  39 #define  XUSB_IO_SPACE_EN                       BIT(0)
  40 #define  XUSB_MEM_SPACE_EN                      BIT(1)
  41 #define  XUSB_BUS_MASTER_EN                     BIT(2)
  42 #define XUSB_CFG_4                              0x010
  43 #define  XUSB_BASE_ADDR_SHIFT                   15
  44 #define  XUSB_BASE_ADDR_MASK                    0x1ffff
  45 #define XUSB_CFG_16                             0x040
  46 #define XUSB_CFG_24                             0x060
  47 #define XUSB_CFG_AXI_CFG                        0x0f8
  48 #define XUSB_CFG_ARU_C11_CSBRANGE               0x41c
  49 #define XUSB_CFG_ARU_CONTEXT                    0x43c
  50 #define XUSB_CFG_ARU_CONTEXT_HS_PLS             0x478
  51 #define XUSB_CFG_ARU_CONTEXT_FS_PLS             0x47c
  52 #define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED         0x480
  53 #define XUSB_CFG_ARU_CONTEXT_HSFS_PP            0x484
  54 #define XUSB_CFG_CSB_BASE_ADDR                  0x800
  55
  56 /* FPCI mailbox registers */
  57 /* XUSB_CFG_ARU_MBOX_CMD */
  58 #define  MBOX_DEST_FALC                         BIT(27)
  59 #define  MBOX_DEST_PME                          BIT(28)
  60 #define  MBOX_DEST_SMI                          BIT(29)
  61 #define  MBOX_DEST_XHCI                         BIT(30)
  62 #define  MBOX_INT_EN                            BIT(31)
  63 /* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */
  64 #define  CMD_DATA_SHIFT                         0
  65 #define  CMD_DATA_MASK                          0xffffff
  66 #define  CMD_TYPE_SHIFT                         24
  67 #define  CMD_TYPE_MASK                          0xff
  68 /* XUSB_CFG_ARU_MBOX_OWNER */
  69 #define  MBOX_OWNER_NONE                        0
  70 #define  MBOX_OWNER_FW                          1
  71 #define  MBOX_OWNER_SW                          2
  72 #define XUSB_CFG_ARU_SMI_INTR                   0x428
  73 #define  MBOX_SMI_INTR_FW_HANG                  BIT(1)
  74 #define  MBOX_SMI_INTR_EN                       BIT(3)
  75
  76 /* IPFS registers */
  77 #define IPFS_XUSB_HOST_MSI_BAR_SZ_0             0x0c0
  78 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0         0x0c4
  79 #define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0        0x0c8
  80 #define IPFS_XUSB_HOST_MSI_VEC0_0               0x100
  81 #define IPFS_XUSB_HOST_MSI_EN_VEC0_0            0x140
  82 #define IPFS_XUSB_HOST_CONFIGURATION_0          0x180
  83 #define  IPFS_EN_FPCI                           BIT(0)
  84 #define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0       0x184
  85 #define IPFS_XUSB_HOST_INTR_MASK_0              0x188
  86 #define  IPFS_IP_INT_MASK                       BIT(16)
  87 #define IPFS_XUSB_HOST_INTR_ENABLE_0            0x198
  88 #define IPFS_XUSB_HOST_UFPCI_CONFIG_0           0x19c
  89 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0     0x1bc
  90 #define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0         0x1dc
  91
  92 #define CSB_PAGE_SELECT_MASK                    0x7fffff
  93 #define CSB_PAGE_SELECT_SHIFT                   9
  94 #define CSB_PAGE_OFFSET_MASK                    0x1ff
  95 #define CSB_PAGE_SELECT(addr)   ((addr) >> (CSB_PAGE_SELECT_SHIFT) &    \
  96                                  CSB_PAGE_SELECT_MASK)
  97 #define CSB_PAGE_OFFSET(addr)   ((addr) & CSB_PAGE_OFFSET_MASK)
  98
  99 /* Falcon CSB registers */
 100 #define XUSB_FALC_CPUCTL                        0x100
 101 #define  CPUCTL_STARTCPU                        BIT(1)
 102 #define  CPUCTL_STATE_HALTED                    BIT(4)
 103 #define  CPUCTL_STATE_STOPPED                   BIT(5)
 104 #define XUSB_FALC_BOOTVEC                       0x104
 105 #define XUSB_FALC_DMACTL                        0x10c
 106 #define XUSB_FALC_IMFILLRNG1                    0x154
 107 #define  IMFILLRNG1_TAG_MASK                    0xffff
 108 #define  IMFILLRNG1_TAG_LO_SHIFT                0
 109 #define  IMFILLRNG1_TAG_HI_SHIFT                16
 110 #define XUSB_FALC_IMFILLCTL                     0x158
 111
 112 /* MP CSB registers */
 113 #define XUSB_CSB_MP_ILOAD_ATTR                  0x101a00
 114 #define XUSB_CSB_MP_ILOAD_BASE_LO               0x101a04
 115 #define XUSB_CSB_MP_ILOAD_BASE_HI               0x101a08
 116 #define XUSB_CSB_MP_L2IMEMOP_SIZE               0x101a10
 117 #define  L2IMEMOP_SIZE_SRC_OFFSET_SHIFT         8
 118 #define  L2IMEMOP_SIZE_SRC_OFFSET_MASK          0x3ff
 119 #define  L2IMEMOP_SIZE_SRC_COUNT_SHIFT          24
 120 #define  L2IMEMOP_SIZE_SRC_COUNT_MASK           0xff
 121 #define XUSB_CSB_MP_L2IMEMOP_TRIG               0x101a14
 122 #define  L2IMEMOP_ACTION_SHIFT                  24
 123 #define  L2IMEMOP_INVALIDATE_ALL                (0x40 << L2IMEMOP_ACTION_SHIFT)
 124 #define  L2IMEMOP_LOAD_LOCKED_RESULT            (0x11 << L2IMEMOP_ACTION_SHIFT)
 125 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT        0x101a18
 126 #define  L2IMEMOP_RESULT_VLD                    BIT(31)
 127 #define XUSB_CSB_MP_APMAP                       0x10181c
 128 #define  APMAP_BOOTPATH                         BIT(31)
 129
 130 #define IMEM_BLOCK_SIZE                         256
 131
 132 struct tegra_xusb_fw_header {
 133         __le32 boot_loadaddr_in_imem;
 134         __le32 boot_codedfi_offset;
 135         __le32 boot_codetag;
 136         __le32 boot_codesize;
 137         __le32 phys_memaddr;
 138         __le16 reqphys_memsize;
 139         __le16 alloc_phys_memsize;
 140         __le32 rodata_img_offset;
 141         __le32 rodata_section_start;
 142         __le32 rodata_section_end;
 143         __le32 main_fnaddr;
 144         __le32 fwimg_cksum;
 145         __le32 fwimg_created_time;
 146         __le32 imem_resident_start;
 147         __le32 imem_resident_end;
 148         __le32 idirect_start;
 149         __le32 idirect_end;
 150         __le32 l2_imem_start;
 151         __le32 l2_imem_end;
 152         __le32 version_id;
 153         u8 init_ddirect;
 154         u8 reserved[3];
 155         __le32 phys_addr_log_buffer;
 156         __le32 total_log_entries;
 157         __le32 dequeue_ptr;
 158         __le32 dummy_var[2];
 159         __le32 fwimg_len;
 160         u8 magic[8];
 161         __le32 ss_low_power_entry_timeout;
 162         u8 num_hsic_port;
 163         u8 padding[139]; /* Pad to 256 bytes */
 164 };
 165
 166 struct tegra_xusb_phy_type {
 167         const char *name;
 168         unsigned int num;
 169 };
 170
 171 struct tegra_xusb_mbox_regs {
 172         u16 cmd;
 173         u16 data_in;
 174         u16 data_out;
 175         u16 owner;
 176 };
 177
 178 struct tegra_xusb_context_soc {
 179         struct {
 180                 const unsigned int *offsets;
 181                 unsigned int num_offsets;
 182         } ipfs;
 183
 184         struct {
 185                 const unsigned int *offsets;
 186                 unsigned int num_offsets;
 187         } fpci;
 188 };
 189
 190 struct tegra_xusb_soc {
 191         const char *firmware;
 192         const char * const *supply_names;
 193         unsigned int num_supplies;
 194         const struct tegra_xusb_phy_type *phy_types;
 195         unsigned int num_types;
 196         const struct tegra_xusb_context_soc *context;
 197
 198         struct {
 199                 struct {
 200                         unsigned int offset;
 201                         unsigned int count;
 202                 } usb2, ulpi, hsic, usb3;
 203         } ports;
 204
 205         struct tegra_xusb_mbox_regs mbox;
 206
 207         bool scale_ss_clock;
 208         bool has_ipfs;
 209         bool lpm_support;
 210         bool otg_reset_sspi;
 211 };
 212
 213 struct tegra_xusb_context {
 214         u32 *ipfs;
 215         u32 *fpci;
 216 };
 217
 218 struct tegra_xusb {
 219         struct device *dev;
 220         void __iomem *regs;
 221         struct usb_hcd *hcd;
 222
 223         struct mutex lock;
 224
 225         int xhci_irq;
 226         int mbox_irq;
 227
 228         void __iomem *ipfs_base;
 229         void __iomem *fpci_base;
 230
 231         const struct tegra_xusb_soc *soc;
 232
 233         struct regulator_bulk_data *supplies;
 234
 235         struct tegra_xusb_padctl *padctl;
 236
 237         struct clk *host_clk;
 238         struct clk *falcon_clk;
 239         struct clk *ss_clk;
 240         struct clk *ss_src_clk;
 241         struct clk *hs_src_clk;
 242         struct clk *fs_src_clk;
 243         struct clk *pll_u_480m;
 244         struct clk *clk_m;
 245         struct clk *pll_e;
 246
 247         struct reset_control *host_rst;
 248         struct reset_control *ss_rst;
 249
 250         struct device *genpd_dev_host;
 251         struct device *genpd_dev_ss;
 252         struct device_link *genpd_dl_host;
 253         struct device_link *genpd_dl_ss;
 254
 255         struct phy **phys;
 256         unsigned int num_phys;
 257
 258         struct usb_phy **usbphy;
 259         unsigned int num_usb_phys;
 260         int otg_usb2_port;
 261         int otg_usb3_port;
 262         bool host_mode;
 263         struct notifier_block id_nb;
 264         struct work_struct id_work;
 265
 266         /* Firmware loading related */
 267         struct {
 268                 size_t size;
 269                 void *virt;
 270                 dma_addr_t phys;
 271         } fw;
 272
 273         struct tegra_xusb_context context;
 274 };
 275
 276 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
 277
 278 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
 279 {
 280         return readl(tegra->fpci_base + offset);
 281 }
 282
 283 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
 284                                unsigned int offset)
 285 {
 286         writel(value, tegra->fpci_base + offset);
 287 }
 288
 289 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
 290 {
 291         return readl(tegra->ipfs_base + offset);
 292 }
 293
 294 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
 295                                unsigned int offset)
 296 {
 297         writel(value, tegra->ipfs_base + offset);
 298 }
 299
 300 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
 301 {
 302         u32 page = CSB_PAGE_SELECT(offset);
 303         u32 ofs = CSB_PAGE_OFFSET(offset);
 304
 305         fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
 306
 307         return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
 308 }
 309
 310 static void csb_writel(struct tegra_xusb *tegra, u32 value,
 311                        unsigned int offset)
 312 {
 313         u32 page = CSB_PAGE_SELECT(offset);
 314         u32 ofs = CSB_PAGE_OFFSET(offset);
 315
 316         fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
 317         fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
 318 }
 319
 320 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
 321                                  unsigned long rate)
 322 {
 323         unsigned long new_parent_rate, old_parent_rate;
 324         struct clk *clk = tegra->ss_src_clk;
 325         unsigned int div;
 326         int err;
 327
 328         if (clk_get_rate(clk) == rate)
 329                 return 0;
 330
 331         switch (rate) {
 332         case TEGRA_XHCI_SS_HIGH_SPEED:
 333                 /*
 334                  * Reparent to PLLU_480M. Set divider first to avoid
 335                  * overclocking.
 336                  */
 337                 old_parent_rate = clk_get_rate(clk_get_parent(clk));
 338                 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
 339                 div = new_parent_rate / rate;
 340
 341                 err = clk_set_rate(clk, old_parent_rate / div);
 342                 if (err)
 343                         return err;
 344
 345                 err = clk_set_parent(clk, tegra->pll_u_480m);
 346                 if (err)
 347                         return err;
 348
 349                 /*
 350                  * The rate should already be correct, but set it again just
 351                  * to be sure.
 352                  */
 353                 err = clk_set_rate(clk, rate);
 354                 if (err)
 355                         return err;
 356
 357                 break;
 358
 359         case TEGRA_XHCI_SS_LOW_SPEED:
 360                 /* Reparent to CLK_M */
 361                 err = clk_set_parent(clk, tegra->clk_m);
 362                 if (err)
 363                         return err;
 364
 365                 err = clk_set_rate(clk, rate);
 366                 if (err)
 367                         return err;
 368
 369                 break;
 370
 371         default:
 372                 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
 373                 return -EINVAL;
 374         }
 375
 376         if (clk_get_rate(clk) != rate) {
 377                 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
 378                 return -EINVAL;
 379         }
 380
 381         return 0;
 382 }
 383
 384 static unsigned long extract_field(u32 value, unsigned int start,
 385                                    unsigned int count)
 386 {
 387         return (value >> start) & ((1 << count) - 1);
 388 }
 389
 390 /* Command requests from the firmware */
 391 enum tegra_xusb_mbox_cmd {
 392         MBOX_CMD_MSG_ENABLED = 1,
 393         MBOX_CMD_INC_FALC_CLOCK,
 394         MBOX_CMD_DEC_FALC_CLOCK,
 395         MBOX_CMD_INC_SSPI_CLOCK,
 396         MBOX_CMD_DEC_SSPI_CLOCK,
 397         MBOX_CMD_SET_BW, /* no ACK/NAK required */
 398         MBOX_CMD_SET_SS_PWR_GATING,
 399         MBOX_CMD_SET_SS_PWR_UNGATING,
 400         MBOX_CMD_SAVE_DFE_CTLE_CTX,
 401         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
 402         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
 403         MBOX_CMD_START_HSIC_IDLE,
 404         MBOX_CMD_STOP_HSIC_IDLE,
 405         MBOX_CMD_DBC_WAKE_STACK, /* unused */
 406         MBOX_CMD_HSIC_PRETEND_CONNECT,
 407         MBOX_CMD_RESET_SSPI,
 408         MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
 409         MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
 410
 411         MBOX_CMD_MAX,
 412
 413         /* Response message to above commands */
 414         MBOX_CMD_ACK = 128,
 415         MBOX_CMD_NAK
 416 };
 417
 418 struct tegra_xusb_mbox_msg {
 419         u32 cmd;
 420         u32 data;
 421 };
 422
 423 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
 424 {
 425         return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
 426                (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
 427 }
 428 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
 429                                           u32 value)
 430 {
 431         msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
 432         msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
 433 }
 434
 435 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
 436 {
 437         switch (cmd) {
 438         case MBOX_CMD_SET_BW:
 439         case MBOX_CMD_ACK:
 440         case MBOX_CMD_NAK:
 441                 return false;
 442
 443         default:
 444                 return true;
 445         }
 446 }
 447
 448 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
 449                                 const struct tegra_xusb_mbox_msg *msg)
 450 {
 451         bool wait_for_idle = false;
 452         u32 value;
 453
 454         /*
 455          * Acquire the mailbox. The firmware still owns the mailbox for
 456          * ACK/NAK messages.
 457          */
 458         if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
 459                 value = fpci_readl(tegra, tegra->soc->mbox.owner);
 460                 if (value != MBOX_OWNER_NONE) {
 461                         dev_err(tegra->dev, "mailbox is busy\n");
 462                         return -EBUSY;
 463                 }
 464
 465                 fpci_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner);
 466
 467                 value = fpci_readl(tegra, tegra->soc->mbox.owner);
 468                 if (value != MBOX_OWNER_SW) {
 469                         dev_err(tegra->dev, "failed to acquire mailbox\n");
 470                         return -EBUSY;
 471                 }
 472
 473                 wait_for_idle = true;
 474         }
 475
 476         value = tegra_xusb_mbox_pack(msg);
 477         fpci_writel(tegra, value, tegra->soc->mbox.data_in);
 478
 479         value = fpci_readl(tegra, tegra->soc->mbox.cmd);
 480         value |= MBOX_INT_EN | MBOX_DEST_FALC;
 481         fpci_writel(tegra, value, tegra->soc->mbox.cmd);
 482
 483         if (wait_for_idle) {
 484                 unsigned long timeout = jiffies + msecs_to_jiffies(250);
 485
 486                 while (time_before(jiffies, timeout)) {
 487                         value = fpci_readl(tegra, tegra->soc->mbox.owner);
 488                         if (value == MBOX_OWNER_NONE)
 489                                 break;
 490
 491                         usleep_range(10, 20);
 492                 }
 493
 494                 if (time_after(jiffies, timeout))
 495                         value = fpci_readl(tegra, tegra->soc->mbox.owner);
 496
 497                 if (value != MBOX_OWNER_NONE)
 498                         return -ETIMEDOUT;
 499         }
 500
 501         return 0;
 502 }
 503
 504 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
 505 {
 506         struct tegra_xusb *tegra = data;
 507         u32 value;
 508
 509         /* clear mailbox interrupts */
 510         value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
 511         fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
 512
 513         if (value & MBOX_SMI_INTR_FW_HANG)
 514                 dev_err(tegra->dev, "controller firmware hang\n");
 515
 516         return IRQ_WAKE_THREAD;
 517 }
 518
 519 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
 520                                    const struct tegra_xusb_mbox_msg *msg)
 521 {
 522         struct tegra_xusb_padctl *padctl = tegra->padctl;
 523         const struct tegra_xusb_soc *soc = tegra->soc;
 524         struct device *dev = tegra->dev;
 525         struct tegra_xusb_mbox_msg rsp;
 526         unsigned long mask;
 527         unsigned int port;
 528         bool idle, enable;
 529         int err = 0;
 530
 531         memset(&rsp, 0, sizeof(rsp));
 532
 533         switch (msg->cmd) {
 534         case MBOX_CMD_INC_FALC_CLOCK:
 535         case MBOX_CMD_DEC_FALC_CLOCK:
 536                 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
 537                 if (rsp.data != msg->data)
 538                         rsp.cmd = MBOX_CMD_NAK;
 539                 else
 540                         rsp.cmd = MBOX_CMD_ACK;
 541
 542                 break;
 543
 544         case MBOX_CMD_INC_SSPI_CLOCK:
 545         case MBOX_CMD_DEC_SSPI_CLOCK:
 546                 if (tegra->soc->scale_ss_clock) {
 547                         err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
 548                         if (err < 0)
 549                                 rsp.cmd = MBOX_CMD_NAK;
 550                         else
 551                                 rsp.cmd = MBOX_CMD_ACK;
 552
 553                         rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
 554                 } else {
 555                         rsp.cmd = MBOX_CMD_ACK;
 556                         rsp.data = msg->data;
 557                 }
 558
 559                 break;
 560
 561         case MBOX_CMD_SET_BW:
 562                 /*
 563                  * TODO: Request bandwidth once EMC scaling is supported.
 564                  * Ignore for now since ACK/NAK is not required for SET_BW
 565                  * messages.
 566                  */
 567                 break;
 568
 569         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
 570                 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
 571                 if (err < 0) {
 572                         dev_err(dev, "failed to save context for USB3#%u: %d\n",
 573                                 msg->data, err);
 574                         rsp.cmd = MBOX_CMD_NAK;
 575                 } else {
 576                         rsp.cmd = MBOX_CMD_ACK;
 577                 }
 578
 579                 rsp.data = msg->data;
 580                 break;
 581
 582         case MBOX_CMD_START_HSIC_IDLE:
 583         case MBOX_CMD_STOP_HSIC_IDLE:
 584                 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
 585                         idle = false;
 586                 else
 587                         idle = true;
 588
 589                 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
 590                                      soc->ports.hsic.count);
 591
 592                 for_each_set_bit(port, &mask, 32) {
 593                         err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
 594                                                               idle);
 595                         if (err < 0)
 596                                 break;
 597                 }
 598
 599                 if (err < 0) {
 600                         dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
 601                                 idle ? "idle" : "busy", err);
 602                         rsp.cmd = MBOX_CMD_NAK;
 603                 } else {
 604                         rsp.cmd = MBOX_CMD_ACK;
 605                 }
 606
 607                 rsp.data = msg->data;
 608                 break;
 609
 610         case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
 611         case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
 612                 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
 613                         enable = false;
 614                 else
 615                         enable = true;
 616
 617                 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
 618                                      soc->ports.usb3.count);
 619
 620                 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
 621                         err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
 622                                                                      port,
 623                                                                      enable);
 624                         if (err < 0)
 625                                 break;
 626
 627                         /*
 628                          * wait 500us for LFPS detector to be disabled before
 629                          * sending ACK
 630                          */
 631                         if (!enable)
 632                                 usleep_range(500, 1000);
 633                 }
 634
 635                 if (err < 0) {
 636                         dev_err(dev,
 637                                 "failed to %s LFPS detection on USB3#%u: %d\n",
 638                                 enable ? "enable" : "disable", port, err);
 639                         rsp.cmd = MBOX_CMD_NAK;
 640                 } else {
 641                         rsp.cmd = MBOX_CMD_ACK;
 642                 }
 643
 644                 rsp.data = msg->data;
 645                 break;
 646
 647         default:
 648                 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
 649                 break;
 650         }
 651
 652         if (rsp.cmd) {
 653                 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
 654
 655                 err = tegra_xusb_mbox_send(tegra, &rsp);
 656                 if (err < 0)
 657                         dev_err(dev, "failed to send %s: %d\n", cmd, err);
 658         }
 659 }
 660
 661 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
 662 {
 663         struct tegra_xusb *tegra = data;
 664         struct tegra_xusb_mbox_msg msg;
 665         u32 value;
 666
 667         mutex_lock(&tegra->lock);
 668
 669         value = fpci_readl(tegra, tegra->soc->mbox.data_out);
 670         tegra_xusb_mbox_unpack(&msg, value);
 671
 672         value = fpci_readl(tegra, tegra->soc->mbox.cmd);
 673         value &= ~MBOX_DEST_SMI;
 674         fpci_writel(tegra, value, tegra->soc->mbox.cmd);
 675
 676         /* clear mailbox owner if no ACK/NAK is required */
 677         if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
 678                 fpci_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner);
 679
 680         tegra_xusb_mbox_handle(tegra, &msg);
 681
 682         mutex_unlock(&tegra->lock);
 683         return IRQ_HANDLED;
 684 }
 685
 686 static void tegra_xusb_config(struct tegra_xusb *tegra)
 687 {
 688         u32 regs = tegra->hcd->rsrc_start;
 689         u32 value;
 690
 691         if (tegra->soc->has_ipfs) {
 692                 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
 693                 value |= IPFS_EN_FPCI;
 694                 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
 695
 696                 usleep_range(10, 20);
 697         }
 698
 699         /* Program BAR0 space */
 700         value = fpci_readl(tegra, XUSB_CFG_4);
 701         value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
 702         value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
 703         fpci_writel(tegra, value, XUSB_CFG_4);
 704
 705         usleep_range(100, 200);
 706
 707         /* Enable bus master */
 708         value = fpci_readl(tegra, XUSB_CFG_1);
 709         value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
 710         fpci_writel(tegra, value, XUSB_CFG_1);
 711
 712         if (tegra->soc->has_ipfs) {
 713                 /* Enable interrupt assertion */
 714                 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
 715                 value |= IPFS_IP_INT_MASK;
 716                 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
 717
 718                 /* Set hysteresis */
 719                 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
 720         }
 721 }
 722
 723 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
 724 {
 725         int err;
 726
 727         err = clk_prepare_enable(tegra->pll_e);
 728         if (err < 0)
 729                 return err;
 730
 731         err = clk_prepare_enable(tegra->host_clk);
 732         if (err < 0)
 733                 goto disable_plle;
 734
 735         err = clk_prepare_enable(tegra->ss_clk);
 736         if (err < 0)
 737                 goto disable_host;
 738
 739         err = clk_prepare_enable(tegra->falcon_clk);
 740         if (err < 0)
 741                 goto disable_ss;
 742
 743         err = clk_prepare_enable(tegra->fs_src_clk);
 744         if (err < 0)
 745                 goto disable_falc;
 746
 747         err = clk_prepare_enable(tegra->hs_src_clk);
 748         if (err < 0)
 749                 goto disable_fs_src;
 750
 751         if (tegra->soc->scale_ss_clock) {
 752                 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
 753                 if (err < 0)
 754                         goto disable_hs_src;
 755         }
 756
 757         return 0;
 758
 759 disable_hs_src:
 760         clk_disable_unprepare(tegra->hs_src_clk);
 761 disable_fs_src:
 762         clk_disable_unprepare(tegra->fs_src_clk);
 763 disable_falc:
 764         clk_disable_unprepare(tegra->falcon_clk);
 765 disable_ss:
 766         clk_disable_unprepare(tegra->ss_clk);
 767 disable_host:
 768         clk_disable_unprepare(tegra->host_clk);
 769 disable_plle:
 770         clk_disable_unprepare(tegra->pll_e);
 771         return err;
 772 }
 773
 774 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
 775 {
 776         clk_disable_unprepare(tegra->pll_e);
 777         clk_disable_unprepare(tegra->host_clk);
 778         clk_disable_unprepare(tegra->ss_clk);
 779         clk_disable_unprepare(tegra->falcon_clk);
 780         clk_disable_unprepare(tegra->fs_src_clk);
 781         clk_disable_unprepare(tegra->hs_src_clk);
 782 }
 783
 784 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
 785 {
 786         unsigned int i;
 787         int err;
 788
 789         for (i = 0; i < tegra->num_phys; i++) {
 790                 err = phy_init(tegra->phys[i]);
 791                 if (err)
 792                         goto disable_phy;
 793
 794                 err = phy_power_on(tegra->phys[i]);
 795                 if (err) {
 796                         phy_exit(tegra->phys[i]);
 797                         goto disable_phy;
 798                 }
 799         }
 800
 801         return 0;
 802
 803 disable_phy:
 804         while (i--) {
 805                 phy_power_off(tegra->phys[i]);
 806                 phy_exit(tegra->phys[i]);
 807         }
 808
 809         return err;
 810 }
 811
 812 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
 813 {
 814         unsigned int i;
 815
 816         for (i = 0; i < tegra->num_phys; i++) {
 817                 phy_power_off(tegra->phys[i]);
 818                 phy_exit(tegra->phys[i]);
 819         }
 820 }
 821
 822 static int tegra_xusb_runtime_suspend(struct device *dev)
 823 {
 824         struct tegra_xusb *tegra = dev_get_drvdata(dev);
 825
 826         regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
 827         tegra_xusb_clk_disable(tegra);
 828
 829         return 0;
 830 }
 831
 832 static int tegra_xusb_runtime_resume(struct device *dev)
 833 {
 834         struct tegra_xusb *tegra = dev_get_drvdata(dev);
 835         int err;
 836
 837         err = tegra_xusb_clk_enable(tegra);
 838         if (err) {
 839                 dev_err(dev, "failed to enable clocks: %d\n", err);
 840                 return err;
 841         }
 842
 843         err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
 844         if (err) {
 845                 dev_err(dev, "failed to enable regulators: %d\n", err);
 846                 goto disable_clk;
 847         }
 848
 849         return 0;
 850
 851 disable_clk:
 852         tegra_xusb_clk_disable(tegra);
 853         return err;
 854 }
 855
 856 #ifdef CONFIG_PM_SLEEP
 857 static int tegra_xusb_init_context(struct tegra_xusb *tegra)
 858 {
 859         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
 860
 861         tegra->context.ipfs = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets,
 862                                            sizeof(u32), GFP_KERNEL);
 863         if (!tegra->context.ipfs)
 864                 return -ENOMEM;
 865
 866         tegra->context.fpci = devm_kcalloc(tegra->dev, soc->fpci.num_offsets,
 867                                            sizeof(u32), GFP_KERNEL);
 868         if (!tegra->context.fpci)
 869                 return -ENOMEM;
 870
 871         return 0;
 872 }
 873 #else
 874 static inline int tegra_xusb_init_context(struct tegra_xusb *tegra)
 875 {
 876         return 0;
 877 }
 878 #endif
 879
 880 static int tegra_xusb_request_firmware(struct tegra_xusb *tegra)
 881 {
 882         struct tegra_xusb_fw_header *header;
 883         const struct firmware *fw;
 884         int err;
 885
 886         err = reject_firmware(&fw, tegra->soc->firmware, tegra->dev);
 887         if (err < 0) {
 888                 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
 889                 return err;
 890         }
 891
 892         /* Load Falcon controller with its firmware. */
 893         header = (struct tegra_xusb_fw_header *)fw->data;
 894         tegra->fw.size = le32_to_cpu(header->fwimg_len);
 895
 896         tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
 897                                             &tegra->fw.phys, GFP_KERNEL);
 898         if (!tegra->fw.virt) {
 899                 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
 900                 release_firmware(fw);
 901                 return -ENOMEM;
 902         }
 903
 904         header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
 905         memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
 906         release_firmware(fw);
 907
 908         return 0;
 909 }
 910
 911 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
 912 {
 913         unsigned int code_tag_blocks, code_size_blocks, code_blocks;
 914         struct xhci_cap_regs __iomem *cap = tegra->regs;
 915         struct tegra_xusb_fw_header *header;
 916         struct device *dev = tegra->dev;
 917         struct xhci_op_regs __iomem *op;
 918         unsigned long timeout;
 919         time64_t timestamp;
 920         struct tm time;
 921         u64 address;
 922         u32 value;
 923         int err;
 924
 925         header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
 926         op = tegra->regs + HC_LENGTH(readl(&cap->hc_capbase));
 927
 928         if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
 929                 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
 930                          csb_readl(tegra, XUSB_FALC_CPUCTL));
 931                 return 0;
 932         }
 933
 934         /* Program the size of DFI into ILOAD_ATTR. */
 935         csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
 936
 937         /*
 938          * Boot code of the firmware reads the ILOAD_BASE registers
 939          * to get to the start of the DFI in system memory.
 940          */
 941         address = tegra->fw.phys + sizeof(*header);
 942         csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
 943         csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
 944
 945         /* Set BOOTPATH to 1 in APMAP. */
 946         csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
 947
 948         /* Invalidate L2IMEM. */
 949         csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
 950
 951         /*
 952          * Initiate fetch of bootcode from system memory into L2IMEM.
 953          * Program bootcode location and size in system memory.
 954          */
 955         code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
 956                                        IMEM_BLOCK_SIZE);
 957         code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
 958                                         IMEM_BLOCK_SIZE);
 959         code_blocks = code_tag_blocks + code_size_blocks;
 960
 961         value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
 962                         L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
 963                 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
 964                         L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
 965         csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
 966
 967         /* Trigger L2IMEM load operation. */
 968         csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
 969                    XUSB_CSB_MP_L2IMEMOP_TRIG);
 970
 971         /* Setup Falcon auto-fill. */
 972         csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
 973
 974         value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
 975                         IMFILLRNG1_TAG_LO_SHIFT) |
 976                 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
 977                         IMFILLRNG1_TAG_HI_SHIFT);
 978         csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
 979
 980         csb_writel(tegra, 0, XUSB_FALC_DMACTL);
 981
 982         /* wait for RESULT_VLD to get set */
 983 #define tegra_csb_readl(offset) csb_readl(tegra, offset)
 984         err = readx_poll_timeout(tegra_csb_readl,
 985                                  XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value,
 986                                  value & L2IMEMOP_RESULT_VLD, 100, 10000);
 987         if (err < 0) {
 988                 dev_err(dev, "DMA controller not ready %#010x\n", value);
 989                 return err;
 990         }
 991 #undef tegra_csb_readl
 992
 993         csb_writel(tegra, le32_to_cpu(header->boot_codetag),
 994                    XUSB_FALC_BOOTVEC);
 995
 996         /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */
 997         csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
 998
 999         timeout = jiffies + msecs_to_jiffies(200);
1000
1001         do {
1002                 value = readl(&op->status);
1003                 if ((value & STS_CNR) == 0)
1004                         break;
1005
1006                 usleep_range(1000, 2000);
1007         } while (time_is_after_jiffies(timeout));
1008
1009         value = readl(&op->status);
1010         if (value & STS_CNR) {
1011                 value = csb_readl(tegra, XUSB_FALC_CPUCTL);
1012                 dev_err(dev, "XHCI controller not read: %#010x\n", value);
1013                 return -EIO;
1014         }
1015
1016         timestamp = le32_to_cpu(header->fwimg_created_time);
1017         time64_to_tm(timestamp, 0, &time);
1018
1019         dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
1020                  time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
1021                  time.tm_hour, time.tm_min, time.tm_sec);
1022
1023         return 0;
1024 }
1025
1026 static void tegra_xusb_powerdomain_remove(struct device *dev,
1027                                           struct tegra_xusb *tegra)
1028 {
1029         if (tegra->genpd_dl_ss)
1030                 device_link_del(tegra->genpd_dl_ss);
1031         if (tegra->genpd_dl_host)
1032                 device_link_del(tegra->genpd_dl_host);
1033         if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss))
1034                 dev_pm_domain_detach(tegra->genpd_dev_ss, true);
1035         if (!IS_ERR_OR_NULL(tegra->genpd_dev_host))
1036                 dev_pm_domain_detach(tegra->genpd_dev_host, true);
1037 }
1038
1039 static int tegra_xusb_powerdomain_init(struct device *dev,
1040                                        struct tegra_xusb *tegra)
1041 {
1042         int err;
1043
1044         tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host");
1045         if (IS_ERR_OR_NULL(tegra->genpd_dev_host)) {
1046                 err = PTR_ERR(tegra->genpd_dev_host) ? : -ENODATA;
1047                 dev_err(dev, "failed to get host pm-domain: %d\n", err);
1048                 return err;
1049         }
1050
1051         tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss");
1052         if (IS_ERR_OR_NULL(tegra->genpd_dev_ss)) {
1053                 err = PTR_ERR(tegra->genpd_dev_ss) ? : -ENODATA;
1054                 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err);
1055                 return err;
1056         }
1057
1058         tegra->genpd_dl_host = device_link_add(dev, tegra->genpd_dev_host,
1059                                                DL_FLAG_PM_RUNTIME |
1060                                                DL_FLAG_STATELESS);
1061         if (!tegra->genpd_dl_host) {
1062                 dev_err(dev, "adding host device link failed!\n");
1063                 return -ENODEV;
1064         }
1065
1066         tegra->genpd_dl_ss = device_link_add(dev, tegra->genpd_dev_ss,
1067                                              DL_FLAG_PM_RUNTIME |
1068                                              DL_FLAG_STATELESS);
1069         if (!tegra->genpd_dl_ss) {
1070                 dev_err(dev, "adding superspeed device link failed!\n");
1071                 return -ENODEV;
1072         }
1073
1074         return 0;
1075 }
1076
1077 static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1078 {
1079         struct tegra_xusb_mbox_msg msg;
1080         int err;
1081
1082         /* Enable firmware messages from controller. */
1083         msg.cmd = MBOX_CMD_MSG_ENABLED;
1084         msg.data = 0;
1085
1086         err = tegra_xusb_mbox_send(tegra, &msg);
1087         if (err < 0)
1088                 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
1089
1090         return err;
1091 }
1092
1093 static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1094 {
1095         int err;
1096
1097         mutex_lock(&tegra->lock);
1098         err = __tegra_xusb_enable_firmware_messages(tegra);
1099         mutex_unlock(&tegra->lock);
1100
1101         return err;
1102 }
1103
1104 static void tegra_xhci_set_port_power(struct tegra_xusb *tegra, bool main,
1105                                                  bool set)
1106 {
1107         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1108         struct usb_hcd *hcd = main ?  xhci->main_hcd : xhci->shared_hcd;
1109         unsigned int wait = (!main && !set) ? 1000 : 10;
1110         u16 typeReq = set ? SetPortFeature : ClearPortFeature;
1111         u16 wIndex = main ? tegra->otg_usb2_port + 1 : tegra->otg_usb3_port + 1;
1112         u32 status;
1113         u32 stat_power = main ? USB_PORT_STAT_POWER : USB_SS_PORT_STAT_POWER;
1114         u32 status_val = set ? stat_power : 0;
1115
1116         dev_dbg(tegra->dev, "%s():%s %s port power\n", __func__,
1117                 set ? "set" : "clear", main ? "HS" : "SS");
1118
1119         hcd->driver->hub_control(hcd, typeReq, USB_PORT_FEAT_POWER, wIndex,
1120                                  NULL, 0);
1121
1122         do {
1123                 tegra_xhci_hc_driver.hub_control(hcd, GetPortStatus, 0, wIndex,
1124                                         (char *) &status, sizeof(status));
1125                 if (status_val == (status & stat_power))
1126                         break;
1127
1128                 if (!main && !set)
1129                         usleep_range(600, 700);
1130                 else
1131                         usleep_range(10, 20);
1132         } while (--wait > 0);
1133
1134         if (status_val != (status & stat_power))
1135                 dev_info(tegra->dev, "failed to %s %s PP %d\n",
1136                                                 set ? "set" : "clear",
1137                                                 main ? "HS" : "SS", status);
1138 }
1139
1140 static struct phy *tegra_xusb_get_phy(struct tegra_xusb *tegra, char *name,
1141                                                                 int port)
1142 {
1143         unsigned int i, phy_count = 0;
1144
1145         for (i = 0; i < tegra->soc->num_types; i++) {
1146                 if (!strncmp(tegra->soc->phy_types[i].name, name,
1147                                                             strlen(name)))
1148                         return tegra->phys[phy_count+port];
1149
1150                 phy_count += tegra->soc->phy_types[i].num;
1151         }
1152
1153         return NULL;
1154 }
1155
1156 static void tegra_xhci_id_work(struct work_struct *work)
1157 {
1158         struct tegra_xusb *tegra = container_of(work, struct tegra_xusb,
1159                                                 id_work);
1160         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1161         struct tegra_xusb_mbox_msg msg;
1162         struct phy *phy = tegra_xusb_get_phy(tegra, "usb2",
1163                                                     tegra->otg_usb2_port);
1164         u32 status;
1165         int ret;
1166
1167         dev_dbg(tegra->dev, "host mode %s\n", tegra->host_mode ? "on" : "off");
1168
1169         mutex_lock(&tegra->lock);
1170
1171         if (tegra->host_mode)
1172                 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_HOST);
1173         else
1174                 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_NONE);
1175
1176         mutex_unlock(&tegra->lock);
1177
1178         if (tegra->host_mode) {
1179                 /* switch to host mode */
1180                 if (tegra->otg_usb3_port >= 0) {
1181                         if (tegra->soc->otg_reset_sspi) {
1182                                 /* set PP=0 */
1183                                 tegra_xhci_hc_driver.hub_control(
1184                                         xhci->shared_hcd, GetPortStatus,
1185                                         0, tegra->otg_usb3_port+1,
1186                                         (char *) &status, sizeof(status));
1187                                 if (status & USB_SS_PORT_STAT_POWER)
1188                                         tegra_xhci_set_port_power(tegra, false,
1189                                                                   false);
1190
1191                                 /* reset OTG port SSPI */
1192                                 msg.cmd = MBOX_CMD_RESET_SSPI;
1193                                 msg.data = tegra->otg_usb3_port+1;
1194
1195                                 ret = tegra_xusb_mbox_send(tegra, &msg);
1196                                 if (ret < 0) {
1197                                         dev_info(tegra->dev,
1198                                                 "failed to RESET_SSPI %d\n",
1199                                                 ret);
1200                                 }
1201                         }
1202
1203                         tegra_xhci_set_port_power(tegra, false, true);
1204                 }
1205
1206                 tegra_xhci_set_port_power(tegra, true, true);
1207
1208         } else {
1209                 if (tegra->otg_usb3_port >= 0)
1210                         tegra_xhci_set_port_power(tegra, false, false);
1211
1212                 tegra_xhci_set_port_power(tegra, true, false);
1213         }
1214 }
1215
1216 static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra,
1217                                               struct usb_phy *usbphy)
1218 {
1219         unsigned int i;
1220
1221         for (i = 0; i < tegra->num_usb_phys; i++) {
1222                 if (tegra->usbphy[i] && usbphy == tegra->usbphy[i])
1223                         return i;
1224         }
1225
1226         return -1;
1227 }
1228
1229 static int tegra_xhci_id_notify(struct notifier_block *nb,
1230                                          unsigned long action, void *data)
1231 {
1232         struct tegra_xusb *tegra = container_of(nb, struct tegra_xusb,
1233                                                     id_nb);
1234         struct usb_phy *usbphy = (struct usb_phy *)data;
1235
1236         dev_dbg(tegra->dev, "%s(): action is %d", __func__, usbphy->last_event);
1237
1238         if ((tegra->host_mode && usbphy->last_event == USB_EVENT_ID) ||
1239                 (!tegra->host_mode && usbphy->last_event != USB_EVENT_ID)) {
1240                 dev_dbg(tegra->dev, "Same role(%d) received. Ignore",
1241                         tegra->host_mode);
1242                 return NOTIFY_OK;
1243         }
1244
1245         tegra->otg_usb2_port = tegra_xusb_get_usb2_port(tegra, usbphy);
1246         tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion(
1247                                                         tegra->padctl,
1248                                                         tegra->otg_usb2_port);
1249
1250         tegra->host_mode = (usbphy->last_event == USB_EVENT_ID) ? true : false;
1251
1252         schedule_work(&tegra->id_work);
1253
1254         return NOTIFY_OK;
1255 }
1256
1257 static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra)
1258 {
1259         unsigned int i;
1260
1261         tegra->usbphy = devm_kcalloc(tegra->dev, tegra->num_usb_phys,
1262                                    sizeof(*tegra->usbphy), GFP_KERNEL);
1263         if (!tegra->usbphy)
1264                 return -ENOMEM;
1265
1266         INIT_WORK(&tegra->id_work, tegra_xhci_id_work);
1267         tegra->id_nb.notifier_call = tegra_xhci_id_notify;
1268         tegra->otg_usb2_port = -EINVAL;
1269         tegra->otg_usb3_port = -EINVAL;
1270
1271         for (i = 0; i < tegra->num_usb_phys; i++) {
1272                 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i);
1273
1274                 if (!phy)
1275                         continue;
1276
1277                 tegra->usbphy[i] = devm_usb_get_phy_by_node(tegra->dev,
1278                                                         phy->dev.of_node,
1279                                                         &tegra->id_nb);
1280                 if (!IS_ERR(tegra->usbphy[i])) {
1281                         dev_dbg(tegra->dev, "usbphy-%d registered", i);
1282                         otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self);
1283                 } else {
1284                         /*
1285                          * usb-phy is optional, continue if its not available.
1286                          */
1287                         tegra->usbphy[i] = NULL;
1288                 }
1289         }
1290
1291         return 0;
1292 }
1293
1294 static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra)
1295 {
1296         unsigned int i;
1297
1298         cancel_work_sync(&tegra->id_work);
1299
1300         for (i = 0; i < tegra->num_usb_phys; i++)
1301                 if (tegra->usbphy[i])
1302                         otg_set_host(tegra->usbphy[i]->otg, NULL);
1303 }
1304
1305 static int tegra_xusb_probe(struct platform_device *pdev)
1306 {
1307         struct tegra_xusb *tegra;
1308         struct resource *regs;
1309         struct xhci_hcd *xhci;
1310         unsigned int i, j, k;
1311         struct phy *phy;
1312         int err;
1313
1314         BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
1315
1316         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
1317         if (!tegra)
1318                 return -ENOMEM;
1319
1320         tegra->soc = of_device_get_match_data(&pdev->dev);
1321         mutex_init(&tegra->lock);
1322         tegra->dev = &pdev->dev;
1323
1324         err = tegra_xusb_init_context(tegra);
1325         if (err < 0)
1326                 return err;
1327
1328         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1329         tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
1330         if (IS_ERR(tegra->regs))
1331                 return PTR_ERR(tegra->regs);
1332
1333         tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1);
1334         if (IS_ERR(tegra->fpci_base))
1335                 return PTR_ERR(tegra->fpci_base);
1336
1337         if (tegra->soc->has_ipfs) {
1338                 tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2);
1339                 if (IS_ERR(tegra->ipfs_base))
1340                         return PTR_ERR(tegra->ipfs_base);
1341         }
1342
1343         tegra->xhci_irq = platform_get_irq(pdev, 0);
1344         if (tegra->xhci_irq < 0)
1345                 return tegra->xhci_irq;
1346
1347         tegra->mbox_irq = platform_get_irq(pdev, 1);
1348         if (tegra->mbox_irq < 0)
1349                 return tegra->mbox_irq;
1350
1351         tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
1352         if (IS_ERR(tegra->padctl))
1353                 return PTR_ERR(tegra->padctl);
1354
1355         tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
1356         if (IS_ERR(tegra->host_clk)) {
1357                 err = PTR_ERR(tegra->host_clk);
1358                 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
1359                 goto put_padctl;
1360         }
1361
1362         tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
1363         if (IS_ERR(tegra->falcon_clk)) {
1364                 err = PTR_ERR(tegra->falcon_clk);
1365                 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
1366                 goto put_padctl;
1367         }
1368
1369         tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
1370         if (IS_ERR(tegra->ss_clk)) {
1371                 err = PTR_ERR(tegra->ss_clk);
1372                 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
1373                 goto put_padctl;
1374         }
1375
1376         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
1377         if (IS_ERR(tegra->ss_src_clk)) {
1378                 err = PTR_ERR(tegra->ss_src_clk);
1379                 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
1380                 goto put_padctl;
1381         }
1382
1383         tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
1384         if (IS_ERR(tegra->hs_src_clk)) {
1385                 err = PTR_ERR(tegra->hs_src_clk);
1386                 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
1387                 goto put_padctl;
1388         }
1389
1390         tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
1391         if (IS_ERR(tegra->fs_src_clk)) {
1392                 err = PTR_ERR(tegra->fs_src_clk);
1393                 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
1394                 goto put_padctl;
1395         }
1396
1397         tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1398         if (IS_ERR(tegra->pll_u_480m)) {
1399                 err = PTR_ERR(tegra->pll_u_480m);
1400                 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1401                 goto put_padctl;
1402         }
1403
1404         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1405         if (IS_ERR(tegra->clk_m)) {
1406                 err = PTR_ERR(tegra->clk_m);
1407                 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1408                 goto put_padctl;
1409         }
1410
1411         tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1412         if (IS_ERR(tegra->pll_e)) {
1413                 err = PTR_ERR(tegra->pll_e);
1414                 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1415                 goto put_padctl;
1416         }
1417
1418         if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1419                 tegra->host_rst = devm_reset_control_get(&pdev->dev,
1420                                                          "xusb_host");
1421                 if (IS_ERR(tegra->host_rst)) {
1422                         err = PTR_ERR(tegra->host_rst);
1423                         dev_err(&pdev->dev,
1424                                 "failed to get xusb_host reset: %d\n", err);
1425                         goto put_padctl;
1426                 }
1427
1428                 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
1429                 if (IS_ERR(tegra->ss_rst)) {
1430                         err = PTR_ERR(tegra->ss_rst);
1431                         dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
1432                                 err);
1433                         goto put_padctl;
1434                 }
1435
1436                 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
1437                                                         tegra->ss_clk,
1438                                                         tegra->ss_rst);
1439                 if (err) {
1440                         dev_err(&pdev->dev,
1441                                 "failed to enable XUSBA domain: %d\n", err);
1442                         goto put_padctl;
1443                 }
1444
1445                 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1446                                                         tegra->host_clk,
1447                                                         tegra->host_rst);
1448                 if (err) {
1449                         tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1450                         dev_err(&pdev->dev,
1451                                 "failed to enable XUSBC domain: %d\n", err);
1452                         goto put_padctl;
1453                 }
1454         } else {
1455                 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra);
1456                 if (err)
1457                         goto put_powerdomains;
1458         }
1459
1460         tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1461                                        sizeof(*tegra->supplies), GFP_KERNEL);
1462         if (!tegra->supplies) {
1463                 err = -ENOMEM;
1464                 goto put_powerdomains;
1465         }
1466
1467         regulator_bulk_set_supply_names(tegra->supplies,
1468                                         tegra->soc->supply_names,
1469                                         tegra->soc->num_supplies);
1470
1471         err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1472                                       tegra->supplies);
1473         if (err) {
1474                 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1475                 goto put_powerdomains;
1476         }
1477
1478         for (i = 0; i < tegra->soc->num_types; i++) {
1479                 if (!strncmp(tegra->soc->phy_types[i].name, "usb2", 4))
1480                         tegra->num_usb_phys = tegra->soc->phy_types[i].num;
1481                 tegra->num_phys += tegra->soc->phy_types[i].num;
1482         }
1483
1484         tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1485                                    sizeof(*tegra->phys), GFP_KERNEL);
1486         if (!tegra->phys) {
1487                 err = -ENOMEM;
1488                 goto put_powerdomains;
1489         }
1490
1491         for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1492                 char prop[8];
1493
1494                 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1495                         snprintf(prop, sizeof(prop), "%s-%d",
1496                                  tegra->soc->phy_types[i].name, j);
1497
1498                         phy = devm_phy_optional_get(&pdev->dev, prop);
1499                         if (IS_ERR(phy)) {
1500                                 dev_err(&pdev->dev,
1501                                         "failed to get PHY %s: %ld\n", prop,
1502                                         PTR_ERR(phy));
1503                                 err = PTR_ERR(phy);
1504                                 goto put_powerdomains;
1505                         }
1506
1507                         tegra->phys[k++] = phy;
1508                 }
1509         }
1510
1511         tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1512                                     dev_name(&pdev->dev));
1513         if (!tegra->hcd) {
1514                 err = -ENOMEM;
1515                 goto put_powerdomains;
1516         }
1517
1518         tegra->hcd->regs = tegra->regs;
1519         tegra->hcd->rsrc_start = regs->start;
1520         tegra->hcd->rsrc_len = resource_size(regs);
1521
1522         /*
1523          * This must happen after usb_create_hcd(), because usb_create_hcd()
1524          * will overwrite the drvdata of the device with the hcd it creates.
1525          */
1526         platform_set_drvdata(pdev, tegra);
1527
1528         err = tegra_xusb_phy_enable(tegra);
1529         if (err < 0) {
1530                 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1531                 goto put_hcd;
1532         }
1533
1534         /*
1535          * The XUSB Falcon microcontroller can only address 40 bits, so set
1536          * the DMA mask accordingly.
1537          */
1538         err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40));
1539         if (err < 0) {
1540                 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
1541                 goto disable_phy;
1542         }
1543
1544         err = tegra_xusb_request_firmware(tegra);
1545         if (err < 0) {
1546                 dev_err(&pdev->dev, "failed to request firmware: %d\n", err);
1547                 goto disable_phy;
1548         }
1549
1550         pm_runtime_enable(&pdev->dev);
1551
1552         if (!pm_runtime_enabled(&pdev->dev))
1553                 err = tegra_xusb_runtime_resume(&pdev->dev);
1554         else
1555                 err = pm_runtime_get_sync(&pdev->dev);
1556
1557         if (err < 0) {
1558                 dev_err(&pdev->dev, "failed to enable device: %d\n", err);
1559                 goto free_firmware;
1560         }
1561
1562         tegra_xusb_config(tegra);
1563
1564         err = tegra_xusb_load_firmware(tegra);
1565         if (err < 0) {
1566                 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1567                 goto put_rpm;
1568         }
1569
1570         err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1571         if (err < 0) {
1572                 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1573                 goto put_rpm;
1574         }
1575
1576         device_wakeup_enable(tegra->hcd->self.controller);
1577
1578         xhci = hcd_to_xhci(tegra->hcd);
1579
1580         xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1581                                                  &pdev->dev,
1582                                                  dev_name(&pdev->dev),
1583                                                  tegra->hcd);
1584         if (!xhci->shared_hcd) {
1585                 dev_err(&pdev->dev, "failed to create shared HCD\n");
1586                 err = -ENOMEM;
1587                 goto remove_usb2;
1588         }
1589
1590         err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1591         if (err < 0) {
1592                 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1593                 goto put_usb3;
1594         }
1595
1596         err = tegra_xusb_enable_firmware_messages(tegra);
1597         if (err < 0) {
1598                 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1599                 goto remove_usb3;
1600         }
1601
1602         err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1603                                         tegra_xusb_mbox_irq,
1604                                         tegra_xusb_mbox_thread, 0,
1605                                         dev_name(&pdev->dev), tegra);
1606         if (err < 0) {
1607                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1608                 goto remove_usb3;
1609         }
1610
1611         err = tegra_xusb_init_usb_phy(tegra);
1612         if (err < 0) {
1613                 dev_err(&pdev->dev, "failed to init USB PHY: %d\n", err);
1614                 goto remove_usb3;
1615         }
1616
1617         return 0;
1618
1619 remove_usb3:
1620         usb_remove_hcd(xhci->shared_hcd);
1621 put_usb3:
1622         usb_put_hcd(xhci->shared_hcd);
1623 remove_usb2:
1624         usb_remove_hcd(tegra->hcd);
1625 put_rpm:
1626         if (!pm_runtime_status_suspended(&pdev->dev))
1627                 tegra_xusb_runtime_suspend(&pdev->dev);
1628 put_hcd:
1629         usb_put_hcd(tegra->hcd);
1630 free_firmware:
1631         dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1632                           tegra->fw.phys);
1633 disable_phy:
1634         tegra_xusb_phy_disable(tegra);
1635         pm_runtime_disable(&pdev->dev);
1636 put_powerdomains:
1637         if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1638                 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1639                 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1640         } else {
1641                 tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1642         }
1643 put_padctl:
1644         tegra_xusb_padctl_put(tegra->padctl);
1645         return err;
1646 }
1647
1648 static int tegra_xusb_remove(struct platform_device *pdev)
1649 {
1650         struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1651         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1652
1653         tegra_xusb_deinit_usb_phy(tegra);
1654
1655         usb_remove_hcd(xhci->shared_hcd);
1656         usb_put_hcd(xhci->shared_hcd);
1657         xhci->shared_hcd = NULL;
1658         usb_remove_hcd(tegra->hcd);
1659         usb_put_hcd(tegra->hcd);
1660
1661         dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1662                           tegra->fw.phys);
1663
1664         pm_runtime_put_sync(&pdev->dev);
1665         pm_runtime_disable(&pdev->dev);
1666
1667         if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1668                 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1669                 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1670         } else {
1671                 tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1672         }
1673
1674         tegra_xusb_phy_disable(tegra);
1675
1676         tegra_xusb_padctl_put(tegra->padctl);
1677
1678         return 0;
1679 }
1680
1681 #ifdef CONFIG_PM_SLEEP
1682 static bool xhci_hub_ports_suspended(struct xhci_hub *hub)
1683 {
1684         struct device *dev = hub->hcd->self.controller;
1685         bool status = true;
1686         unsigned int i;
1687         u32 value;
1688
1689         for (i = 0; i < hub->num_ports; i++) {
1690                 value = readl(hub->ports[i]->addr);
1691                 if ((value & PORT_PE) == 0)
1692                         continue;
1693
1694                 if ((value & PORT_PLS_MASK) != XDEV_U3) {
1695                         dev_info(dev, "%u-%u isn't suspended: %#010x\n",
1696                                  hub->hcd->self.busnum, i + 1, value);
1697                         status = false;
1698                 }
1699         }
1700
1701         return status;
1702 }
1703
1704 static int tegra_xusb_check_ports(struct tegra_xusb *tegra)
1705 {
1706         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1707         unsigned long flags;
1708         int err = 0;
1709
1710         spin_lock_irqsave(&xhci->lock, flags);
1711
1712         if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) ||
1713             !xhci_hub_ports_suspended(&xhci->usb3_rhub))
1714                 err = -EBUSY;
1715
1716         spin_unlock_irqrestore(&xhci->lock, flags);
1717
1718         return err;
1719 }
1720
1721 static void tegra_xusb_save_context(struct tegra_xusb *tegra)
1722 {
1723         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
1724         struct tegra_xusb_context *ctx = &tegra->context;
1725         unsigned int i;
1726
1727         if (soc->ipfs.num_offsets > 0) {
1728                 for (i = 0; i < soc->ipfs.num_offsets; i++)
1729                         ctx->ipfs[i] = ipfs_readl(tegra, soc->ipfs.offsets[i]);
1730         }
1731
1732         if (soc->fpci.num_offsets > 0) {
1733                 for (i = 0; i < soc->fpci.num_offsets; i++)
1734                         ctx->fpci[i] = fpci_readl(tegra, soc->fpci.offsets[i]);
1735         }
1736 }
1737
1738 static void tegra_xusb_restore_context(struct tegra_xusb *tegra)
1739 {
1740         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
1741         struct tegra_xusb_context *ctx = &tegra->context;
1742         unsigned int i;
1743
1744         if (soc->fpci.num_offsets > 0) {
1745                 for (i = 0; i < soc->fpci.num_offsets; i++)
1746                         fpci_writel(tegra, ctx->fpci[i], soc->fpci.offsets[i]);
1747         }
1748
1749         if (soc->ipfs.num_offsets > 0) {
1750                 for (i = 0; i < soc->ipfs.num_offsets; i++)
1751                         ipfs_writel(tegra, ctx->ipfs[i], soc->ipfs.offsets[i]);
1752         }
1753 }
1754
1755 static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool wakeup)
1756 {
1757         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1758         int err;
1759
1760         err = tegra_xusb_check_ports(tegra);
1761         if (err < 0) {
1762                 dev_err(tegra->dev, "not all ports suspended: %d\n", err);
1763                 return err;
1764         }
1765
1766         err = xhci_suspend(xhci, wakeup);
1767         if (err < 0) {
1768                 dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err);
1769                 return err;
1770         }
1771
1772         tegra_xusb_save_context(tegra);
1773         tegra_xusb_phy_disable(tegra);
1774         tegra_xusb_clk_disable(tegra);
1775
1776         return 0;
1777 }
1778
1779 static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool wakeup)
1780 {
1781         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1782         int err;
1783
1784         err = tegra_xusb_clk_enable(tegra);
1785         if (err < 0) {
1786                 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
1787                 return err;
1788         }
1789
1790         err = tegra_xusb_phy_enable(tegra);
1791         if (err < 0) {
1792                 dev_err(tegra->dev, "failed to enable PHYs: %d\n", err);
1793                 goto disable_clk;
1794         }
1795
1796         tegra_xusb_config(tegra);
1797         tegra_xusb_restore_context(tegra);
1798
1799         err = tegra_xusb_load_firmware(tegra);
1800         if (err < 0) {
1801                 dev_err(tegra->dev, "failed to load firmware: %d\n", err);
1802                 goto disable_phy;
1803         }
1804
1805         err = __tegra_xusb_enable_firmware_messages(tegra);
1806         if (err < 0) {
1807                 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
1808                 goto disable_phy;
1809         }
1810
1811         err = xhci_resume(xhci, true);
1812         if (err < 0) {
1813                 dev_err(tegra->dev, "failed to resume XHCI: %d\n", err);
1814                 goto disable_phy;
1815         }
1816
1817         return 0;
1818
1819 disable_phy:
1820         tegra_xusb_phy_disable(tegra);
1821 disable_clk:
1822         tegra_xusb_clk_disable(tegra);
1823         return err;
1824 }
1825
1826 static int tegra_xusb_suspend(struct device *dev)
1827 {
1828         struct tegra_xusb *tegra = dev_get_drvdata(dev);
1829         bool wakeup = device_may_wakeup(dev);
1830         int err;
1831
1832         synchronize_irq(tegra->mbox_irq);
1833
1834         mutex_lock(&tegra->lock);
1835         err = tegra_xusb_enter_elpg(tegra, wakeup);
1836         mutex_unlock(&tegra->lock);
1837
1838         return err;
1839 }
1840
1841 static int tegra_xusb_resume(struct device *dev)
1842 {
1843         struct tegra_xusb *tegra = dev_get_drvdata(dev);
1844         bool wakeup = device_may_wakeup(dev);
1845         int err;
1846
1847         mutex_lock(&tegra->lock);
1848         err = tegra_xusb_exit_elpg(tegra, wakeup);
1849         mutex_unlock(&tegra->lock);
1850
1851         return err;
1852 }
1853 #endif
1854
1855 static const struct dev_pm_ops tegra_xusb_pm_ops = {
1856         SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
1857                            tegra_xusb_runtime_resume, NULL)
1858         SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
1859 };
1860
1861 static const char * const tegra124_supply_names[] = {
1862         "avddio-pex",
1863         "dvddio-pex",
1864         "avdd-usb",
1865         "hvdd-usb-ss",
1866 };
1867
1868 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
1869         { .name = "usb3", .num = 2, },
1870         { .name = "usb2", .num = 3, },
1871         { .name = "hsic", .num = 2, },
1872 };
1873
1874 static const unsigned int tegra124_xusb_context_ipfs[] = {
1875         IPFS_XUSB_HOST_MSI_BAR_SZ_0,
1876         IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0,
1877         IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0,
1878         IPFS_XUSB_HOST_MSI_VEC0_0,
1879         IPFS_XUSB_HOST_MSI_EN_VEC0_0,
1880         IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0,
1881         IPFS_XUSB_HOST_INTR_MASK_0,
1882         IPFS_XUSB_HOST_INTR_ENABLE_0,
1883         IPFS_XUSB_HOST_UFPCI_CONFIG_0,
1884         IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0,
1885         IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0,
1886 };
1887
1888 static const unsigned int tegra124_xusb_context_fpci[] = {
1889         XUSB_CFG_ARU_CONTEXT_HS_PLS,
1890         XUSB_CFG_ARU_CONTEXT_FS_PLS,
1891         XUSB_CFG_ARU_CONTEXT_HSFS_SPEED,
1892         XUSB_CFG_ARU_CONTEXT_HSFS_PP,
1893         XUSB_CFG_ARU_CONTEXT,
1894         XUSB_CFG_AXI_CFG,
1895         XUSB_CFG_24,
1896         XUSB_CFG_16,
1897 };
1898
1899 static const struct tegra_xusb_context_soc tegra124_xusb_context = {
1900         .ipfs = {
1901                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs),
1902                 .offsets = tegra124_xusb_context_ipfs,
1903         },
1904         .fpci = {
1905                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
1906                 .offsets = tegra124_xusb_context_fpci,
1907         },
1908 };
1909
1910 static const struct tegra_xusb_soc tegra124_soc = {
1911         .firmware = "/*(DEBLOBBED)*/",
1912         .supply_names = tegra124_supply_names,
1913         .num_supplies = ARRAY_SIZE(tegra124_supply_names),
1914         .phy_types = tegra124_phy_types,
1915         .num_types = ARRAY_SIZE(tegra124_phy_types),
1916         .context = &tegra124_xusb_context,
1917         .ports = {
1918                 .usb2 = { .offset = 4, .count = 4, },
1919                 .hsic = { .offset = 6, .count = 2, },
1920                 .usb3 = { .offset = 0, .count = 2, },
1921         },
1922         .scale_ss_clock = true,
1923         .has_ipfs = true,
1924         .otg_reset_sspi = false,
1925         .mbox = {
1926                 .cmd = 0xe4,
1927                 .data_in = 0xe8,
1928                 .data_out = 0xec,
1929                 .owner = 0xf0,
1930         },
1931 };
1932 /*(DEBLOBBED)*/
1933
1934 static const char * const tegra210_supply_names[] = {
1935         "dvddio-pex",
1936         "hvddio-pex",
1937         "avdd-usb",
1938 };
1939
1940 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
1941         { .name = "usb3", .num = 4, },
1942         { .name = "usb2", .num = 4, },
1943         { .name = "hsic", .num = 1, },
1944 };
1945
1946 static const struct tegra_xusb_soc tegra210_soc = {
1947         .firmware = "/*(DEBLOBBED)*/",
1948         .supply_names = tegra210_supply_names,
1949         .num_supplies = ARRAY_SIZE(tegra210_supply_names),
1950         .phy_types = tegra210_phy_types,
1951         .num_types = ARRAY_SIZE(tegra210_phy_types),
1952         .context = &tegra124_xusb_context,
1953         .ports = {
1954                 .usb2 = { .offset = 4, .count = 4, },
1955                 .hsic = { .offset = 8, .count = 1, },
1956                 .usb3 = { .offset = 0, .count = 4, },
1957         },
1958         .scale_ss_clock = false,
1959         .has_ipfs = true,
1960         .otg_reset_sspi = true,
1961         .mbox = {
1962                 .cmd = 0xe4,
1963                 .data_in = 0xe8,
1964                 .data_out = 0xec,
1965                 .owner = 0xf0,
1966         },
1967 };
1968 /*(DEBLOBBED)*/
1969
1970 static const char * const tegra186_supply_names[] = {
1971 };
1972 /*(DEBLOBBED)*/
1973
1974 static const struct tegra_xusb_phy_type tegra186_phy_types[] = {
1975         { .name = "usb3", .num = 3, },
1976         { .name = "usb2", .num = 3, },
1977         { .name = "hsic", .num = 1, },
1978 };
1979
1980 static const struct tegra_xusb_context_soc tegra186_xusb_context = {
1981         .fpci = {
1982                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
1983                 .offsets = tegra124_xusb_context_fpci,
1984         },
1985 };
1986
1987 static const struct tegra_xusb_soc tegra186_soc = {
1988         .firmware = "/*(DEBLOBBED)*/",
1989         .supply_names = tegra186_supply_names,
1990         .num_supplies = ARRAY_SIZE(tegra186_supply_names),
1991         .phy_types = tegra186_phy_types,
1992         .num_types = ARRAY_SIZE(tegra186_phy_types),
1993         .context = &tegra186_xusb_context,
1994         .ports = {
1995                 .usb3 = { .offset = 0, .count = 3, },
1996                 .usb2 = { .offset = 3, .count = 3, },
1997                 .hsic = { .offset = 6, .count = 1, },
1998         },
1999         .scale_ss_clock = false,
2000         .has_ipfs = false,
2001         .otg_reset_sspi = false,
2002         .mbox = {
2003                 .cmd = 0xe4,
2004                 .data_in = 0xe8,
2005                 .data_out = 0xec,
2006                 .owner = 0xf0,
2007         },
2008         .lpm_support = true,
2009 };
2010
2011 static const char * const tegra194_supply_names[] = {
2012 };
2013
2014 static const struct tegra_xusb_phy_type tegra194_phy_types[] = {
2015         { .name = "usb3", .num = 4, },
2016         { .name = "usb2", .num = 4, },
2017 };
2018
2019 static const struct tegra_xusb_soc tegra194_soc = {
2020         .firmware = "/*(DEBLOBBED)*/",
2021         .supply_names = tegra194_supply_names,
2022         .num_supplies = ARRAY_SIZE(tegra194_supply_names),
2023         .phy_types = tegra194_phy_types,
2024         .num_types = ARRAY_SIZE(tegra194_phy_types),
2025         .context = &tegra186_xusb_context,
2026         .ports = {
2027                 .usb3 = { .offset = 0, .count = 4, },
2028                 .usb2 = { .offset = 4, .count = 4, },
2029         },
2030         .scale_ss_clock = false,
2031         .has_ipfs = false,
2032         .otg_reset_sspi = false,
2033         .mbox = {
2034                 .cmd = 0x68,
2035                 .data_in = 0x6c,
2036                 .data_out = 0x70,
2037                 .owner = 0x74,
2038         },
2039         .lpm_support = true,
2040 };
2041 /*(DEBLOBBED)*/
2042
2043 static const struct of_device_id tegra_xusb_of_match[] = {
2044         { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
2045         { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
2046         { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc },
2047         { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc },
2048         { },
2049 };
2050 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
2051
2052 static struct platform_driver tegra_xusb_driver = {
2053         .probe = tegra_xusb_probe,
2054         .remove = tegra_xusb_remove,
2055         .driver = {
2056                 .name = "tegra-xusb",
2057                 .pm = &tegra_xusb_pm_ops,
2058                 .of_match_table = tegra_xusb_of_match,
2059         },
2060 };
2061
2062 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
2063 {
2064         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2065
2066         xhci->quirks |= XHCI_PLAT;
2067         if (tegra && tegra->soc->lpm_support)
2068                 xhci->quirks |= XHCI_LPM_SUPPORT;
2069 }
2070
2071 static int tegra_xhci_setup(struct usb_hcd *hcd)
2072 {
2073         return xhci_gen_setup(hcd, tegra_xhci_quirks);
2074 }
2075
2076 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
2077         .reset = tegra_xhci_setup,
2078 };
2079
2080 static int __init tegra_xusb_init(void)
2081 {
2082         xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
2083
2084         return platform_driver_register(&tegra_xusb_driver);
2085 }
2086 module_init(tegra_xusb_init);
2087
2088 static void __exit tegra_xusb_exit(void)
2089 {
2090         platform_driver_unregister(&tegra_xusb_driver);
2091 }
2092 module_exit(tegra_xusb_exit);
2093
2094 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
2095 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
2096 MODULE_LICENSE("GPL v2");