1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
59 #include "xhci-trace.h"
63 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
66 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
69 unsigned long segment_offset;
71 if (!seg || !trb || trb < seg->trbs)
74 segment_offset = trb - seg->trbs;
75 if (segment_offset >= TRBS_PER_SEGMENT)
77 return seg->dma + (segment_offset * sizeof(*trb));
80 static bool trb_is_noop(union xhci_trb *trb)
82 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
85 static bool trb_is_link(union xhci_trb *trb)
87 return TRB_TYPE_LINK_LE32(trb->link.control);
90 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
92 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
95 static bool last_trb_on_ring(struct xhci_ring *ring,
96 struct xhci_segment *seg, union xhci_trb *trb)
98 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
101 static bool link_trb_toggles_cycle(union xhci_trb *trb)
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
106 static bool last_td_in_urb(struct xhci_td *td)
108 struct urb_priv *urb_priv = td->urb->hcpriv;
110 return urb_priv->num_tds_done == urb_priv->num_tds;
113 static void inc_td_cnt(struct urb *urb)
115 struct urb_priv *urb_priv = urb->hcpriv;
117 urb_priv->num_tds_done++;
120 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
122 if (trb_is_link(trb)) {
123 /* unchain chained link TRBs */
124 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
126 trb->generic.field[0] = 0;
127 trb->generic.field[1] = 0;
128 trb->generic.field[2] = 0;
129 /* Preserve only the cycle bit of this TRB */
130 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
131 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
135 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
136 * TRB is in a new segment. This does not skip over link TRBs, and it does not
137 * effect the ring dequeue or enqueue pointers.
139 static void next_trb(struct xhci_hcd *xhci,
140 struct xhci_ring *ring,
141 struct xhci_segment **seg,
142 union xhci_trb **trb)
144 if (trb_is_link(*trb)) {
146 *trb = ((*seg)->trbs);
153 * See Cycle bit rules. SW is the consumer for the event ring only.
154 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
156 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
158 /* event ring doesn't have link trbs, check for last trb */
159 if (ring->type == TYPE_EVENT) {
160 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
164 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
165 ring->cycle_state ^= 1;
166 ring->deq_seg = ring->deq_seg->next;
167 ring->dequeue = ring->deq_seg->trbs;
171 /* All other rings have link trbs */
172 if (!trb_is_link(ring->dequeue)) {
174 ring->num_trbs_free++;
176 while (trb_is_link(ring->dequeue)) {
177 ring->deq_seg = ring->deq_seg->next;
178 ring->dequeue = ring->deq_seg->trbs;
182 trace_xhci_inc_deq(ring);
188 * See Cycle bit rules. SW is the consumer for the event ring only.
189 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
191 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
192 * chain bit is set), then set the chain bit in all the following link TRBs.
193 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
194 * have their chain bit cleared (so that each Link TRB is a separate TD).
196 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
197 * set, but other sections talk about dealing with the chain bit set. This was
198 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
199 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
201 * @more_trbs_coming: Will you enqueue more TRBs before calling
202 * prepare_transfer()?
204 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
205 bool more_trbs_coming)
208 union xhci_trb *next;
210 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
211 /* If this is not event ring, there is one less usable TRB */
212 if (!trb_is_link(ring->enqueue))
213 ring->num_trbs_free--;
214 next = ++(ring->enqueue);
216 /* Update the dequeue pointer further if that was a link TRB */
217 while (trb_is_link(next)) {
220 * If the caller doesn't plan on enqueueing more TDs before
221 * ringing the doorbell, then we don't want to give the link TRB
222 * to the hardware just yet. We'll give the link TRB back in
223 * prepare_ring() just before we enqueue the TD at the top of
226 if (!chain && !more_trbs_coming)
229 /* If we're not dealing with 0.95 hardware or isoc rings on
230 * AMD 0.96 host, carry over the chain bit of the previous TRB
231 * (which may mean the chain bit is cleared).
233 if (!(ring->type == TYPE_ISOC &&
234 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
235 !xhci_link_trb_quirk(xhci)) {
236 next->link.control &= cpu_to_le32(~TRB_CHAIN);
237 next->link.control |= cpu_to_le32(chain);
239 /* Give this link TRB to the hardware */
241 next->link.control ^= cpu_to_le32(TRB_CYCLE);
243 /* Toggle the cycle bit after the last ring segment. */
244 if (link_trb_toggles_cycle(next))
245 ring->cycle_state ^= 1;
247 ring->enq_seg = ring->enq_seg->next;
248 ring->enqueue = ring->enq_seg->trbs;
249 next = ring->enqueue;
252 trace_xhci_inc_enq(ring);
256 * Check to see if there's room to enqueue num_trbs on the ring and make sure
257 * enqueue pointer will not advance into dequeue segment. See rules above.
259 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
260 unsigned int num_trbs)
262 int num_trbs_in_deq_seg;
264 if (ring->num_trbs_free < num_trbs)
267 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
268 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
269 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
276 /* Ring the host controller doorbell after placing a command on the ring */
277 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
279 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
282 xhci_dbg(xhci, "// Ding dong!\n");
284 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
286 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
287 /* Flush PCI posted writes */
288 readl(&xhci->dba->doorbell[0]);
291 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
293 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
296 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
298 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
303 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
304 * If there are other commands waiting then restart the ring and kick the timer.
305 * This must be called with command ring stopped and xhci->lock held.
307 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
308 struct xhci_command *cur_cmd)
310 struct xhci_command *i_cmd;
312 /* Turn all aborted commands in list to no-ops, then restart */
313 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
315 if (i_cmd->status != COMP_COMMAND_ABORTED)
318 i_cmd->status = COMP_COMMAND_RING_STOPPED;
320 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
323 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
326 * caller waiting for completion is called when command
327 * completion event is received for these no-op commands
331 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
333 /* ring command ring doorbell to restart the command ring */
334 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
335 !(xhci->xhc_state & XHCI_STATE_DYING)) {
336 xhci->current_cmd = cur_cmd;
337 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
338 xhci_ring_cmd_db(xhci);
342 /* Must be called with xhci->lock held, releases and aquires lock back */
343 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
345 struct xhci_segment *new_seg = xhci->cmd_ring->deq_seg;
346 union xhci_trb *new_deq = xhci->cmd_ring->dequeue;
350 xhci_dbg(xhci, "Abort command ring\n");
352 reinit_completion(&xhci->cmd_ring_stop_completion);
355 * The control bits like command stop, abort are located in lower
356 * dword of the command ring control register.
357 * Some controllers require all 64 bits to be written to abort the ring.
358 * Make sure the upper dword is valid, pointing to the next command,
359 * avoiding corrupting the command ring pointer in case the command ring
360 * is stopped by the time the upper dword is written.
362 next_trb(xhci, NULL, &new_seg, &new_deq);
363 if (trb_is_link(new_deq))
364 next_trb(xhci, NULL, &new_seg, &new_deq);
366 crcr = xhci_trb_virt_to_dma(new_seg, new_deq);
367 xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
369 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
370 * completion of the Command Abort operation. If CRR is not negated in 5
371 * seconds then driver handles it as if host died (-ENODEV).
372 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
373 * and try to recover a -ETIMEDOUT with a host controller reset.
375 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
376 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
378 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
384 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
385 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
386 * but the completion event in never sent. Wait 2 secs (arbitrary
387 * number) to handle those cases after negation of CMD_RING_RUNNING.
389 spin_unlock_irqrestore(&xhci->lock, flags);
390 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
391 msecs_to_jiffies(2000));
392 spin_lock_irqsave(&xhci->lock, flags);
394 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
395 xhci_cleanup_command_queue(xhci);
397 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
402 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
403 unsigned int slot_id,
404 unsigned int ep_index,
405 unsigned int stream_id)
407 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
408 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
409 unsigned int ep_state = ep->ep_state;
411 /* Don't ring the doorbell for this endpoint if there are pending
412 * cancellations because we don't want to interrupt processing.
413 * We don't want to restart any stream rings if there's a set dequeue
414 * pointer command pending because the device can choose to start any
415 * stream once the endpoint is on the HW schedule.
417 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
418 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
421 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
423 writel(DB_VALUE(ep_index, stream_id), db_addr);
424 /* The CPU has better things to do at this point than wait for a
425 * write-posting flush. It'll get there soon enough.
429 /* Ring the doorbell for any rings with pending URBs */
430 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
431 unsigned int slot_id,
432 unsigned int ep_index)
434 unsigned int stream_id;
435 struct xhci_virt_ep *ep;
437 ep = &xhci->devs[slot_id]->eps[ep_index];
439 /* A ring has pending URBs if its TD list is not empty */
440 if (!(ep->ep_state & EP_HAS_STREAMS)) {
441 if (ep->ring && !(list_empty(&ep->ring->td_list)))
442 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
446 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
448 struct xhci_stream_info *stream_info = ep->stream_info;
449 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
450 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
455 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
456 unsigned int slot_id,
457 unsigned int ep_index)
459 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
462 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
463 unsigned int slot_id,
464 unsigned int ep_index)
466 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
467 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
470 if (ep_index >= EP_CTX_PER_DEV) {
471 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
474 if (!xhci->devs[slot_id]) {
475 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
479 return &xhci->devs[slot_id]->eps[ep_index];
482 /* Get the right ring for the given slot_id, ep_index and stream_id.
483 * If the endpoint supports streams, boundary check the URB's stream ID.
484 * If the endpoint doesn't support streams, return the singular endpoint ring.
486 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
487 unsigned int slot_id, unsigned int ep_index,
488 unsigned int stream_id)
490 struct xhci_virt_ep *ep;
492 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
496 /* Common case: no streams */
497 if (!(ep->ep_state & EP_HAS_STREAMS))
500 if (stream_id == 0) {
502 "WARN: Slot ID %u, ep index %u has streams, "
503 "but URB has no stream ID.\n",
508 if (stream_id < ep->stream_info->num_streams)
509 return ep->stream_info->stream_rings[stream_id];
512 "WARN: Slot ID %u, ep index %u has "
513 "stream IDs 1 to %u allocated, "
514 "but stream ID %u is requested.\n",
516 ep->stream_info->num_streams - 1,
523 * Get the hw dequeue pointer xHC stopped on, either directly from the
524 * endpoint context, or if streams are in use from the stream context.
525 * The returned hw_dequeue contains the lowest four bits with cycle state
526 * and possbile stream context type.
528 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
529 unsigned int ep_index, unsigned int stream_id)
531 struct xhci_ep_ctx *ep_ctx;
532 struct xhci_stream_ctx *st_ctx;
533 struct xhci_virt_ep *ep;
535 ep = &vdev->eps[ep_index];
537 if (ep->ep_state & EP_HAS_STREAMS) {
538 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
539 return le64_to_cpu(st_ctx->stream_ring);
541 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
542 return le64_to_cpu(ep_ctx->deq);
546 * Move the xHC's endpoint ring dequeue pointer past cur_td.
547 * Record the new state of the xHC's endpoint ring dequeue segment,
548 * dequeue pointer, stream id, and new consumer cycle state in state.
549 * Update our internal representation of the ring's dequeue pointer.
551 * We do this in three jumps:
552 * - First we update our new ring state to be the same as when the xHC stopped.
553 * - Then we traverse the ring to find the segment that contains
554 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
555 * any link TRBs with the toggle cycle bit set.
556 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
557 * if we've moved it past a link TRB with the toggle cycle bit set.
559 * Some of the uses of xhci_generic_trb are grotty, but if they're done
560 * with correct __le32 accesses they should work fine. Only users of this are
563 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
564 unsigned int slot_id, unsigned int ep_index,
565 unsigned int stream_id, struct xhci_td *cur_td,
566 struct xhci_dequeue_state *state)
568 struct xhci_virt_device *dev = xhci->devs[slot_id];
569 struct xhci_virt_ep *ep = &dev->eps[ep_index];
570 struct xhci_ring *ep_ring;
571 struct xhci_segment *new_seg;
572 struct xhci_segment *halted_seg = NULL;
573 union xhci_trb *new_deq;
574 union xhci_trb *halted_trb;
578 bool cycle_found = false;
579 bool td_last_trb_found = false;
581 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
582 ep_index, stream_id);
584 xhci_warn(xhci, "WARN can't find new dequeue state "
585 "for invalid stream ID %u.\n",
590 * A cancelled TD can complete with a stall if HW cached the trb.
591 * In this case driver can't find cur_td, but if the ring is empty we
592 * can move the dequeue pointer to the current enqueue position.
595 if (list_empty(&ep_ring->td_list)) {
596 state->new_deq_seg = ep_ring->enq_seg;
597 state->new_deq_ptr = ep_ring->enqueue;
598 state->new_cycle_state = ep_ring->cycle_state;
601 xhci_warn(xhci, "Can't find new dequeue state, missing cur_td\n");
606 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
607 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
608 "Finding endpoint context");
610 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
611 new_seg = ep_ring->deq_seg;
612 new_deq = ep_ring->dequeue;
615 * Quirk: xHC write-back of the DCS field in the hardware dequeue
616 * pointer is wrong - use the cycle state of the TRB pointed to by
617 * the dequeue pointer.
619 if (xhci->quirks & XHCI_EP_CTX_BROKEN_DCS &&
620 !(ep->ep_state & EP_HAS_STREAMS))
621 halted_seg = trb_in_td(xhci, cur_td->start_seg,
622 cur_td->first_trb, cur_td->last_trb,
623 hw_dequeue & ~0xf, false);
625 index = ((dma_addr_t)(hw_dequeue & ~0xf) - halted_seg->dma) /
627 halted_trb = &halted_seg->trbs[index];
628 state->new_cycle_state = halted_trb->generic.field[3] & 0x1;
629 xhci_dbg(xhci, "Endpoint DCS = %d TRB index = %d cycle = %d\n",
630 (u8)(hw_dequeue & 0x1), index,
631 state->new_cycle_state);
633 state->new_cycle_state = hw_dequeue & 0x1;
635 state->stream_id = stream_id;
638 * We want to find the pointer, segment and cycle state of the new trb
639 * (the one after current TD's last_trb). We know the cycle state at
640 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
644 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
645 == (dma_addr_t)(hw_dequeue & ~0xf)) {
647 if (td_last_trb_found)
650 if (new_deq == cur_td->last_trb)
651 td_last_trb_found = true;
653 if (cycle_found && trb_is_link(new_deq) &&
654 link_trb_toggles_cycle(new_deq))
655 state->new_cycle_state ^= 0x1;
657 next_trb(xhci, ep_ring, &new_seg, &new_deq);
659 /* Search wrapped around, bail out */
660 if (new_deq == ep->ring->dequeue) {
661 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
662 state->new_deq_seg = NULL;
663 state->new_deq_ptr = NULL;
667 } while (!cycle_found || !td_last_trb_found);
669 state->new_deq_seg = new_seg;
670 state->new_deq_ptr = new_deq;
673 /* Don't update the ring cycle state for the producer (us). */
674 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
675 "Cycle state = 0x%x", state->new_cycle_state);
677 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
678 "New dequeue segment = %p (virtual)",
680 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
681 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
682 "New dequeue pointer = 0x%llx (DMA)",
683 (unsigned long long) addr);
686 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
687 * (The last TRB actually points to the ring enqueue pointer, which is not part
688 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
690 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
691 struct xhci_td *td, bool flip_cycle)
693 struct xhci_segment *seg = td->start_seg;
694 union xhci_trb *trb = td->first_trb;
697 trb_to_noop(trb, TRB_TR_NOOP);
699 /* flip cycle if asked to */
700 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
701 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
703 if (trb == td->last_trb)
706 next_trb(xhci, ep_ring, &seg, &trb);
710 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
711 struct xhci_virt_ep *ep)
713 ep->ep_state &= ~EP_STOP_CMD_PENDING;
714 /* Can't del_timer_sync in interrupt */
715 del_timer(&ep->stop_cmd_timer);
719 * Must be called with xhci->lock held in interrupt context,
720 * releases and re-acquires xhci->lock
722 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
723 struct xhci_td *cur_td, int status)
725 struct urb *urb = cur_td->urb;
726 struct urb_priv *urb_priv = urb->hcpriv;
727 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
729 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
730 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
731 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
732 if (xhci->quirks & XHCI_AMD_PLL_FIX)
733 usb_amd_quirk_pll_enable();
736 xhci_urb_free_priv(urb_priv);
737 usb_hcd_unlink_urb_from_ep(hcd, urb);
738 trace_xhci_urb_giveback(urb);
739 usb_hcd_giveback_urb(hcd, urb, status);
742 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
743 struct xhci_ring *ring, struct xhci_td *td)
745 struct device *dev = xhci_to_hcd(xhci)->self.controller;
746 struct xhci_segment *seg = td->bounce_seg;
747 struct urb *urb = td->urb;
750 if (!ring || !seg || !urb)
753 if (usb_urb_dir_out(urb)) {
754 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
759 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
761 /* for in tranfers we need to copy the data from bounce to sg */
763 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
764 seg->bounce_len, seg->bounce_offs);
765 if (len != seg->bounce_len)
766 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
767 len, seg->bounce_len);
769 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
773 seg->bounce_offs = 0;
777 * When we get a command completion for a Stop Endpoint Command, we need to
778 * unlink any cancelled TDs from the ring. There are two ways to do that:
780 * 1. If the HW was in the middle of processing the TD that needs to be
781 * cancelled, then we must move the ring's dequeue pointer past the last TRB
782 * in the TD with a Set Dequeue Pointer Command.
783 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
784 * bit cleared) so that the HW will skip over them.
786 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
787 union xhci_trb *trb, struct xhci_event_cmd *event)
789 unsigned int ep_index;
790 struct xhci_ring *ep_ring;
791 struct xhci_virt_ep *ep;
792 struct xhci_td *cur_td = NULL;
793 struct xhci_td *last_unlinked_td;
794 struct xhci_ep_ctx *ep_ctx;
795 struct xhci_virt_device *vdev;
797 struct xhci_dequeue_state deq_state;
799 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
800 if (!xhci->devs[slot_id])
801 xhci_warn(xhci, "Stop endpoint command "
802 "completion for disabled slot %u\n",
807 memset(&deq_state, 0, sizeof(deq_state));
808 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
810 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
814 vdev = xhci->devs[slot_id];
815 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
816 trace_xhci_handle_cmd_stop_ep(ep_ctx);
818 last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
819 struct xhci_td, cancelled_td_list);
821 if (list_empty(&ep->cancelled_td_list)) {
822 xhci_stop_watchdog_timer_in_irq(xhci, ep);
823 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
827 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
828 * We have the xHCI lock, so nothing can modify this list until we drop
829 * it. We're also in the event handler, so we can't get re-interrupted
830 * if another Stop Endpoint command completes
832 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
833 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
834 "Removing canceled TD starting at 0x%llx (dma).",
835 (unsigned long long)xhci_trb_virt_to_dma(
836 cur_td->start_seg, cur_td->first_trb));
837 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
839 /* This shouldn't happen unless a driver is mucking
840 * with the stream ID after submission. This will
841 * leave the TD on the hardware ring, and the hardware
842 * will try to execute it, and may access a buffer
843 * that has already been freed. In the best case, the
844 * hardware will execute it, and the event handler will
845 * ignore the completion event for that TD, since it was
846 * removed from the td_list for that endpoint. In
847 * short, don't muck with the stream ID after
850 xhci_warn(xhci, "WARN Cancelled URB %p "
851 "has invalid stream ID %u.\n",
853 cur_td->urb->stream_id);
854 goto remove_finished_td;
857 * If we stopped on the TD we need to cancel, then we have to
858 * move the xHC endpoint ring dequeue pointer past this TD.
860 hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
861 cur_td->urb->stream_id);
864 if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
865 cur_td->last_trb, hw_deq, false)) {
866 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
867 cur_td->urb->stream_id,
870 td_to_noop(xhci, ep_ring, cur_td, false);
875 * The event handler won't see a completion for this TD anymore,
876 * so remove it from the endpoint ring's TD list. Keep it in
877 * the cancelled TD list for URB completion later.
879 list_del_init(&cur_td->td_list);
882 xhci_stop_watchdog_timer_in_irq(xhci, ep);
884 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
885 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
886 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
888 xhci_ring_cmd_db(xhci);
890 /* Otherwise ring the doorbell(s) to restart queued transfers */
891 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
895 * Drop the lock and complete the URBs in the cancelled TD list.
896 * New TDs to be cancelled might be added to the end of the list before
897 * we can complete all the URBs for the TDs we already unlinked.
898 * So stop when we've completed the URB for the last TD we unlinked.
901 cur_td = list_first_entry(&ep->cancelled_td_list,
902 struct xhci_td, cancelled_td_list);
903 list_del_init(&cur_td->cancelled_td_list);
905 /* Clean up the cancelled URB */
906 /* Doesn't matter what we pass for status, since the core will
907 * just overwrite it (because the URB has been unlinked).
909 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
910 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
911 inc_td_cnt(cur_td->urb);
912 if (last_td_in_urb(cur_td))
913 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
915 /* Stop processing the cancelled list if the watchdog timer is
918 if (xhci->xhc_state & XHCI_STATE_DYING)
920 } while (cur_td != last_unlinked_td);
922 /* Return to the event handler with xhci->lock re-acquired */
925 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
927 struct xhci_td *cur_td;
930 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
931 list_del_init(&cur_td->td_list);
933 if (!list_empty(&cur_td->cancelled_td_list))
934 list_del_init(&cur_td->cancelled_td_list);
936 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
938 inc_td_cnt(cur_td->urb);
939 if (last_td_in_urb(cur_td))
940 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
944 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
945 int slot_id, int ep_index)
947 struct xhci_td *cur_td;
949 struct xhci_virt_ep *ep;
950 struct xhci_ring *ring;
952 ep = &xhci->devs[slot_id]->eps[ep_index];
953 if ((ep->ep_state & EP_HAS_STREAMS) ||
954 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
957 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
959 ring = ep->stream_info->stream_rings[stream_id];
963 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
964 "Killing URBs for slot ID %u, ep index %u, stream %u",
965 slot_id, ep_index, stream_id);
966 xhci_kill_ring_urbs(xhci, ring);
972 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
973 "Killing URBs for slot ID %u, ep index %u",
975 xhci_kill_ring_urbs(xhci, ring);
978 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
980 list_del_init(&cur_td->cancelled_td_list);
981 inc_td_cnt(cur_td->urb);
983 if (last_td_in_urb(cur_td))
984 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
989 * host controller died, register read returns 0xffffffff
990 * Complete pending commands, mark them ABORTED.
991 * URBs need to be given back as usb core might be waiting with device locks
992 * held for the URBs to finish during device disconnect, blocking host remove.
994 * Call with xhci->lock held.
995 * lock is relased and re-acquired while giving back urb.
997 void xhci_hc_died(struct xhci_hcd *xhci)
1001 if (xhci->xhc_state & XHCI_STATE_DYING)
1004 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1005 xhci->xhc_state |= XHCI_STATE_DYING;
1007 xhci_cleanup_command_queue(xhci);
1009 /* return any pending urbs, remove may be waiting for them */
1010 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
1013 for (j = 0; j < 31; j++)
1014 xhci_kill_endpoint_urbs(xhci, i, j);
1017 /* inform usb core hc died if PCI remove isn't already handling it */
1018 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
1019 usb_hc_died(xhci_to_hcd(xhci));
1022 /* Watchdog timer function for when a stop endpoint command fails to complete.
1023 * In this case, we assume the host controller is broken or dying or dead. The
1024 * host may still be completing some other events, so we have to be careful to
1025 * let the event ring handler and the URB dequeueing/enqueueing functions know
1026 * through xhci->state.
1028 * The timer may also fire if the host takes a very long time to respond to the
1029 * command, and the stop endpoint command completion handler cannot delete the
1030 * timer before the timer function is called. Another endpoint cancellation may
1031 * sneak in before the timer function can grab the lock, and that may queue
1032 * another stop endpoint command and add the timer back. So we cannot use a
1033 * simple flag to say whether there is a pending stop endpoint command for a
1034 * particular endpoint.
1036 * Instead we use a combination of that flag and checking if a new timer is
1039 void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
1041 struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
1042 struct xhci_hcd *xhci = ep->xhci;
1043 unsigned long flags;
1045 char str[XHCI_MSG_MAX];
1047 spin_lock_irqsave(&xhci->lock, flags);
1049 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
1050 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
1051 timer_pending(&ep->stop_cmd_timer)) {
1052 spin_unlock_irqrestore(&xhci->lock, flags);
1053 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
1056 usbsts = readl(&xhci->op_regs->status);
1058 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
1059 xhci_warn(xhci, "USBSTS:%s\n", xhci_decode_usbsts(str, usbsts));
1061 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1066 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
1067 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
1068 * and try to recover a -ETIMEDOUT with a host controller reset
1072 spin_unlock_irqrestore(&xhci->lock, flags);
1073 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1074 "xHCI host controller is dead.");
1077 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1078 struct xhci_virt_device *dev,
1079 struct xhci_ring *ep_ring,
1080 unsigned int ep_index)
1082 union xhci_trb *dequeue_temp;
1083 int num_trbs_free_temp;
1084 bool revert = false;
1086 num_trbs_free_temp = ep_ring->num_trbs_free;
1087 dequeue_temp = ep_ring->dequeue;
1089 /* If we get two back-to-back stalls, and the first stalled transfer
1090 * ends just before a link TRB, the dequeue pointer will be left on
1091 * the link TRB by the code in the while loop. So we have to update
1092 * the dequeue pointer one segment further, or we'll jump off
1093 * the segment into la-la-land.
1095 if (trb_is_link(ep_ring->dequeue)) {
1096 ep_ring->deq_seg = ep_ring->deq_seg->next;
1097 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1100 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1101 /* We have more usable TRBs */
1102 ep_ring->num_trbs_free++;
1104 if (trb_is_link(ep_ring->dequeue)) {
1105 if (ep_ring->dequeue ==
1106 dev->eps[ep_index].queued_deq_ptr)
1108 ep_ring->deq_seg = ep_ring->deq_seg->next;
1109 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1111 if (ep_ring->dequeue == dequeue_temp) {
1118 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1119 ep_ring->num_trbs_free = num_trbs_free_temp;
1124 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1125 * we need to clear the set deq pending flag in the endpoint ring state, so that
1126 * the TD queueing code can ring the doorbell again. We also need to ring the
1127 * endpoint doorbell to restart the ring, but only if there aren't more
1128 * cancellations pending.
1130 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1131 union xhci_trb *trb, u32 cmd_comp_code)
1133 unsigned int ep_index;
1134 unsigned int stream_id;
1135 struct xhci_ring *ep_ring;
1136 struct xhci_virt_device *dev;
1137 struct xhci_virt_ep *ep;
1138 struct xhci_ep_ctx *ep_ctx;
1139 struct xhci_slot_ctx *slot_ctx;
1141 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1142 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1143 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1147 dev = xhci->devs[slot_id];
1148 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1150 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1152 /* XXX: Harmless??? */
1156 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1157 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1158 trace_xhci_handle_cmd_set_deq(slot_ctx);
1159 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1161 if (cmd_comp_code != COMP_SUCCESS) {
1162 unsigned int ep_state;
1163 unsigned int slot_state;
1165 switch (cmd_comp_code) {
1166 case COMP_TRB_ERROR:
1167 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1169 case COMP_CONTEXT_STATE_ERROR:
1170 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1171 ep_state = GET_EP_CTX_STATE(ep_ctx);
1172 slot_state = le32_to_cpu(slot_ctx->dev_state);
1173 slot_state = GET_SLOT_STATE(slot_state);
1174 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1175 "Slot state = %u, EP state = %u",
1176 slot_state, ep_state);
1178 case COMP_SLOT_NOT_ENABLED_ERROR:
1179 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1183 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1187 /* OK what do we do now? The endpoint state is hosed, and we
1188 * should never get to this point if the synchronization between
1189 * queueing, and endpoint state are correct. This might happen
1190 * if the device gets disconnected after we've finished
1191 * cancelling URBs, which might not be an error...
1195 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1196 if (ep->ep_state & EP_HAS_STREAMS) {
1197 struct xhci_stream_ctx *ctx =
1198 &ep->stream_info->stream_ctx_array[stream_id];
1199 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1201 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1203 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1204 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1205 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1206 ep->queued_deq_ptr) == deq) {
1207 /* Update the ring's dequeue segment and dequeue pointer
1208 * to reflect the new position.
1210 update_ring_for_set_deq_completion(xhci, dev,
1213 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1214 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1215 ep->queued_deq_seg, ep->queued_deq_ptr);
1220 ep->ep_state &= ~SET_DEQ_PENDING;
1221 ep->queued_deq_seg = NULL;
1222 ep->queued_deq_ptr = NULL;
1223 /* Restart any rings with pending URBs */
1224 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1227 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1228 union xhci_trb *trb, u32 cmd_comp_code)
1230 struct xhci_virt_device *vdev;
1231 struct xhci_virt_ep *ep;
1232 struct xhci_ep_ctx *ep_ctx;
1233 unsigned int ep_index;
1235 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1236 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1240 vdev = xhci->devs[slot_id];
1241 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1242 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1244 /* This command will only fail if the endpoint wasn't halted,
1245 * but we don't care.
1247 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1248 "Ignoring reset ep completion code of %u", cmd_comp_code);
1250 /* HW with the reset endpoint quirk needs to have a configure endpoint
1251 * command complete before the endpoint can be used. Queue that here
1252 * because the HW can't handle two commands being queued in a row.
1254 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1255 struct xhci_command *command;
1257 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1261 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1262 "Queueing configure endpoint command");
1263 xhci_queue_configure_endpoint(xhci, command,
1264 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1266 xhci_ring_cmd_db(xhci);
1268 /* Clear our internal halted state */
1269 ep->ep_state &= ~EP_HALTED;
1272 /* if this was a soft reset, then restart */
1273 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1274 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1277 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1278 struct xhci_command *command, u32 cmd_comp_code)
1280 if (cmd_comp_code == COMP_SUCCESS)
1281 command->slot_id = slot_id;
1283 command->slot_id = 0;
1286 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1288 struct xhci_virt_device *virt_dev;
1289 struct xhci_slot_ctx *slot_ctx;
1291 virt_dev = xhci->devs[slot_id];
1295 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1296 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1298 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1299 /* Delete default control endpoint resources */
1300 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1303 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1304 struct xhci_event_cmd *event, u32 cmd_comp_code)
1306 struct xhci_virt_device *virt_dev;
1307 struct xhci_input_control_ctx *ctrl_ctx;
1308 struct xhci_ep_ctx *ep_ctx;
1309 unsigned int ep_index;
1310 unsigned int ep_state;
1311 u32 add_flags, drop_flags;
1314 * Configure endpoint commands can come from the USB core
1315 * configuration or alt setting changes, or because the HW
1316 * needed an extra configure endpoint command after a reset
1317 * endpoint command or streams were being configured.
1318 * If the command was for a halted endpoint, the xHCI driver
1319 * is not waiting on the configure endpoint command.
1321 virt_dev = xhci->devs[slot_id];
1322 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1324 xhci_warn(xhci, "Could not get input context, bad type.\n");
1328 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1329 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1330 /* Input ctx add_flags are the endpoint index plus one */
1331 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1333 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1334 trace_xhci_handle_cmd_config_ep(ep_ctx);
1336 /* A usb_set_interface() call directly after clearing a halted
1337 * condition may race on this quirky hardware. Not worth
1338 * worrying about, since this is prototype hardware. Not sure
1339 * if this will work for streams, but streams support was
1340 * untested on this prototype.
1342 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1343 ep_index != (unsigned int) -1 &&
1344 add_flags - SLOT_FLAG == drop_flags) {
1345 ep_state = virt_dev->eps[ep_index].ep_state;
1346 if (!(ep_state & EP_HALTED))
1348 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1349 "Completed config ep cmd - "
1350 "last ep index = %d, state = %d",
1351 ep_index, ep_state);
1352 /* Clear internal halted state and restart ring(s) */
1353 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1354 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1360 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1362 struct xhci_virt_device *vdev;
1363 struct xhci_slot_ctx *slot_ctx;
1365 vdev = xhci->devs[slot_id];
1366 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1367 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1370 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1371 struct xhci_event_cmd *event)
1373 struct xhci_virt_device *vdev;
1374 struct xhci_slot_ctx *slot_ctx;
1376 vdev = xhci->devs[slot_id];
1377 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1378 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1380 xhci_dbg(xhci, "Completed reset device command.\n");
1381 if (!xhci->devs[slot_id])
1382 xhci_warn(xhci, "Reset device command completion "
1383 "for disabled slot %u\n", slot_id);
1386 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1387 struct xhci_event_cmd *event)
1389 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1390 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1393 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1394 "NEC firmware version %2x.%02x",
1395 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1396 NEC_FW_MINOR(le32_to_cpu(event->status)));
1399 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1401 list_del(&cmd->cmd_list);
1403 if (cmd->completion) {
1404 cmd->status = status;
1405 complete(cmd->completion);
1411 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1413 struct xhci_command *cur_cmd, *tmp_cmd;
1414 xhci->current_cmd = NULL;
1415 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1416 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1419 void xhci_handle_command_timeout(struct work_struct *work)
1421 struct xhci_hcd *xhci;
1422 unsigned long flags;
1425 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1427 spin_lock_irqsave(&xhci->lock, flags);
1430 * If timeout work is pending, or current_cmd is NULL, it means we
1431 * raced with command completion. Command is handled so just return.
1433 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1434 spin_unlock_irqrestore(&xhci->lock, flags);
1437 /* mark this command to be cancelled */
1438 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1440 /* Make sure command ring is running before aborting it */
1441 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1442 if (hw_ring_state == ~(u64)0) {
1444 goto time_out_completed;
1447 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1448 (hw_ring_state & CMD_RING_RUNNING)) {
1449 /* Prevent new doorbell, and start command abort */
1450 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1451 xhci_dbg(xhci, "Command timeout\n");
1452 xhci_abort_cmd_ring(xhci, flags);
1453 goto time_out_completed;
1456 /* host removed. Bail out */
1457 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1458 xhci_dbg(xhci, "host removed, ring start fail?\n");
1459 xhci_cleanup_command_queue(xhci);
1461 goto time_out_completed;
1464 /* command timeout on stopped ring, ring can't be aborted */
1465 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1466 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1469 spin_unlock_irqrestore(&xhci->lock, flags);
1473 static void handle_cmd_completion(struct xhci_hcd *xhci,
1474 struct xhci_event_cmd *event)
1476 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1478 dma_addr_t cmd_dequeue_dma;
1480 union xhci_trb *cmd_trb;
1481 struct xhci_command *cmd;
1484 cmd_dma = le64_to_cpu(event->cmd_trb);
1485 cmd_trb = xhci->cmd_ring->dequeue;
1487 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1489 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1492 * Check whether the completion event is for our internal kept
1495 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1497 "ERROR mismatched command completion event\n");
1501 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1503 cancel_delayed_work(&xhci->cmd_timer);
1505 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1507 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1508 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1509 complete_all(&xhci->cmd_ring_stop_completion);
1513 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1515 "Command completion event does not match command\n");
1520 * Host aborted the command ring, check if the current command was
1521 * supposed to be aborted, otherwise continue normally.
1522 * The command ring is stopped now, but the xHC will issue a Command
1523 * Ring Stopped event which will cause us to restart it.
1525 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1526 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1527 if (cmd->status == COMP_COMMAND_ABORTED) {
1528 if (xhci->current_cmd == cmd)
1529 xhci->current_cmd = NULL;
1534 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1536 case TRB_ENABLE_SLOT:
1537 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1539 case TRB_DISABLE_SLOT:
1540 xhci_handle_cmd_disable_slot(xhci, slot_id);
1543 if (!cmd->completion)
1544 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1547 case TRB_EVAL_CONTEXT:
1550 xhci_handle_cmd_addr_dev(xhci, slot_id);
1553 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1554 le32_to_cpu(cmd_trb->generic.field[3])));
1555 if (!cmd->completion)
1556 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1559 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1560 le32_to_cpu(cmd_trb->generic.field[3])));
1561 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1564 /* Is this an aborted command turned to NO-OP? */
1565 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1566 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1569 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1570 le32_to_cpu(cmd_trb->generic.field[3])));
1571 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1574 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1575 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1577 slot_id = TRB_TO_SLOT_ID(
1578 le32_to_cpu(cmd_trb->generic.field[3]));
1579 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1581 case TRB_NEC_GET_FW:
1582 xhci_handle_cmd_nec_get_fw(xhci, event);
1585 /* Skip over unknown commands on the event ring */
1586 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1590 /* restart timer if this wasn't the last command */
1591 if (!list_is_singular(&xhci->cmd_list)) {
1592 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1593 struct xhci_command, cmd_list);
1594 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1595 } else if (xhci->current_cmd == cmd) {
1596 xhci->current_cmd = NULL;
1600 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1602 inc_deq(xhci, xhci->cmd_ring);
1605 static void handle_vendor_event(struct xhci_hcd *xhci,
1606 union xhci_trb *event)
1610 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1611 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1612 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1613 handle_cmd_completion(xhci, &event->event_cmd);
1616 static void handle_device_notification(struct xhci_hcd *xhci,
1617 union xhci_trb *event)
1620 struct usb_device *udev;
1622 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1623 if (!xhci->devs[slot_id]) {
1624 xhci_warn(xhci, "Device Notification event for "
1625 "unused slot %u\n", slot_id);
1629 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1631 udev = xhci->devs[slot_id]->udev;
1632 if (udev && udev->parent)
1633 usb_wakeup_notification(udev->parent, udev->portnum);
1637 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1639 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1640 * If a connection to a USB 1 device is followed by another connection
1641 * to a USB 2 device.
1643 * Reset the PHY after the USB device is disconnected if device speed
1644 * is less than HCD_USB3.
1645 * Retry the reset sequence max of 4 times checking the PLL lock status.
1648 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1650 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1652 u32 retry_count = 4;
1655 /* Assert PHY reset */
1656 writel(0x6F, hcd->regs + 0x1048);
1658 /* De-assert the PHY reset */
1659 writel(0x7F, hcd->regs + 0x1048);
1661 pll_lock_check = readl(hcd->regs + 0x1070);
1662 } while (!(pll_lock_check & 0x1) && --retry_count);
1665 static void handle_port_status(struct xhci_hcd *xhci,
1666 union xhci_trb *event)
1668 struct usb_hcd *hcd;
1670 u32 portsc, cmd_reg;
1673 unsigned int hcd_portnum;
1674 struct xhci_bus_state *bus_state;
1675 bool bogus_port_status = false;
1676 struct xhci_port *port;
1678 /* Port status change events always have a successful completion code */
1679 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1681 "WARN: xHC returned failed port status event\n");
1683 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1684 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1686 if ((port_id <= 0) || (port_id > max_ports)) {
1687 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1689 inc_deq(xhci, xhci->event_ring);
1693 port = &xhci->hw_ports[port_id - 1];
1694 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1695 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1697 bogus_port_status = true;
1701 /* We might get interrupts after shared_hcd is removed */
1702 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1703 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1704 bogus_port_status = true;
1708 hcd = port->rhub->hcd;
1709 bus_state = &port->rhub->bus_state;
1710 hcd_portnum = port->hcd_portnum;
1711 portsc = readl(port->addr);
1713 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1714 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1716 trace_xhci_handle_port_status(hcd_portnum, portsc);
1718 if (hcd->state == HC_STATE_SUSPENDED) {
1719 xhci_dbg(xhci, "resume root hub\n");
1720 usb_hcd_resume_root_hub(hcd);
1723 if (hcd->speed >= HCD_USB3 &&
1724 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1725 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1726 if (slot_id && xhci->devs[slot_id])
1727 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1730 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1731 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1733 cmd_reg = readl(&xhci->op_regs->command);
1734 if (!(cmd_reg & CMD_RUN)) {
1735 xhci_warn(xhci, "xHC is not running.\n");
1739 if (DEV_SUPERSPEED_ANY(portsc)) {
1740 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1741 /* Set a flag to say the port signaled remote wakeup,
1742 * so we can tell the difference between the end of
1743 * device and host initiated resume.
1745 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1746 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1747 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1748 xhci_set_link_state(xhci, port, XDEV_U0);
1749 /* Need to wait until the next link state change
1750 * indicates the device is actually in U0.
1752 bogus_port_status = true;
1754 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1755 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1756 bus_state->resume_done[hcd_portnum] = jiffies +
1757 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1758 set_bit(hcd_portnum, &bus_state->resuming_ports);
1759 /* Do the rest in GetPortStatus after resume time delay.
1760 * Avoid polling roothub status before that so that a
1761 * usb device auto-resume latency around ~40ms.
1763 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1764 mod_timer(&hcd->rh_timer,
1765 bus_state->resume_done[hcd_portnum]);
1766 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1767 bogus_port_status = true;
1771 if ((portsc & PORT_PLC) &&
1772 DEV_SUPERSPEED_ANY(portsc) &&
1773 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1774 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1775 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1776 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1777 complete(&bus_state->u3exit_done[hcd_portnum]);
1778 /* We've just brought the device into U0/1/2 through either the
1779 * Resume state after a device remote wakeup, or through the
1780 * U3Exit state after a host-initiated resume. If it's a device
1781 * initiated remote wake, don't pass up the link state change,
1782 * so the roothub behavior is consistent with external
1783 * USB 3.0 hub behavior.
1785 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1786 if (slot_id && xhci->devs[slot_id])
1787 xhci_ring_device(xhci, slot_id);
1788 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1789 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1790 usb_wakeup_notification(hcd->self.root_hub,
1792 bogus_port_status = true;
1798 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1799 * RExit to a disconnect state). If so, let the the driver know it's
1800 * out of the RExit state.
1802 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1803 test_and_clear_bit(hcd_portnum,
1804 &bus_state->rexit_ports)) {
1805 complete(&bus_state->rexit_done[hcd_portnum]);
1806 bogus_port_status = true;
1810 if (hcd->speed < HCD_USB3) {
1811 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1812 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1813 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1814 xhci_cavium_reset_phy_quirk(xhci);
1818 /* Update event ring dequeue pointer before dropping the lock */
1819 inc_deq(xhci, xhci->event_ring);
1821 /* Don't make the USB core poll the roothub if we got a bad port status
1822 * change event. Besides, at that point we can't tell which roothub
1823 * (USB 2.0 or USB 3.0) to kick.
1825 if (bogus_port_status)
1829 * xHCI port-status-change events occur when the "or" of all the
1830 * status-change bits in the portsc register changes from 0 to 1.
1831 * New status changes won't cause an event if any other change
1832 * bits are still set. When an event occurs, switch over to
1833 * polling to avoid losing status changes.
1835 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1836 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1837 spin_unlock(&xhci->lock);
1838 /* Pass this up to the core */
1839 usb_hcd_poll_rh_status(hcd);
1840 spin_lock(&xhci->lock);
1844 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1845 * at end_trb, which may be in another segment. If the suspect DMA address is a
1846 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1849 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1850 struct xhci_segment *start_seg,
1851 union xhci_trb *start_trb,
1852 union xhci_trb *end_trb,
1853 dma_addr_t suspect_dma,
1856 dma_addr_t start_dma;
1857 dma_addr_t end_seg_dma;
1858 dma_addr_t end_trb_dma;
1859 struct xhci_segment *cur_seg;
1861 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1862 cur_seg = start_seg;
1867 /* We may get an event for a Link TRB in the middle of a TD */
1868 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1869 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1870 /* If the end TRB isn't in this segment, this is set to 0 */
1871 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1875 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1876 (unsigned long long)suspect_dma,
1877 (unsigned long long)start_dma,
1878 (unsigned long long)end_trb_dma,
1879 (unsigned long long)cur_seg->dma,
1880 (unsigned long long)end_seg_dma);
1882 if (end_trb_dma > 0) {
1883 /* The end TRB is in this segment, so suspect should be here */
1884 if (start_dma <= end_trb_dma) {
1885 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1888 /* Case for one segment with
1889 * a TD wrapped around to the top
1891 if ((suspect_dma >= start_dma &&
1892 suspect_dma <= end_seg_dma) ||
1893 (suspect_dma >= cur_seg->dma &&
1894 suspect_dma <= end_trb_dma))
1899 /* Might still be somewhere in this segment */
1900 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1903 cur_seg = cur_seg->next;
1904 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1905 } while (cur_seg != start_seg);
1910 static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
1911 struct xhci_virt_ep *ep)
1914 * As part of low/full-speed endpoint-halt processing
1915 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
1917 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
1918 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
1919 !(ep->ep_state & EP_CLEARING_TT)) {
1920 ep->ep_state |= EP_CLEARING_TT;
1921 td->urb->ep->hcpriv = td->urb->dev;
1922 if (usb_hub_clear_tt_buffer(td->urb))
1923 ep->ep_state &= ~EP_CLEARING_TT;
1927 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1928 unsigned int slot_id, unsigned int ep_index,
1929 unsigned int stream_id, struct xhci_td *td,
1930 enum xhci_ep_reset_type reset_type)
1932 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1933 struct xhci_command *command;
1936 * Avoid resetting endpoint if link is inactive. Can cause host hang.
1937 * Device will be reset soon to recover the link so don't do anything
1939 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR)
1942 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1946 ep->ep_state |= EP_HALTED;
1948 xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
1950 if (reset_type == EP_HARD_RESET) {
1951 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
1952 xhci_cleanup_stalled_ring(xhci, slot_id, ep_index, stream_id,
1955 xhci_ring_cmd_db(xhci);
1958 /* Check if an error has halted the endpoint ring. The class driver will
1959 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1960 * However, a babble and other errors also halt the endpoint ring, and the class
1961 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1962 * Ring Dequeue Pointer command manually.
1964 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1965 struct xhci_ep_ctx *ep_ctx,
1966 unsigned int trb_comp_code)
1968 /* TRB completion codes that may require a manual halt cleanup */
1969 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1970 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1971 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1972 /* The 0.95 spec says a babbling control endpoint
1973 * is not halted. The 0.96 spec says it is. Some HW
1974 * claims to be 0.95 compliant, but it halts the control
1975 * endpoint anyway. Check if a babble halted the
1978 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1984 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1986 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1987 /* Vendor defined "informational" completion code,
1988 * treat as not-an-error.
1990 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1992 xhci_dbg(xhci, "Treating code as success.\n");
1998 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1999 struct xhci_ring *ep_ring, int *status)
2001 struct urb *urb = NULL;
2003 /* Clean up the endpoint's TD list */
2006 /* if a bounce buffer was used to align this td then unmap it */
2007 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
2009 /* Do one last check of the actual transfer length.
2010 * If the host controller said we transferred more data than the buffer
2011 * length, urb->actual_length will be a very big number (since it's
2012 * unsigned). Play it safe and say we didn't transfer anything.
2014 if (urb->actual_length > urb->transfer_buffer_length) {
2015 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
2016 urb->transfer_buffer_length, urb->actual_length);
2017 urb->actual_length = 0;
2020 list_del_init(&td->td_list);
2021 /* Was this TD slated to be cancelled but completed anyway? */
2022 if (!list_empty(&td->cancelled_td_list))
2023 list_del_init(&td->cancelled_td_list);
2026 /* Giveback the urb when all the tds are completed */
2027 if (last_td_in_urb(td)) {
2028 if ((urb->actual_length != urb->transfer_buffer_length &&
2029 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
2030 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2031 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
2032 urb, urb->actual_length,
2033 urb->transfer_buffer_length, *status);
2035 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
2036 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2038 xhci_giveback_urb_in_irq(xhci, td, *status);
2044 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
2045 struct xhci_transfer_event *event,
2046 struct xhci_virt_ep *ep, int *status)
2048 struct xhci_virt_device *xdev;
2049 struct xhci_ep_ctx *ep_ctx;
2050 struct xhci_ring *ep_ring;
2051 unsigned int slot_id;
2055 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2056 xdev = xhci->devs[slot_id];
2057 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2058 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2059 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2060 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2062 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2063 trb_comp_code == COMP_STOPPED ||
2064 trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
2065 /* The Endpoint Stop Command completion will take care of any
2066 * stopped TDs. A stopped TD may be restarted, so don't update
2067 * the ring dequeue pointer or take this TD off any lists yet.
2071 if (trb_comp_code == COMP_STALL_ERROR ||
2072 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2075 * xhci internal endpoint state will go to a "halt" state for
2076 * any stall, including default control pipe protocol stall.
2077 * To clear the host side halt we need to issue a reset endpoint
2078 * command, followed by a set dequeue command to move past the
2080 * Class drivers clear the device side halt from a functional
2081 * stall later. Hub TT buffer should only be cleared for FS/LS
2082 * devices behind HS hubs for functional stalls.
2084 if ((ep_index != 0) || (trb_comp_code != COMP_STALL_ERROR))
2085 xhci_clear_hub_tt_buffer(xhci, td, ep);
2086 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
2087 ep_ring->stream_id, td, EP_HARD_RESET);
2089 /* Update ring dequeue pointer */
2090 while (ep_ring->dequeue != td->last_trb)
2091 inc_deq(xhci, ep_ring);
2092 inc_deq(xhci, ep_ring);
2095 return xhci_td_cleanup(xhci, td, ep_ring, status);
2098 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2099 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2100 union xhci_trb *stop_trb)
2103 union xhci_trb *trb = ring->dequeue;
2104 struct xhci_segment *seg = ring->deq_seg;
2106 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2107 if (!trb_is_noop(trb) && !trb_is_link(trb))
2108 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2114 * Process control tds, update urb status and actual_length.
2116 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2117 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2118 struct xhci_virt_ep *ep, int *status)
2120 struct xhci_virt_device *xdev;
2121 unsigned int slot_id;
2123 struct xhci_ep_ctx *ep_ctx;
2125 u32 remaining, requested;
2128 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2129 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2130 xdev = xhci->devs[slot_id];
2131 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2132 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2133 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2134 requested = td->urb->transfer_buffer_length;
2135 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2137 switch (trb_comp_code) {
2139 if (trb_type != TRB_STATUS) {
2140 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2141 (trb_type == TRB_DATA) ? "data" : "setup");
2142 *status = -ESHUTDOWN;
2147 case COMP_SHORT_PACKET:
2150 case COMP_STOPPED_SHORT_PACKET:
2151 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2152 td->urb->actual_length = remaining;
2154 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2159 td->urb->actual_length = 0;
2163 td->urb->actual_length = requested - remaining;
2166 td->urb->actual_length = requested;
2169 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2173 case COMP_STOPPED_LENGTH_INVALID:
2176 if (!xhci_requires_manual_halt_cleanup(xhci,
2177 ep_ctx, trb_comp_code))
2179 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2180 trb_comp_code, ep_index);
2182 case COMP_STALL_ERROR:
2183 /* Did we transfer part of the data (middle) phase? */
2184 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2185 td->urb->actual_length = requested - remaining;
2186 else if (!td->urb_length_set)
2187 td->urb->actual_length = 0;
2191 /* stopped at setup stage, no data transferred */
2192 if (trb_type == TRB_SETUP)
2196 * if on data stage then update the actual_length of the URB and flag it
2197 * as set, so it won't be overwritten in the event for the last TRB.
2199 if (trb_type == TRB_DATA ||
2200 trb_type == TRB_NORMAL) {
2201 td->urb_length_set = true;
2202 td->urb->actual_length = requested - remaining;
2203 xhci_dbg(xhci, "Waiting for status stage event\n");
2207 /* at status stage */
2208 if (!td->urb_length_set)
2209 td->urb->actual_length = requested;
2212 return finish_td(xhci, td, event, ep, status);
2216 * Process isochronous tds, update urb packet status and actual_length.
2218 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2219 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2220 struct xhci_virt_ep *ep, int *status)
2222 struct xhci_ring *ep_ring;
2223 struct urb_priv *urb_priv;
2225 struct usb_iso_packet_descriptor *frame;
2227 bool sum_trbs_for_length = false;
2228 u32 remaining, requested, ep_trb_len;
2229 int short_framestatus;
2231 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2232 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2233 urb_priv = td->urb->hcpriv;
2234 idx = urb_priv->num_tds_done;
2235 frame = &td->urb->iso_frame_desc[idx];
2236 requested = frame->length;
2237 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2238 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2239 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2242 /* handle completion code */
2243 switch (trb_comp_code) {
2246 frame->status = short_framestatus;
2247 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2248 sum_trbs_for_length = true;
2253 case COMP_SHORT_PACKET:
2254 frame->status = short_framestatus;
2255 sum_trbs_for_length = true;
2257 case COMP_BANDWIDTH_OVERRUN_ERROR:
2258 frame->status = -ECOMM;
2260 case COMP_ISOCH_BUFFER_OVERRUN:
2261 case COMP_BABBLE_DETECTED_ERROR:
2262 frame->status = -EOVERFLOW;
2264 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2265 case COMP_STALL_ERROR:
2266 frame->status = -EPROTO;
2268 case COMP_USB_TRANSACTION_ERROR:
2269 frame->status = -EPROTO;
2270 if (ep_trb != td->last_trb)
2274 sum_trbs_for_length = true;
2276 case COMP_STOPPED_SHORT_PACKET:
2277 /* field normally containing residue now contains tranferred */
2278 frame->status = short_framestatus;
2279 requested = remaining;
2281 case COMP_STOPPED_LENGTH_INVALID:
2286 sum_trbs_for_length = true;
2291 if (sum_trbs_for_length)
2292 frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2293 ep_trb_len - remaining;
2295 frame->actual_length = requested;
2297 td->urb->actual_length += frame->actual_length;
2299 return finish_td(xhci, td, event, ep, status);
2302 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2303 struct xhci_transfer_event *event,
2304 struct xhci_virt_ep *ep, int *status)
2306 struct xhci_ring *ep_ring;
2307 struct urb_priv *urb_priv;
2308 struct usb_iso_packet_descriptor *frame;
2311 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2312 urb_priv = td->urb->hcpriv;
2313 idx = urb_priv->num_tds_done;
2314 frame = &td->urb->iso_frame_desc[idx];
2316 /* The transfer is partly done. */
2317 frame->status = -EXDEV;
2319 /* calc actual length */
2320 frame->actual_length = 0;
2322 /* Update ring dequeue pointer */
2323 while (ep_ring->dequeue != td->last_trb)
2324 inc_deq(xhci, ep_ring);
2325 inc_deq(xhci, ep_ring);
2327 return xhci_td_cleanup(xhci, td, ep_ring, status);
2331 * Process bulk and interrupt tds, update urb status and actual_length.
2333 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2334 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2335 struct xhci_virt_ep *ep, int *status)
2337 struct xhci_slot_ctx *slot_ctx;
2338 struct xhci_ring *ep_ring;
2340 u32 remaining, requested, ep_trb_len;
2341 unsigned int slot_id;
2344 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2345 slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[slot_id]->out_ctx);
2346 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2347 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2348 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2349 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2350 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2351 requested = td->urb->transfer_buffer_length;
2353 switch (trb_comp_code) {
2355 ep_ring->err_count = 0;
2356 /* handle success with untransferred data as short packet */
2357 if (ep_trb != td->last_trb || remaining) {
2358 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2359 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2360 td->urb->ep->desc.bEndpointAddress,
2361 requested, remaining);
2365 case COMP_SHORT_PACKET:
2366 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2367 td->urb->ep->desc.bEndpointAddress,
2368 requested, remaining);
2371 case COMP_STOPPED_SHORT_PACKET:
2372 td->urb->actual_length = remaining;
2374 case COMP_STOPPED_LENGTH_INVALID:
2375 /* stopped on ep trb with invalid length, exclude it */
2379 case COMP_USB_TRANSACTION_ERROR:
2380 if (xhci->quirks & XHCI_NO_SOFT_RETRY ||
2381 (ep_ring->err_count++ > MAX_SOFT_RETRY) ||
2382 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2385 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
2386 ep_ring->stream_id, td, EP_SOFT_RESET);
2393 if (ep_trb == td->last_trb)
2394 td->urb->actual_length = requested - remaining;
2396 td->urb->actual_length =
2397 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2398 ep_trb_len - remaining;
2400 if (remaining > requested) {
2401 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2403 td->urb->actual_length = 0;
2405 return finish_td(xhci, td, event, ep, status);
2409 * If this function returns an error condition, it means it got a Transfer
2410 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2411 * At this point, the host controller is probably hosed and should be reset.
2413 static int handle_tx_event(struct xhci_hcd *xhci,
2414 struct xhci_transfer_event *event)
2416 struct xhci_virt_device *xdev;
2417 struct xhci_virt_ep *ep;
2418 struct xhci_ring *ep_ring;
2419 unsigned int slot_id;
2421 struct xhci_td *td = NULL;
2422 dma_addr_t ep_trb_dma;
2423 struct xhci_segment *ep_seg;
2424 union xhci_trb *ep_trb;
2425 int status = -EINPROGRESS;
2426 struct xhci_ep_ctx *ep_ctx;
2427 struct list_head *tmp;
2430 bool handling_skipped_tds = false;
2432 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2433 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2434 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2435 ep_trb_dma = le64_to_cpu(event->buffer);
2437 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2439 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2443 xdev = xhci->devs[slot_id];
2444 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2445 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2447 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2449 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2454 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2456 switch (trb_comp_code) {
2457 case COMP_STALL_ERROR:
2458 case COMP_USB_TRANSACTION_ERROR:
2459 case COMP_INVALID_STREAM_TYPE_ERROR:
2460 case COMP_INVALID_STREAM_ID_ERROR:
2461 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
2462 NULL, EP_SOFT_RESET);
2464 case COMP_RING_UNDERRUN:
2465 case COMP_RING_OVERRUN:
2466 case COMP_STOPPED_LENGTH_INVALID:
2469 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2475 /* Count current td numbers if ep->skip is set */
2477 list_for_each(tmp, &ep_ring->td_list)
2481 /* Look for common error cases */
2482 switch (trb_comp_code) {
2483 /* Skip codes that require special handling depending on
2487 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2489 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2490 ep_ring->last_td_was_short)
2491 trb_comp_code = COMP_SHORT_PACKET;
2493 xhci_warn_ratelimited(xhci,
2494 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2496 case COMP_SHORT_PACKET:
2498 /* Completion codes for endpoint stopped state */
2500 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2503 case COMP_STOPPED_LENGTH_INVALID:
2505 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2508 case COMP_STOPPED_SHORT_PACKET:
2510 "Stopped with short packet transfer detected for slot %u ep %u\n",
2513 /* Completion codes for endpoint halted state */
2514 case COMP_STALL_ERROR:
2515 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2517 ep->ep_state |= EP_HALTED;
2520 case COMP_SPLIT_TRANSACTION_ERROR:
2521 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2525 case COMP_USB_TRANSACTION_ERROR:
2526 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2530 case COMP_BABBLE_DETECTED_ERROR:
2531 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2533 status = -EOVERFLOW;
2535 /* Completion codes for endpoint error state */
2536 case COMP_TRB_ERROR:
2538 "WARN: TRB error for slot %u ep %u on endpoint\n",
2542 /* completion codes not indicating endpoint state change */
2543 case COMP_DATA_BUFFER_ERROR:
2545 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2549 case COMP_BANDWIDTH_OVERRUN_ERROR:
2551 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2554 case COMP_ISOCH_BUFFER_OVERRUN:
2556 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2559 case COMP_RING_UNDERRUN:
2561 * When the Isoch ring is empty, the xHC will generate
2562 * a Ring Overrun Event for IN Isoch endpoint or Ring
2563 * Underrun Event for OUT Isoch endpoint.
2565 xhci_dbg(xhci, "underrun event on endpoint\n");
2566 if (!list_empty(&ep_ring->td_list))
2567 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2568 "still with TDs queued?\n",
2569 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2572 case COMP_RING_OVERRUN:
2573 xhci_dbg(xhci, "overrun event on endpoint\n");
2574 if (!list_empty(&ep_ring->td_list))
2575 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2576 "still with TDs queued?\n",
2577 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2580 case COMP_MISSED_SERVICE_ERROR:
2582 * When encounter missed service error, one or more isoc tds
2583 * may be missed by xHC.
2584 * Set skip flag of the ep_ring; Complete the missed tds as
2585 * short transfer when process the ep_ring next time.
2589 "Miss service interval error for slot %u ep %u, set skip flag\n",
2592 case COMP_NO_PING_RESPONSE_ERROR:
2595 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2599 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2600 /* needs disable slot command to recover */
2602 "WARN: detect an incompatible device for slot %u ep %u",
2607 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2612 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2613 trb_comp_code, slot_id, ep_index);
2618 /* This TRB should be in the TD at the head of this ring's
2621 if (list_empty(&ep_ring->td_list)) {
2623 * Don't print wanings if it's due to a stopped endpoint
2624 * generating an extra completion event if the device
2625 * was suspended. Or, a event for the last TRB of a
2626 * short TD we already got a short event for.
2627 * The short TD is already removed from the TD list.
2630 if (!(trb_comp_code == COMP_STOPPED ||
2631 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2632 ep_ring->last_td_was_short)) {
2633 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2634 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2639 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2642 if (trb_comp_code == COMP_STALL_ERROR ||
2643 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2645 xhci_cleanup_halted_endpoint(xhci, slot_id,
2654 /* We've skipped all the TDs on the ep ring when ep->skip set */
2655 if (ep->skip && td_num == 0) {
2657 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2662 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2667 /* Is this a TRB in the currently executing TD? */
2668 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2669 td->last_trb, ep_trb_dma, false);
2672 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2673 * is not in the current TD pointed by ep_ring->dequeue because
2674 * that the hardware dequeue pointer still at the previous TRB
2675 * of the current TD. The previous TRB maybe a Link TD or the
2676 * last TRB of the previous TD. The command completion handle
2677 * will take care the rest.
2679 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2680 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2686 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2687 /* Some host controllers give a spurious
2688 * successful event after a short transfer.
2691 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2692 ep_ring->last_td_was_short) {
2693 ep_ring->last_td_was_short = false;
2696 /* HC is busted, give up! */
2698 "ERROR Transfer event TRB DMA ptr not "
2699 "part of current TD ep_index %d "
2700 "comp_code %u\n", ep_index,
2702 trb_in_td(xhci, ep_ring->deq_seg,
2703 ep_ring->dequeue, td->last_trb,
2708 skip_isoc_td(xhci, td, event, ep, &status);
2711 if (trb_comp_code == COMP_SHORT_PACKET)
2712 ep_ring->last_td_was_short = true;
2714 ep_ring->last_td_was_short = false;
2718 "Found td. Clear skip flag for slot %u ep %u.\n",
2723 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2726 trace_xhci_handle_transfer(ep_ring,
2727 (struct xhci_generic_trb *) ep_trb);
2730 * No-op TRB could trigger interrupts in a case where
2731 * a URB was killed and a STALL_ERROR happens right
2732 * after the endpoint ring stopped. Reset the halted
2733 * endpoint. Otherwise, the endpoint remains stalled
2736 if (trb_is_noop(ep_trb)) {
2737 if (trb_comp_code == COMP_STALL_ERROR ||
2738 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2740 xhci_cleanup_halted_endpoint(xhci, slot_id,
2747 /* update the urb's actual_length and give back to the core */
2748 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2749 process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2750 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2751 process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2753 process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2756 handling_skipped_tds = ep->skip &&
2757 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2758 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2761 * Do not update event ring dequeue pointer if we're in a loop
2762 * processing missed tds.
2764 if (!handling_skipped_tds)
2765 inc_deq(xhci, xhci->event_ring);
2768 * If ep->skip is set, it means there are missed tds on the
2769 * endpoint ring need to take care of.
2770 * Process them as short transfer until reach the td pointed by
2773 } while (handling_skipped_tds);
2778 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2779 (unsigned long long) xhci_trb_virt_to_dma(
2780 xhci->event_ring->deq_seg,
2781 xhci->event_ring->dequeue),
2782 lower_32_bits(le64_to_cpu(event->buffer)),
2783 upper_32_bits(le64_to_cpu(event->buffer)),
2784 le32_to_cpu(event->transfer_len),
2785 le32_to_cpu(event->flags));
2790 * This function handles all OS-owned events on the event ring. It may drop
2791 * xhci->lock between event processing (e.g. to pass up port status changes).
2792 * Returns >0 for "possibly more events to process" (caller should call again),
2793 * otherwise 0 if done. In future, <0 returns should indicate error code.
2795 static int xhci_handle_event(struct xhci_hcd *xhci)
2797 union xhci_trb *event;
2798 int update_ptrs = 1;
2801 /* Event ring hasn't been allocated yet. */
2802 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2803 xhci_err(xhci, "ERROR event ring not ready\n");
2807 event = xhci->event_ring->dequeue;
2808 /* Does the HC or OS own the TRB? */
2809 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2810 xhci->event_ring->cycle_state)
2813 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2816 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2817 * speculative reads of the event's flags/data below.
2820 /* FIXME: Handle more event types. */
2821 switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2822 case TRB_TYPE(TRB_COMPLETION):
2823 handle_cmd_completion(xhci, &event->event_cmd);
2825 case TRB_TYPE(TRB_PORT_STATUS):
2826 handle_port_status(xhci, event);
2829 case TRB_TYPE(TRB_TRANSFER):
2830 ret = handle_tx_event(xhci, &event->trans_event);
2834 case TRB_TYPE(TRB_DEV_NOTE):
2835 handle_device_notification(xhci, event);
2838 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2840 handle_vendor_event(xhci, event);
2842 xhci_warn(xhci, "ERROR unknown event type %d\n",
2844 le32_to_cpu(event->event_cmd.flags)));
2846 /* Any of the above functions may drop and re-acquire the lock, so check
2847 * to make sure a watchdog timer didn't mark the host as non-responsive.
2849 if (xhci->xhc_state & XHCI_STATE_DYING) {
2850 xhci_dbg(xhci, "xHCI host dying, returning from "
2851 "event handler.\n");
2856 /* Update SW event ring dequeue pointer */
2857 inc_deq(xhci, xhci->event_ring);
2859 /* Are there more items on the event ring? Caller will call us again to
2866 * Update Event Ring Dequeue Pointer:
2867 * - When all events have finished
2868 * - To avoid "Event Ring Full Error" condition
2870 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2871 union xhci_trb *event_ring_deq)
2876 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2877 /* If necessary, update the HW's version of the event ring deq ptr. */
2878 if (event_ring_deq != xhci->event_ring->dequeue) {
2879 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2880 xhci->event_ring->dequeue);
2882 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
2884 * Per 4.9.4, Software writes to the ERDP register shall
2885 * always advance the Event Ring Dequeue Pointer value.
2887 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
2888 ((u64) deq & (u64) ~ERST_PTR_MASK))
2891 /* Update HC event ring dequeue pointer */
2892 temp_64 &= ERST_PTR_MASK;
2893 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2896 /* Clear the event handler busy flag (RW1C) */
2897 temp_64 |= ERST_EHB;
2898 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2902 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2903 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2904 * indicators of an event TRB error, but we check the status *first* to be safe.
2906 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2908 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2909 union xhci_trb *event_ring_deq;
2910 irqreturn_t ret = IRQ_NONE;
2911 unsigned long flags;
2916 spin_lock_irqsave(&xhci->lock, flags);
2917 /* Check if the xHC generated the interrupt, or the irq is shared */
2918 status = readl(&xhci->op_regs->status);
2919 if (status == ~(u32)0) {
2925 if (!(status & STS_EINT))
2928 if (status & STS_FATAL) {
2929 xhci_warn(xhci, "WARNING: Host System Error\n");
2936 * Clear the op reg interrupt status first,
2937 * so we can receive interrupts from other MSI-X interrupters.
2938 * Write 1 to clear the interrupt status.
2941 writel(status, &xhci->op_regs->status);
2943 if (!hcd->msi_enabled) {
2945 irq_pending = readl(&xhci->ir_set->irq_pending);
2946 irq_pending |= IMAN_IP;
2947 writel(irq_pending, &xhci->ir_set->irq_pending);
2950 if (xhci->xhc_state & XHCI_STATE_DYING ||
2951 xhci->xhc_state & XHCI_STATE_HALTED) {
2952 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2953 "Shouldn't IRQs be disabled?\n");
2954 /* Clear the event handler busy flag (RW1C);
2955 * the event ring should be empty.
2957 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2958 xhci_write_64(xhci, temp_64 | ERST_EHB,
2959 &xhci->ir_set->erst_dequeue);
2964 event_ring_deq = xhci->event_ring->dequeue;
2965 /* FIXME this should be a delayed service routine
2966 * that clears the EHB.
2968 while (xhci_handle_event(xhci) > 0) {
2969 if (event_loop++ < TRBS_PER_SEGMENT / 2)
2971 xhci_update_erst_dequeue(xhci, event_ring_deq);
2972 event_ring_deq = xhci->event_ring->dequeue;
2977 xhci_update_erst_dequeue(xhci, event_ring_deq);
2981 spin_unlock_irqrestore(&xhci->lock, flags);
2986 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2988 return xhci_irq(hcd);
2991 /**** Endpoint Ring Operations ****/
2994 * Generic function for queueing a TRB on a ring.
2995 * The caller must have checked to make sure there's room on the ring.
2997 * @more_trbs_coming: Will you enqueue more TRBs before calling
2998 * prepare_transfer()?
3000 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3001 bool more_trbs_coming,
3002 u32 field1, u32 field2, u32 field3, u32 field4)
3004 struct xhci_generic_trb *trb;
3006 trb = &ring->enqueue->generic;
3007 trb->field[0] = cpu_to_le32(field1);
3008 trb->field[1] = cpu_to_le32(field2);
3009 trb->field[2] = cpu_to_le32(field3);
3010 /* make sure TRB is fully written before giving it to the controller */
3012 trb->field[3] = cpu_to_le32(field4);
3014 trace_xhci_queue_trb(ring, trb);
3016 inc_enq(xhci, ring, more_trbs_coming);
3020 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3021 * FIXME allocate segments if the ring is full.
3023 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3024 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
3026 unsigned int num_trbs_needed;
3028 /* Make sure the endpoint has been added to xHC schedule */
3030 case EP_STATE_DISABLED:
3032 * USB core changed config/interfaces without notifying us,
3033 * or hardware is reporting the wrong state.
3035 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3037 case EP_STATE_ERROR:
3038 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3039 /* FIXME event handling code for error needs to clear it */
3040 /* XXX not sure if this should be -ENOENT or not */
3042 case EP_STATE_HALTED:
3043 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3044 case EP_STATE_STOPPED:
3045 case EP_STATE_RUNNING:
3048 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3050 * FIXME issue Configure Endpoint command to try to get the HC
3051 * back into a known state.
3057 if (room_on_ring(xhci, ep_ring, num_trbs))
3060 if (ep_ring == xhci->cmd_ring) {
3061 xhci_err(xhci, "Do not support expand command ring\n");
3065 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3066 "ERROR no room on ep ring, try ring expansion");
3067 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3068 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3070 xhci_err(xhci, "Ring expansion failed\n");
3075 while (trb_is_link(ep_ring->enqueue)) {
3076 /* If we're not dealing with 0.95 hardware or isoc rings
3077 * on AMD 0.96 host, clear the chain bit.
3079 if (!xhci_link_trb_quirk(xhci) &&
3080 !(ep_ring->type == TYPE_ISOC &&
3081 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3082 ep_ring->enqueue->link.control &=
3083 cpu_to_le32(~TRB_CHAIN);
3085 ep_ring->enqueue->link.control |=
3086 cpu_to_le32(TRB_CHAIN);
3089 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3091 /* Toggle the cycle bit after the last ring segment. */
3092 if (link_trb_toggles_cycle(ep_ring->enqueue))
3093 ep_ring->cycle_state ^= 1;
3095 ep_ring->enq_seg = ep_ring->enq_seg->next;
3096 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3101 static int prepare_transfer(struct xhci_hcd *xhci,
3102 struct xhci_virt_device *xdev,
3103 unsigned int ep_index,
3104 unsigned int stream_id,
3105 unsigned int num_trbs,
3107 unsigned int td_index,
3111 struct urb_priv *urb_priv;
3113 struct xhci_ring *ep_ring;
3114 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3116 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
3118 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3123 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3124 num_trbs, mem_flags);
3128 urb_priv = urb->hcpriv;
3129 td = &urb_priv->td[td_index];
3131 INIT_LIST_HEAD(&td->td_list);
3132 INIT_LIST_HEAD(&td->cancelled_td_list);
3134 if (td_index == 0) {
3135 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3141 /* Add this TD to the tail of the endpoint ring's TD list */
3142 list_add_tail(&td->td_list, &ep_ring->td_list);
3143 td->start_seg = ep_ring->enq_seg;
3144 td->first_trb = ep_ring->enqueue;
3149 unsigned int count_trbs(u64 addr, u64 len)
3151 unsigned int num_trbs;
3153 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3161 static inline unsigned int count_trbs_needed(struct urb *urb)
3163 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3166 static unsigned int count_sg_trbs_needed(struct urb *urb)
3168 struct scatterlist *sg;
3169 unsigned int i, len, full_len, num_trbs = 0;
3171 full_len = urb->transfer_buffer_length;
3173 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3174 len = sg_dma_len(sg);
3175 num_trbs += count_trbs(sg_dma_address(sg), len);
3176 len = min_t(unsigned int, len, full_len);
3185 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3189 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3190 len = urb->iso_frame_desc[i].length;
3192 return count_trbs(addr, len);
3195 static void check_trb_math(struct urb *urb, int running_total)
3197 if (unlikely(running_total != urb->transfer_buffer_length))
3198 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3199 "queued %#x (%d), asked for %#x (%d)\n",
3201 urb->ep->desc.bEndpointAddress,
3202 running_total, running_total,
3203 urb->transfer_buffer_length,
3204 urb->transfer_buffer_length);
3207 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3208 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3209 struct xhci_generic_trb *start_trb)
3212 * Pass all the TRBs to the hardware at once and make sure this write
3217 start_trb->field[3] |= cpu_to_le32(start_cycle);
3219 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3220 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3223 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3224 struct xhci_ep_ctx *ep_ctx)
3229 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3230 ep_interval = urb->interval;
3232 /* Convert to microframes */
3233 if (urb->dev->speed == USB_SPEED_LOW ||
3234 urb->dev->speed == USB_SPEED_FULL)
3237 /* FIXME change this to a warning and a suggestion to use the new API
3238 * to set the polling interval (once the API is added).
3240 if (xhci_interval != ep_interval) {
3241 dev_dbg_ratelimited(&urb->dev->dev,
3242 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3243 ep_interval, ep_interval == 1 ? "" : "s",
3244 xhci_interval, xhci_interval == 1 ? "" : "s");
3245 urb->interval = xhci_interval;
3246 /* Convert back to frames for LS/FS devices */
3247 if (urb->dev->speed == USB_SPEED_LOW ||
3248 urb->dev->speed == USB_SPEED_FULL)
3254 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3255 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3256 * (comprised of sg list entries) can take several service intervals to
3259 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3260 struct urb *urb, int slot_id, unsigned int ep_index)
3262 struct xhci_ep_ctx *ep_ctx;
3264 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3265 check_interval(xhci, urb, ep_ctx);
3267 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3271 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3272 * packets remaining in the TD (*not* including this TRB).
3274 * Total TD packet count = total_packet_count =
3275 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3277 * Packets transferred up to and including this TRB = packets_transferred =
3278 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3280 * TD size = total_packet_count - packets_transferred
3282 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3283 * including this TRB, right shifted by 10
3285 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3286 * This is taken care of in the TRB_TD_SIZE() macro
3288 * The last TRB in a TD must have the TD size set to zero.
3290 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3291 int trb_buff_len, unsigned int td_total_len,
3292 struct urb *urb, bool more_trbs_coming)
3294 u32 maxp, total_packet_count;
3296 /* MTK xHCI 0.96 contains some features from 1.0 */
3297 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3298 return ((td_total_len - transferred) >> 10);
3300 /* One TRB with a zero-length data packet. */
3301 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3302 trb_buff_len == td_total_len)
3305 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3306 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3309 maxp = usb_endpoint_maxp(&urb->ep->desc);
3310 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3312 /* Queueing functions don't count the current TRB into transferred */
3313 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3317 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3318 u32 *trb_buff_len, struct xhci_segment *seg)
3320 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3321 unsigned int unalign;
3322 unsigned int max_pkt;
3326 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3327 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3329 /* we got lucky, last normal TRB data on segment is packet aligned */
3333 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3334 unalign, *trb_buff_len);
3336 /* is the last nornal TRB alignable by splitting it */
3337 if (*trb_buff_len > unalign) {
3338 *trb_buff_len -= unalign;
3339 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3344 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3345 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3346 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3348 new_buff_len = max_pkt - (enqd_len % max_pkt);
3350 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3351 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3353 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3354 if (usb_urb_dir_out(urb)) {
3356 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3357 seg->bounce_buf, new_buff_len, enqd_len);
3358 if (len != new_buff_len)
3359 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3362 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3365 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3366 max_pkt, DMA_TO_DEVICE);
3368 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3369 max_pkt, DMA_FROM_DEVICE);
3372 if (dma_mapping_error(dev, seg->bounce_dma)) {
3373 /* try without aligning. Some host controllers survive */
3374 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3377 *trb_buff_len = new_buff_len;
3378 seg->bounce_len = new_buff_len;
3379 seg->bounce_offs = enqd_len;
3381 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3386 /* This is very similar to what ehci-q.c qtd_fill() does */
3387 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3388 struct urb *urb, int slot_id, unsigned int ep_index)
3390 struct xhci_ring *ring;
3391 struct urb_priv *urb_priv;
3393 struct xhci_generic_trb *start_trb;
3394 struct scatterlist *sg = NULL;
3395 bool more_trbs_coming = true;
3396 bool need_zero_pkt = false;
3397 bool first_trb = true;
3398 unsigned int num_trbs;
3399 unsigned int start_cycle, num_sgs = 0;
3400 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3402 u32 field, length_field, remainder;
3403 u64 addr, send_addr;
3405 ring = xhci_urb_to_transfer_ring(xhci, urb);
3409 full_len = urb->transfer_buffer_length;
3410 /* If we have scatter/gather list, we use it. */
3412 num_sgs = urb->num_mapped_sgs;
3414 addr = (u64) sg_dma_address(sg);
3415 block_len = sg_dma_len(sg);
3416 num_trbs = count_sg_trbs_needed(urb);
3418 num_trbs = count_trbs_needed(urb);
3419 addr = (u64) urb->transfer_dma;
3420 block_len = full_len;
3422 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3423 ep_index, urb->stream_id,
3424 num_trbs, urb, 0, mem_flags);
3425 if (unlikely(ret < 0))
3428 urb_priv = urb->hcpriv;
3430 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3431 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3432 need_zero_pkt = true;
3434 td = &urb_priv->td[0];
3437 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3438 * until we've finished creating all the other TRBs. The ring's cycle
3439 * state may change as we enqueue the other TRBs, so save it too.
3441 start_trb = &ring->enqueue->generic;
3442 start_cycle = ring->cycle_state;
3445 /* Queue the TRBs, even if they are zero-length */
3446 for (enqd_len = 0; first_trb || enqd_len < full_len;
3447 enqd_len += trb_buff_len) {
3448 field = TRB_TYPE(TRB_NORMAL);
3450 /* TRB buffer should not cross 64KB boundaries */
3451 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3452 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3454 if (enqd_len + trb_buff_len > full_len)
3455 trb_buff_len = full_len - enqd_len;
3457 /* Don't change the cycle bit of the first TRB until later */
3460 if (start_cycle == 0)
3463 field |= ring->cycle_state;
3465 /* Chain all the TRBs together; clear the chain bit in the last
3466 * TRB to indicate it's the last TRB in the chain.
3468 if (enqd_len + trb_buff_len < full_len) {
3470 if (trb_is_link(ring->enqueue + 1)) {
3471 if (xhci_align_td(xhci, urb, enqd_len,
3474 send_addr = ring->enq_seg->bounce_dma;
3475 /* assuming TD won't span 2 segs */
3476 td->bounce_seg = ring->enq_seg;
3480 if (enqd_len + trb_buff_len >= full_len) {
3481 field &= ~TRB_CHAIN;
3483 more_trbs_coming = false;
3484 td->last_trb = ring->enqueue;
3486 if (xhci_urb_suitable_for_idt(urb)) {
3487 memcpy(&send_addr, urb->transfer_buffer,
3489 le64_to_cpus(&send_addr);
3494 /* Only set interrupt on short packet for IN endpoints */
3495 if (usb_urb_dir_in(urb))
3498 /* Set the TRB length, TD size, and interrupter fields. */
3499 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3500 full_len, urb, more_trbs_coming);
3502 length_field = TRB_LEN(trb_buff_len) |
3503 TRB_TD_SIZE(remainder) |
3506 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3507 lower_32_bits(send_addr),
3508 upper_32_bits(send_addr),
3512 addr += trb_buff_len;
3513 sent_len = trb_buff_len;
3515 while (sg && sent_len >= block_len) {
3518 sent_len -= block_len;
3520 if (num_sgs != 0 && sg) {
3521 block_len = sg_dma_len(sg);
3522 addr = (u64) sg_dma_address(sg);
3526 block_len -= sent_len;
3530 if (need_zero_pkt) {
3531 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3532 ep_index, urb->stream_id,
3533 1, urb, 1, mem_flags);
3534 urb_priv->td[1].last_trb = ring->enqueue;
3535 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3536 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3539 check_trb_math(urb, enqd_len);
3540 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3541 start_cycle, start_trb);
3545 /* Caller must have locked xhci->lock */
3546 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3547 struct urb *urb, int slot_id, unsigned int ep_index)
3549 struct xhci_ring *ep_ring;
3552 struct usb_ctrlrequest *setup;
3553 struct xhci_generic_trb *start_trb;
3556 struct urb_priv *urb_priv;
3559 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3564 * Need to copy setup packet into setup TRB, so we can't use the setup
3567 if (!urb->setup_packet)
3570 /* 1 TRB for setup, 1 for status */
3573 * Don't need to check if we need additional event data and normal TRBs,
3574 * since data in control transfers will never get bigger than 16MB
3575 * XXX: can we get a buffer that crosses 64KB boundaries?
3577 if (urb->transfer_buffer_length > 0)
3579 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3580 ep_index, urb->stream_id,
3581 num_trbs, urb, 0, mem_flags);
3585 urb_priv = urb->hcpriv;
3586 td = &urb_priv->td[0];
3589 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3590 * until we've finished creating all the other TRBs. The ring's cycle
3591 * state may change as we enqueue the other TRBs, so save it too.
3593 start_trb = &ep_ring->enqueue->generic;
3594 start_cycle = ep_ring->cycle_state;
3596 /* Queue setup TRB - see section 6.4.1.2.1 */
3597 /* FIXME better way to translate setup_packet into two u32 fields? */
3598 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3600 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3601 if (start_cycle == 0)
3604 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3605 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3606 if (urb->transfer_buffer_length > 0) {
3607 if (setup->bRequestType & USB_DIR_IN)
3608 field |= TRB_TX_TYPE(TRB_DATA_IN);
3610 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3614 queue_trb(xhci, ep_ring, true,
3615 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3616 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3617 TRB_LEN(8) | TRB_INTR_TARGET(0),
3618 /* Immediate data in pointer */
3621 /* If there's data, queue data TRBs */
3622 /* Only set interrupt on short packet for IN endpoints */
3623 if (usb_urb_dir_in(urb))
3624 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3626 field = TRB_TYPE(TRB_DATA);
3628 if (urb->transfer_buffer_length > 0) {
3629 u32 length_field, remainder;
3632 if (xhci_urb_suitable_for_idt(urb)) {
3633 memcpy(&addr, urb->transfer_buffer,
3634 urb->transfer_buffer_length);
3635 le64_to_cpus(&addr);
3638 addr = (u64) urb->transfer_dma;
3641 remainder = xhci_td_remainder(xhci, 0,
3642 urb->transfer_buffer_length,
3643 urb->transfer_buffer_length,
3645 length_field = TRB_LEN(urb->transfer_buffer_length) |
3646 TRB_TD_SIZE(remainder) |
3648 if (setup->bRequestType & USB_DIR_IN)
3649 field |= TRB_DIR_IN;
3650 queue_trb(xhci, ep_ring, true,
3651 lower_32_bits(addr),
3652 upper_32_bits(addr),
3654 field | ep_ring->cycle_state);
3657 /* Save the DMA address of the last TRB in the TD */
3658 td->last_trb = ep_ring->enqueue;
3660 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3661 /* If the device sent data, the status stage is an OUT transfer */
3662 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3666 queue_trb(xhci, ep_ring, false,
3670 /* Event on completion */
3671 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3673 giveback_first_trb(xhci, slot_id, ep_index, 0,
3674 start_cycle, start_trb);
3679 * The transfer burst count field of the isochronous TRB defines the number of
3680 * bursts that are required to move all packets in this TD. Only SuperSpeed
3681 * devices can burst up to bMaxBurst number of packets per service interval.
3682 * This field is zero based, meaning a value of zero in the field means one
3683 * burst. Basically, for everything but SuperSpeed devices, this field will be
3684 * zero. Only xHCI 1.0 host controllers support this field.
3686 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3687 struct urb *urb, unsigned int total_packet_count)
3689 unsigned int max_burst;
3691 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3694 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3695 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3699 * Returns the number of packets in the last "burst" of packets. This field is
3700 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3701 * the last burst packet count is equal to the total number of packets in the
3702 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3703 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3704 * contain 1 to (bMaxBurst + 1) packets.
3706 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3707 struct urb *urb, unsigned int total_packet_count)
3709 unsigned int max_burst;
3710 unsigned int residue;
3712 if (xhci->hci_version < 0x100)
3715 if (urb->dev->speed >= USB_SPEED_SUPER) {
3716 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3717 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3718 residue = total_packet_count % (max_burst + 1);
3719 /* If residue is zero, the last burst contains (max_burst + 1)
3720 * number of packets, but the TLBPC field is zero-based.
3726 if (total_packet_count == 0)
3728 return total_packet_count - 1;
3732 * Calculates Frame ID field of the isochronous TRB identifies the
3733 * target frame that the Interval associated with this Isochronous
3734 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3736 * Returns actual frame id on success, negative value on error.
3738 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3739 struct urb *urb, int index)
3741 int start_frame, ist, ret = 0;
3742 int start_frame_id, end_frame_id, current_frame_id;
3744 if (urb->dev->speed == USB_SPEED_LOW ||
3745 urb->dev->speed == USB_SPEED_FULL)
3746 start_frame = urb->start_frame + index * urb->interval;
3748 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3750 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3752 * If bit [3] of IST is cleared to '0', software can add a TRB no
3753 * later than IST[2:0] Microframes before that TRB is scheduled to
3755 * If bit [3] of IST is set to '1', software can add a TRB no later
3756 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3758 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3759 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3762 /* Software shall not schedule an Isoch TD with a Frame ID value that
3763 * is less than the Start Frame ID or greater than the End Frame ID,
3766 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3767 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3769 * Both the End Frame ID and Start Frame ID values are calculated
3770 * in microframes. When software determines the valid Frame ID value;
3771 * The End Frame ID value should be rounded down to the nearest Frame
3772 * boundary, and the Start Frame ID value should be rounded up to the
3773 * nearest Frame boundary.
3775 current_frame_id = readl(&xhci->run_regs->microframe_index);
3776 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3777 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3779 start_frame &= 0x7ff;
3780 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3781 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3783 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3784 __func__, index, readl(&xhci->run_regs->microframe_index),
3785 start_frame_id, end_frame_id, start_frame);
3787 if (start_frame_id < end_frame_id) {
3788 if (start_frame > end_frame_id ||
3789 start_frame < start_frame_id)
3791 } else if (start_frame_id > end_frame_id) {
3792 if ((start_frame > end_frame_id &&
3793 start_frame < start_frame_id))
3800 if (ret == -EINVAL || start_frame == start_frame_id) {
3801 start_frame = start_frame_id + 1;
3802 if (urb->dev->speed == USB_SPEED_LOW ||
3803 urb->dev->speed == USB_SPEED_FULL)
3804 urb->start_frame = start_frame;
3806 urb->start_frame = start_frame << 3;
3812 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3813 start_frame, current_frame_id, index,
3814 start_frame_id, end_frame_id);
3815 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3822 /* Check if we should generate event interrupt for a TD in an isoc URB */
3823 static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i)
3825 if (xhci->hci_version < 0x100)
3827 /* always generate an event interrupt for the last TD */
3828 if (i == num_tds - 1)
3831 * If AVOID_BEI is set the host handles full event rings poorly,
3832 * generate an event at least every 8th TD to clear the event ring
3834 if (i && xhci->quirks & XHCI_AVOID_BEI)
3840 /* This is for isoc transfer */
3841 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3842 struct urb *urb, int slot_id, unsigned int ep_index)
3844 struct xhci_ring *ep_ring;
3845 struct urb_priv *urb_priv;
3847 int num_tds, trbs_per_td;
3848 struct xhci_generic_trb *start_trb;
3851 u32 field, length_field;
3852 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3853 u64 start_addr, addr;
3855 bool more_trbs_coming;
3856 struct xhci_virt_ep *xep;
3859 xep = &xhci->devs[slot_id]->eps[ep_index];
3860 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3862 num_tds = urb->number_of_packets;
3864 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3867 start_addr = (u64) urb->transfer_dma;
3868 start_trb = &ep_ring->enqueue->generic;
3869 start_cycle = ep_ring->cycle_state;
3871 urb_priv = urb->hcpriv;
3872 /* Queue the TRBs for each TD, even if they are zero-length */
3873 for (i = 0; i < num_tds; i++) {
3874 unsigned int total_pkt_count, max_pkt;
3875 unsigned int burst_count, last_burst_pkt_count;
3880 addr = start_addr + urb->iso_frame_desc[i].offset;
3881 td_len = urb->iso_frame_desc[i].length;
3882 td_remain_len = td_len;
3883 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3884 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3886 /* A zero-length transfer still involves at least one packet. */
3887 if (total_pkt_count == 0)
3889 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3890 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3891 urb, total_pkt_count);
3893 trbs_per_td = count_isoc_trbs_needed(urb, i);
3895 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3896 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3902 td = &urb_priv->td[i];
3904 /* use SIA as default, if frame id is used overwrite it */
3905 sia_frame_id = TRB_SIA;
3906 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3907 HCC_CFC(xhci->hcc_params)) {
3908 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3910 sia_frame_id = TRB_FRAME_ID(frame_id);
3913 * Set isoc specific data for the first TRB in a TD.
3914 * Prevent HW from getting the TRBs by keeping the cycle state
3915 * inverted in the first TDs isoc TRB.
3917 field = TRB_TYPE(TRB_ISOC) |
3918 TRB_TLBPC(last_burst_pkt_count) |
3920 (i ? ep_ring->cycle_state : !start_cycle);
3922 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3923 if (!xep->use_extended_tbc)
3924 field |= TRB_TBC(burst_count);
3926 /* fill the rest of the TRB fields, and remaining normal TRBs */
3927 for (j = 0; j < trbs_per_td; j++) {
3930 /* only first TRB is isoc, overwrite otherwise */
3932 field = TRB_TYPE(TRB_NORMAL) |
3933 ep_ring->cycle_state;
3935 /* Only set interrupt on short packet for IN EPs */
3936 if (usb_urb_dir_in(urb))
3939 /* Set the chain bit for all except the last TRB */
3940 if (j < trbs_per_td - 1) {
3941 more_trbs_coming = true;
3944 more_trbs_coming = false;
3945 td->last_trb = ep_ring->enqueue;
3947 if (trb_block_event_intr(xhci, num_tds, i))
3950 /* Calculate TRB length */
3951 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3952 if (trb_buff_len > td_remain_len)
3953 trb_buff_len = td_remain_len;
3955 /* Set the TRB length, TD size, & interrupter fields. */
3956 remainder = xhci_td_remainder(xhci, running_total,
3957 trb_buff_len, td_len,
3958 urb, more_trbs_coming);
3960 length_field = TRB_LEN(trb_buff_len) |
3963 /* xhci 1.1 with ETE uses TD Size field for TBC */
3964 if (first_trb && xep->use_extended_tbc)
3965 length_field |= TRB_TD_SIZE_TBC(burst_count);
3967 length_field |= TRB_TD_SIZE(remainder);
3970 queue_trb(xhci, ep_ring, more_trbs_coming,
3971 lower_32_bits(addr),
3972 upper_32_bits(addr),
3975 running_total += trb_buff_len;
3977 addr += trb_buff_len;
3978 td_remain_len -= trb_buff_len;
3981 /* Check TD length */
3982 if (running_total != td_len) {
3983 xhci_err(xhci, "ISOC TD length unmatch\n");
3989 /* store the next frame id */
3990 if (HCC_CFC(xhci->hcc_params))
3991 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3993 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3994 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3995 usb_amd_quirk_pll_disable();
3997 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3999 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
4000 start_cycle, start_trb);
4003 /* Clean up a partially enqueued isoc transfer. */
4005 for (i--; i >= 0; i--)
4006 list_del_init(&urb_priv->td[i].td_list);
4008 /* Use the first TD as a temporary variable to turn the TDs we've queued
4009 * into No-ops with a software-owned cycle bit. That way the hardware
4010 * won't accidentally start executing bogus TDs when we partially
4011 * overwrite them. td->first_trb and td->start_seg are already set.
4013 urb_priv->td[0].last_trb = ep_ring->enqueue;
4014 /* Every TRB except the first & last will have its cycle bit flipped. */
4015 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
4017 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4018 ep_ring->enqueue = urb_priv->td[0].first_trb;
4019 ep_ring->enq_seg = urb_priv->td[0].start_seg;
4020 ep_ring->cycle_state = start_cycle;
4021 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
4022 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4027 * Check transfer ring to guarantee there is enough room for the urb.
4028 * Update ISO URB start_frame and interval.
4029 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4030 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4031 * Contiguous Frame ID is not supported by HC.
4033 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4034 struct urb *urb, int slot_id, unsigned int ep_index)
4036 struct xhci_virt_device *xdev;
4037 struct xhci_ring *ep_ring;
4038 struct xhci_ep_ctx *ep_ctx;
4040 int num_tds, num_trbs, i;
4042 struct xhci_virt_ep *xep;
4045 xdev = xhci->devs[slot_id];
4046 xep = &xhci->devs[slot_id]->eps[ep_index];
4047 ep_ring = xdev->eps[ep_index].ring;
4048 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4051 num_tds = urb->number_of_packets;
4052 for (i = 0; i < num_tds; i++)
4053 num_trbs += count_isoc_trbs_needed(urb, i);
4055 /* Check the ring to guarantee there is enough room for the whole urb.
4056 * Do not insert any td of the urb to the ring if the check failed.
4058 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4059 num_trbs, mem_flags);
4064 * Check interval value. This should be done before we start to
4065 * calculate the start frame value.
4067 check_interval(xhci, urb, ep_ctx);
4069 /* Calculate the start frame and put it in urb->start_frame. */
4070 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4071 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
4072 urb->start_frame = xep->next_frame_id;
4073 goto skip_start_over;
4077 start_frame = readl(&xhci->run_regs->microframe_index);
4078 start_frame &= 0x3fff;
4080 * Round up to the next frame and consider the time before trb really
4081 * gets scheduled by hardare.
4083 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4084 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4086 start_frame += ist + XHCI_CFC_DELAY;
4087 start_frame = roundup(start_frame, 8);
4090 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4091 * is greate than 8 microframes.
4093 if (urb->dev->speed == USB_SPEED_LOW ||
4094 urb->dev->speed == USB_SPEED_FULL) {
4095 start_frame = roundup(start_frame, urb->interval << 3);
4096 urb->start_frame = start_frame >> 3;
4098 start_frame = roundup(start_frame, urb->interval);
4099 urb->start_frame = start_frame;
4103 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4105 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4108 /**** Command Ring Operations ****/
4110 /* Generic function for queueing a command TRB on the command ring.
4111 * Check to make sure there's room on the command ring for one command TRB.
4112 * Also check that there's room reserved for commands that must not fail.
4113 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4114 * then only check for the number of reserved spots.
4115 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4116 * because the command event handler may want to resubmit a failed command.
4118 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4119 u32 field1, u32 field2,
4120 u32 field3, u32 field4, bool command_must_succeed)
4122 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4125 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4126 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4127 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4131 if (!command_must_succeed)
4134 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4135 reserved_trbs, GFP_ATOMIC);
4137 xhci_err(xhci, "ERR: No room for command on command ring\n");
4138 if (command_must_succeed)
4139 xhci_err(xhci, "ERR: Reserved TRB counting for "
4140 "unfailable commands failed.\n");
4144 cmd->command_trb = xhci->cmd_ring->enqueue;
4146 /* if there are no other commands queued we start the timeout timer */
4147 if (list_empty(&xhci->cmd_list)) {
4148 xhci->current_cmd = cmd;
4149 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4152 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4154 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4155 field4 | xhci->cmd_ring->cycle_state);
4159 /* Queue a slot enable or disable request on the command ring */
4160 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4161 u32 trb_type, u32 slot_id)
4163 return queue_command(xhci, cmd, 0, 0, 0,
4164 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4167 /* Queue an address device command TRB */
4168 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4169 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4171 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4172 upper_32_bits(in_ctx_ptr), 0,
4173 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4174 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4177 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4178 u32 field1, u32 field2, u32 field3, u32 field4)
4180 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4183 /* Queue a reset device command TRB */
4184 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4187 return queue_command(xhci, cmd, 0, 0, 0,
4188 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4192 /* Queue a configure endpoint command TRB */
4193 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4194 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4195 u32 slot_id, bool command_must_succeed)
4197 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4198 upper_32_bits(in_ctx_ptr), 0,
4199 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4200 command_must_succeed);
4203 /* Queue an evaluate context command TRB */
4204 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4205 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4207 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4208 upper_32_bits(in_ctx_ptr), 0,
4209 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4210 command_must_succeed);
4214 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4215 * activity on an endpoint that is about to be suspended.
4217 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4218 int slot_id, unsigned int ep_index, int suspend)
4220 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4221 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4222 u32 type = TRB_TYPE(TRB_STOP_RING);
4223 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4225 return queue_command(xhci, cmd, 0, 0, 0,
4226 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4229 /* Set Transfer Ring Dequeue Pointer command */
4230 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4231 unsigned int slot_id, unsigned int ep_index,
4232 struct xhci_dequeue_state *deq_state)
4235 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4236 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4237 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4239 u32 type = TRB_TYPE(TRB_SET_DEQ);
4240 struct xhci_virt_ep *ep;
4241 struct xhci_command *cmd;
4244 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4245 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4246 deq_state->new_deq_seg,
4247 (unsigned long long)deq_state->new_deq_seg->dma,
4248 deq_state->new_deq_ptr,
4249 (unsigned long long)xhci_trb_virt_to_dma(
4250 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4251 deq_state->new_cycle_state);
4253 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4254 deq_state->new_deq_ptr);
4256 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4257 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4258 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4261 ep = &xhci->devs[slot_id]->eps[ep_index];
4262 if ((ep->ep_state & SET_DEQ_PENDING)) {
4263 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4264 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4268 /* This function gets called from contexts where it cannot sleep */
4269 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
4273 ep->queued_deq_seg = deq_state->new_deq_seg;
4274 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4275 if (deq_state->stream_id)
4276 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4277 ret = queue_command(xhci, cmd,
4278 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4279 upper_32_bits(addr), trb_stream_id,
4280 trb_slot_id | trb_ep_index | type, false);
4282 xhci_free_command(xhci, cmd);
4286 /* Stop the TD queueing code from ringing the doorbell until
4287 * this command completes. The HC won't set the dequeue pointer
4288 * if the ring is running, and ringing the doorbell starts the
4291 ep->ep_state |= SET_DEQ_PENDING;
4294 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4295 int slot_id, unsigned int ep_index,
4296 enum xhci_ep_reset_type reset_type)
4298 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4299 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4300 u32 type = TRB_TYPE(TRB_RESET_EP);
4302 if (reset_type == EP_SOFT_RESET)
4305 return queue_command(xhci, cmd, 0, 0, 0,
4306 trb_slot_id | trb_ep_index | type, false);