1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
59 #include "xhci-trace.h"
63 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
66 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
69 unsigned long segment_offset;
71 if (!seg || !trb || trb < seg->trbs)
74 segment_offset = trb - seg->trbs;
75 if (segment_offset >= TRBS_PER_SEGMENT)
77 return seg->dma + (segment_offset * sizeof(*trb));
80 static bool trb_is_noop(union xhci_trb *trb)
82 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
85 static bool trb_is_link(union xhci_trb *trb)
87 return TRB_TYPE_LINK_LE32(trb->link.control);
90 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
92 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
95 static bool last_trb_on_ring(struct xhci_ring *ring,
96 struct xhci_segment *seg, union xhci_trb *trb)
98 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
101 static bool link_trb_toggles_cycle(union xhci_trb *trb)
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
106 static bool last_td_in_urb(struct xhci_td *td)
108 struct urb_priv *urb_priv = td->urb->hcpriv;
110 return urb_priv->num_tds_done == urb_priv->num_tds;
113 static void inc_td_cnt(struct urb *urb)
115 struct urb_priv *urb_priv = urb->hcpriv;
117 urb_priv->num_tds_done++;
120 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
122 if (trb_is_link(trb)) {
123 /* unchain chained link TRBs */
124 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
126 trb->generic.field[0] = 0;
127 trb->generic.field[1] = 0;
128 trb->generic.field[2] = 0;
129 /* Preserve only the cycle bit of this TRB */
130 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
131 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
135 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
136 * TRB is in a new segment. This does not skip over link TRBs, and it does not
137 * effect the ring dequeue or enqueue pointers.
139 static void next_trb(struct xhci_hcd *xhci,
140 struct xhci_ring *ring,
141 struct xhci_segment **seg,
142 union xhci_trb **trb)
144 if (trb_is_link(*trb)) {
146 *trb = ((*seg)->trbs);
153 * See Cycle bit rules. SW is the consumer for the event ring only.
154 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
156 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
158 /* event ring doesn't have link trbs, check for last trb */
159 if (ring->type == TYPE_EVENT) {
160 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
164 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
165 ring->cycle_state ^= 1;
166 ring->deq_seg = ring->deq_seg->next;
167 ring->dequeue = ring->deq_seg->trbs;
171 /* All other rings have link trbs */
172 if (!trb_is_link(ring->dequeue)) {
174 ring->num_trbs_free++;
176 while (trb_is_link(ring->dequeue)) {
177 ring->deq_seg = ring->deq_seg->next;
178 ring->dequeue = ring->deq_seg->trbs;
182 trace_xhci_inc_deq(ring);
188 * See Cycle bit rules. SW is the consumer for the event ring only.
189 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
191 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
192 * chain bit is set), then set the chain bit in all the following link TRBs.
193 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
194 * have their chain bit cleared (so that each Link TRB is a separate TD).
196 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
197 * set, but other sections talk about dealing with the chain bit set. This was
198 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
199 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
201 * @more_trbs_coming: Will you enqueue more TRBs before calling
202 * prepare_transfer()?
204 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
205 bool more_trbs_coming)
208 union xhci_trb *next;
210 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
211 /* If this is not event ring, there is one less usable TRB */
212 if (!trb_is_link(ring->enqueue))
213 ring->num_trbs_free--;
214 next = ++(ring->enqueue);
216 /* Update the dequeue pointer further if that was a link TRB */
217 while (trb_is_link(next)) {
220 * If the caller doesn't plan on enqueueing more TDs before
221 * ringing the doorbell, then we don't want to give the link TRB
222 * to the hardware just yet. We'll give the link TRB back in
223 * prepare_ring() just before we enqueue the TD at the top of
226 if (!chain && !more_trbs_coming)
229 /* If we're not dealing with 0.95 hardware or isoc rings on
230 * AMD 0.96 host, carry over the chain bit of the previous TRB
231 * (which may mean the chain bit is cleared).
233 if (!(ring->type == TYPE_ISOC &&
234 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
235 !xhci_link_trb_quirk(xhci)) {
236 next->link.control &= cpu_to_le32(~TRB_CHAIN);
237 next->link.control |= cpu_to_le32(chain);
239 /* Give this link TRB to the hardware */
241 next->link.control ^= cpu_to_le32(TRB_CYCLE);
243 /* Toggle the cycle bit after the last ring segment. */
244 if (link_trb_toggles_cycle(next))
245 ring->cycle_state ^= 1;
247 ring->enq_seg = ring->enq_seg->next;
248 ring->enqueue = ring->enq_seg->trbs;
249 next = ring->enqueue;
252 trace_xhci_inc_enq(ring);
256 * Check to see if there's room to enqueue num_trbs on the ring and make sure
257 * enqueue pointer will not advance into dequeue segment. See rules above.
259 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
260 unsigned int num_trbs)
262 int num_trbs_in_deq_seg;
264 if (ring->num_trbs_free < num_trbs)
267 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
268 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
269 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
276 /* Ring the host controller doorbell after placing a command on the ring */
277 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
279 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
282 xhci_dbg(xhci, "// Ding dong!\n");
283 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
284 /* Flush PCI posted writes */
285 readl(&xhci->dba->doorbell[0]);
288 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
290 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
293 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
295 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
300 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
301 * If there are other commands waiting then restart the ring and kick the timer.
302 * This must be called with command ring stopped and xhci->lock held.
304 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
305 struct xhci_command *cur_cmd)
307 struct xhci_command *i_cmd;
309 /* Turn all aborted commands in list to no-ops, then restart */
310 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
312 if (i_cmd->status != COMP_COMMAND_ABORTED)
315 i_cmd->status = COMP_COMMAND_RING_STOPPED;
317 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
320 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
323 * caller waiting for completion is called when command
324 * completion event is received for these no-op commands
328 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
330 /* ring command ring doorbell to restart the command ring */
331 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
332 !(xhci->xhc_state & XHCI_STATE_DYING)) {
333 xhci->current_cmd = cur_cmd;
334 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
335 xhci_ring_cmd_db(xhci);
339 /* Must be called with xhci->lock held, releases and aquires lock back */
340 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
342 struct xhci_segment *new_seg = xhci->cmd_ring->deq_seg;
343 union xhci_trb *new_deq = xhci->cmd_ring->dequeue;
347 xhci_dbg(xhci, "Abort command ring\n");
349 reinit_completion(&xhci->cmd_ring_stop_completion);
352 * The control bits like command stop, abort are located in lower
353 * dword of the command ring control register.
354 * Some controllers require all 64 bits to be written to abort the ring.
355 * Make sure the upper dword is valid, pointing to the next command,
356 * avoiding corrupting the command ring pointer in case the command ring
357 * is stopped by the time the upper dword is written.
359 next_trb(xhci, NULL, &new_seg, &new_deq);
360 if (trb_is_link(new_deq))
361 next_trb(xhci, NULL, &new_seg, &new_deq);
363 crcr = xhci_trb_virt_to_dma(new_seg, new_deq);
364 xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
366 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
367 * completion of the Command Abort operation. If CRR is not negated in 5
368 * seconds then driver handles it as if host died (-ENODEV).
369 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
370 * and try to recover a -ETIMEDOUT with a host controller reset.
372 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
373 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
375 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
381 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
382 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
383 * but the completion event in never sent. Wait 2 secs (arbitrary
384 * number) to handle those cases after negation of CMD_RING_RUNNING.
386 spin_unlock_irqrestore(&xhci->lock, flags);
387 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
388 msecs_to_jiffies(2000));
389 spin_lock_irqsave(&xhci->lock, flags);
391 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
392 xhci_cleanup_command_queue(xhci);
394 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
399 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
400 unsigned int slot_id,
401 unsigned int ep_index,
402 unsigned int stream_id)
404 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
405 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
406 unsigned int ep_state = ep->ep_state;
408 /* Don't ring the doorbell for this endpoint if there are pending
409 * cancellations because we don't want to interrupt processing.
410 * We don't want to restart any stream rings if there's a set dequeue
411 * pointer command pending because the device can choose to start any
412 * stream once the endpoint is on the HW schedule.
414 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
415 (ep_state & EP_HALTED))
417 writel(DB_VALUE(ep_index, stream_id), db_addr);
418 /* The CPU has better things to do at this point than wait for a
419 * write-posting flush. It'll get there soon enough.
423 /* Ring the doorbell for any rings with pending URBs */
424 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
425 unsigned int slot_id,
426 unsigned int ep_index)
428 unsigned int stream_id;
429 struct xhci_virt_ep *ep;
431 ep = &xhci->devs[slot_id]->eps[ep_index];
433 /* A ring has pending URBs if its TD list is not empty */
434 if (!(ep->ep_state & EP_HAS_STREAMS)) {
435 if (ep->ring && !(list_empty(&ep->ring->td_list)))
436 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
440 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
442 struct xhci_stream_info *stream_info = ep->stream_info;
443 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
444 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
449 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
450 unsigned int slot_id,
451 unsigned int ep_index)
453 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
454 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
457 if (ep_index >= EP_CTX_PER_DEV) {
458 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
461 if (!xhci->devs[slot_id]) {
462 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
466 return &xhci->devs[slot_id]->eps[ep_index];
469 /* Get the right ring for the given slot_id, ep_index and stream_id.
470 * If the endpoint supports streams, boundary check the URB's stream ID.
471 * If the endpoint doesn't support streams, return the singular endpoint ring.
473 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
474 unsigned int slot_id, unsigned int ep_index,
475 unsigned int stream_id)
477 struct xhci_virt_ep *ep;
479 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
483 /* Common case: no streams */
484 if (!(ep->ep_state & EP_HAS_STREAMS))
487 if (stream_id == 0) {
489 "WARN: Slot ID %u, ep index %u has streams, "
490 "but URB has no stream ID.\n",
495 if (stream_id < ep->stream_info->num_streams)
496 return ep->stream_info->stream_rings[stream_id];
499 "WARN: Slot ID %u, ep index %u has "
500 "stream IDs 1 to %u allocated, "
501 "but stream ID %u is requested.\n",
503 ep->stream_info->num_streams - 1,
510 * Get the hw dequeue pointer xHC stopped on, either directly from the
511 * endpoint context, or if streams are in use from the stream context.
512 * The returned hw_dequeue contains the lowest four bits with cycle state
513 * and possbile stream context type.
515 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
516 unsigned int ep_index, unsigned int stream_id)
518 struct xhci_ep_ctx *ep_ctx;
519 struct xhci_stream_ctx *st_ctx;
520 struct xhci_virt_ep *ep;
522 ep = &vdev->eps[ep_index];
524 if (ep->ep_state & EP_HAS_STREAMS) {
525 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
526 return le64_to_cpu(st_ctx->stream_ring);
528 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
529 return le64_to_cpu(ep_ctx->deq);
533 * Move the xHC's endpoint ring dequeue pointer past cur_td.
534 * Record the new state of the xHC's endpoint ring dequeue segment,
535 * dequeue pointer, stream id, and new consumer cycle state in state.
536 * Update our internal representation of the ring's dequeue pointer.
538 * We do this in three jumps:
539 * - First we update our new ring state to be the same as when the xHC stopped.
540 * - Then we traverse the ring to find the segment that contains
541 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
542 * any link TRBs with the toggle cycle bit set.
543 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
544 * if we've moved it past a link TRB with the toggle cycle bit set.
546 * Some of the uses of xhci_generic_trb are grotty, but if they're done
547 * with correct __le32 accesses they should work fine. Only users of this are
550 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
551 unsigned int slot_id, unsigned int ep_index,
552 unsigned int stream_id, struct xhci_td *cur_td,
553 struct xhci_dequeue_state *state)
555 struct xhci_virt_device *dev = xhci->devs[slot_id];
556 struct xhci_virt_ep *ep = &dev->eps[ep_index];
557 struct xhci_ring *ep_ring;
558 struct xhci_segment *new_seg;
559 union xhci_trb *new_deq;
562 bool cycle_found = false;
563 bool td_last_trb_found = false;
565 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
566 ep_index, stream_id);
568 xhci_warn(xhci, "WARN can't find new dequeue state "
569 "for invalid stream ID %u.\n",
573 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
574 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
575 "Finding endpoint context");
577 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
578 new_seg = ep_ring->deq_seg;
579 new_deq = ep_ring->dequeue;
580 state->new_cycle_state = hw_dequeue & 0x1;
581 state->stream_id = stream_id;
584 * We want to find the pointer, segment and cycle state of the new trb
585 * (the one after current TD's last_trb). We know the cycle state at
586 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
590 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
591 == (dma_addr_t)(hw_dequeue & ~0xf)) {
593 if (td_last_trb_found)
596 if (new_deq == cur_td->last_trb)
597 td_last_trb_found = true;
599 if (cycle_found && trb_is_link(new_deq) &&
600 link_trb_toggles_cycle(new_deq))
601 state->new_cycle_state ^= 0x1;
603 next_trb(xhci, ep_ring, &new_seg, &new_deq);
605 /* Search wrapped around, bail out */
606 if (new_deq == ep->ring->dequeue) {
607 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
608 state->new_deq_seg = NULL;
609 state->new_deq_ptr = NULL;
613 } while (!cycle_found || !td_last_trb_found);
615 state->new_deq_seg = new_seg;
616 state->new_deq_ptr = new_deq;
618 /* Don't update the ring cycle state for the producer (us). */
619 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
620 "Cycle state = 0x%x", state->new_cycle_state);
622 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
623 "New dequeue segment = %p (virtual)",
625 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
626 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
627 "New dequeue pointer = 0x%llx (DMA)",
628 (unsigned long long) addr);
631 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
632 * (The last TRB actually points to the ring enqueue pointer, which is not part
633 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
635 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
636 struct xhci_td *td, bool flip_cycle)
638 struct xhci_segment *seg = td->start_seg;
639 union xhci_trb *trb = td->first_trb;
642 trb_to_noop(trb, TRB_TR_NOOP);
644 /* flip cycle if asked to */
645 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
646 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
648 if (trb == td->last_trb)
651 next_trb(xhci, ep_ring, &seg, &trb);
655 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
656 struct xhci_virt_ep *ep)
658 ep->ep_state &= ~EP_STOP_CMD_PENDING;
659 /* Can't del_timer_sync in interrupt */
660 del_timer(&ep->stop_cmd_timer);
664 * Must be called with xhci->lock held in interrupt context,
665 * releases and re-acquires xhci->lock
667 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
668 struct xhci_td *cur_td, int status)
670 struct urb *urb = cur_td->urb;
671 struct urb_priv *urb_priv = urb->hcpriv;
672 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
674 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
675 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
676 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
677 if (xhci->quirks & XHCI_AMD_PLL_FIX)
678 usb_amd_quirk_pll_enable();
681 xhci_urb_free_priv(urb_priv);
682 usb_hcd_unlink_urb_from_ep(hcd, urb);
683 spin_unlock(&xhci->lock);
684 trace_xhci_urb_giveback(urb);
685 usb_hcd_giveback_urb(hcd, urb, status);
686 spin_lock(&xhci->lock);
689 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
690 struct xhci_ring *ring, struct xhci_td *td)
692 struct device *dev = xhci_to_hcd(xhci)->self.controller;
693 struct xhci_segment *seg = td->bounce_seg;
694 struct urb *urb = td->urb;
697 if (!ring || !seg || !urb)
700 if (usb_urb_dir_out(urb)) {
701 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
706 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
708 /* for in tranfers we need to copy the data from bounce to sg */
710 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
711 seg->bounce_len, seg->bounce_offs);
712 if (len != seg->bounce_len)
713 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
714 len, seg->bounce_len);
716 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
720 seg->bounce_offs = 0;
724 * When we get a command completion for a Stop Endpoint Command, we need to
725 * unlink any cancelled TDs from the ring. There are two ways to do that:
727 * 1. If the HW was in the middle of processing the TD that needs to be
728 * cancelled, then we must move the ring's dequeue pointer past the last TRB
729 * in the TD with a Set Dequeue Pointer Command.
730 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
731 * bit cleared) so that the HW will skip over them.
733 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
734 union xhci_trb *trb, struct xhci_event_cmd *event)
736 unsigned int ep_index;
737 struct xhci_ring *ep_ring;
738 struct xhci_virt_ep *ep;
739 struct xhci_td *cur_td = NULL;
740 struct xhci_td *last_unlinked_td;
741 struct xhci_ep_ctx *ep_ctx;
742 struct xhci_virt_device *vdev;
744 struct xhci_dequeue_state deq_state;
746 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
747 if (!xhci->devs[slot_id])
748 xhci_warn(xhci, "Stop endpoint command "
749 "completion for disabled slot %u\n",
754 memset(&deq_state, 0, sizeof(deq_state));
755 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
757 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
761 vdev = xhci->devs[slot_id];
762 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
763 trace_xhci_handle_cmd_stop_ep(ep_ctx);
765 last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
766 struct xhci_td, cancelled_td_list);
768 if (list_empty(&ep->cancelled_td_list)) {
769 xhci_stop_watchdog_timer_in_irq(xhci, ep);
770 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
774 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
775 * We have the xHCI lock, so nothing can modify this list until we drop
776 * it. We're also in the event handler, so we can't get re-interrupted
777 * if another Stop Endpoint command completes
779 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
780 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
781 "Removing canceled TD starting at 0x%llx (dma).",
782 (unsigned long long)xhci_trb_virt_to_dma(
783 cur_td->start_seg, cur_td->first_trb));
784 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
786 /* This shouldn't happen unless a driver is mucking
787 * with the stream ID after submission. This will
788 * leave the TD on the hardware ring, and the hardware
789 * will try to execute it, and may access a buffer
790 * that has already been freed. In the best case, the
791 * hardware will execute it, and the event handler will
792 * ignore the completion event for that TD, since it was
793 * removed from the td_list for that endpoint. In
794 * short, don't muck with the stream ID after
797 xhci_warn(xhci, "WARN Cancelled URB %p "
798 "has invalid stream ID %u.\n",
800 cur_td->urb->stream_id);
801 goto remove_finished_td;
804 * If we stopped on the TD we need to cancel, then we have to
805 * move the xHC endpoint ring dequeue pointer past this TD.
807 hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
808 cur_td->urb->stream_id);
811 if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
812 cur_td->last_trb, hw_deq, false)) {
813 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
814 cur_td->urb->stream_id,
817 td_to_noop(xhci, ep_ring, cur_td, false);
822 * The event handler won't see a completion for this TD anymore,
823 * so remove it from the endpoint ring's TD list. Keep it in
824 * the cancelled TD list for URB completion later.
826 list_del_init(&cur_td->td_list);
829 xhci_stop_watchdog_timer_in_irq(xhci, ep);
831 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
832 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
833 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
835 xhci_ring_cmd_db(xhci);
837 /* Otherwise ring the doorbell(s) to restart queued transfers */
838 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
842 * Drop the lock and complete the URBs in the cancelled TD list.
843 * New TDs to be cancelled might be added to the end of the list before
844 * we can complete all the URBs for the TDs we already unlinked.
845 * So stop when we've completed the URB for the last TD we unlinked.
848 cur_td = list_first_entry(&ep->cancelled_td_list,
849 struct xhci_td, cancelled_td_list);
850 list_del_init(&cur_td->cancelled_td_list);
852 /* Clean up the cancelled URB */
853 /* Doesn't matter what we pass for status, since the core will
854 * just overwrite it (because the URB has been unlinked).
856 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
857 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
858 inc_td_cnt(cur_td->urb);
859 if (last_td_in_urb(cur_td))
860 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
862 /* Stop processing the cancelled list if the watchdog timer is
865 if (xhci->xhc_state & XHCI_STATE_DYING)
867 } while (cur_td != last_unlinked_td);
869 /* Return to the event handler with xhci->lock re-acquired */
872 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
874 struct xhci_td *cur_td;
877 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
878 list_del_init(&cur_td->td_list);
880 if (!list_empty(&cur_td->cancelled_td_list))
881 list_del_init(&cur_td->cancelled_td_list);
883 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
885 inc_td_cnt(cur_td->urb);
886 if (last_td_in_urb(cur_td))
887 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
891 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
892 int slot_id, int ep_index)
894 struct xhci_td *cur_td;
896 struct xhci_virt_ep *ep;
897 struct xhci_ring *ring;
899 ep = &xhci->devs[slot_id]->eps[ep_index];
900 if ((ep->ep_state & EP_HAS_STREAMS) ||
901 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
904 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
906 ring = ep->stream_info->stream_rings[stream_id];
910 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
911 "Killing URBs for slot ID %u, ep index %u, stream %u",
912 slot_id, ep_index, stream_id);
913 xhci_kill_ring_urbs(xhci, ring);
919 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
920 "Killing URBs for slot ID %u, ep index %u",
922 xhci_kill_ring_urbs(xhci, ring);
925 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
927 list_del_init(&cur_td->cancelled_td_list);
928 inc_td_cnt(cur_td->urb);
930 if (last_td_in_urb(cur_td))
931 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
936 * host controller died, register read returns 0xffffffff
937 * Complete pending commands, mark them ABORTED.
938 * URBs need to be given back as usb core might be waiting with device locks
939 * held for the URBs to finish during device disconnect, blocking host remove.
941 * Call with xhci->lock held.
942 * lock is relased and re-acquired while giving back urb.
944 void xhci_hc_died(struct xhci_hcd *xhci)
948 if (xhci->xhc_state & XHCI_STATE_DYING)
951 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
952 xhci->xhc_state |= XHCI_STATE_DYING;
954 xhci_cleanup_command_queue(xhci);
956 /* return any pending urbs, remove may be waiting for them */
957 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
960 for (j = 0; j < 31; j++)
961 xhci_kill_endpoint_urbs(xhci, i, j);
964 /* inform usb core hc died if PCI remove isn't already handling it */
965 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
966 usb_hc_died(xhci_to_hcd(xhci));
969 /* Watchdog timer function for when a stop endpoint command fails to complete.
970 * In this case, we assume the host controller is broken or dying or dead. The
971 * host may still be completing some other events, so we have to be careful to
972 * let the event ring handler and the URB dequeueing/enqueueing functions know
973 * through xhci->state.
975 * The timer may also fire if the host takes a very long time to respond to the
976 * command, and the stop endpoint command completion handler cannot delete the
977 * timer before the timer function is called. Another endpoint cancellation may
978 * sneak in before the timer function can grab the lock, and that may queue
979 * another stop endpoint command and add the timer back. So we cannot use a
980 * simple flag to say whether there is a pending stop endpoint command for a
981 * particular endpoint.
983 * Instead we use a combination of that flag and checking if a new timer is
986 void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
988 struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
989 struct xhci_hcd *xhci = ep->xhci;
992 spin_lock_irqsave(&xhci->lock, flags);
994 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
995 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
996 timer_pending(&ep->stop_cmd_timer)) {
997 spin_unlock_irqrestore(&xhci->lock, flags);
998 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
1002 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
1003 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1008 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
1009 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
1010 * and try to recover a -ETIMEDOUT with a host controller reset
1014 spin_unlock_irqrestore(&xhci->lock, flags);
1015 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1016 "xHCI host controller is dead.");
1019 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1020 struct xhci_virt_device *dev,
1021 struct xhci_ring *ep_ring,
1022 unsigned int ep_index)
1024 union xhci_trb *dequeue_temp;
1025 int num_trbs_free_temp;
1026 bool revert = false;
1028 num_trbs_free_temp = ep_ring->num_trbs_free;
1029 dequeue_temp = ep_ring->dequeue;
1031 /* If we get two back-to-back stalls, and the first stalled transfer
1032 * ends just before a link TRB, the dequeue pointer will be left on
1033 * the link TRB by the code in the while loop. So we have to update
1034 * the dequeue pointer one segment further, or we'll jump off
1035 * the segment into la-la-land.
1037 if (trb_is_link(ep_ring->dequeue)) {
1038 ep_ring->deq_seg = ep_ring->deq_seg->next;
1039 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1042 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1043 /* We have more usable TRBs */
1044 ep_ring->num_trbs_free++;
1046 if (trb_is_link(ep_ring->dequeue)) {
1047 if (ep_ring->dequeue ==
1048 dev->eps[ep_index].queued_deq_ptr)
1050 ep_ring->deq_seg = ep_ring->deq_seg->next;
1051 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1053 if (ep_ring->dequeue == dequeue_temp) {
1060 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1061 ep_ring->num_trbs_free = num_trbs_free_temp;
1066 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1067 * we need to clear the set deq pending flag in the endpoint ring state, so that
1068 * the TD queueing code can ring the doorbell again. We also need to ring the
1069 * endpoint doorbell to restart the ring, but only if there aren't more
1070 * cancellations pending.
1072 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1073 union xhci_trb *trb, u32 cmd_comp_code)
1075 unsigned int ep_index;
1076 unsigned int stream_id;
1077 struct xhci_ring *ep_ring;
1078 struct xhci_virt_device *dev;
1079 struct xhci_virt_ep *ep;
1080 struct xhci_ep_ctx *ep_ctx;
1081 struct xhci_slot_ctx *slot_ctx;
1083 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1084 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1085 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1089 dev = xhci->devs[slot_id];
1090 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1092 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1094 /* XXX: Harmless??? */
1098 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1099 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1100 trace_xhci_handle_cmd_set_deq(slot_ctx);
1101 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1103 if (cmd_comp_code != COMP_SUCCESS) {
1104 unsigned int ep_state;
1105 unsigned int slot_state;
1107 switch (cmd_comp_code) {
1108 case COMP_TRB_ERROR:
1109 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1111 case COMP_CONTEXT_STATE_ERROR:
1112 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1113 ep_state = GET_EP_CTX_STATE(ep_ctx);
1114 slot_state = le32_to_cpu(slot_ctx->dev_state);
1115 slot_state = GET_SLOT_STATE(slot_state);
1116 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1117 "Slot state = %u, EP state = %u",
1118 slot_state, ep_state);
1120 case COMP_SLOT_NOT_ENABLED_ERROR:
1121 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1125 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1129 /* OK what do we do now? The endpoint state is hosed, and we
1130 * should never get to this point if the synchronization between
1131 * queueing, and endpoint state are correct. This might happen
1132 * if the device gets disconnected after we've finished
1133 * cancelling URBs, which might not be an error...
1137 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1138 if (ep->ep_state & EP_HAS_STREAMS) {
1139 struct xhci_stream_ctx *ctx =
1140 &ep->stream_info->stream_ctx_array[stream_id];
1141 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1143 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1145 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1146 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1147 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1148 ep->queued_deq_ptr) == deq) {
1149 /* Update the ring's dequeue segment and dequeue pointer
1150 * to reflect the new position.
1152 update_ring_for_set_deq_completion(xhci, dev,
1155 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1156 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1157 ep->queued_deq_seg, ep->queued_deq_ptr);
1162 ep->ep_state &= ~SET_DEQ_PENDING;
1163 ep->queued_deq_seg = NULL;
1164 ep->queued_deq_ptr = NULL;
1165 /* Restart any rings with pending URBs */
1166 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1169 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1170 union xhci_trb *trb, u32 cmd_comp_code)
1172 struct xhci_virt_device *vdev;
1173 struct xhci_virt_ep *ep;
1174 struct xhci_ep_ctx *ep_ctx;
1175 unsigned int ep_index;
1177 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1178 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1182 vdev = xhci->devs[slot_id];
1183 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1184 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1186 /* This command will only fail if the endpoint wasn't halted,
1187 * but we don't care.
1189 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1190 "Ignoring reset ep completion code of %u", cmd_comp_code);
1192 /* HW with the reset endpoint quirk needs to have a configure endpoint
1193 * command complete before the endpoint can be used. Queue that here
1194 * because the HW can't handle two commands being queued in a row.
1196 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1197 struct xhci_command *command;
1199 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1203 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1204 "Queueing configure endpoint command");
1205 xhci_queue_configure_endpoint(xhci, command,
1206 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1208 xhci_ring_cmd_db(xhci);
1210 /* Clear our internal halted state */
1211 ep->ep_state &= ~EP_HALTED;
1215 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1216 struct xhci_command *command, u32 cmd_comp_code)
1218 if (cmd_comp_code == COMP_SUCCESS)
1219 command->slot_id = slot_id;
1221 command->slot_id = 0;
1224 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1226 struct xhci_virt_device *virt_dev;
1227 struct xhci_slot_ctx *slot_ctx;
1229 virt_dev = xhci->devs[slot_id];
1233 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1234 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1236 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1237 /* Delete default control endpoint resources */
1238 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1241 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1242 struct xhci_event_cmd *event, u32 cmd_comp_code)
1244 struct xhci_virt_device *virt_dev;
1245 struct xhci_input_control_ctx *ctrl_ctx;
1246 struct xhci_ep_ctx *ep_ctx;
1247 unsigned int ep_index;
1248 unsigned int ep_state;
1249 u32 add_flags, drop_flags;
1252 * Configure endpoint commands can come from the USB core
1253 * configuration or alt setting changes, or because the HW
1254 * needed an extra configure endpoint command after a reset
1255 * endpoint command or streams were being configured.
1256 * If the command was for a halted endpoint, the xHCI driver
1257 * is not waiting on the configure endpoint command.
1259 virt_dev = xhci->devs[slot_id];
1260 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1262 xhci_warn(xhci, "Could not get input context, bad type.\n");
1266 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1267 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1268 /* Input ctx add_flags are the endpoint index plus one */
1269 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1271 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1272 trace_xhci_handle_cmd_config_ep(ep_ctx);
1274 /* A usb_set_interface() call directly after clearing a halted
1275 * condition may race on this quirky hardware. Not worth
1276 * worrying about, since this is prototype hardware. Not sure
1277 * if this will work for streams, but streams support was
1278 * untested on this prototype.
1280 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1281 ep_index != (unsigned int) -1 &&
1282 add_flags - SLOT_FLAG == drop_flags) {
1283 ep_state = virt_dev->eps[ep_index].ep_state;
1284 if (!(ep_state & EP_HALTED))
1286 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1287 "Completed config ep cmd - "
1288 "last ep index = %d, state = %d",
1289 ep_index, ep_state);
1290 /* Clear internal halted state and restart ring(s) */
1291 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1292 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1298 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1300 struct xhci_virt_device *vdev;
1301 struct xhci_slot_ctx *slot_ctx;
1303 vdev = xhci->devs[slot_id];
1304 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1305 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1308 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1309 struct xhci_event_cmd *event)
1311 struct xhci_virt_device *vdev;
1312 struct xhci_slot_ctx *slot_ctx;
1314 vdev = xhci->devs[slot_id];
1315 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1316 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1318 xhci_dbg(xhci, "Completed reset device command.\n");
1319 if (!xhci->devs[slot_id])
1320 xhci_warn(xhci, "Reset device command completion "
1321 "for disabled slot %u\n", slot_id);
1324 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1325 struct xhci_event_cmd *event)
1327 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1328 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1331 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1332 "NEC firmware version %2x.%02x",
1333 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1334 NEC_FW_MINOR(le32_to_cpu(event->status)));
1337 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1339 list_del(&cmd->cmd_list);
1341 if (cmd->completion) {
1342 cmd->status = status;
1343 complete(cmd->completion);
1349 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1351 struct xhci_command *cur_cmd, *tmp_cmd;
1352 xhci->current_cmd = NULL;
1353 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1354 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1357 void xhci_handle_command_timeout(struct work_struct *work)
1359 struct xhci_hcd *xhci;
1360 unsigned long flags;
1363 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1365 spin_lock_irqsave(&xhci->lock, flags);
1368 * If timeout work is pending, or current_cmd is NULL, it means we
1369 * raced with command completion. Command is handled so just return.
1371 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1372 spin_unlock_irqrestore(&xhci->lock, flags);
1375 /* mark this command to be cancelled */
1376 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1378 /* Make sure command ring is running before aborting it */
1379 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1380 if (hw_ring_state == ~(u64)0) {
1382 goto time_out_completed;
1385 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1386 (hw_ring_state & CMD_RING_RUNNING)) {
1387 /* Prevent new doorbell, and start command abort */
1388 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1389 xhci_dbg(xhci, "Command timeout\n");
1390 xhci_abort_cmd_ring(xhci, flags);
1391 goto time_out_completed;
1394 /* host removed. Bail out */
1395 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1396 xhci_dbg(xhci, "host removed, ring start fail?\n");
1397 xhci_cleanup_command_queue(xhci);
1399 goto time_out_completed;
1402 /* command timeout on stopped ring, ring can't be aborted */
1403 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1404 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1407 spin_unlock_irqrestore(&xhci->lock, flags);
1411 static void handle_cmd_completion(struct xhci_hcd *xhci,
1412 struct xhci_event_cmd *event)
1414 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1416 dma_addr_t cmd_dequeue_dma;
1418 union xhci_trb *cmd_trb;
1419 struct xhci_command *cmd;
1422 cmd_dma = le64_to_cpu(event->cmd_trb);
1423 cmd_trb = xhci->cmd_ring->dequeue;
1425 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1427 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1430 * Check whether the completion event is for our internal kept
1433 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1435 "ERROR mismatched command completion event\n");
1439 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1441 cancel_delayed_work(&xhci->cmd_timer);
1443 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1445 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1446 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1447 complete_all(&xhci->cmd_ring_stop_completion);
1451 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1453 "Command completion event does not match command\n");
1458 * Host aborted the command ring, check if the current command was
1459 * supposed to be aborted, otherwise continue normally.
1460 * The command ring is stopped now, but the xHC will issue a Command
1461 * Ring Stopped event which will cause us to restart it.
1463 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1464 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1465 if (cmd->status == COMP_COMMAND_ABORTED) {
1466 if (xhci->current_cmd == cmd)
1467 xhci->current_cmd = NULL;
1472 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1474 case TRB_ENABLE_SLOT:
1475 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1477 case TRB_DISABLE_SLOT:
1478 xhci_handle_cmd_disable_slot(xhci, slot_id);
1481 if (!cmd->completion)
1482 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1485 case TRB_EVAL_CONTEXT:
1488 xhci_handle_cmd_addr_dev(xhci, slot_id);
1491 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1492 le32_to_cpu(cmd_trb->generic.field[3])));
1493 if (!cmd->completion)
1494 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1497 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1498 le32_to_cpu(cmd_trb->generic.field[3])));
1499 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1502 /* Is this an aborted command turned to NO-OP? */
1503 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1504 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1507 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1508 le32_to_cpu(cmd_trb->generic.field[3])));
1509 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1512 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1513 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1515 slot_id = TRB_TO_SLOT_ID(
1516 le32_to_cpu(cmd_trb->generic.field[3]));
1517 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1519 case TRB_NEC_GET_FW:
1520 xhci_handle_cmd_nec_get_fw(xhci, event);
1523 /* Skip over unknown commands on the event ring */
1524 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1528 /* restart timer if this wasn't the last command */
1529 if (!list_is_singular(&xhci->cmd_list)) {
1530 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1531 struct xhci_command, cmd_list);
1532 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1533 } else if (xhci->current_cmd == cmd) {
1534 xhci->current_cmd = NULL;
1538 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1540 inc_deq(xhci, xhci->cmd_ring);
1543 static void handle_vendor_event(struct xhci_hcd *xhci,
1544 union xhci_trb *event)
1548 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1549 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1550 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1551 handle_cmd_completion(xhci, &event->event_cmd);
1554 static void handle_device_notification(struct xhci_hcd *xhci,
1555 union xhci_trb *event)
1558 struct usb_device *udev;
1560 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1561 if (!xhci->devs[slot_id]) {
1562 xhci_warn(xhci, "Device Notification event for "
1563 "unused slot %u\n", slot_id);
1567 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1569 udev = xhci->devs[slot_id]->udev;
1570 if (udev && udev->parent)
1571 usb_wakeup_notification(udev->parent, udev->portnum);
1575 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1577 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1578 * If a connection to a USB 1 device is followed by another connection
1579 * to a USB 2 device.
1581 * Reset the PHY after the USB device is disconnected if device speed
1582 * is less than HCD_USB3.
1583 * Retry the reset sequence max of 4 times checking the PLL lock status.
1586 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1588 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1590 u32 retry_count = 4;
1593 /* Assert PHY reset */
1594 writel(0x6F, hcd->regs + 0x1048);
1596 /* De-assert the PHY reset */
1597 writel(0x7F, hcd->regs + 0x1048);
1599 pll_lock_check = readl(hcd->regs + 0x1070);
1600 } while (!(pll_lock_check & 0x1) && --retry_count);
1603 static void handle_port_status(struct xhci_hcd *xhci,
1604 union xhci_trb *event)
1606 struct usb_hcd *hcd;
1608 u32 portsc, cmd_reg;
1611 unsigned int hcd_portnum;
1612 struct xhci_bus_state *bus_state;
1613 bool bogus_port_status = false;
1614 struct xhci_port *port;
1616 /* Port status change events always have a successful completion code */
1617 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1619 "WARN: xHC returned failed port status event\n");
1621 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1622 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1624 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1625 if ((port_id <= 0) || (port_id > max_ports)) {
1626 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1627 inc_deq(xhci, xhci->event_ring);
1631 port = &xhci->hw_ports[port_id - 1];
1632 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1633 xhci_warn(xhci, "Event for invalid port %u\n", port_id);
1634 bogus_port_status = true;
1638 /* We might get interrupts after shared_hcd is removed */
1639 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1640 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1641 bogus_port_status = true;
1645 hcd = port->rhub->hcd;
1646 bus_state = &xhci->bus_state[hcd_index(hcd)];
1647 hcd_portnum = port->hcd_portnum;
1648 portsc = readl(port->addr);
1650 trace_xhci_handle_port_status(hcd_portnum, portsc);
1652 if (hcd->state == HC_STATE_SUSPENDED) {
1653 xhci_dbg(xhci, "resume root hub\n");
1654 usb_hcd_resume_root_hub(hcd);
1657 if (hcd->speed >= HCD_USB3 &&
1658 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1659 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1660 if (slot_id && xhci->devs[slot_id])
1661 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1664 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1665 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1667 cmd_reg = readl(&xhci->op_regs->command);
1668 if (!(cmd_reg & CMD_RUN)) {
1669 xhci_warn(xhci, "xHC is not running.\n");
1673 if (DEV_SUPERSPEED_ANY(portsc)) {
1674 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1675 /* Set a flag to say the port signaled remote wakeup,
1676 * so we can tell the difference between the end of
1677 * device and host initiated resume.
1679 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1680 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1681 xhci_set_link_state(xhci, port, XDEV_U0);
1682 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1683 /* Need to wait until the next link state change
1684 * indicates the device is actually in U0.
1686 bogus_port_status = true;
1688 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1689 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1690 bus_state->resume_done[hcd_portnum] = jiffies +
1691 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1692 set_bit(hcd_portnum, &bus_state->resuming_ports);
1693 /* Do the rest in GetPortStatus after resume time delay.
1694 * Avoid polling roothub status before that so that a
1695 * usb device auto-resume latency around ~40ms.
1697 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1698 mod_timer(&hcd->rh_timer,
1699 bus_state->resume_done[hcd_portnum]);
1700 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1701 bogus_port_status = true;
1705 if ((portsc & PORT_PLC) &&
1706 DEV_SUPERSPEED_ANY(portsc) &&
1707 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1708 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1709 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1710 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1711 /* We've just brought the device into U0/1/2 through either the
1712 * Resume state after a device remote wakeup, or through the
1713 * U3Exit state after a host-initiated resume. If it's a device
1714 * initiated remote wake, don't pass up the link state change,
1715 * so the roothub behavior is consistent with external
1716 * USB 3.0 hub behavior.
1718 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1719 if (slot_id && xhci->devs[slot_id])
1720 xhci_ring_device(xhci, slot_id);
1721 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1722 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1723 usb_wakeup_notification(hcd->self.root_hub,
1725 bogus_port_status = true;
1731 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1732 * RExit to a disconnect state). If so, let the the driver know it's
1733 * out of the RExit state.
1735 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1736 test_and_clear_bit(hcd_portnum,
1737 &bus_state->rexit_ports)) {
1738 complete(&bus_state->rexit_done[hcd_portnum]);
1739 bogus_port_status = true;
1743 if (hcd->speed < HCD_USB3) {
1744 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1745 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1746 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1747 xhci_cavium_reset_phy_quirk(xhci);
1751 /* Update event ring dequeue pointer before dropping the lock */
1752 inc_deq(xhci, xhci->event_ring);
1754 /* Don't make the USB core poll the roothub if we got a bad port status
1755 * change event. Besides, at that point we can't tell which roothub
1756 * (USB 2.0 or USB 3.0) to kick.
1758 if (bogus_port_status)
1762 * xHCI port-status-change events occur when the "or" of all the
1763 * status-change bits in the portsc register changes from 0 to 1.
1764 * New status changes won't cause an event if any other change
1765 * bits are still set. When an event occurs, switch over to
1766 * polling to avoid losing status changes.
1768 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1769 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1770 spin_unlock(&xhci->lock);
1771 /* Pass this up to the core */
1772 usb_hcd_poll_rh_status(hcd);
1773 spin_lock(&xhci->lock);
1777 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1778 * at end_trb, which may be in another segment. If the suspect DMA address is a
1779 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1782 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1783 struct xhci_segment *start_seg,
1784 union xhci_trb *start_trb,
1785 union xhci_trb *end_trb,
1786 dma_addr_t suspect_dma,
1789 dma_addr_t start_dma;
1790 dma_addr_t end_seg_dma;
1791 dma_addr_t end_trb_dma;
1792 struct xhci_segment *cur_seg;
1794 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1795 cur_seg = start_seg;
1800 /* We may get an event for a Link TRB in the middle of a TD */
1801 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1802 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1803 /* If the end TRB isn't in this segment, this is set to 0 */
1804 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1808 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1809 (unsigned long long)suspect_dma,
1810 (unsigned long long)start_dma,
1811 (unsigned long long)end_trb_dma,
1812 (unsigned long long)cur_seg->dma,
1813 (unsigned long long)end_seg_dma);
1815 if (end_trb_dma > 0) {
1816 /* The end TRB is in this segment, so suspect should be here */
1817 if (start_dma <= end_trb_dma) {
1818 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1821 /* Case for one segment with
1822 * a TD wrapped around to the top
1824 if ((suspect_dma >= start_dma &&
1825 suspect_dma <= end_seg_dma) ||
1826 (suspect_dma >= cur_seg->dma &&
1827 suspect_dma <= end_trb_dma))
1832 /* Might still be somewhere in this segment */
1833 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1836 cur_seg = cur_seg->next;
1837 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1838 } while (cur_seg != start_seg);
1843 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1844 unsigned int slot_id, unsigned int ep_index,
1845 unsigned int stream_id, struct xhci_td *td,
1846 enum xhci_ep_reset_type reset_type)
1848 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1849 struct xhci_command *command;
1852 * Avoid resetting endpoint if link is inactive. Can cause host hang.
1853 * Device will be reset soon to recover the link so don't do anything
1855 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR)
1858 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1862 ep->ep_state |= EP_HALTED;
1864 xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
1866 if (reset_type == EP_HARD_RESET) {
1867 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
1868 xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td);
1870 xhci_ring_cmd_db(xhci);
1873 /* Check if an error has halted the endpoint ring. The class driver will
1874 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1875 * However, a babble and other errors also halt the endpoint ring, and the class
1876 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1877 * Ring Dequeue Pointer command manually.
1879 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1880 struct xhci_ep_ctx *ep_ctx,
1881 unsigned int trb_comp_code)
1883 /* TRB completion codes that may require a manual halt cleanup */
1884 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1885 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1886 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1887 /* The 0.95 spec says a babbling control endpoint
1888 * is not halted. The 0.96 spec says it is. Some HW
1889 * claims to be 0.95 compliant, but it halts the control
1890 * endpoint anyway. Check if a babble halted the
1893 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1899 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1901 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1902 /* Vendor defined "informational" completion code,
1903 * treat as not-an-error.
1905 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1907 xhci_dbg(xhci, "Treating code as success.\n");
1913 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1914 struct xhci_ring *ep_ring, int *status)
1916 struct urb *urb = NULL;
1918 /* Clean up the endpoint's TD list */
1921 /* if a bounce buffer was used to align this td then unmap it */
1922 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1924 /* Do one last check of the actual transfer length.
1925 * If the host controller said we transferred more data than the buffer
1926 * length, urb->actual_length will be a very big number (since it's
1927 * unsigned). Play it safe and say we didn't transfer anything.
1929 if (urb->actual_length > urb->transfer_buffer_length) {
1930 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
1931 urb->transfer_buffer_length, urb->actual_length);
1932 urb->actual_length = 0;
1935 list_del_init(&td->td_list);
1936 /* Was this TD slated to be cancelled but completed anyway? */
1937 if (!list_empty(&td->cancelled_td_list))
1938 list_del_init(&td->cancelled_td_list);
1941 /* Giveback the urb when all the tds are completed */
1942 if (last_td_in_urb(td)) {
1943 if ((urb->actual_length != urb->transfer_buffer_length &&
1944 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
1945 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
1946 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
1947 urb, urb->actual_length,
1948 urb->transfer_buffer_length, *status);
1950 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
1951 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
1953 xhci_giveback_urb_in_irq(xhci, td, *status);
1959 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1960 struct xhci_transfer_event *event,
1961 struct xhci_virt_ep *ep, int *status)
1963 struct xhci_virt_device *xdev;
1964 struct xhci_ep_ctx *ep_ctx;
1965 struct xhci_ring *ep_ring;
1966 unsigned int slot_id;
1970 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1971 xdev = xhci->devs[slot_id];
1972 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1973 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1974 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1975 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1977 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
1978 trb_comp_code == COMP_STOPPED ||
1979 trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
1980 /* The Endpoint Stop Command completion will take care of any
1981 * stopped TDs. A stopped TD may be restarted, so don't update
1982 * the ring dequeue pointer or take this TD off any lists yet.
1986 if (trb_comp_code == COMP_STALL_ERROR ||
1987 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1989 /* Issue a reset endpoint command to clear the host side
1990 * halt, followed by a set dequeue command to move the
1991 * dequeue pointer past the TD.
1992 * The class driver clears the device side halt later.
1994 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1995 ep_ring->stream_id, td, EP_HARD_RESET);
1997 /* Update ring dequeue pointer */
1998 while (ep_ring->dequeue != td->last_trb)
1999 inc_deq(xhci, ep_ring);
2000 inc_deq(xhci, ep_ring);
2003 return xhci_td_cleanup(xhci, td, ep_ring, status);
2006 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2007 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2008 union xhci_trb *stop_trb)
2011 union xhci_trb *trb = ring->dequeue;
2012 struct xhci_segment *seg = ring->deq_seg;
2014 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2015 if (!trb_is_noop(trb) && !trb_is_link(trb))
2016 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2022 * Process control tds, update urb status and actual_length.
2024 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2025 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2026 struct xhci_virt_ep *ep, int *status)
2028 struct xhci_virt_device *xdev;
2029 unsigned int slot_id;
2031 struct xhci_ep_ctx *ep_ctx;
2033 u32 remaining, requested;
2036 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2037 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2038 xdev = xhci->devs[slot_id];
2039 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2040 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2041 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2042 requested = td->urb->transfer_buffer_length;
2043 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2045 switch (trb_comp_code) {
2047 if (trb_type != TRB_STATUS) {
2048 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2049 (trb_type == TRB_DATA) ? "data" : "setup");
2050 *status = -ESHUTDOWN;
2055 case COMP_SHORT_PACKET:
2058 case COMP_STOPPED_SHORT_PACKET:
2059 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2060 td->urb->actual_length = remaining;
2062 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2067 td->urb->actual_length = 0;
2071 td->urb->actual_length = requested - remaining;
2074 td->urb->actual_length = requested;
2077 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2081 case COMP_STOPPED_LENGTH_INVALID:
2084 if (!xhci_requires_manual_halt_cleanup(xhci,
2085 ep_ctx, trb_comp_code))
2087 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2088 trb_comp_code, ep_index);
2089 /* else fall through */
2090 case COMP_STALL_ERROR:
2091 /* Did we transfer part of the data (middle) phase? */
2092 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2093 td->urb->actual_length = requested - remaining;
2094 else if (!td->urb_length_set)
2095 td->urb->actual_length = 0;
2099 /* stopped at setup stage, no data transferred */
2100 if (trb_type == TRB_SETUP)
2104 * if on data stage then update the actual_length of the URB and flag it
2105 * as set, so it won't be overwritten in the event for the last TRB.
2107 if (trb_type == TRB_DATA ||
2108 trb_type == TRB_NORMAL) {
2109 td->urb_length_set = true;
2110 td->urb->actual_length = requested - remaining;
2111 xhci_dbg(xhci, "Waiting for status stage event\n");
2115 /* at status stage */
2116 if (!td->urb_length_set)
2117 td->urb->actual_length = requested;
2120 return finish_td(xhci, td, event, ep, status);
2124 * Process isochronous tds, update urb packet status and actual_length.
2126 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2127 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2128 struct xhci_virt_ep *ep, int *status)
2130 struct xhci_ring *ep_ring;
2131 struct urb_priv *urb_priv;
2133 struct usb_iso_packet_descriptor *frame;
2135 bool sum_trbs_for_length = false;
2136 u32 remaining, requested, ep_trb_len;
2137 int short_framestatus;
2139 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2140 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2141 urb_priv = td->urb->hcpriv;
2142 idx = urb_priv->num_tds_done;
2143 frame = &td->urb->iso_frame_desc[idx];
2144 requested = frame->length;
2145 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2146 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2147 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2150 /* handle completion code */
2151 switch (trb_comp_code) {
2154 frame->status = short_framestatus;
2155 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2156 sum_trbs_for_length = true;
2161 case COMP_SHORT_PACKET:
2162 frame->status = short_framestatus;
2163 sum_trbs_for_length = true;
2165 case COMP_BANDWIDTH_OVERRUN_ERROR:
2166 frame->status = -ECOMM;
2168 case COMP_ISOCH_BUFFER_OVERRUN:
2169 case COMP_BABBLE_DETECTED_ERROR:
2170 frame->status = -EOVERFLOW;
2172 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2173 case COMP_STALL_ERROR:
2174 frame->status = -EPROTO;
2176 case COMP_USB_TRANSACTION_ERROR:
2177 frame->status = -EPROTO;
2178 if (ep_trb != td->last_trb)
2182 sum_trbs_for_length = true;
2184 case COMP_STOPPED_SHORT_PACKET:
2185 /* field normally containing residue now contains tranferred */
2186 frame->status = short_framestatus;
2187 requested = remaining;
2189 case COMP_STOPPED_LENGTH_INVALID:
2194 sum_trbs_for_length = true;
2199 if (sum_trbs_for_length)
2200 frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2201 ep_trb_len - remaining;
2203 frame->actual_length = requested;
2205 td->urb->actual_length += frame->actual_length;
2207 return finish_td(xhci, td, event, ep, status);
2210 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2211 struct xhci_transfer_event *event,
2212 struct xhci_virt_ep *ep, int *status)
2214 struct xhci_ring *ep_ring;
2215 struct urb_priv *urb_priv;
2216 struct usb_iso_packet_descriptor *frame;
2219 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2220 urb_priv = td->urb->hcpriv;
2221 idx = urb_priv->num_tds_done;
2222 frame = &td->urb->iso_frame_desc[idx];
2224 /* The transfer is partly done. */
2225 frame->status = -EXDEV;
2227 /* calc actual length */
2228 frame->actual_length = 0;
2230 /* Update ring dequeue pointer */
2231 while (ep_ring->dequeue != td->last_trb)
2232 inc_deq(xhci, ep_ring);
2233 inc_deq(xhci, ep_ring);
2235 return xhci_td_cleanup(xhci, td, ep_ring, status);
2239 * Process bulk and interrupt tds, update urb status and actual_length.
2241 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2242 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2243 struct xhci_virt_ep *ep, int *status)
2245 struct xhci_ring *ep_ring;
2247 u32 remaining, requested, ep_trb_len;
2249 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2250 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2251 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2252 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2253 requested = td->urb->transfer_buffer_length;
2255 switch (trb_comp_code) {
2257 /* handle success with untransferred data as short packet */
2258 if (ep_trb != td->last_trb || remaining) {
2259 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2260 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2261 td->urb->ep->desc.bEndpointAddress,
2262 requested, remaining);
2266 case COMP_SHORT_PACKET:
2267 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2268 td->urb->ep->desc.bEndpointAddress,
2269 requested, remaining);
2272 case COMP_STOPPED_SHORT_PACKET:
2273 td->urb->actual_length = remaining;
2275 case COMP_STOPPED_LENGTH_INVALID:
2276 /* stopped on ep trb with invalid length, exclude it */
2285 if (ep_trb == td->last_trb)
2286 td->urb->actual_length = requested - remaining;
2288 td->urb->actual_length =
2289 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2290 ep_trb_len - remaining;
2292 if (remaining > requested) {
2293 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2295 td->urb->actual_length = 0;
2297 return finish_td(xhci, td, event, ep, status);
2301 * If this function returns an error condition, it means it got a Transfer
2302 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2303 * At this point, the host controller is probably hosed and should be reset.
2305 static int handle_tx_event(struct xhci_hcd *xhci,
2306 struct xhci_transfer_event *event)
2308 struct xhci_virt_device *xdev;
2309 struct xhci_virt_ep *ep;
2310 struct xhci_ring *ep_ring;
2311 unsigned int slot_id;
2313 struct xhci_td *td = NULL;
2314 dma_addr_t ep_trb_dma;
2315 struct xhci_segment *ep_seg;
2316 union xhci_trb *ep_trb;
2317 int status = -EINPROGRESS;
2318 struct xhci_ep_ctx *ep_ctx;
2319 struct list_head *tmp;
2322 bool handling_skipped_tds = false;
2324 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2325 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2326 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2327 ep_trb_dma = le64_to_cpu(event->buffer);
2329 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2331 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2335 xdev = xhci->devs[slot_id];
2336 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2337 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2339 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2341 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2346 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2348 switch (trb_comp_code) {
2349 case COMP_STALL_ERROR:
2350 case COMP_USB_TRANSACTION_ERROR:
2351 case COMP_INVALID_STREAM_TYPE_ERROR:
2352 case COMP_INVALID_STREAM_ID_ERROR:
2353 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
2354 NULL, EP_SOFT_RESET);
2356 case COMP_RING_UNDERRUN:
2357 case COMP_RING_OVERRUN:
2358 case COMP_STOPPED_LENGTH_INVALID:
2361 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2367 /* Count current td numbers if ep->skip is set */
2369 list_for_each(tmp, &ep_ring->td_list)
2373 /* Look for common error cases */
2374 switch (trb_comp_code) {
2375 /* Skip codes that require special handling depending on
2379 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2381 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2382 ep_ring->last_td_was_short)
2383 trb_comp_code = COMP_SHORT_PACKET;
2385 xhci_warn_ratelimited(xhci,
2386 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2388 case COMP_SHORT_PACKET:
2390 /* Completion codes for endpoint stopped state */
2392 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2395 case COMP_STOPPED_LENGTH_INVALID:
2397 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2400 case COMP_STOPPED_SHORT_PACKET:
2402 "Stopped with short packet transfer detected for slot %u ep %u\n",
2405 /* Completion codes for endpoint halted state */
2406 case COMP_STALL_ERROR:
2407 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2409 ep->ep_state |= EP_HALTED;
2412 case COMP_SPLIT_TRANSACTION_ERROR:
2413 case COMP_USB_TRANSACTION_ERROR:
2414 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2418 case COMP_BABBLE_DETECTED_ERROR:
2419 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2421 status = -EOVERFLOW;
2423 /* Completion codes for endpoint error state */
2424 case COMP_TRB_ERROR:
2426 "WARN: TRB error for slot %u ep %u on endpoint\n",
2430 /* completion codes not indicating endpoint state change */
2431 case COMP_DATA_BUFFER_ERROR:
2433 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2437 case COMP_BANDWIDTH_OVERRUN_ERROR:
2439 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2442 case COMP_ISOCH_BUFFER_OVERRUN:
2444 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2447 case COMP_RING_UNDERRUN:
2449 * When the Isoch ring is empty, the xHC will generate
2450 * a Ring Overrun Event for IN Isoch endpoint or Ring
2451 * Underrun Event for OUT Isoch endpoint.
2453 xhci_dbg(xhci, "underrun event on endpoint\n");
2454 if (!list_empty(&ep_ring->td_list))
2455 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2456 "still with TDs queued?\n",
2457 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2460 case COMP_RING_OVERRUN:
2461 xhci_dbg(xhci, "overrun event on endpoint\n");
2462 if (!list_empty(&ep_ring->td_list))
2463 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2464 "still with TDs queued?\n",
2465 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2468 case COMP_MISSED_SERVICE_ERROR:
2470 * When encounter missed service error, one or more isoc tds
2471 * may be missed by xHC.
2472 * Set skip flag of the ep_ring; Complete the missed tds as
2473 * short transfer when process the ep_ring next time.
2477 "Miss service interval error for slot %u ep %u, set skip flag\n",
2480 case COMP_NO_PING_RESPONSE_ERROR:
2483 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2487 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2488 /* needs disable slot command to recover */
2490 "WARN: detect an incompatible device for slot %u ep %u",
2495 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2500 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2501 trb_comp_code, slot_id, ep_index);
2506 /* This TRB should be in the TD at the head of this ring's
2509 if (list_empty(&ep_ring->td_list)) {
2511 * Don't print wanings if it's due to a stopped endpoint
2512 * generating an extra completion event if the device
2513 * was suspended. Or, a event for the last TRB of a
2514 * short TD we already got a short event for.
2515 * The short TD is already removed from the TD list.
2518 if (!(trb_comp_code == COMP_STOPPED ||
2519 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2520 ep_ring->last_td_was_short)) {
2521 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2522 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2527 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2533 /* We've skipped all the TDs on the ep ring when ep->skip set */
2534 if (ep->skip && td_num == 0) {
2536 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2541 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2546 /* Is this a TRB in the currently executing TD? */
2547 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2548 td->last_trb, ep_trb_dma, false);
2551 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2552 * is not in the current TD pointed by ep_ring->dequeue because
2553 * that the hardware dequeue pointer still at the previous TRB
2554 * of the current TD. The previous TRB maybe a Link TD or the
2555 * last TRB of the previous TD. The command completion handle
2556 * will take care the rest.
2558 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2559 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2565 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2566 /* Some host controllers give a spurious
2567 * successful event after a short transfer.
2570 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2571 ep_ring->last_td_was_short) {
2572 ep_ring->last_td_was_short = false;
2575 /* HC is busted, give up! */
2577 "ERROR Transfer event TRB DMA ptr not "
2578 "part of current TD ep_index %d "
2579 "comp_code %u\n", ep_index,
2581 trb_in_td(xhci, ep_ring->deq_seg,
2582 ep_ring->dequeue, td->last_trb,
2587 skip_isoc_td(xhci, td, event, ep, &status);
2590 if (trb_comp_code == COMP_SHORT_PACKET)
2591 ep_ring->last_td_was_short = true;
2593 ep_ring->last_td_was_short = false;
2597 "Found td. Clear skip flag for slot %u ep %u.\n",
2602 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2605 trace_xhci_handle_transfer(ep_ring,
2606 (struct xhci_generic_trb *) ep_trb);
2609 * No-op TRB could trigger interrupts in a case where
2610 * a URB was killed and a STALL_ERROR happens right
2611 * after the endpoint ring stopped. Reset the halted
2612 * endpoint. Otherwise, the endpoint remains stalled
2615 if (trb_is_noop(ep_trb)) {
2616 if (trb_comp_code == COMP_STALL_ERROR ||
2617 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2619 xhci_cleanup_halted_endpoint(xhci, slot_id,
2626 /* update the urb's actual_length and give back to the core */
2627 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2628 process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2629 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2630 process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2632 process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2635 handling_skipped_tds = ep->skip &&
2636 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2637 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2640 * Do not update event ring dequeue pointer if we're in a loop
2641 * processing missed tds.
2643 if (!handling_skipped_tds)
2644 inc_deq(xhci, xhci->event_ring);
2647 * If ep->skip is set, it means there are missed tds on the
2648 * endpoint ring need to take care of.
2649 * Process them as short transfer until reach the td pointed by
2652 } while (handling_skipped_tds);
2657 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2658 (unsigned long long) xhci_trb_virt_to_dma(
2659 xhci->event_ring->deq_seg,
2660 xhci->event_ring->dequeue),
2661 lower_32_bits(le64_to_cpu(event->buffer)),
2662 upper_32_bits(le64_to_cpu(event->buffer)),
2663 le32_to_cpu(event->transfer_len),
2664 le32_to_cpu(event->flags));
2669 * This function handles all OS-owned events on the event ring. It may drop
2670 * xhci->lock between event processing (e.g. to pass up port status changes).
2671 * Returns >0 for "possibly more events to process" (caller should call again),
2672 * otherwise 0 if done. In future, <0 returns should indicate error code.
2674 static int xhci_handle_event(struct xhci_hcd *xhci)
2676 union xhci_trb *event;
2677 int update_ptrs = 1;
2680 /* Event ring hasn't been allocated yet. */
2681 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2682 xhci_err(xhci, "ERROR event ring not ready\n");
2686 event = xhci->event_ring->dequeue;
2687 /* Does the HC or OS own the TRB? */
2688 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2689 xhci->event_ring->cycle_state)
2692 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2695 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2696 * speculative reads of the event's flags/data below.
2699 /* FIXME: Handle more event types. */
2700 switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2701 case TRB_TYPE(TRB_COMPLETION):
2702 handle_cmd_completion(xhci, &event->event_cmd);
2704 case TRB_TYPE(TRB_PORT_STATUS):
2705 handle_port_status(xhci, event);
2708 case TRB_TYPE(TRB_TRANSFER):
2709 ret = handle_tx_event(xhci, &event->trans_event);
2713 case TRB_TYPE(TRB_DEV_NOTE):
2714 handle_device_notification(xhci, event);
2717 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2719 handle_vendor_event(xhci, event);
2721 xhci_warn(xhci, "ERROR unknown event type %d\n",
2723 le32_to_cpu(event->event_cmd.flags)));
2725 /* Any of the above functions may drop and re-acquire the lock, so check
2726 * to make sure a watchdog timer didn't mark the host as non-responsive.
2728 if (xhci->xhc_state & XHCI_STATE_DYING) {
2729 xhci_dbg(xhci, "xHCI host dying, returning from "
2730 "event handler.\n");
2735 /* Update SW event ring dequeue pointer */
2736 inc_deq(xhci, xhci->event_ring);
2738 /* Are there more items on the event ring? Caller will call us again to
2745 * Update Event Ring Dequeue Pointer:
2746 * - When all events have finished
2747 * - To avoid "Event Ring Full Error" condition
2749 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2750 union xhci_trb *event_ring_deq)
2755 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2756 /* If necessary, update the HW's version of the event ring deq ptr. */
2757 if (event_ring_deq != xhci->event_ring->dequeue) {
2758 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2759 xhci->event_ring->dequeue);
2761 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
2763 * Per 4.9.4, Software writes to the ERDP register shall
2764 * always advance the Event Ring Dequeue Pointer value.
2766 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
2767 ((u64) deq & (u64) ~ERST_PTR_MASK))
2770 /* Update HC event ring dequeue pointer */
2771 temp_64 &= ERST_PTR_MASK;
2772 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2775 /* Clear the event handler busy flag (RW1C) */
2776 temp_64 |= ERST_EHB;
2777 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2781 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2782 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2783 * indicators of an event TRB error, but we check the status *first* to be safe.
2785 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2787 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2788 union xhci_trb *event_ring_deq;
2789 irqreturn_t ret = IRQ_NONE;
2790 unsigned long flags;
2795 spin_lock_irqsave(&xhci->lock, flags);
2796 /* Check if the xHC generated the interrupt, or the irq is shared */
2797 status = readl(&xhci->op_regs->status);
2798 if (status == ~(u32)0) {
2804 if (!(status & STS_EINT))
2807 if (status & STS_FATAL) {
2808 xhci_warn(xhci, "WARNING: Host System Error\n");
2815 * Clear the op reg interrupt status first,
2816 * so we can receive interrupts from other MSI-X interrupters.
2817 * Write 1 to clear the interrupt status.
2820 writel(status, &xhci->op_regs->status);
2822 if (!hcd->msi_enabled) {
2824 irq_pending = readl(&xhci->ir_set->irq_pending);
2825 irq_pending |= IMAN_IP;
2826 writel(irq_pending, &xhci->ir_set->irq_pending);
2829 if (xhci->xhc_state & XHCI_STATE_DYING ||
2830 xhci->xhc_state & XHCI_STATE_HALTED) {
2831 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2832 "Shouldn't IRQs be disabled?\n");
2833 /* Clear the event handler busy flag (RW1C);
2834 * the event ring should be empty.
2836 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2837 xhci_write_64(xhci, temp_64 | ERST_EHB,
2838 &xhci->ir_set->erst_dequeue);
2843 event_ring_deq = xhci->event_ring->dequeue;
2844 /* FIXME this should be a delayed service routine
2845 * that clears the EHB.
2847 while (xhci_handle_event(xhci) > 0) {
2848 if (event_loop++ < TRBS_PER_SEGMENT / 2)
2850 xhci_update_erst_dequeue(xhci, event_ring_deq);
2851 event_ring_deq = xhci->event_ring->dequeue;
2856 xhci_update_erst_dequeue(xhci, event_ring_deq);
2860 spin_unlock_irqrestore(&xhci->lock, flags);
2865 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2867 return xhci_irq(hcd);
2870 /**** Endpoint Ring Operations ****/
2873 * Generic function for queueing a TRB on a ring.
2874 * The caller must have checked to make sure there's room on the ring.
2876 * @more_trbs_coming: Will you enqueue more TRBs before calling
2877 * prepare_transfer()?
2879 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2880 bool more_trbs_coming,
2881 u32 field1, u32 field2, u32 field3, u32 field4)
2883 struct xhci_generic_trb *trb;
2885 trb = &ring->enqueue->generic;
2886 trb->field[0] = cpu_to_le32(field1);
2887 trb->field[1] = cpu_to_le32(field2);
2888 trb->field[2] = cpu_to_le32(field3);
2889 /* make sure TRB is fully written before giving it to the controller */
2891 trb->field[3] = cpu_to_le32(field4);
2893 trace_xhci_queue_trb(ring, trb);
2895 inc_enq(xhci, ring, more_trbs_coming);
2899 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2900 * FIXME allocate segments if the ring is full.
2902 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2903 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2905 unsigned int num_trbs_needed;
2907 /* Make sure the endpoint has been added to xHC schedule */
2909 case EP_STATE_DISABLED:
2911 * USB core changed config/interfaces without notifying us,
2912 * or hardware is reporting the wrong state.
2914 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2916 case EP_STATE_ERROR:
2917 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2918 /* FIXME event handling code for error needs to clear it */
2919 /* XXX not sure if this should be -ENOENT or not */
2921 case EP_STATE_HALTED:
2922 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2923 case EP_STATE_STOPPED:
2924 case EP_STATE_RUNNING:
2927 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2929 * FIXME issue Configure Endpoint command to try to get the HC
2930 * back into a known state.
2936 if (room_on_ring(xhci, ep_ring, num_trbs))
2939 if (ep_ring == xhci->cmd_ring) {
2940 xhci_err(xhci, "Do not support expand command ring\n");
2944 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2945 "ERROR no room on ep ring, try ring expansion");
2946 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2947 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2949 xhci_err(xhci, "Ring expansion failed\n");
2954 while (trb_is_link(ep_ring->enqueue)) {
2955 /* If we're not dealing with 0.95 hardware or isoc rings
2956 * on AMD 0.96 host, clear the chain bit.
2958 if (!xhci_link_trb_quirk(xhci) &&
2959 !(ep_ring->type == TYPE_ISOC &&
2960 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2961 ep_ring->enqueue->link.control &=
2962 cpu_to_le32(~TRB_CHAIN);
2964 ep_ring->enqueue->link.control |=
2965 cpu_to_le32(TRB_CHAIN);
2968 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
2970 /* Toggle the cycle bit after the last ring segment. */
2971 if (link_trb_toggles_cycle(ep_ring->enqueue))
2972 ep_ring->cycle_state ^= 1;
2974 ep_ring->enq_seg = ep_ring->enq_seg->next;
2975 ep_ring->enqueue = ep_ring->enq_seg->trbs;
2980 static int prepare_transfer(struct xhci_hcd *xhci,
2981 struct xhci_virt_device *xdev,
2982 unsigned int ep_index,
2983 unsigned int stream_id,
2984 unsigned int num_trbs,
2986 unsigned int td_index,
2990 struct urb_priv *urb_priv;
2992 struct xhci_ring *ep_ring;
2993 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2995 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2997 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3002 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3003 num_trbs, mem_flags);
3007 urb_priv = urb->hcpriv;
3008 td = &urb_priv->td[td_index];
3010 INIT_LIST_HEAD(&td->td_list);
3011 INIT_LIST_HEAD(&td->cancelled_td_list);
3013 if (td_index == 0) {
3014 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3020 /* Add this TD to the tail of the endpoint ring's TD list */
3021 list_add_tail(&td->td_list, &ep_ring->td_list);
3022 td->start_seg = ep_ring->enq_seg;
3023 td->first_trb = ep_ring->enqueue;
3028 unsigned int count_trbs(u64 addr, u64 len)
3030 unsigned int num_trbs;
3032 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3040 static inline unsigned int count_trbs_needed(struct urb *urb)
3042 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3045 static unsigned int count_sg_trbs_needed(struct urb *urb)
3047 struct scatterlist *sg;
3048 unsigned int i, len, full_len, num_trbs = 0;
3050 full_len = urb->transfer_buffer_length;
3052 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3053 len = sg_dma_len(sg);
3054 num_trbs += count_trbs(sg_dma_address(sg), len);
3055 len = min_t(unsigned int, len, full_len);
3064 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3068 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3069 len = urb->iso_frame_desc[i].length;
3071 return count_trbs(addr, len);
3074 static void check_trb_math(struct urb *urb, int running_total)
3076 if (unlikely(running_total != urb->transfer_buffer_length))
3077 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3078 "queued %#x (%d), asked for %#x (%d)\n",
3080 urb->ep->desc.bEndpointAddress,
3081 running_total, running_total,
3082 urb->transfer_buffer_length,
3083 urb->transfer_buffer_length);
3086 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3087 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3088 struct xhci_generic_trb *start_trb)
3091 * Pass all the TRBs to the hardware at once and make sure this write
3096 start_trb->field[3] |= cpu_to_le32(start_cycle);
3098 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3099 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3102 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3103 struct xhci_ep_ctx *ep_ctx)
3108 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3109 ep_interval = urb->interval;
3111 /* Convert to microframes */
3112 if (urb->dev->speed == USB_SPEED_LOW ||
3113 urb->dev->speed == USB_SPEED_FULL)
3116 /* FIXME change this to a warning and a suggestion to use the new API
3117 * to set the polling interval (once the API is added).
3119 if (xhci_interval != ep_interval) {
3120 dev_dbg_ratelimited(&urb->dev->dev,
3121 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3122 ep_interval, ep_interval == 1 ? "" : "s",
3123 xhci_interval, xhci_interval == 1 ? "" : "s");
3124 urb->interval = xhci_interval;
3125 /* Convert back to frames for LS/FS devices */
3126 if (urb->dev->speed == USB_SPEED_LOW ||
3127 urb->dev->speed == USB_SPEED_FULL)
3133 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3134 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3135 * (comprised of sg list entries) can take several service intervals to
3138 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3139 struct urb *urb, int slot_id, unsigned int ep_index)
3141 struct xhci_ep_ctx *ep_ctx;
3143 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3144 check_interval(xhci, urb, ep_ctx);
3146 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3150 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3151 * packets remaining in the TD (*not* including this TRB).
3153 * Total TD packet count = total_packet_count =
3154 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3156 * Packets transferred up to and including this TRB = packets_transferred =
3157 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3159 * TD size = total_packet_count - packets_transferred
3161 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3162 * including this TRB, right shifted by 10
3164 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3165 * This is taken care of in the TRB_TD_SIZE() macro
3167 * The last TRB in a TD must have the TD size set to zero.
3169 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3170 int trb_buff_len, unsigned int td_total_len,
3171 struct urb *urb, bool more_trbs_coming)
3173 u32 maxp, total_packet_count;
3175 /* MTK xHCI 0.96 contains some features from 1.0 */
3176 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3177 return ((td_total_len - transferred) >> 10);
3179 /* One TRB with a zero-length data packet. */
3180 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3181 trb_buff_len == td_total_len)
3184 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3185 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3188 maxp = usb_endpoint_maxp(&urb->ep->desc);
3189 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3191 /* Queueing functions don't count the current TRB into transferred */
3192 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3196 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3197 u32 *trb_buff_len, struct xhci_segment *seg)
3199 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3200 unsigned int unalign;
3201 unsigned int max_pkt;
3205 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3206 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3208 /* we got lucky, last normal TRB data on segment is packet aligned */
3212 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3213 unalign, *trb_buff_len);
3215 /* is the last nornal TRB alignable by splitting it */
3216 if (*trb_buff_len > unalign) {
3217 *trb_buff_len -= unalign;
3218 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3223 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3224 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3225 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3227 new_buff_len = max_pkt - (enqd_len % max_pkt);
3229 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3230 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3232 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3233 if (usb_urb_dir_out(urb)) {
3235 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3236 seg->bounce_buf, new_buff_len, enqd_len);
3237 if (len != new_buff_len)
3238 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3241 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3244 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3245 max_pkt, DMA_TO_DEVICE);
3247 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3248 max_pkt, DMA_FROM_DEVICE);
3251 if (dma_mapping_error(dev, seg->bounce_dma)) {
3252 /* try without aligning. Some host controllers survive */
3253 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3256 *trb_buff_len = new_buff_len;
3257 seg->bounce_len = new_buff_len;
3258 seg->bounce_offs = enqd_len;
3260 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3265 /* This is very similar to what ehci-q.c qtd_fill() does */
3266 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3267 struct urb *urb, int slot_id, unsigned int ep_index)
3269 struct xhci_ring *ring;
3270 struct urb_priv *urb_priv;
3272 struct xhci_generic_trb *start_trb;
3273 struct scatterlist *sg = NULL;
3274 bool more_trbs_coming = true;
3275 bool need_zero_pkt = false;
3276 bool first_trb = true;
3277 unsigned int num_trbs;
3278 unsigned int start_cycle, num_sgs = 0;
3279 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3281 u32 field, length_field, remainder;
3282 u64 addr, send_addr;
3284 ring = xhci_urb_to_transfer_ring(xhci, urb);
3288 full_len = urb->transfer_buffer_length;
3289 /* If we have scatter/gather list, we use it. */
3291 num_sgs = urb->num_mapped_sgs;
3293 addr = (u64) sg_dma_address(sg);
3294 block_len = sg_dma_len(sg);
3295 num_trbs = count_sg_trbs_needed(urb);
3297 num_trbs = count_trbs_needed(urb);
3298 addr = (u64) urb->transfer_dma;
3299 block_len = full_len;
3301 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3302 ep_index, urb->stream_id,
3303 num_trbs, urb, 0, mem_flags);
3304 if (unlikely(ret < 0))
3307 urb_priv = urb->hcpriv;
3309 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3310 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3311 need_zero_pkt = true;
3313 td = &urb_priv->td[0];
3316 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3317 * until we've finished creating all the other TRBs. The ring's cycle
3318 * state may change as we enqueue the other TRBs, so save it too.
3320 start_trb = &ring->enqueue->generic;
3321 start_cycle = ring->cycle_state;
3324 /* Queue the TRBs, even if they are zero-length */
3325 for (enqd_len = 0; first_trb || enqd_len < full_len;
3326 enqd_len += trb_buff_len) {
3327 field = TRB_TYPE(TRB_NORMAL);
3329 /* TRB buffer should not cross 64KB boundaries */
3330 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3331 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3333 if (enqd_len + trb_buff_len > full_len)
3334 trb_buff_len = full_len - enqd_len;
3336 /* Don't change the cycle bit of the first TRB until later */
3339 if (start_cycle == 0)
3342 field |= ring->cycle_state;
3344 /* Chain all the TRBs together; clear the chain bit in the last
3345 * TRB to indicate it's the last TRB in the chain.
3347 if (enqd_len + trb_buff_len < full_len) {
3349 if (trb_is_link(ring->enqueue + 1)) {
3350 if (xhci_align_td(xhci, urb, enqd_len,
3353 send_addr = ring->enq_seg->bounce_dma;
3354 /* assuming TD won't span 2 segs */
3355 td->bounce_seg = ring->enq_seg;
3359 if (enqd_len + trb_buff_len >= full_len) {
3360 field &= ~TRB_CHAIN;
3362 more_trbs_coming = false;
3363 td->last_trb = ring->enqueue;
3366 /* Only set interrupt on short packet for IN endpoints */
3367 if (usb_urb_dir_in(urb))
3370 /* Set the TRB length, TD size, and interrupter fields. */
3371 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3372 full_len, urb, more_trbs_coming);
3374 length_field = TRB_LEN(trb_buff_len) |
3375 TRB_TD_SIZE(remainder) |
3378 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3379 lower_32_bits(send_addr),
3380 upper_32_bits(send_addr),
3384 addr += trb_buff_len;
3385 sent_len = trb_buff_len;
3387 while (sg && sent_len >= block_len) {
3390 sent_len -= block_len;
3392 if (num_sgs != 0 && sg) {
3393 block_len = sg_dma_len(sg);
3394 addr = (u64) sg_dma_address(sg);
3398 block_len -= sent_len;
3402 if (need_zero_pkt) {
3403 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3404 ep_index, urb->stream_id,
3405 1, urb, 1, mem_flags);
3406 urb_priv->td[1].last_trb = ring->enqueue;
3407 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3408 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3411 check_trb_math(urb, enqd_len);
3412 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3413 start_cycle, start_trb);
3417 /* Caller must have locked xhci->lock */
3418 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3419 struct urb *urb, int slot_id, unsigned int ep_index)
3421 struct xhci_ring *ep_ring;
3424 struct usb_ctrlrequest *setup;
3425 struct xhci_generic_trb *start_trb;
3428 struct urb_priv *urb_priv;
3431 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3436 * Need to copy setup packet into setup TRB, so we can't use the setup
3439 if (!urb->setup_packet)
3442 /* 1 TRB for setup, 1 for status */
3445 * Don't need to check if we need additional event data and normal TRBs,
3446 * since data in control transfers will never get bigger than 16MB
3447 * XXX: can we get a buffer that crosses 64KB boundaries?
3449 if (urb->transfer_buffer_length > 0)
3451 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3452 ep_index, urb->stream_id,
3453 num_trbs, urb, 0, mem_flags);
3457 urb_priv = urb->hcpriv;
3458 td = &urb_priv->td[0];
3461 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3462 * until we've finished creating all the other TRBs. The ring's cycle
3463 * state may change as we enqueue the other TRBs, so save it too.
3465 start_trb = &ep_ring->enqueue->generic;
3466 start_cycle = ep_ring->cycle_state;
3468 /* Queue setup TRB - see section 6.4.1.2.1 */
3469 /* FIXME better way to translate setup_packet into two u32 fields? */
3470 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3472 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3473 if (start_cycle == 0)
3476 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3477 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3478 if (urb->transfer_buffer_length > 0) {
3479 if (setup->bRequestType & USB_DIR_IN)
3480 field |= TRB_TX_TYPE(TRB_DATA_IN);
3482 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3486 queue_trb(xhci, ep_ring, true,
3487 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3488 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3489 TRB_LEN(8) | TRB_INTR_TARGET(0),
3490 /* Immediate data in pointer */
3493 /* If there's data, queue data TRBs */
3494 /* Only set interrupt on short packet for IN endpoints */
3495 if (usb_urb_dir_in(urb))
3496 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3498 field = TRB_TYPE(TRB_DATA);
3500 if (urb->transfer_buffer_length > 0) {
3501 u32 length_field, remainder;
3503 remainder = xhci_td_remainder(xhci, 0,
3504 urb->transfer_buffer_length,
3505 urb->transfer_buffer_length,
3507 length_field = TRB_LEN(urb->transfer_buffer_length) |
3508 TRB_TD_SIZE(remainder) |
3510 if (setup->bRequestType & USB_DIR_IN)
3511 field |= TRB_DIR_IN;
3512 queue_trb(xhci, ep_ring, true,
3513 lower_32_bits(urb->transfer_dma),
3514 upper_32_bits(urb->transfer_dma),
3516 field | ep_ring->cycle_state);
3519 /* Save the DMA address of the last TRB in the TD */
3520 td->last_trb = ep_ring->enqueue;
3522 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3523 /* If the device sent data, the status stage is an OUT transfer */
3524 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3528 queue_trb(xhci, ep_ring, false,
3532 /* Event on completion */
3533 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3535 giveback_first_trb(xhci, slot_id, ep_index, 0,
3536 start_cycle, start_trb);
3541 * The transfer burst count field of the isochronous TRB defines the number of
3542 * bursts that are required to move all packets in this TD. Only SuperSpeed
3543 * devices can burst up to bMaxBurst number of packets per service interval.
3544 * This field is zero based, meaning a value of zero in the field means one
3545 * burst. Basically, for everything but SuperSpeed devices, this field will be
3546 * zero. Only xHCI 1.0 host controllers support this field.
3548 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3549 struct urb *urb, unsigned int total_packet_count)
3551 unsigned int max_burst;
3553 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3556 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3557 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3561 * Returns the number of packets in the last "burst" of packets. This field is
3562 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3563 * the last burst packet count is equal to the total number of packets in the
3564 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3565 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3566 * contain 1 to (bMaxBurst + 1) packets.
3568 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3569 struct urb *urb, unsigned int total_packet_count)
3571 unsigned int max_burst;
3572 unsigned int residue;
3574 if (xhci->hci_version < 0x100)
3577 if (urb->dev->speed >= USB_SPEED_SUPER) {
3578 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3579 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3580 residue = total_packet_count % (max_burst + 1);
3581 /* If residue is zero, the last burst contains (max_burst + 1)
3582 * number of packets, but the TLBPC field is zero-based.
3588 if (total_packet_count == 0)
3590 return total_packet_count - 1;
3594 * Calculates Frame ID field of the isochronous TRB identifies the
3595 * target frame that the Interval associated with this Isochronous
3596 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3598 * Returns actual frame id on success, negative value on error.
3600 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3601 struct urb *urb, int index)
3603 int start_frame, ist, ret = 0;
3604 int start_frame_id, end_frame_id, current_frame_id;
3606 if (urb->dev->speed == USB_SPEED_LOW ||
3607 urb->dev->speed == USB_SPEED_FULL)
3608 start_frame = urb->start_frame + index * urb->interval;
3610 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3612 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3614 * If bit [3] of IST is cleared to '0', software can add a TRB no
3615 * later than IST[2:0] Microframes before that TRB is scheduled to
3617 * If bit [3] of IST is set to '1', software can add a TRB no later
3618 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3620 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3621 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3624 /* Software shall not schedule an Isoch TD with a Frame ID value that
3625 * is less than the Start Frame ID or greater than the End Frame ID,
3628 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3629 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3631 * Both the End Frame ID and Start Frame ID values are calculated
3632 * in microframes. When software determines the valid Frame ID value;
3633 * The End Frame ID value should be rounded down to the nearest Frame
3634 * boundary, and the Start Frame ID value should be rounded up to the
3635 * nearest Frame boundary.
3637 current_frame_id = readl(&xhci->run_regs->microframe_index);
3638 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3639 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3641 start_frame &= 0x7ff;
3642 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3643 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3645 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3646 __func__, index, readl(&xhci->run_regs->microframe_index),
3647 start_frame_id, end_frame_id, start_frame);
3649 if (start_frame_id < end_frame_id) {
3650 if (start_frame > end_frame_id ||
3651 start_frame < start_frame_id)
3653 } else if (start_frame_id > end_frame_id) {
3654 if ((start_frame > end_frame_id &&
3655 start_frame < start_frame_id))
3662 if (ret == -EINVAL || start_frame == start_frame_id) {
3663 start_frame = start_frame_id + 1;
3664 if (urb->dev->speed == USB_SPEED_LOW ||
3665 urb->dev->speed == USB_SPEED_FULL)
3666 urb->start_frame = start_frame;
3668 urb->start_frame = start_frame << 3;
3674 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3675 start_frame, current_frame_id, index,
3676 start_frame_id, end_frame_id);
3677 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3684 /* This is for isoc transfer */
3685 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3686 struct urb *urb, int slot_id, unsigned int ep_index)
3688 struct xhci_ring *ep_ring;
3689 struct urb_priv *urb_priv;
3691 int num_tds, trbs_per_td;
3692 struct xhci_generic_trb *start_trb;
3695 u32 field, length_field;
3696 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3697 u64 start_addr, addr;
3699 bool more_trbs_coming;
3700 struct xhci_virt_ep *xep;
3703 xep = &xhci->devs[slot_id]->eps[ep_index];
3704 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3706 num_tds = urb->number_of_packets;
3708 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3711 start_addr = (u64) urb->transfer_dma;
3712 start_trb = &ep_ring->enqueue->generic;
3713 start_cycle = ep_ring->cycle_state;
3715 urb_priv = urb->hcpriv;
3716 /* Queue the TRBs for each TD, even if they are zero-length */
3717 for (i = 0; i < num_tds; i++) {
3718 unsigned int total_pkt_count, max_pkt;
3719 unsigned int burst_count, last_burst_pkt_count;
3724 addr = start_addr + urb->iso_frame_desc[i].offset;
3725 td_len = urb->iso_frame_desc[i].length;
3726 td_remain_len = td_len;
3727 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3728 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3730 /* A zero-length transfer still involves at least one packet. */
3731 if (total_pkt_count == 0)
3733 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3734 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3735 urb, total_pkt_count);
3737 trbs_per_td = count_isoc_trbs_needed(urb, i);
3739 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3740 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3746 td = &urb_priv->td[i];
3748 /* use SIA as default, if frame id is used overwrite it */
3749 sia_frame_id = TRB_SIA;
3750 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3751 HCC_CFC(xhci->hcc_params)) {
3752 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3754 sia_frame_id = TRB_FRAME_ID(frame_id);
3757 * Set isoc specific data for the first TRB in a TD.
3758 * Prevent HW from getting the TRBs by keeping the cycle state
3759 * inverted in the first TDs isoc TRB.
3761 field = TRB_TYPE(TRB_ISOC) |
3762 TRB_TLBPC(last_burst_pkt_count) |
3764 (i ? ep_ring->cycle_state : !start_cycle);
3766 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3767 if (!xep->use_extended_tbc)
3768 field |= TRB_TBC(burst_count);
3770 /* fill the rest of the TRB fields, and remaining normal TRBs */
3771 for (j = 0; j < trbs_per_td; j++) {
3774 /* only first TRB is isoc, overwrite otherwise */
3776 field = TRB_TYPE(TRB_NORMAL) |
3777 ep_ring->cycle_state;
3779 /* Only set interrupt on short packet for IN EPs */
3780 if (usb_urb_dir_in(urb))
3783 /* Set the chain bit for all except the last TRB */
3784 if (j < trbs_per_td - 1) {
3785 more_trbs_coming = true;
3788 more_trbs_coming = false;
3789 td->last_trb = ep_ring->enqueue;
3791 /* set BEI, except for the last TD */
3792 if (xhci->hci_version >= 0x100 &&
3793 !(xhci->quirks & XHCI_AVOID_BEI) &&
3797 /* Calculate TRB length */
3798 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3799 if (trb_buff_len > td_remain_len)
3800 trb_buff_len = td_remain_len;
3802 /* Set the TRB length, TD size, & interrupter fields. */
3803 remainder = xhci_td_remainder(xhci, running_total,
3804 trb_buff_len, td_len,
3805 urb, more_trbs_coming);
3807 length_field = TRB_LEN(trb_buff_len) |
3810 /* xhci 1.1 with ETE uses TD Size field for TBC */
3811 if (first_trb && xep->use_extended_tbc)
3812 length_field |= TRB_TD_SIZE_TBC(burst_count);
3814 length_field |= TRB_TD_SIZE(remainder);
3817 queue_trb(xhci, ep_ring, more_trbs_coming,
3818 lower_32_bits(addr),
3819 upper_32_bits(addr),
3822 running_total += trb_buff_len;
3824 addr += trb_buff_len;
3825 td_remain_len -= trb_buff_len;
3828 /* Check TD length */
3829 if (running_total != td_len) {
3830 xhci_err(xhci, "ISOC TD length unmatch\n");
3836 /* store the next frame id */
3837 if (HCC_CFC(xhci->hcc_params))
3838 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3840 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3841 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3842 usb_amd_quirk_pll_disable();
3844 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3846 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3847 start_cycle, start_trb);
3850 /* Clean up a partially enqueued isoc transfer. */
3852 for (i--; i >= 0; i--)
3853 list_del_init(&urb_priv->td[i].td_list);
3855 /* Use the first TD as a temporary variable to turn the TDs we've queued
3856 * into No-ops with a software-owned cycle bit. That way the hardware
3857 * won't accidentally start executing bogus TDs when we partially
3858 * overwrite them. td->first_trb and td->start_seg are already set.
3860 urb_priv->td[0].last_trb = ep_ring->enqueue;
3861 /* Every TRB except the first & last will have its cycle bit flipped. */
3862 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
3864 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3865 ep_ring->enqueue = urb_priv->td[0].first_trb;
3866 ep_ring->enq_seg = urb_priv->td[0].start_seg;
3867 ep_ring->cycle_state = start_cycle;
3868 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3869 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3874 * Check transfer ring to guarantee there is enough room for the urb.
3875 * Update ISO URB start_frame and interval.
3876 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3877 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3878 * Contiguous Frame ID is not supported by HC.
3880 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3881 struct urb *urb, int slot_id, unsigned int ep_index)
3883 struct xhci_virt_device *xdev;
3884 struct xhci_ring *ep_ring;
3885 struct xhci_ep_ctx *ep_ctx;
3887 int num_tds, num_trbs, i;
3889 struct xhci_virt_ep *xep;
3892 xdev = xhci->devs[slot_id];
3893 xep = &xhci->devs[slot_id]->eps[ep_index];
3894 ep_ring = xdev->eps[ep_index].ring;
3895 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3898 num_tds = urb->number_of_packets;
3899 for (i = 0; i < num_tds; i++)
3900 num_trbs += count_isoc_trbs_needed(urb, i);
3902 /* Check the ring to guarantee there is enough room for the whole urb.
3903 * Do not insert any td of the urb to the ring if the check failed.
3905 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3906 num_trbs, mem_flags);
3911 * Check interval value. This should be done before we start to
3912 * calculate the start frame value.
3914 check_interval(xhci, urb, ep_ctx);
3916 /* Calculate the start frame and put it in urb->start_frame. */
3917 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3918 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
3919 urb->start_frame = xep->next_frame_id;
3920 goto skip_start_over;
3924 start_frame = readl(&xhci->run_regs->microframe_index);
3925 start_frame &= 0x3fff;
3927 * Round up to the next frame and consider the time before trb really
3928 * gets scheduled by hardare.
3930 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3931 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3933 start_frame += ist + XHCI_CFC_DELAY;
3934 start_frame = roundup(start_frame, 8);
3937 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
3938 * is greate than 8 microframes.
3940 if (urb->dev->speed == USB_SPEED_LOW ||
3941 urb->dev->speed == USB_SPEED_FULL) {
3942 start_frame = roundup(start_frame, urb->interval << 3);
3943 urb->start_frame = start_frame >> 3;
3945 start_frame = roundup(start_frame, urb->interval);
3946 urb->start_frame = start_frame;
3950 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3952 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3955 /**** Command Ring Operations ****/
3957 /* Generic function for queueing a command TRB on the command ring.
3958 * Check to make sure there's room on the command ring for one command TRB.
3959 * Also check that there's room reserved for commands that must not fail.
3960 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3961 * then only check for the number of reserved spots.
3962 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3963 * because the command event handler may want to resubmit a failed command.
3965 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3966 u32 field1, u32 field2,
3967 u32 field3, u32 field4, bool command_must_succeed)
3969 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3972 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3973 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3974 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
3978 if (!command_must_succeed)
3981 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3982 reserved_trbs, GFP_ATOMIC);
3984 xhci_err(xhci, "ERR: No room for command on command ring\n");
3985 if (command_must_succeed)
3986 xhci_err(xhci, "ERR: Reserved TRB counting for "
3987 "unfailable commands failed.\n");
3991 cmd->command_trb = xhci->cmd_ring->enqueue;
3993 /* if there are no other commands queued we start the timeout timer */
3994 if (list_empty(&xhci->cmd_list)) {
3995 xhci->current_cmd = cmd;
3996 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
3999 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4001 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4002 field4 | xhci->cmd_ring->cycle_state);
4006 /* Queue a slot enable or disable request on the command ring */
4007 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4008 u32 trb_type, u32 slot_id)
4010 return queue_command(xhci, cmd, 0, 0, 0,
4011 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4014 /* Queue an address device command TRB */
4015 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4016 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4018 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4019 upper_32_bits(in_ctx_ptr), 0,
4020 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4021 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4024 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4025 u32 field1, u32 field2, u32 field3, u32 field4)
4027 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4030 /* Queue a reset device command TRB */
4031 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4034 return queue_command(xhci, cmd, 0, 0, 0,
4035 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4039 /* Queue a configure endpoint command TRB */
4040 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4041 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4042 u32 slot_id, bool command_must_succeed)
4044 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4045 upper_32_bits(in_ctx_ptr), 0,
4046 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4047 command_must_succeed);
4050 /* Queue an evaluate context command TRB */
4051 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4052 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4054 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4055 upper_32_bits(in_ctx_ptr), 0,
4056 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4057 command_must_succeed);
4061 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4062 * activity on an endpoint that is about to be suspended.
4064 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4065 int slot_id, unsigned int ep_index, int suspend)
4067 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4068 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4069 u32 type = TRB_TYPE(TRB_STOP_RING);
4070 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4072 return queue_command(xhci, cmd, 0, 0, 0,
4073 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4076 /* Set Transfer Ring Dequeue Pointer command */
4077 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4078 unsigned int slot_id, unsigned int ep_index,
4079 struct xhci_dequeue_state *deq_state)
4082 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4083 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4084 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4086 u32 type = TRB_TYPE(TRB_SET_DEQ);
4087 struct xhci_virt_ep *ep;
4088 struct xhci_command *cmd;
4091 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4092 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4093 deq_state->new_deq_seg,
4094 (unsigned long long)deq_state->new_deq_seg->dma,
4095 deq_state->new_deq_ptr,
4096 (unsigned long long)xhci_trb_virt_to_dma(
4097 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4098 deq_state->new_cycle_state);
4100 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4101 deq_state->new_deq_ptr);
4103 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4104 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4105 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4108 ep = &xhci->devs[slot_id]->eps[ep_index];
4109 if ((ep->ep_state & SET_DEQ_PENDING)) {
4110 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4111 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4115 /* This function gets called from contexts where it cannot sleep */
4116 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
4120 ep->queued_deq_seg = deq_state->new_deq_seg;
4121 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4122 if (deq_state->stream_id)
4123 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4124 ret = queue_command(xhci, cmd,
4125 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4126 upper_32_bits(addr), trb_stream_id,
4127 trb_slot_id | trb_ep_index | type, false);
4129 xhci_free_command(xhci, cmd);
4133 /* Stop the TD queueing code from ringing the doorbell until
4134 * this command completes. The HC won't set the dequeue pointer
4135 * if the ring is running, and ringing the doorbell starts the
4138 ep->ep_state |= SET_DEQ_PENDING;
4141 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4142 int slot_id, unsigned int ep_index,
4143 enum xhci_ep_reset_type reset_type)
4145 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4146 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4147 u32 type = TRB_TYPE(TRB_RESET_EP);
4149 if (reset_type == EP_SOFT_RESET)
4152 return queue_command(xhci, cmd, 0, 0, 0,
4153 trb_slot_id | trb_ep_index | type, false);