2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
69 #include <linux/dma-mapping.h>
71 #include "xhci-trace.h"
75 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
78 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
81 unsigned long segment_offset;
83 if (!seg || !trb || trb < seg->trbs)
86 segment_offset = trb - seg->trbs;
87 if (segment_offset >= TRBS_PER_SEGMENT)
89 return seg->dma + (segment_offset * sizeof(*trb));
92 static bool trb_is_noop(union xhci_trb *trb)
94 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
97 static bool trb_is_link(union xhci_trb *trb)
99 return TRB_TYPE_LINK_LE32(trb->link.control);
102 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
104 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
107 static bool last_trb_on_ring(struct xhci_ring *ring,
108 struct xhci_segment *seg, union xhci_trb *trb)
110 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
113 static bool link_trb_toggles_cycle(union xhci_trb *trb)
115 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
118 static bool last_td_in_urb(struct xhci_td *td)
120 struct urb_priv *urb_priv = td->urb->hcpriv;
122 return urb_priv->num_tds_done == urb_priv->num_tds;
125 static void inc_td_cnt(struct urb *urb)
127 struct urb_priv *urb_priv = urb->hcpriv;
129 urb_priv->num_tds_done++;
132 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
134 if (trb_is_link(trb)) {
135 /* unchain chained link TRBs */
136 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
138 trb->generic.field[0] = 0;
139 trb->generic.field[1] = 0;
140 trb->generic.field[2] = 0;
141 /* Preserve only the cycle bit of this TRB */
142 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
143 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
147 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
148 * TRB is in a new segment. This does not skip over link TRBs, and it does not
149 * effect the ring dequeue or enqueue pointers.
151 static void next_trb(struct xhci_hcd *xhci,
152 struct xhci_ring *ring,
153 struct xhci_segment **seg,
154 union xhci_trb **trb)
156 if (trb_is_link(*trb)) {
158 *trb = ((*seg)->trbs);
165 * See Cycle bit rules. SW is the consumer for the event ring only.
166 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
168 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
170 /* event ring doesn't have link trbs, check for last trb */
171 if (ring->type == TYPE_EVENT) {
172 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
176 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
177 ring->cycle_state ^= 1;
178 ring->deq_seg = ring->deq_seg->next;
179 ring->dequeue = ring->deq_seg->trbs;
183 /* All other rings have link trbs */
184 if (!trb_is_link(ring->dequeue)) {
186 ring->num_trbs_free++;
188 while (trb_is_link(ring->dequeue)) {
189 ring->deq_seg = ring->deq_seg->next;
190 ring->dequeue = ring->deq_seg->trbs;
193 trace_xhci_inc_deq(ring);
199 * See Cycle bit rules. SW is the consumer for the event ring only.
200 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
202 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
203 * chain bit is set), then set the chain bit in all the following link TRBs.
204 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
205 * have their chain bit cleared (so that each Link TRB is a separate TD).
207 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
208 * set, but other sections talk about dealing with the chain bit set. This was
209 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
210 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
212 * @more_trbs_coming: Will you enqueue more TRBs before calling
213 * prepare_transfer()?
215 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
216 bool more_trbs_coming)
219 union xhci_trb *next;
221 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
222 /* If this is not event ring, there is one less usable TRB */
223 if (!trb_is_link(ring->enqueue))
224 ring->num_trbs_free--;
225 next = ++(ring->enqueue);
227 /* Update the dequeue pointer further if that was a link TRB */
228 while (trb_is_link(next)) {
231 * If the caller doesn't plan on enqueueing more TDs before
232 * ringing the doorbell, then we don't want to give the link TRB
233 * to the hardware just yet. We'll give the link TRB back in
234 * prepare_ring() just before we enqueue the TD at the top of
237 if (!chain && !more_trbs_coming)
240 /* If we're not dealing with 0.95 hardware or isoc rings on
241 * AMD 0.96 host, carry over the chain bit of the previous TRB
242 * (which may mean the chain bit is cleared).
244 if (!(ring->type == TYPE_ISOC &&
245 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
246 !xhci_link_trb_quirk(xhci)) {
247 next->link.control &= cpu_to_le32(~TRB_CHAIN);
248 next->link.control |= cpu_to_le32(chain);
250 /* Give this link TRB to the hardware */
252 next->link.control ^= cpu_to_le32(TRB_CYCLE);
254 /* Toggle the cycle bit after the last ring segment. */
255 if (link_trb_toggles_cycle(next))
256 ring->cycle_state ^= 1;
258 ring->enq_seg = ring->enq_seg->next;
259 ring->enqueue = ring->enq_seg->trbs;
260 next = ring->enqueue;
263 trace_xhci_inc_enq(ring);
267 * Check to see if there's room to enqueue num_trbs on the ring and make sure
268 * enqueue pointer will not advance into dequeue segment. See rules above.
270 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
271 unsigned int num_trbs)
273 int num_trbs_in_deq_seg;
275 if (ring->num_trbs_free < num_trbs)
278 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
279 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
280 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
287 /* Ring the host controller doorbell after placing a command on the ring */
288 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
290 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
293 xhci_dbg(xhci, "// Ding dong!\n");
294 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
295 /* Flush PCI posted writes */
296 readl(&xhci->dba->doorbell[0]);
299 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
301 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
304 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
306 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
311 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
312 * If there are other commands waiting then restart the ring and kick the timer.
313 * This must be called with command ring stopped and xhci->lock held.
315 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
316 struct xhci_command *cur_cmd)
318 struct xhci_command *i_cmd;
320 /* Turn all aborted commands in list to no-ops, then restart */
321 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
323 if (i_cmd->status != COMP_COMMAND_ABORTED)
326 i_cmd->status = COMP_COMMAND_RING_STOPPED;
328 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
331 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
334 * caller waiting for completion is called when command
335 * completion event is received for these no-op commands
339 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
341 /* ring command ring doorbell to restart the command ring */
342 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
343 !(xhci->xhc_state & XHCI_STATE_DYING)) {
344 xhci->current_cmd = cur_cmd;
345 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
346 xhci_ring_cmd_db(xhci);
350 /* Must be called with xhci->lock held, releases and aquires lock back */
351 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
356 xhci_dbg(xhci, "Abort command ring\n");
358 reinit_completion(&xhci->cmd_ring_stop_completion);
361 * The control bits like command stop, abort are located in lower
362 * dword of the command ring control register. Limit the write
363 * to the lower dword to avoid corrupting the command ring pointer
364 * in case if the command ring is stopped by the time upper dword
367 temp_32 = readl(&xhci->op_regs->cmd_ring);
368 writel(temp_32 | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
370 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
371 * completion of the Command Abort operation. If CRR is not negated in 5
372 * seconds then driver handles it as if host died (-ENODEV).
373 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
374 * and try to recover a -ETIMEDOUT with a host controller reset.
376 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
377 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
379 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
385 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
386 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
387 * but the completion event in never sent. Wait 2 secs (arbitrary
388 * number) to handle those cases after negation of CMD_RING_RUNNING.
390 spin_unlock_irqrestore(&xhci->lock, flags);
391 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
392 msecs_to_jiffies(2000));
393 spin_lock_irqsave(&xhci->lock, flags);
395 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
396 xhci_cleanup_command_queue(xhci);
398 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
403 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
404 unsigned int slot_id,
405 unsigned int ep_index,
406 unsigned int stream_id)
408 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
409 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
410 unsigned int ep_state = ep->ep_state;
412 /* Don't ring the doorbell for this endpoint if there are pending
413 * cancellations because we don't want to interrupt processing.
414 * We don't want to restart any stream rings if there's a set dequeue
415 * pointer command pending because the device can choose to start any
416 * stream once the endpoint is on the HW schedule.
418 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
419 (ep_state & EP_HALTED))
421 writel(DB_VALUE(ep_index, stream_id), db_addr);
422 /* The CPU has better things to do at this point than wait for a
423 * write-posting flush. It'll get there soon enough.
427 /* Ring the doorbell for any rings with pending URBs */
428 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
429 unsigned int slot_id,
430 unsigned int ep_index)
432 unsigned int stream_id;
433 struct xhci_virt_ep *ep;
435 ep = &xhci->devs[slot_id]->eps[ep_index];
437 /* A ring has pending URBs if its TD list is not empty */
438 if (!(ep->ep_state & EP_HAS_STREAMS)) {
439 if (ep->ring && !(list_empty(&ep->ring->td_list)))
440 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
444 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
446 struct xhci_stream_info *stream_info = ep->stream_info;
447 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
448 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
453 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
454 unsigned int slot_id,
455 unsigned int ep_index)
457 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
458 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
461 if (ep_index >= EP_CTX_PER_DEV) {
462 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
465 if (!xhci->devs[slot_id]) {
466 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
470 return &xhci->devs[slot_id]->eps[ep_index];
473 /* Get the right ring for the given slot_id, ep_index and stream_id.
474 * If the endpoint supports streams, boundary check the URB's stream ID.
475 * If the endpoint doesn't support streams, return the singular endpoint ring.
477 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
478 unsigned int slot_id, unsigned int ep_index,
479 unsigned int stream_id)
481 struct xhci_virt_ep *ep;
483 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
487 /* Common case: no streams */
488 if (!(ep->ep_state & EP_HAS_STREAMS))
491 if (stream_id == 0) {
493 "WARN: Slot ID %u, ep index %u has streams, "
494 "but URB has no stream ID.\n",
499 if (stream_id < ep->stream_info->num_streams)
500 return ep->stream_info->stream_rings[stream_id];
503 "WARN: Slot ID %u, ep index %u has "
504 "stream IDs 1 to %u allocated, "
505 "but stream ID %u is requested.\n",
507 ep->stream_info->num_streams - 1,
514 * Get the hw dequeue pointer xHC stopped on, either directly from the
515 * endpoint context, or if streams are in use from the stream context.
516 * The returned hw_dequeue contains the lowest four bits with cycle state
517 * and possbile stream context type.
519 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
520 unsigned int ep_index, unsigned int stream_id)
522 struct xhci_ep_ctx *ep_ctx;
523 struct xhci_stream_ctx *st_ctx;
524 struct xhci_virt_ep *ep;
526 ep = &vdev->eps[ep_index];
528 if (ep->ep_state & EP_HAS_STREAMS) {
529 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
530 return le64_to_cpu(st_ctx->stream_ring);
532 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
533 return le64_to_cpu(ep_ctx->deq);
537 * Move the xHC's endpoint ring dequeue pointer past cur_td.
538 * Record the new state of the xHC's endpoint ring dequeue segment,
539 * dequeue pointer, stream id, and new consumer cycle state in state.
540 * Update our internal representation of the ring's dequeue pointer.
542 * We do this in three jumps:
543 * - First we update our new ring state to be the same as when the xHC stopped.
544 * - Then we traverse the ring to find the segment that contains
545 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
546 * any link TRBs with the toggle cycle bit set.
547 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
548 * if we've moved it past a link TRB with the toggle cycle bit set.
550 * Some of the uses of xhci_generic_trb are grotty, but if they're done
551 * with correct __le32 accesses they should work fine. Only users of this are
554 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
555 unsigned int slot_id, unsigned int ep_index,
556 unsigned int stream_id, struct xhci_td *cur_td,
557 struct xhci_dequeue_state *state)
559 struct xhci_virt_device *dev = xhci->devs[slot_id];
560 struct xhci_virt_ep *ep = &dev->eps[ep_index];
561 struct xhci_ring *ep_ring;
562 struct xhci_segment *new_seg;
563 union xhci_trb *new_deq;
566 bool cycle_found = false;
567 bool td_last_trb_found = false;
569 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
570 ep_index, stream_id);
572 xhci_warn(xhci, "WARN can't find new dequeue state "
573 "for invalid stream ID %u.\n",
577 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
578 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
579 "Finding endpoint context");
581 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
582 new_seg = ep_ring->deq_seg;
583 new_deq = ep_ring->dequeue;
584 state->new_cycle_state = hw_dequeue & 0x1;
585 state->stream_id = stream_id;
588 * We want to find the pointer, segment and cycle state of the new trb
589 * (the one after current TD's last_trb). We know the cycle state at
590 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
594 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
595 == (dma_addr_t)(hw_dequeue & ~0xf)) {
597 if (td_last_trb_found)
600 if (new_deq == cur_td->last_trb)
601 td_last_trb_found = true;
603 if (cycle_found && trb_is_link(new_deq) &&
604 link_trb_toggles_cycle(new_deq))
605 state->new_cycle_state ^= 0x1;
607 next_trb(xhci, ep_ring, &new_seg, &new_deq);
609 /* Search wrapped around, bail out */
610 if (new_deq == ep->ring->dequeue) {
611 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
612 state->new_deq_seg = NULL;
613 state->new_deq_ptr = NULL;
617 } while (!cycle_found || !td_last_trb_found);
619 state->new_deq_seg = new_seg;
620 state->new_deq_ptr = new_deq;
622 /* Don't update the ring cycle state for the producer (us). */
623 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
624 "Cycle state = 0x%x", state->new_cycle_state);
626 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
627 "New dequeue segment = %p (virtual)",
629 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
630 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
631 "New dequeue pointer = 0x%llx (DMA)",
632 (unsigned long long) addr);
635 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
636 * (The last TRB actually points to the ring enqueue pointer, which is not part
637 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
639 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
640 struct xhci_td *td, bool flip_cycle)
642 struct xhci_segment *seg = td->start_seg;
643 union xhci_trb *trb = td->first_trb;
646 trb_to_noop(trb, TRB_TR_NOOP);
648 /* flip cycle if asked to */
649 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
650 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
652 if (trb == td->last_trb)
655 next_trb(xhci, ep_ring, &seg, &trb);
659 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
660 struct xhci_virt_ep *ep)
662 ep->ep_state &= ~EP_STOP_CMD_PENDING;
663 /* Can't del_timer_sync in interrupt */
664 del_timer(&ep->stop_cmd_timer);
668 * Must be called with xhci->lock held in interrupt context,
669 * releases and re-acquires xhci->lock
671 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
672 struct xhci_td *cur_td, int status)
674 struct urb *urb = cur_td->urb;
675 struct urb_priv *urb_priv = urb->hcpriv;
676 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
678 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
679 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
680 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
681 if (xhci->quirks & XHCI_AMD_PLL_FIX)
682 usb_amd_quirk_pll_enable();
685 xhci_urb_free_priv(urb_priv);
686 usb_hcd_unlink_urb_from_ep(hcd, urb);
687 spin_unlock(&xhci->lock);
688 trace_xhci_urb_giveback(urb);
689 usb_hcd_giveback_urb(hcd, urb, status);
690 spin_lock(&xhci->lock);
693 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
694 struct xhci_ring *ring, struct xhci_td *td)
696 struct device *dev = xhci_to_hcd(xhci)->self.controller;
697 struct xhci_segment *seg = td->bounce_seg;
698 struct urb *urb = td->urb;
701 if (!ring || !seg || !urb)
704 if (usb_urb_dir_out(urb)) {
705 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
710 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
712 /* for in tranfers we need to copy the data from bounce to sg */
714 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
715 seg->bounce_len, seg->bounce_offs);
716 if (len != seg->bounce_len)
717 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
718 len, seg->bounce_len);
720 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
724 seg->bounce_offs = 0;
728 * When we get a command completion for a Stop Endpoint Command, we need to
729 * unlink any cancelled TDs from the ring. There are two ways to do that:
731 * 1. If the HW was in the middle of processing the TD that needs to be
732 * cancelled, then we must move the ring's dequeue pointer past the last TRB
733 * in the TD with a Set Dequeue Pointer Command.
734 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
735 * bit cleared) so that the HW will skip over them.
737 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
738 union xhci_trb *trb, struct xhci_event_cmd *event)
740 unsigned int ep_index;
741 struct xhci_ring *ep_ring;
742 struct xhci_virt_ep *ep;
743 struct xhci_td *cur_td = NULL;
744 struct xhci_td *last_unlinked_td;
745 struct xhci_ep_ctx *ep_ctx;
746 struct xhci_virt_device *vdev;
748 struct xhci_dequeue_state deq_state;
750 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
751 if (!xhci->devs[slot_id])
752 xhci_warn(xhci, "Stop endpoint command "
753 "completion for disabled slot %u\n",
758 memset(&deq_state, 0, sizeof(deq_state));
759 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
761 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
765 vdev = xhci->devs[slot_id];
766 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
767 trace_xhci_handle_cmd_stop_ep(ep_ctx);
769 last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
770 struct xhci_td, cancelled_td_list);
772 if (list_empty(&ep->cancelled_td_list)) {
773 xhci_stop_watchdog_timer_in_irq(xhci, ep);
774 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
778 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
779 * We have the xHCI lock, so nothing can modify this list until we drop
780 * it. We're also in the event handler, so we can't get re-interrupted
781 * if another Stop Endpoint command completes
783 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
784 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
785 "Removing canceled TD starting at 0x%llx (dma).",
786 (unsigned long long)xhci_trb_virt_to_dma(
787 cur_td->start_seg, cur_td->first_trb));
788 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
790 /* This shouldn't happen unless a driver is mucking
791 * with the stream ID after submission. This will
792 * leave the TD on the hardware ring, and the hardware
793 * will try to execute it, and may access a buffer
794 * that has already been freed. In the best case, the
795 * hardware will execute it, and the event handler will
796 * ignore the completion event for that TD, since it was
797 * removed from the td_list for that endpoint. In
798 * short, don't muck with the stream ID after
801 xhci_warn(xhci, "WARN Cancelled URB %p "
802 "has invalid stream ID %u.\n",
804 cur_td->urb->stream_id);
805 goto remove_finished_td;
808 * If we stopped on the TD we need to cancel, then we have to
809 * move the xHC endpoint ring dequeue pointer past this TD.
811 hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
812 cur_td->urb->stream_id);
815 if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
816 cur_td->last_trb, hw_deq, false)) {
817 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
818 cur_td->urb->stream_id,
821 td_to_noop(xhci, ep_ring, cur_td, false);
826 * The event handler won't see a completion for this TD anymore,
827 * so remove it from the endpoint ring's TD list. Keep it in
828 * the cancelled TD list for URB completion later.
830 list_del_init(&cur_td->td_list);
833 xhci_stop_watchdog_timer_in_irq(xhci, ep);
835 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
836 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
837 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
839 xhci_ring_cmd_db(xhci);
841 /* Otherwise ring the doorbell(s) to restart queued transfers */
842 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
846 * Drop the lock and complete the URBs in the cancelled TD list.
847 * New TDs to be cancelled might be added to the end of the list before
848 * we can complete all the URBs for the TDs we already unlinked.
849 * So stop when we've completed the URB for the last TD we unlinked.
852 cur_td = list_first_entry(&ep->cancelled_td_list,
853 struct xhci_td, cancelled_td_list);
854 list_del_init(&cur_td->cancelled_td_list);
856 /* Clean up the cancelled URB */
857 /* Doesn't matter what we pass for status, since the core will
858 * just overwrite it (because the URB has been unlinked).
860 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
861 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
862 inc_td_cnt(cur_td->urb);
863 if (last_td_in_urb(cur_td))
864 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
866 /* Stop processing the cancelled list if the watchdog timer is
869 if (xhci->xhc_state & XHCI_STATE_DYING)
871 } while (cur_td != last_unlinked_td);
873 /* Return to the event handler with xhci->lock re-acquired */
876 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
878 struct xhci_td *cur_td;
881 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
882 list_del_init(&cur_td->td_list);
884 if (!list_empty(&cur_td->cancelled_td_list))
885 list_del_init(&cur_td->cancelled_td_list);
887 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
889 inc_td_cnt(cur_td->urb);
890 if (last_td_in_urb(cur_td))
891 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
895 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
896 int slot_id, int ep_index)
898 struct xhci_td *cur_td;
900 struct xhci_virt_ep *ep;
901 struct xhci_ring *ring;
903 ep = &xhci->devs[slot_id]->eps[ep_index];
904 if ((ep->ep_state & EP_HAS_STREAMS) ||
905 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
908 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
910 ring = ep->stream_info->stream_rings[stream_id];
914 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
915 "Killing URBs for slot ID %u, ep index %u, stream %u",
916 slot_id, ep_index, stream_id);
917 xhci_kill_ring_urbs(xhci, ring);
923 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
924 "Killing URBs for slot ID %u, ep index %u",
926 xhci_kill_ring_urbs(xhci, ring);
929 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
931 list_del_init(&cur_td->cancelled_td_list);
932 inc_td_cnt(cur_td->urb);
934 if (last_td_in_urb(cur_td))
935 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
940 * host controller died, register read returns 0xffffffff
941 * Complete pending commands, mark them ABORTED.
942 * URBs need to be given back as usb core might be waiting with device locks
943 * held for the URBs to finish during device disconnect, blocking host remove.
945 * Call with xhci->lock held.
946 * lock is relased and re-acquired while giving back urb.
948 void xhci_hc_died(struct xhci_hcd *xhci)
952 if (xhci->xhc_state & XHCI_STATE_DYING)
955 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
956 xhci->xhc_state |= XHCI_STATE_DYING;
958 xhci_cleanup_command_queue(xhci);
960 /* return any pending urbs, remove may be waiting for them */
961 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
964 for (j = 0; j < 31; j++)
965 xhci_kill_endpoint_urbs(xhci, i, j);
968 /* inform usb core hc died if PCI remove isn't already handling it */
969 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
970 usb_hc_died(xhci_to_hcd(xhci));
973 /* Watchdog timer function for when a stop endpoint command fails to complete.
974 * In this case, we assume the host controller is broken or dying or dead. The
975 * host may still be completing some other events, so we have to be careful to
976 * let the event ring handler and the URB dequeueing/enqueueing functions know
977 * through xhci->state.
979 * The timer may also fire if the host takes a very long time to respond to the
980 * command, and the stop endpoint command completion handler cannot delete the
981 * timer before the timer function is called. Another endpoint cancellation may
982 * sneak in before the timer function can grab the lock, and that may queue
983 * another stop endpoint command and add the timer back. So we cannot use a
984 * simple flag to say whether there is a pending stop endpoint command for a
985 * particular endpoint.
987 * Instead we use a combination of that flag and checking if a new timer is
990 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
992 struct xhci_hcd *xhci;
993 struct xhci_virt_ep *ep;
996 ep = (struct xhci_virt_ep *) arg;
999 spin_lock_irqsave(&xhci->lock, flags);
1001 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
1002 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
1003 timer_pending(&ep->stop_cmd_timer)) {
1004 spin_unlock_irqrestore(&xhci->lock, flags);
1005 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
1009 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
1010 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1015 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
1016 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
1017 * and try to recover a -ETIMEDOUT with a host controller reset
1021 spin_unlock_irqrestore(&xhci->lock, flags);
1022 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1023 "xHCI host controller is dead.");
1026 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1027 struct xhci_virt_device *dev,
1028 struct xhci_ring *ep_ring,
1029 unsigned int ep_index)
1031 union xhci_trb *dequeue_temp;
1032 int num_trbs_free_temp;
1033 bool revert = false;
1035 num_trbs_free_temp = ep_ring->num_trbs_free;
1036 dequeue_temp = ep_ring->dequeue;
1038 /* If we get two back-to-back stalls, and the first stalled transfer
1039 * ends just before a link TRB, the dequeue pointer will be left on
1040 * the link TRB by the code in the while loop. So we have to update
1041 * the dequeue pointer one segment further, or we'll jump off
1042 * the segment into la-la-land.
1044 if (trb_is_link(ep_ring->dequeue)) {
1045 ep_ring->deq_seg = ep_ring->deq_seg->next;
1046 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1049 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1050 /* We have more usable TRBs */
1051 ep_ring->num_trbs_free++;
1053 if (trb_is_link(ep_ring->dequeue)) {
1054 if (ep_ring->dequeue ==
1055 dev->eps[ep_index].queued_deq_ptr)
1057 ep_ring->deq_seg = ep_ring->deq_seg->next;
1058 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1060 if (ep_ring->dequeue == dequeue_temp) {
1067 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1068 ep_ring->num_trbs_free = num_trbs_free_temp;
1073 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1074 * we need to clear the set deq pending flag in the endpoint ring state, so that
1075 * the TD queueing code can ring the doorbell again. We also need to ring the
1076 * endpoint doorbell to restart the ring, but only if there aren't more
1077 * cancellations pending.
1079 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1080 union xhci_trb *trb, u32 cmd_comp_code)
1082 unsigned int ep_index;
1083 unsigned int stream_id;
1084 struct xhci_ring *ep_ring;
1085 struct xhci_virt_device *dev;
1086 struct xhci_virt_ep *ep;
1087 struct xhci_ep_ctx *ep_ctx;
1088 struct xhci_slot_ctx *slot_ctx;
1090 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1091 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1092 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1096 dev = xhci->devs[slot_id];
1097 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1099 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1101 /* XXX: Harmless??? */
1105 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1106 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1107 trace_xhci_handle_cmd_set_deq(slot_ctx);
1108 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1110 if (cmd_comp_code != COMP_SUCCESS) {
1111 unsigned int ep_state;
1112 unsigned int slot_state;
1114 switch (cmd_comp_code) {
1115 case COMP_TRB_ERROR:
1116 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1118 case COMP_CONTEXT_STATE_ERROR:
1119 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1120 ep_state = GET_EP_CTX_STATE(ep_ctx);
1121 slot_state = le32_to_cpu(slot_ctx->dev_state);
1122 slot_state = GET_SLOT_STATE(slot_state);
1123 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1124 "Slot state = %u, EP state = %u",
1125 slot_state, ep_state);
1127 case COMP_SLOT_NOT_ENABLED_ERROR:
1128 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1132 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1136 /* OK what do we do now? The endpoint state is hosed, and we
1137 * should never get to this point if the synchronization between
1138 * queueing, and endpoint state are correct. This might happen
1139 * if the device gets disconnected after we've finished
1140 * cancelling URBs, which might not be an error...
1144 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1145 if (ep->ep_state & EP_HAS_STREAMS) {
1146 struct xhci_stream_ctx *ctx =
1147 &ep->stream_info->stream_ctx_array[stream_id];
1148 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1150 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1152 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1153 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1154 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1155 ep->queued_deq_ptr) == deq) {
1156 /* Update the ring's dequeue segment and dequeue pointer
1157 * to reflect the new position.
1159 update_ring_for_set_deq_completion(xhci, dev,
1162 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1163 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1164 ep->queued_deq_seg, ep->queued_deq_ptr);
1169 ep->ep_state &= ~SET_DEQ_PENDING;
1170 ep->queued_deq_seg = NULL;
1171 ep->queued_deq_ptr = NULL;
1172 /* Restart any rings with pending URBs */
1173 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1176 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1177 union xhci_trb *trb, u32 cmd_comp_code)
1179 struct xhci_virt_device *vdev;
1180 struct xhci_virt_ep *ep;
1181 struct xhci_ep_ctx *ep_ctx;
1182 unsigned int ep_index;
1184 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1185 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1189 vdev = xhci->devs[slot_id];
1190 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1191 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1193 /* This command will only fail if the endpoint wasn't halted,
1194 * but we don't care.
1196 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1197 "Ignoring reset ep completion code of %u", cmd_comp_code);
1199 /* HW with the reset endpoint quirk needs to have a configure endpoint
1200 * command complete before the endpoint can be used. Queue that here
1201 * because the HW can't handle two commands being queued in a row.
1203 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1204 struct xhci_command *command;
1206 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1210 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1211 "Queueing configure endpoint command");
1212 xhci_queue_configure_endpoint(xhci, command,
1213 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1215 xhci_ring_cmd_db(xhci);
1217 /* Clear our internal halted state */
1218 ep->ep_state &= ~EP_HALTED;
1222 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1223 struct xhci_command *command, u32 cmd_comp_code)
1225 if (cmd_comp_code == COMP_SUCCESS)
1226 command->slot_id = slot_id;
1228 command->slot_id = 0;
1231 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1233 struct xhci_virt_device *virt_dev;
1234 struct xhci_slot_ctx *slot_ctx;
1236 virt_dev = xhci->devs[slot_id];
1240 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1241 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1243 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1244 /* Delete default control endpoint resources */
1245 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1246 xhci_free_virt_device(xhci, slot_id);
1249 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1250 struct xhci_event_cmd *event, u32 cmd_comp_code)
1252 struct xhci_virt_device *virt_dev;
1253 struct xhci_input_control_ctx *ctrl_ctx;
1254 struct xhci_ep_ctx *ep_ctx;
1255 unsigned int ep_index;
1256 unsigned int ep_state;
1257 u32 add_flags, drop_flags;
1260 * Configure endpoint commands can come from the USB core
1261 * configuration or alt setting changes, or because the HW
1262 * needed an extra configure endpoint command after a reset
1263 * endpoint command or streams were being configured.
1264 * If the command was for a halted endpoint, the xHCI driver
1265 * is not waiting on the configure endpoint command.
1267 virt_dev = xhci->devs[slot_id];
1268 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1270 xhci_warn(xhci, "Could not get input context, bad type.\n");
1274 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1275 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1276 /* Input ctx add_flags are the endpoint index plus one */
1277 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1279 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1280 trace_xhci_handle_cmd_config_ep(ep_ctx);
1282 /* A usb_set_interface() call directly after clearing a halted
1283 * condition may race on this quirky hardware. Not worth
1284 * worrying about, since this is prototype hardware. Not sure
1285 * if this will work for streams, but streams support was
1286 * untested on this prototype.
1288 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1289 ep_index != (unsigned int) -1 &&
1290 add_flags - SLOT_FLAG == drop_flags) {
1291 ep_state = virt_dev->eps[ep_index].ep_state;
1292 if (!(ep_state & EP_HALTED))
1294 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1295 "Completed config ep cmd - "
1296 "last ep index = %d, state = %d",
1297 ep_index, ep_state);
1298 /* Clear internal halted state and restart ring(s) */
1299 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1300 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1306 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1308 struct xhci_virt_device *vdev;
1309 struct xhci_slot_ctx *slot_ctx;
1311 vdev = xhci->devs[slot_id];
1312 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1313 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1316 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1317 struct xhci_event_cmd *event)
1319 struct xhci_virt_device *vdev;
1320 struct xhci_slot_ctx *slot_ctx;
1322 vdev = xhci->devs[slot_id];
1323 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1324 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1326 xhci_dbg(xhci, "Completed reset device command.\n");
1327 if (!xhci->devs[slot_id])
1328 xhci_warn(xhci, "Reset device command completion "
1329 "for disabled slot %u\n", slot_id);
1332 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1333 struct xhci_event_cmd *event)
1335 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1336 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1339 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1340 "NEC firmware version %2x.%02x",
1341 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1342 NEC_FW_MINOR(le32_to_cpu(event->status)));
1345 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1347 list_del(&cmd->cmd_list);
1349 if (cmd->completion) {
1350 cmd->status = status;
1351 complete(cmd->completion);
1357 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1359 struct xhci_command *cur_cmd, *tmp_cmd;
1360 xhci->current_cmd = NULL;
1361 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1362 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1365 void xhci_handle_command_timeout(struct work_struct *work)
1367 struct xhci_hcd *xhci;
1368 unsigned long flags;
1371 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1373 spin_lock_irqsave(&xhci->lock, flags);
1376 * If timeout work is pending, or current_cmd is NULL, it means we
1377 * raced with command completion. Command is handled so just return.
1379 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1380 spin_unlock_irqrestore(&xhci->lock, flags);
1383 /* mark this command to be cancelled */
1384 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1386 /* Make sure command ring is running before aborting it */
1387 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1388 if (hw_ring_state == ~(u64)0) {
1390 goto time_out_completed;
1393 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1394 (hw_ring_state & CMD_RING_RUNNING)) {
1395 /* Prevent new doorbell, and start command abort */
1396 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1397 xhci_dbg(xhci, "Command timeout\n");
1398 xhci_abort_cmd_ring(xhci, flags);
1399 goto time_out_completed;
1402 /* host removed. Bail out */
1403 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1404 xhci_dbg(xhci, "host removed, ring start fail?\n");
1405 xhci_cleanup_command_queue(xhci);
1407 goto time_out_completed;
1410 /* command timeout on stopped ring, ring can't be aborted */
1411 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1412 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1415 spin_unlock_irqrestore(&xhci->lock, flags);
1419 static void handle_cmd_completion(struct xhci_hcd *xhci,
1420 struct xhci_event_cmd *event)
1422 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1424 dma_addr_t cmd_dequeue_dma;
1426 union xhci_trb *cmd_trb;
1427 struct xhci_command *cmd;
1430 cmd_dma = le64_to_cpu(event->cmd_trb);
1431 cmd_trb = xhci->cmd_ring->dequeue;
1433 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1435 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1438 * Check whether the completion event is for our internal kept
1441 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1443 "ERROR mismatched command completion event\n");
1447 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1449 cancel_delayed_work(&xhci->cmd_timer);
1451 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1453 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1454 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1455 complete_all(&xhci->cmd_ring_stop_completion);
1459 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1461 "Command completion event does not match command\n");
1466 * Host aborted the command ring, check if the current command was
1467 * supposed to be aborted, otherwise continue normally.
1468 * The command ring is stopped now, but the xHC will issue a Command
1469 * Ring Stopped event which will cause us to restart it.
1471 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1472 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1473 if (cmd->status == COMP_COMMAND_ABORTED) {
1474 if (xhci->current_cmd == cmd)
1475 xhci->current_cmd = NULL;
1480 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1482 case TRB_ENABLE_SLOT:
1483 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1485 case TRB_DISABLE_SLOT:
1486 xhci_handle_cmd_disable_slot(xhci, slot_id);
1489 if (!cmd->completion)
1490 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1493 case TRB_EVAL_CONTEXT:
1496 xhci_handle_cmd_addr_dev(xhci, slot_id);
1499 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1500 le32_to_cpu(cmd_trb->generic.field[3])));
1501 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1504 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1505 le32_to_cpu(cmd_trb->generic.field[3])));
1506 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1509 /* Is this an aborted command turned to NO-OP? */
1510 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1511 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1514 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1515 le32_to_cpu(cmd_trb->generic.field[3])));
1516 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1519 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1520 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1522 slot_id = TRB_TO_SLOT_ID(
1523 le32_to_cpu(cmd_trb->generic.field[3]));
1524 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1526 case TRB_NEC_GET_FW:
1527 xhci_handle_cmd_nec_get_fw(xhci, event);
1530 /* Skip over unknown commands on the event ring */
1531 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1535 /* restart timer if this wasn't the last command */
1536 if (!list_is_singular(&xhci->cmd_list)) {
1537 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1538 struct xhci_command, cmd_list);
1539 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1540 } else if (xhci->current_cmd == cmd) {
1541 xhci->current_cmd = NULL;
1545 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1547 inc_deq(xhci, xhci->cmd_ring);
1550 static void handle_vendor_event(struct xhci_hcd *xhci,
1551 union xhci_trb *event)
1555 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1556 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1557 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1558 handle_cmd_completion(xhci, &event->event_cmd);
1561 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1562 * port registers -- USB 3.0 and USB 2.0).
1564 * Returns a zero-based port number, which is suitable for indexing into each of
1565 * the split roothubs' port arrays and bus state arrays.
1566 * Add one to it in order to call xhci_find_slot_id_by_port.
1568 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1569 struct xhci_hcd *xhci, u32 port_id)
1572 unsigned int num_similar_speed_ports = 0;
1574 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1575 * and usb2_ports are 0-based indexes. Count the number of similar
1576 * speed ports, up to 1 port before this port.
1578 for (i = 0; i < (port_id - 1); i++) {
1579 u8 port_speed = xhci->port_array[i];
1582 * Skip ports that don't have known speeds, or have duplicate
1583 * Extended Capabilities port speed entries.
1585 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1589 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1590 * 1.1 ports are under the USB 2.0 hub. If the port speed
1591 * matches the device speed, it's a similar speed port.
1593 if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3))
1594 num_similar_speed_ports++;
1596 return num_similar_speed_ports;
1599 static void handle_device_notification(struct xhci_hcd *xhci,
1600 union xhci_trb *event)
1603 struct usb_device *udev;
1605 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1606 if (!xhci->devs[slot_id]) {
1607 xhci_warn(xhci, "Device Notification event for "
1608 "unused slot %u\n", slot_id);
1612 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1614 udev = xhci->devs[slot_id]->udev;
1615 if (udev && udev->parent)
1616 usb_wakeup_notification(udev->parent, udev->portnum);
1620 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1622 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1623 * If a connection to a USB 1 device is followed by another connection
1624 * to a USB 2 device.
1626 * Reset the PHY after the USB device is disconnected if device speed
1627 * is less than HCD_USB3.
1628 * Retry the reset sequence max of 4 times checking the PLL lock status.
1631 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1633 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1635 u32 retry_count = 4;
1638 /* Assert PHY reset */
1639 writel(0x6F, hcd->regs + 0x1048);
1641 /* De-assert the PHY reset */
1642 writel(0x7F, hcd->regs + 0x1048);
1644 pll_lock_check = readl(hcd->regs + 0x1070);
1645 } while (!(pll_lock_check & 0x1) && --retry_count);
1648 static void handle_port_status(struct xhci_hcd *xhci,
1649 union xhci_trb *event)
1651 struct usb_hcd *hcd;
1653 u32 portsc, cmd_reg;
1656 unsigned int faked_port_index;
1658 struct xhci_bus_state *bus_state;
1659 __le32 __iomem **port_array;
1660 bool bogus_port_status = false;
1662 /* Port status change events always have a successful completion code */
1663 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1665 "WARN: xHC returned failed port status event\n");
1667 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1668 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1670 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1671 if ((port_id <= 0) || (port_id > max_ports)) {
1672 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1673 inc_deq(xhci, xhci->event_ring);
1677 /* Figure out which usb_hcd this port is attached to:
1678 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1680 major_revision = xhci->port_array[port_id - 1];
1682 /* Find the right roothub. */
1683 hcd = xhci_to_hcd(xhci);
1684 if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3))
1685 hcd = xhci->shared_hcd;
1688 xhci_dbg(xhci, "No hcd found for port %u event\n", port_id);
1689 bogus_port_status = true;
1693 if (major_revision == 0) {
1694 xhci_warn(xhci, "Event for port %u not in "
1695 "Extended Capabilities, ignoring.\n",
1697 bogus_port_status = true;
1700 if (major_revision == DUPLICATE_ENTRY) {
1701 xhci_warn(xhci, "Event for port %u duplicated in"
1702 "Extended Capabilities, ignoring.\n",
1704 bogus_port_status = true;
1709 * Hardware port IDs reported by a Port Status Change Event include USB
1710 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1711 * resume event, but we first need to translate the hardware port ID
1712 * into the index into the ports on the correct split roothub, and the
1713 * correct bus_state structure.
1715 bus_state = &xhci->bus_state[hcd_index(hcd)];
1716 if (hcd->speed >= HCD_USB3)
1717 port_array = xhci->usb3_ports;
1719 port_array = xhci->usb2_ports;
1720 /* Find the faked port hub number */
1721 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1723 portsc = readl(port_array[faked_port_index]);
1725 trace_xhci_handle_port_status(faked_port_index, portsc);
1727 if (hcd->state == HC_STATE_SUSPENDED) {
1728 xhci_dbg(xhci, "resume root hub\n");
1729 usb_hcd_resume_root_hub(hcd);
1732 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1733 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1735 cmd_reg = readl(&xhci->op_regs->command);
1736 if (!(cmd_reg & CMD_RUN)) {
1737 xhci_warn(xhci, "xHC is not running.\n");
1741 if (DEV_SUPERSPEED_ANY(portsc)) {
1742 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1743 /* Set a flag to say the port signaled remote wakeup,
1744 * so we can tell the difference between the end of
1745 * device and host initiated resume.
1747 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1748 xhci_test_and_clear_bit(xhci, port_array,
1749 faked_port_index, PORT_PLC);
1750 usb_hcd_start_port_resume(&hcd->self, faked_port_index);
1751 xhci_set_link_state(xhci, port_array, faked_port_index,
1753 /* Need to wait until the next link state change
1754 * indicates the device is actually in U0.
1756 bogus_port_status = true;
1758 } else if (!test_bit(faked_port_index,
1759 &bus_state->resuming_ports)) {
1760 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1761 bus_state->resume_done[faked_port_index] = jiffies +
1762 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1763 set_bit(faked_port_index, &bus_state->resuming_ports);
1764 mod_timer(&hcd->rh_timer,
1765 bus_state->resume_done[faked_port_index]);
1766 /* Do the rest in GetPortStatus */
1770 if ((portsc & PORT_PLC) &&
1771 DEV_SUPERSPEED_ANY(portsc) &&
1772 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1773 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1774 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1775 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1776 /* We've just brought the device into U0/1/2 through either the
1777 * Resume state after a device remote wakeup, or through the
1778 * U3Exit state after a host-initiated resume. If it's a device
1779 * initiated remote wake, don't pass up the link state change,
1780 * so the roothub behavior is consistent with external
1781 * USB 3.0 hub behavior.
1783 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1784 faked_port_index + 1);
1785 if (slot_id && xhci->devs[slot_id])
1786 xhci_ring_device(xhci, slot_id);
1787 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1788 xhci_test_and_clear_bit(xhci, port_array,
1789 faked_port_index, PORT_PLC);
1790 usb_wakeup_notification(hcd->self.root_hub,
1791 faked_port_index + 1);
1792 bogus_port_status = true;
1798 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1799 * RExit to a disconnect state). If so, let the the driver know it's
1800 * out of the RExit state.
1802 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1803 test_and_clear_bit(faked_port_index,
1804 &bus_state->rexit_ports)) {
1805 complete(&bus_state->rexit_done[faked_port_index]);
1806 bogus_port_status = true;
1810 if (hcd->speed < HCD_USB3) {
1811 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1813 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1814 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1815 xhci_cavium_reset_phy_quirk(xhci);
1819 /* Update event ring dequeue pointer before dropping the lock */
1820 inc_deq(xhci, xhci->event_ring);
1822 /* Don't make the USB core poll the roothub if we got a bad port status
1823 * change event. Besides, at that point we can't tell which roothub
1824 * (USB 2.0 or USB 3.0) to kick.
1826 if (bogus_port_status)
1830 * xHCI port-status-change events occur when the "or" of all the
1831 * status-change bits in the portsc register changes from 0 to 1.
1832 * New status changes won't cause an event if any other change
1833 * bits are still set. When an event occurs, switch over to
1834 * polling to avoid losing status changes.
1836 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1837 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1838 spin_unlock(&xhci->lock);
1839 /* Pass this up to the core */
1840 usb_hcd_poll_rh_status(hcd);
1841 spin_lock(&xhci->lock);
1845 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1846 * at end_trb, which may be in another segment. If the suspect DMA address is a
1847 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1850 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1851 struct xhci_segment *start_seg,
1852 union xhci_trb *start_trb,
1853 union xhci_trb *end_trb,
1854 dma_addr_t suspect_dma,
1857 dma_addr_t start_dma;
1858 dma_addr_t end_seg_dma;
1859 dma_addr_t end_trb_dma;
1860 struct xhci_segment *cur_seg;
1862 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1863 cur_seg = start_seg;
1868 /* We may get an event for a Link TRB in the middle of a TD */
1869 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1870 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1871 /* If the end TRB isn't in this segment, this is set to 0 */
1872 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1876 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1877 (unsigned long long)suspect_dma,
1878 (unsigned long long)start_dma,
1879 (unsigned long long)end_trb_dma,
1880 (unsigned long long)cur_seg->dma,
1881 (unsigned long long)end_seg_dma);
1883 if (end_trb_dma > 0) {
1884 /* The end TRB is in this segment, so suspect should be here */
1885 if (start_dma <= end_trb_dma) {
1886 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1889 /* Case for one segment with
1890 * a TD wrapped around to the top
1892 if ((suspect_dma >= start_dma &&
1893 suspect_dma <= end_seg_dma) ||
1894 (suspect_dma >= cur_seg->dma &&
1895 suspect_dma <= end_trb_dma))
1900 /* Might still be somewhere in this segment */
1901 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1904 cur_seg = cur_seg->next;
1905 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1906 } while (cur_seg != start_seg);
1911 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1912 unsigned int slot_id, unsigned int ep_index,
1913 unsigned int stream_id,
1914 struct xhci_td *td, union xhci_trb *ep_trb,
1915 enum xhci_ep_reset_type reset_type)
1917 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1918 struct xhci_command *command;
1919 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1923 ep->ep_state |= EP_HALTED;
1925 xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
1927 if (reset_type == EP_HARD_RESET)
1928 xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td);
1930 xhci_ring_cmd_db(xhci);
1933 /* Check if an error has halted the endpoint ring. The class driver will
1934 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1935 * However, a babble and other errors also halt the endpoint ring, and the class
1936 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1937 * Ring Dequeue Pointer command manually.
1939 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1940 struct xhci_ep_ctx *ep_ctx,
1941 unsigned int trb_comp_code)
1943 /* TRB completion codes that may require a manual halt cleanup */
1944 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1945 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1946 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1947 /* The 0.95 spec says a babbling control endpoint
1948 * is not halted. The 0.96 spec says it is. Some HW
1949 * claims to be 0.95 compliant, but it halts the control
1950 * endpoint anyway. Check if a babble halted the
1953 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1959 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1961 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1962 /* Vendor defined "informational" completion code,
1963 * treat as not-an-error.
1965 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1967 xhci_dbg(xhci, "Treating code as success.\n");
1973 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1974 struct xhci_ring *ep_ring, int *status)
1976 struct urb_priv *urb_priv;
1977 struct urb *urb = NULL;
1979 /* Clean up the endpoint's TD list */
1981 urb_priv = urb->hcpriv;
1983 /* if a bounce buffer was used to align this td then unmap it */
1984 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1986 /* Do one last check of the actual transfer length.
1987 * If the host controller said we transferred more data than the buffer
1988 * length, urb->actual_length will be a very big number (since it's
1989 * unsigned). Play it safe and say we didn't transfer anything.
1991 if (urb->actual_length > urb->transfer_buffer_length) {
1992 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
1993 urb->transfer_buffer_length, urb->actual_length);
1994 urb->actual_length = 0;
1997 list_del_init(&td->td_list);
1998 /* Was this TD slated to be cancelled but completed anyway? */
1999 if (!list_empty(&td->cancelled_td_list))
2000 list_del_init(&td->cancelled_td_list);
2003 /* Giveback the urb when all the tds are completed */
2004 if (last_td_in_urb(td)) {
2005 if ((urb->actual_length != urb->transfer_buffer_length &&
2006 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
2007 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2008 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
2009 urb, urb->actual_length,
2010 urb->transfer_buffer_length, *status);
2012 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
2013 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2015 xhci_giveback_urb_in_irq(xhci, td, *status);
2021 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
2022 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2023 struct xhci_virt_ep *ep, int *status)
2025 struct xhci_virt_device *xdev;
2026 struct xhci_ep_ctx *ep_ctx;
2027 struct xhci_ring *ep_ring;
2028 unsigned int slot_id;
2032 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2033 xdev = xhci->devs[slot_id];
2034 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2035 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2036 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2037 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2039 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2040 trb_comp_code == COMP_STOPPED ||
2041 trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
2042 /* The Endpoint Stop Command completion will take care of any
2043 * stopped TDs. A stopped TD may be restarted, so don't update
2044 * the ring dequeue pointer or take this TD off any lists yet.
2048 if (trb_comp_code == COMP_STALL_ERROR ||
2049 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2051 /* Issue a reset endpoint command to clear the host side
2052 * halt, followed by a set dequeue command to move the
2053 * dequeue pointer past the TD.
2054 * The class driver clears the device side halt later.
2056 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
2057 ep_ring->stream_id, td, ep_trb,
2060 /* Update ring dequeue pointer */
2061 while (ep_ring->dequeue != td->last_trb)
2062 inc_deq(xhci, ep_ring);
2063 inc_deq(xhci, ep_ring);
2066 return xhci_td_cleanup(xhci, td, ep_ring, status);
2069 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2070 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2071 union xhci_trb *stop_trb)
2074 union xhci_trb *trb = ring->dequeue;
2075 struct xhci_segment *seg = ring->deq_seg;
2077 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2078 if (!trb_is_noop(trb) && !trb_is_link(trb))
2079 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2085 * Process control tds, update urb status and actual_length.
2087 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2088 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2089 struct xhci_virt_ep *ep, int *status)
2091 struct xhci_virt_device *xdev;
2092 struct xhci_ring *ep_ring;
2093 unsigned int slot_id;
2095 struct xhci_ep_ctx *ep_ctx;
2097 u32 remaining, requested;
2100 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2101 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2102 xdev = xhci->devs[slot_id];
2103 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2104 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2105 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2106 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2107 requested = td->urb->transfer_buffer_length;
2108 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2110 switch (trb_comp_code) {
2112 if (trb_type != TRB_STATUS) {
2113 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2114 (trb_type == TRB_DATA) ? "data" : "setup");
2115 *status = -ESHUTDOWN;
2120 case COMP_SHORT_PACKET:
2123 case COMP_STOPPED_SHORT_PACKET:
2124 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2125 td->urb->actual_length = remaining;
2127 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2132 td->urb->actual_length = 0;
2136 td->urb->actual_length = requested - remaining;
2139 td->urb->actual_length = requested;
2142 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2146 case COMP_STOPPED_LENGTH_INVALID:
2149 if (!xhci_requires_manual_halt_cleanup(xhci,
2150 ep_ctx, trb_comp_code))
2152 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2153 trb_comp_code, ep_index);
2154 /* else fall through */
2155 case COMP_STALL_ERROR:
2156 /* Did we transfer part of the data (middle) phase? */
2157 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2158 td->urb->actual_length = requested - remaining;
2159 else if (!td->urb_length_set)
2160 td->urb->actual_length = 0;
2164 /* stopped at setup stage, no data transferred */
2165 if (trb_type == TRB_SETUP)
2169 * if on data stage then update the actual_length of the URB and flag it
2170 * as set, so it won't be overwritten in the event for the last TRB.
2172 if (trb_type == TRB_DATA ||
2173 trb_type == TRB_NORMAL) {
2174 td->urb_length_set = true;
2175 td->urb->actual_length = requested - remaining;
2176 xhci_dbg(xhci, "Waiting for status stage event\n");
2180 /* at status stage */
2181 if (!td->urb_length_set)
2182 td->urb->actual_length = requested;
2185 return finish_td(xhci, td, ep_trb, event, ep, status);
2189 * Process isochronous tds, update urb packet status and actual_length.
2191 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2192 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2193 struct xhci_virt_ep *ep, int *status)
2195 struct xhci_ring *ep_ring;
2196 struct urb_priv *urb_priv;
2198 struct usb_iso_packet_descriptor *frame;
2200 bool sum_trbs_for_length = false;
2201 u32 remaining, requested, ep_trb_len;
2202 int short_framestatus;
2204 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2205 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2206 urb_priv = td->urb->hcpriv;
2207 idx = urb_priv->num_tds_done;
2208 frame = &td->urb->iso_frame_desc[idx];
2209 requested = frame->length;
2210 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2211 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2212 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2215 /* handle completion code */
2216 switch (trb_comp_code) {
2219 frame->status = short_framestatus;
2220 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2221 sum_trbs_for_length = true;
2226 case COMP_SHORT_PACKET:
2227 frame->status = short_framestatus;
2228 sum_trbs_for_length = true;
2230 case COMP_BANDWIDTH_OVERRUN_ERROR:
2231 frame->status = -ECOMM;
2233 case COMP_ISOCH_BUFFER_OVERRUN:
2234 case COMP_BABBLE_DETECTED_ERROR:
2235 frame->status = -EOVERFLOW;
2237 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2238 case COMP_STALL_ERROR:
2239 frame->status = -EPROTO;
2241 case COMP_USB_TRANSACTION_ERROR:
2242 frame->status = -EPROTO;
2243 if (ep_trb != td->last_trb)
2247 sum_trbs_for_length = true;
2249 case COMP_STOPPED_SHORT_PACKET:
2250 /* field normally containing residue now contains tranferred */
2251 frame->status = short_framestatus;
2252 requested = remaining;
2254 case COMP_STOPPED_LENGTH_INVALID:
2259 sum_trbs_for_length = true;
2264 if (sum_trbs_for_length)
2265 frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2266 ep_trb_len - remaining;
2268 frame->actual_length = requested;
2270 td->urb->actual_length += frame->actual_length;
2272 return finish_td(xhci, td, ep_trb, event, ep, status);
2275 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2276 struct xhci_transfer_event *event,
2277 struct xhci_virt_ep *ep, int *status)
2279 struct xhci_ring *ep_ring;
2280 struct urb_priv *urb_priv;
2281 struct usb_iso_packet_descriptor *frame;
2284 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2285 urb_priv = td->urb->hcpriv;
2286 idx = urb_priv->num_tds_done;
2287 frame = &td->urb->iso_frame_desc[idx];
2289 /* The transfer is partly done. */
2290 frame->status = -EXDEV;
2292 /* calc actual length */
2293 frame->actual_length = 0;
2295 /* Update ring dequeue pointer */
2296 while (ep_ring->dequeue != td->last_trb)
2297 inc_deq(xhci, ep_ring);
2298 inc_deq(xhci, ep_ring);
2300 return xhci_td_cleanup(xhci, td, ep_ring, status);
2304 * Process bulk and interrupt tds, update urb status and actual_length.
2306 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2307 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2308 struct xhci_virt_ep *ep, int *status)
2310 struct xhci_ring *ep_ring;
2312 u32 remaining, requested, ep_trb_len;
2314 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2315 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2316 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2317 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2318 requested = td->urb->transfer_buffer_length;
2320 switch (trb_comp_code) {
2322 /* handle success with untransferred data as short packet */
2323 if (ep_trb != td->last_trb || remaining) {
2324 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2325 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2326 td->urb->ep->desc.bEndpointAddress,
2327 requested, remaining);
2331 case COMP_SHORT_PACKET:
2332 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2333 td->urb->ep->desc.bEndpointAddress,
2334 requested, remaining);
2337 case COMP_STOPPED_SHORT_PACKET:
2338 td->urb->actual_length = remaining;
2340 case COMP_STOPPED_LENGTH_INVALID:
2341 /* stopped on ep trb with invalid length, exclude it */
2350 if (ep_trb == td->last_trb)
2351 td->urb->actual_length = requested - remaining;
2353 td->urb->actual_length =
2354 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2355 ep_trb_len - remaining;
2357 if (remaining > requested) {
2358 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2360 td->urb->actual_length = 0;
2362 return finish_td(xhci, td, ep_trb, event, ep, status);
2366 * If this function returns an error condition, it means it got a Transfer
2367 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2368 * At this point, the host controller is probably hosed and should be reset.
2370 static int handle_tx_event(struct xhci_hcd *xhci,
2371 struct xhci_transfer_event *event)
2373 struct xhci_virt_device *xdev;
2374 struct xhci_virt_ep *ep;
2375 struct xhci_ring *ep_ring;
2376 unsigned int slot_id;
2378 struct xhci_td *td = NULL;
2379 dma_addr_t ep_trb_dma;
2380 struct xhci_segment *ep_seg;
2381 union xhci_trb *ep_trb;
2382 int status = -EINPROGRESS;
2383 struct xhci_ep_ctx *ep_ctx;
2384 struct list_head *tmp;
2387 bool handling_skipped_tds = false;
2389 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2390 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2391 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2392 ep_trb_dma = le64_to_cpu(event->buffer);
2394 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2396 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2400 xdev = xhci->devs[slot_id];
2401 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2402 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2404 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2406 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2411 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2413 switch (trb_comp_code) {
2414 case COMP_STALL_ERROR:
2415 case COMP_USB_TRANSACTION_ERROR:
2416 case COMP_INVALID_STREAM_TYPE_ERROR:
2417 case COMP_INVALID_STREAM_ID_ERROR:
2418 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
2419 NULL, NULL, EP_SOFT_RESET);
2421 case COMP_RING_UNDERRUN:
2422 case COMP_RING_OVERRUN:
2423 case COMP_STOPPED_LENGTH_INVALID:
2426 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2432 /* Count current td numbers if ep->skip is set */
2434 list_for_each(tmp, &ep_ring->td_list)
2438 /* Look for common error cases */
2439 switch (trb_comp_code) {
2440 /* Skip codes that require special handling depending on
2444 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2446 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2447 ep_ring->last_td_was_short)
2448 trb_comp_code = COMP_SHORT_PACKET;
2450 xhci_warn_ratelimited(xhci,
2451 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2453 case COMP_SHORT_PACKET:
2455 /* Completion codes for endpoint stopped state */
2457 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2460 case COMP_STOPPED_LENGTH_INVALID:
2462 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2465 case COMP_STOPPED_SHORT_PACKET:
2467 "Stopped with short packet transfer detected for slot %u ep %u\n",
2470 /* Completion codes for endpoint halted state */
2471 case COMP_STALL_ERROR:
2472 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2474 ep->ep_state |= EP_HALTED;
2477 case COMP_SPLIT_TRANSACTION_ERROR:
2478 case COMP_USB_TRANSACTION_ERROR:
2479 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2483 case COMP_BABBLE_DETECTED_ERROR:
2484 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2486 status = -EOVERFLOW;
2488 /* Completion codes for endpoint error state */
2489 case COMP_TRB_ERROR:
2491 "WARN: TRB error for slot %u ep %u on endpoint\n",
2495 /* completion codes not indicating endpoint state change */
2496 case COMP_DATA_BUFFER_ERROR:
2498 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2502 case COMP_BANDWIDTH_OVERRUN_ERROR:
2504 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2507 case COMP_ISOCH_BUFFER_OVERRUN:
2509 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2512 case COMP_RING_UNDERRUN:
2514 * When the Isoch ring is empty, the xHC will generate
2515 * a Ring Overrun Event for IN Isoch endpoint or Ring
2516 * Underrun Event for OUT Isoch endpoint.
2518 xhci_dbg(xhci, "underrun event on endpoint\n");
2519 if (!list_empty(&ep_ring->td_list))
2520 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2521 "still with TDs queued?\n",
2522 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2525 case COMP_RING_OVERRUN:
2526 xhci_dbg(xhci, "overrun event on endpoint\n");
2527 if (!list_empty(&ep_ring->td_list))
2528 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2529 "still with TDs queued?\n",
2530 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2533 case COMP_MISSED_SERVICE_ERROR:
2535 * When encounter missed service error, one or more isoc tds
2536 * may be missed by xHC.
2537 * Set skip flag of the ep_ring; Complete the missed tds as
2538 * short transfer when process the ep_ring next time.
2542 "Miss service interval error for slot %u ep %u, set skip flag\n",
2545 case COMP_NO_PING_RESPONSE_ERROR:
2548 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2552 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2553 /* needs disable slot command to recover */
2555 "WARN: detect an incompatible device for slot %u ep %u",
2560 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2565 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2566 trb_comp_code, slot_id, ep_index);
2571 /* This TRB should be in the TD at the head of this ring's
2574 if (list_empty(&ep_ring->td_list)) {
2576 * Don't print wanings if it's due to a stopped endpoint
2577 * generating an extra completion event if the device
2578 * was suspended. Or, a event for the last TRB of a
2579 * short TD we already got a short event for.
2580 * The short TD is already removed from the TD list.
2583 if (!(trb_comp_code == COMP_STOPPED ||
2584 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2585 ep_ring->last_td_was_short)) {
2586 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2587 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2592 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2598 /* We've skipped all the TDs on the ep ring when ep->skip set */
2599 if (ep->skip && td_num == 0) {
2601 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2606 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2611 /* Is this a TRB in the currently executing TD? */
2612 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2613 td->last_trb, ep_trb_dma, false);
2616 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2617 * is not in the current TD pointed by ep_ring->dequeue because
2618 * that the hardware dequeue pointer still at the previous TRB
2619 * of the current TD. The previous TRB maybe a Link TD or the
2620 * last TRB of the previous TD. The command completion handle
2621 * will take care the rest.
2623 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2624 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2630 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2631 /* Some host controllers give a spurious
2632 * successful event after a short transfer.
2635 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2636 ep_ring->last_td_was_short) {
2637 ep_ring->last_td_was_short = false;
2640 /* HC is busted, give up! */
2642 "ERROR Transfer event TRB DMA ptr not "
2643 "part of current TD ep_index %d "
2644 "comp_code %u\n", ep_index,
2646 trb_in_td(xhci, ep_ring->deq_seg,
2647 ep_ring->dequeue, td->last_trb,
2652 skip_isoc_td(xhci, td, event, ep, &status);
2655 if (trb_comp_code == COMP_SHORT_PACKET)
2656 ep_ring->last_td_was_short = true;
2658 ep_ring->last_td_was_short = false;
2662 "Found td. Clear skip flag for slot %u ep %u.\n",
2667 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2670 trace_xhci_handle_transfer(ep_ring,
2671 (struct xhci_generic_trb *) ep_trb);
2674 * No-op TRB could trigger interrupts in a case where
2675 * a URB was killed and a STALL_ERROR happens right
2676 * after the endpoint ring stopped. Reset the halted
2677 * endpoint. Otherwise, the endpoint remains stalled
2680 if (trb_is_noop(ep_trb)) {
2681 if (trb_comp_code == COMP_STALL_ERROR ||
2682 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2684 xhci_cleanup_halted_endpoint(xhci, slot_id,
2692 /* update the urb's actual_length and give back to the core */
2693 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2694 process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2695 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2696 process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2698 process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2701 handling_skipped_tds = ep->skip &&
2702 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2703 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2706 * Do not update event ring dequeue pointer if we're in a loop
2707 * processing missed tds.
2709 if (!handling_skipped_tds)
2710 inc_deq(xhci, xhci->event_ring);
2713 * If ep->skip is set, it means there are missed tds on the
2714 * endpoint ring need to take care of.
2715 * Process them as short transfer until reach the td pointed by
2718 } while (handling_skipped_tds);
2723 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2724 (unsigned long long) xhci_trb_virt_to_dma(
2725 xhci->event_ring->deq_seg,
2726 xhci->event_ring->dequeue),
2727 lower_32_bits(le64_to_cpu(event->buffer)),
2728 upper_32_bits(le64_to_cpu(event->buffer)),
2729 le32_to_cpu(event->transfer_len),
2730 le32_to_cpu(event->flags));
2735 * This function handles all OS-owned events on the event ring. It may drop
2736 * xhci->lock between event processing (e.g. to pass up port status changes).
2737 * Returns >0 for "possibly more events to process" (caller should call again),
2738 * otherwise 0 if done. In future, <0 returns should indicate error code.
2740 static int xhci_handle_event(struct xhci_hcd *xhci)
2742 union xhci_trb *event;
2743 int update_ptrs = 1;
2746 /* Event ring hasn't been allocated yet. */
2747 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2748 xhci_err(xhci, "ERROR event ring not ready\n");
2752 event = xhci->event_ring->dequeue;
2753 /* Does the HC or OS own the TRB? */
2754 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2755 xhci->event_ring->cycle_state)
2758 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2761 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2762 * speculative reads of the event's flags/data below.
2765 /* FIXME: Handle more event types. */
2766 switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2767 case TRB_TYPE(TRB_COMPLETION):
2768 handle_cmd_completion(xhci, &event->event_cmd);
2770 case TRB_TYPE(TRB_PORT_STATUS):
2771 handle_port_status(xhci, event);
2774 case TRB_TYPE(TRB_TRANSFER):
2775 ret = handle_tx_event(xhci, &event->trans_event);
2779 case TRB_TYPE(TRB_DEV_NOTE):
2780 handle_device_notification(xhci, event);
2783 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2785 handle_vendor_event(xhci, event);
2787 xhci_warn(xhci, "ERROR unknown event type %d\n",
2789 le32_to_cpu(event->event_cmd.flags)));
2791 /* Any of the above functions may drop and re-acquire the lock, so check
2792 * to make sure a watchdog timer didn't mark the host as non-responsive.
2794 if (xhci->xhc_state & XHCI_STATE_DYING) {
2795 xhci_dbg(xhci, "xHCI host dying, returning from "
2796 "event handler.\n");
2801 /* Update SW event ring dequeue pointer */
2802 inc_deq(xhci, xhci->event_ring);
2804 /* Are there more items on the event ring? Caller will call us again to
2811 * Update Event Ring Dequeue Pointer:
2812 * - When all events have finished
2813 * - To avoid "Event Ring Full Error" condition
2815 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2816 union xhci_trb *event_ring_deq)
2821 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2822 /* If necessary, update the HW's version of the event ring deq ptr. */
2823 if (event_ring_deq != xhci->event_ring->dequeue) {
2824 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2825 xhci->event_ring->dequeue);
2827 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
2829 * Per 4.9.4, Software writes to the ERDP register shall
2830 * always advance the Event Ring Dequeue Pointer value.
2832 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
2833 ((u64) deq & (u64) ~ERST_PTR_MASK))
2836 /* Update HC event ring dequeue pointer */
2837 temp_64 &= ERST_PTR_MASK;
2838 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2841 /* Clear the event handler busy flag (RW1C) */
2842 temp_64 |= ERST_EHB;
2843 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2847 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2848 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2849 * indicators of an event TRB error, but we check the status *first* to be safe.
2851 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2853 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2854 union xhci_trb *event_ring_deq;
2855 irqreturn_t ret = IRQ_NONE;
2856 unsigned long flags;
2861 spin_lock_irqsave(&xhci->lock, flags);
2862 /* Check if the xHC generated the interrupt, or the irq is shared */
2863 status = readl(&xhci->op_regs->status);
2864 if (status == ~(u32)0) {
2870 if (!(status & STS_EINT))
2873 if (status & STS_FATAL) {
2874 xhci_warn(xhci, "WARNING: Host System Error\n");
2881 * Clear the op reg interrupt status first,
2882 * so we can receive interrupts from other MSI-X interrupters.
2883 * Write 1 to clear the interrupt status.
2886 writel(status, &xhci->op_regs->status);
2888 if (!hcd->msi_enabled) {
2890 irq_pending = readl(&xhci->ir_set->irq_pending);
2891 irq_pending |= IMAN_IP;
2892 writel(irq_pending, &xhci->ir_set->irq_pending);
2895 if (xhci->xhc_state & XHCI_STATE_DYING ||
2896 xhci->xhc_state & XHCI_STATE_HALTED) {
2897 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2898 "Shouldn't IRQs be disabled?\n");
2899 /* Clear the event handler busy flag (RW1C);
2900 * the event ring should be empty.
2902 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2903 xhci_write_64(xhci, temp_64 | ERST_EHB,
2904 &xhci->ir_set->erst_dequeue);
2909 event_ring_deq = xhci->event_ring->dequeue;
2910 /* FIXME this should be a delayed service routine
2911 * that clears the EHB.
2913 while (xhci_handle_event(xhci) > 0) {
2914 if (event_loop++ < TRBS_PER_SEGMENT / 2)
2916 xhci_update_erst_dequeue(xhci, event_ring_deq);
2920 xhci_update_erst_dequeue(xhci, event_ring_deq);
2924 spin_unlock_irqrestore(&xhci->lock, flags);
2929 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2931 return xhci_irq(hcd);
2934 /**** Endpoint Ring Operations ****/
2937 * Generic function for queueing a TRB on a ring.
2938 * The caller must have checked to make sure there's room on the ring.
2940 * @more_trbs_coming: Will you enqueue more TRBs before calling
2941 * prepare_transfer()?
2943 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2944 bool more_trbs_coming,
2945 u32 field1, u32 field2, u32 field3, u32 field4)
2947 struct xhci_generic_trb *trb;
2949 trb = &ring->enqueue->generic;
2950 trb->field[0] = cpu_to_le32(field1);
2951 trb->field[1] = cpu_to_le32(field2);
2952 trb->field[2] = cpu_to_le32(field3);
2953 /* make sure TRB is fully written before giving it to the controller */
2955 trb->field[3] = cpu_to_le32(field4);
2957 trace_xhci_queue_trb(ring, trb);
2959 inc_enq(xhci, ring, more_trbs_coming);
2963 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2964 * FIXME allocate segments if the ring is full.
2966 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2967 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2969 unsigned int num_trbs_needed;
2971 /* Make sure the endpoint has been added to xHC schedule */
2973 case EP_STATE_DISABLED:
2975 * USB core changed config/interfaces without notifying us,
2976 * or hardware is reporting the wrong state.
2978 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2980 case EP_STATE_ERROR:
2981 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2982 /* FIXME event handling code for error needs to clear it */
2983 /* XXX not sure if this should be -ENOENT or not */
2985 case EP_STATE_HALTED:
2986 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2987 case EP_STATE_STOPPED:
2988 case EP_STATE_RUNNING:
2991 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2993 * FIXME issue Configure Endpoint command to try to get the HC
2994 * back into a known state.
3000 if (room_on_ring(xhci, ep_ring, num_trbs))
3003 if (ep_ring == xhci->cmd_ring) {
3004 xhci_err(xhci, "Do not support expand command ring\n");
3008 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3009 "ERROR no room on ep ring, try ring expansion");
3010 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3011 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3013 xhci_err(xhci, "Ring expansion failed\n");
3018 while (trb_is_link(ep_ring->enqueue)) {
3019 /* If we're not dealing with 0.95 hardware or isoc rings
3020 * on AMD 0.96 host, clear the chain bit.
3022 if (!xhci_link_trb_quirk(xhci) &&
3023 !(ep_ring->type == TYPE_ISOC &&
3024 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3025 ep_ring->enqueue->link.control &=
3026 cpu_to_le32(~TRB_CHAIN);
3028 ep_ring->enqueue->link.control |=
3029 cpu_to_le32(TRB_CHAIN);
3032 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3034 /* Toggle the cycle bit after the last ring segment. */
3035 if (link_trb_toggles_cycle(ep_ring->enqueue))
3036 ep_ring->cycle_state ^= 1;
3038 ep_ring->enq_seg = ep_ring->enq_seg->next;
3039 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3044 static int prepare_transfer(struct xhci_hcd *xhci,
3045 struct xhci_virt_device *xdev,
3046 unsigned int ep_index,
3047 unsigned int stream_id,
3048 unsigned int num_trbs,
3050 unsigned int td_index,
3054 struct urb_priv *urb_priv;
3056 struct xhci_ring *ep_ring;
3057 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3059 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
3061 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3066 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3067 num_trbs, mem_flags);
3071 urb_priv = urb->hcpriv;
3072 td = &urb_priv->td[td_index];
3074 INIT_LIST_HEAD(&td->td_list);
3075 INIT_LIST_HEAD(&td->cancelled_td_list);
3077 if (td_index == 0) {
3078 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3084 /* Add this TD to the tail of the endpoint ring's TD list */
3085 list_add_tail(&td->td_list, &ep_ring->td_list);
3086 td->start_seg = ep_ring->enq_seg;
3087 td->first_trb = ep_ring->enqueue;
3092 static unsigned int count_trbs(u64 addr, u64 len)
3094 unsigned int num_trbs;
3096 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3104 static inline unsigned int count_trbs_needed(struct urb *urb)
3106 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3109 static unsigned int count_sg_trbs_needed(struct urb *urb)
3111 struct scatterlist *sg;
3112 unsigned int i, len, full_len, num_trbs = 0;
3114 full_len = urb->transfer_buffer_length;
3116 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3117 len = sg_dma_len(sg);
3118 num_trbs += count_trbs(sg_dma_address(sg), len);
3119 len = min_t(unsigned int, len, full_len);
3128 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3132 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3133 len = urb->iso_frame_desc[i].length;
3135 return count_trbs(addr, len);
3138 static void check_trb_math(struct urb *urb, int running_total)
3140 if (unlikely(running_total != urb->transfer_buffer_length))
3141 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3142 "queued %#x (%d), asked for %#x (%d)\n",
3144 urb->ep->desc.bEndpointAddress,
3145 running_total, running_total,
3146 urb->transfer_buffer_length,
3147 urb->transfer_buffer_length);
3150 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3151 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3152 struct xhci_generic_trb *start_trb)
3155 * Pass all the TRBs to the hardware at once and make sure this write
3160 start_trb->field[3] |= cpu_to_le32(start_cycle);
3162 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3163 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3166 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3167 struct xhci_ep_ctx *ep_ctx)
3172 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3173 ep_interval = urb->interval;
3175 /* Convert to microframes */
3176 if (urb->dev->speed == USB_SPEED_LOW ||
3177 urb->dev->speed == USB_SPEED_FULL)
3180 /* FIXME change this to a warning and a suggestion to use the new API
3181 * to set the polling interval (once the API is added).
3183 if (xhci_interval != ep_interval) {
3184 dev_dbg_ratelimited(&urb->dev->dev,
3185 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3186 ep_interval, ep_interval == 1 ? "" : "s",
3187 xhci_interval, xhci_interval == 1 ? "" : "s");
3188 urb->interval = xhci_interval;
3189 /* Convert back to frames for LS/FS devices */
3190 if (urb->dev->speed == USB_SPEED_LOW ||
3191 urb->dev->speed == USB_SPEED_FULL)
3197 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3198 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3199 * (comprised of sg list entries) can take several service intervals to
3202 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3203 struct urb *urb, int slot_id, unsigned int ep_index)
3205 struct xhci_ep_ctx *ep_ctx;
3207 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3208 check_interval(xhci, urb, ep_ctx);
3210 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3214 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3215 * packets remaining in the TD (*not* including this TRB).
3217 * Total TD packet count = total_packet_count =
3218 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3220 * Packets transferred up to and including this TRB = packets_transferred =
3221 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3223 * TD size = total_packet_count - packets_transferred
3225 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3226 * including this TRB, right shifted by 10
3228 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3229 * This is taken care of in the TRB_TD_SIZE() macro
3231 * The last TRB in a TD must have the TD size set to zero.
3233 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3234 int trb_buff_len, unsigned int td_total_len,
3235 struct urb *urb, bool more_trbs_coming)
3237 u32 maxp, total_packet_count;
3239 /* MTK xHCI 0.96 contains some features from 1.0 */
3240 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3241 return ((td_total_len - transferred) >> 10);
3243 /* One TRB with a zero-length data packet. */
3244 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3245 trb_buff_len == td_total_len)
3248 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3249 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3252 maxp = usb_endpoint_maxp(&urb->ep->desc);
3253 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3255 /* Queueing functions don't count the current TRB into transferred */
3256 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3260 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3261 u32 *trb_buff_len, struct xhci_segment *seg)
3263 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3264 unsigned int unalign;
3265 unsigned int max_pkt;
3269 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3270 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3272 /* we got lucky, last normal TRB data on segment is packet aligned */
3276 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3277 unalign, *trb_buff_len);
3279 /* is the last nornal TRB alignable by splitting it */
3280 if (*trb_buff_len > unalign) {
3281 *trb_buff_len -= unalign;
3282 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3287 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3288 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3289 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3291 new_buff_len = max_pkt - (enqd_len % max_pkt);
3293 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3294 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3296 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3297 if (usb_urb_dir_out(urb)) {
3299 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3300 seg->bounce_buf, new_buff_len, enqd_len);
3301 if (len != new_buff_len)
3302 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3305 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3308 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3309 max_pkt, DMA_TO_DEVICE);
3311 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3312 max_pkt, DMA_FROM_DEVICE);
3315 if (dma_mapping_error(dev, seg->bounce_dma)) {
3316 /* try without aligning. Some host controllers survive */
3317 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3320 *trb_buff_len = new_buff_len;
3321 seg->bounce_len = new_buff_len;
3322 seg->bounce_offs = enqd_len;
3324 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3329 /* This is very similar to what ehci-q.c qtd_fill() does */
3330 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3331 struct urb *urb, int slot_id, unsigned int ep_index)
3333 struct xhci_ring *ring;
3334 struct urb_priv *urb_priv;
3336 struct xhci_generic_trb *start_trb;
3337 struct scatterlist *sg = NULL;
3338 bool more_trbs_coming = true;
3339 bool need_zero_pkt = false;
3340 bool first_trb = true;
3341 unsigned int num_trbs;
3342 unsigned int start_cycle, num_sgs = 0;
3343 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3345 u32 field, length_field, remainder;
3346 u64 addr, send_addr;
3348 ring = xhci_urb_to_transfer_ring(xhci, urb);
3352 full_len = urb->transfer_buffer_length;
3353 /* If we have scatter/gather list, we use it. */
3355 num_sgs = urb->num_mapped_sgs;
3357 addr = (u64) sg_dma_address(sg);
3358 block_len = sg_dma_len(sg);
3359 num_trbs = count_sg_trbs_needed(urb);
3361 num_trbs = count_trbs_needed(urb);
3362 addr = (u64) urb->transfer_dma;
3363 block_len = full_len;
3365 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3366 ep_index, urb->stream_id,
3367 num_trbs, urb, 0, mem_flags);
3368 if (unlikely(ret < 0))
3371 urb_priv = urb->hcpriv;
3373 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3374 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3375 need_zero_pkt = true;
3377 td = &urb_priv->td[0];
3380 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3381 * until we've finished creating all the other TRBs. The ring's cycle
3382 * state may change as we enqueue the other TRBs, so save it too.
3384 start_trb = &ring->enqueue->generic;
3385 start_cycle = ring->cycle_state;
3388 /* Queue the TRBs, even if they are zero-length */
3389 for (enqd_len = 0; first_trb || enqd_len < full_len;
3390 enqd_len += trb_buff_len) {
3391 field = TRB_TYPE(TRB_NORMAL);
3393 /* TRB buffer should not cross 64KB boundaries */
3394 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3395 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3397 if (enqd_len + trb_buff_len > full_len)
3398 trb_buff_len = full_len - enqd_len;
3400 /* Don't change the cycle bit of the first TRB until later */
3403 if (start_cycle == 0)
3406 field |= ring->cycle_state;
3408 /* Chain all the TRBs together; clear the chain bit in the last
3409 * TRB to indicate it's the last TRB in the chain.
3411 if (enqd_len + trb_buff_len < full_len) {
3413 if (trb_is_link(ring->enqueue + 1)) {
3414 if (xhci_align_td(xhci, urb, enqd_len,
3417 send_addr = ring->enq_seg->bounce_dma;
3418 /* assuming TD won't span 2 segs */
3419 td->bounce_seg = ring->enq_seg;
3423 if (enqd_len + trb_buff_len >= full_len) {
3424 field &= ~TRB_CHAIN;
3426 more_trbs_coming = false;
3427 td->last_trb = ring->enqueue;
3430 /* Only set interrupt on short packet for IN endpoints */
3431 if (usb_urb_dir_in(urb))
3434 /* Set the TRB length, TD size, and interrupter fields. */
3435 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3436 full_len, urb, more_trbs_coming);
3438 length_field = TRB_LEN(trb_buff_len) |
3439 TRB_TD_SIZE(remainder) |
3442 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3443 lower_32_bits(send_addr),
3444 upper_32_bits(send_addr),
3448 addr += trb_buff_len;
3449 sent_len = trb_buff_len;
3451 while (sg && sent_len >= block_len) {
3454 sent_len -= block_len;
3456 if (num_sgs != 0 && sg) {
3457 block_len = sg_dma_len(sg);
3458 addr = (u64) sg_dma_address(sg);
3462 block_len -= sent_len;
3466 if (need_zero_pkt) {
3467 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3468 ep_index, urb->stream_id,
3469 1, urb, 1, mem_flags);
3470 urb_priv->td[1].last_trb = ring->enqueue;
3471 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3472 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3475 check_trb_math(urb, enqd_len);
3476 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3477 start_cycle, start_trb);
3481 /* Caller must have locked xhci->lock */
3482 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3483 struct urb *urb, int slot_id, unsigned int ep_index)
3485 struct xhci_ring *ep_ring;
3488 struct usb_ctrlrequest *setup;
3489 struct xhci_generic_trb *start_trb;
3492 struct urb_priv *urb_priv;
3495 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3500 * Need to copy setup packet into setup TRB, so we can't use the setup
3503 if (!urb->setup_packet)
3506 /* 1 TRB for setup, 1 for status */
3509 * Don't need to check if we need additional event data and normal TRBs,
3510 * since data in control transfers will never get bigger than 16MB
3511 * XXX: can we get a buffer that crosses 64KB boundaries?
3513 if (urb->transfer_buffer_length > 0)
3515 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3516 ep_index, urb->stream_id,
3517 num_trbs, urb, 0, mem_flags);
3521 urb_priv = urb->hcpriv;
3522 td = &urb_priv->td[0];
3525 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3526 * until we've finished creating all the other TRBs. The ring's cycle
3527 * state may change as we enqueue the other TRBs, so save it too.
3529 start_trb = &ep_ring->enqueue->generic;
3530 start_cycle = ep_ring->cycle_state;
3532 /* Queue setup TRB - see section 6.4.1.2.1 */
3533 /* FIXME better way to translate setup_packet into two u32 fields? */
3534 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3536 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3537 if (start_cycle == 0)
3540 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3541 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3542 if (urb->transfer_buffer_length > 0) {
3543 if (setup->bRequestType & USB_DIR_IN)
3544 field |= TRB_TX_TYPE(TRB_DATA_IN);
3546 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3550 queue_trb(xhci, ep_ring, true,
3551 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3552 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3553 TRB_LEN(8) | TRB_INTR_TARGET(0),
3554 /* Immediate data in pointer */
3557 /* If there's data, queue data TRBs */
3558 /* Only set interrupt on short packet for IN endpoints */
3559 if (usb_urb_dir_in(urb))
3560 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3562 field = TRB_TYPE(TRB_DATA);
3564 if (urb->transfer_buffer_length > 0) {
3565 u32 length_field, remainder;
3567 remainder = xhci_td_remainder(xhci, 0,
3568 urb->transfer_buffer_length,
3569 urb->transfer_buffer_length,
3571 length_field = TRB_LEN(urb->transfer_buffer_length) |
3572 TRB_TD_SIZE(remainder) |
3574 if (setup->bRequestType & USB_DIR_IN)
3575 field |= TRB_DIR_IN;
3576 queue_trb(xhci, ep_ring, true,
3577 lower_32_bits(urb->transfer_dma),
3578 upper_32_bits(urb->transfer_dma),
3580 field | ep_ring->cycle_state);
3583 /* Save the DMA address of the last TRB in the TD */
3584 td->last_trb = ep_ring->enqueue;
3586 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3587 /* If the device sent data, the status stage is an OUT transfer */
3588 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3592 queue_trb(xhci, ep_ring, false,
3596 /* Event on completion */
3597 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3599 giveback_first_trb(xhci, slot_id, ep_index, 0,
3600 start_cycle, start_trb);
3605 * The transfer burst count field of the isochronous TRB defines the number of
3606 * bursts that are required to move all packets in this TD. Only SuperSpeed
3607 * devices can burst up to bMaxBurst number of packets per service interval.
3608 * This field is zero based, meaning a value of zero in the field means one
3609 * burst. Basically, for everything but SuperSpeed devices, this field will be
3610 * zero. Only xHCI 1.0 host controllers support this field.
3612 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3613 struct urb *urb, unsigned int total_packet_count)
3615 unsigned int max_burst;
3617 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3620 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3621 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3625 * Returns the number of packets in the last "burst" of packets. This field is
3626 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3627 * the last burst packet count is equal to the total number of packets in the
3628 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3629 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3630 * contain 1 to (bMaxBurst + 1) packets.
3632 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3633 struct urb *urb, unsigned int total_packet_count)
3635 unsigned int max_burst;
3636 unsigned int residue;
3638 if (xhci->hci_version < 0x100)
3641 if (urb->dev->speed >= USB_SPEED_SUPER) {
3642 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3643 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3644 residue = total_packet_count % (max_burst + 1);
3645 /* If residue is zero, the last burst contains (max_burst + 1)
3646 * number of packets, but the TLBPC field is zero-based.
3652 if (total_packet_count == 0)
3654 return total_packet_count - 1;
3658 * Calculates Frame ID field of the isochronous TRB identifies the
3659 * target frame that the Interval associated with this Isochronous
3660 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3662 * Returns actual frame id on success, negative value on error.
3664 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3665 struct urb *urb, int index)
3667 int start_frame, ist, ret = 0;
3668 int start_frame_id, end_frame_id, current_frame_id;
3670 if (urb->dev->speed == USB_SPEED_LOW ||
3671 urb->dev->speed == USB_SPEED_FULL)
3672 start_frame = urb->start_frame + index * urb->interval;
3674 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3676 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3678 * If bit [3] of IST is cleared to '0', software can add a TRB no
3679 * later than IST[2:0] Microframes before that TRB is scheduled to
3681 * If bit [3] of IST is set to '1', software can add a TRB no later
3682 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3684 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3685 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3688 /* Software shall not schedule an Isoch TD with a Frame ID value that
3689 * is less than the Start Frame ID or greater than the End Frame ID,
3692 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3693 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3695 * Both the End Frame ID and Start Frame ID values are calculated
3696 * in microframes. When software determines the valid Frame ID value;
3697 * The End Frame ID value should be rounded down to the nearest Frame
3698 * boundary, and the Start Frame ID value should be rounded up to the
3699 * nearest Frame boundary.
3701 current_frame_id = readl(&xhci->run_regs->microframe_index);
3702 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3703 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3705 start_frame &= 0x7ff;
3706 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3707 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3709 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3710 __func__, index, readl(&xhci->run_regs->microframe_index),
3711 start_frame_id, end_frame_id, start_frame);
3713 if (start_frame_id < end_frame_id) {
3714 if (start_frame > end_frame_id ||
3715 start_frame < start_frame_id)
3717 } else if (start_frame_id > end_frame_id) {
3718 if ((start_frame > end_frame_id &&
3719 start_frame < start_frame_id))
3726 if (ret == -EINVAL || start_frame == start_frame_id) {
3727 start_frame = start_frame_id + 1;
3728 if (urb->dev->speed == USB_SPEED_LOW ||
3729 urb->dev->speed == USB_SPEED_FULL)
3730 urb->start_frame = start_frame;
3732 urb->start_frame = start_frame << 3;
3738 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3739 start_frame, current_frame_id, index,
3740 start_frame_id, end_frame_id);
3741 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3748 /* This is for isoc transfer */
3749 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3750 struct urb *urb, int slot_id, unsigned int ep_index)
3752 struct xhci_ring *ep_ring;
3753 struct urb_priv *urb_priv;
3755 int num_tds, trbs_per_td;
3756 struct xhci_generic_trb *start_trb;
3759 u32 field, length_field;
3760 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3761 u64 start_addr, addr;
3763 bool more_trbs_coming;
3764 struct xhci_virt_ep *xep;
3767 xep = &xhci->devs[slot_id]->eps[ep_index];
3768 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3770 num_tds = urb->number_of_packets;
3772 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3775 start_addr = (u64) urb->transfer_dma;
3776 start_trb = &ep_ring->enqueue->generic;
3777 start_cycle = ep_ring->cycle_state;
3779 urb_priv = urb->hcpriv;
3780 /* Queue the TRBs for each TD, even if they are zero-length */
3781 for (i = 0; i < num_tds; i++) {
3782 unsigned int total_pkt_count, max_pkt;
3783 unsigned int burst_count, last_burst_pkt_count;
3788 addr = start_addr + urb->iso_frame_desc[i].offset;
3789 td_len = urb->iso_frame_desc[i].length;
3790 td_remain_len = td_len;
3791 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3792 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3794 /* A zero-length transfer still involves at least one packet. */
3795 if (total_pkt_count == 0)
3797 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3798 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3799 urb, total_pkt_count);
3801 trbs_per_td = count_isoc_trbs_needed(urb, i);
3803 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3804 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3810 td = &urb_priv->td[i];
3812 /* use SIA as default, if frame id is used overwrite it */
3813 sia_frame_id = TRB_SIA;
3814 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3815 HCC_CFC(xhci->hcc_params)) {
3816 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3818 sia_frame_id = TRB_FRAME_ID(frame_id);
3821 * Set isoc specific data for the first TRB in a TD.
3822 * Prevent HW from getting the TRBs by keeping the cycle state
3823 * inverted in the first TDs isoc TRB.
3825 field = TRB_TYPE(TRB_ISOC) |
3826 TRB_TLBPC(last_burst_pkt_count) |
3828 (i ? ep_ring->cycle_state : !start_cycle);
3830 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3831 if (!xep->use_extended_tbc)
3832 field |= TRB_TBC(burst_count);
3834 /* fill the rest of the TRB fields, and remaining normal TRBs */
3835 for (j = 0; j < trbs_per_td; j++) {
3838 /* only first TRB is isoc, overwrite otherwise */
3840 field = TRB_TYPE(TRB_NORMAL) |
3841 ep_ring->cycle_state;
3843 /* Only set interrupt on short packet for IN EPs */
3844 if (usb_urb_dir_in(urb))
3847 /* Set the chain bit for all except the last TRB */
3848 if (j < trbs_per_td - 1) {
3849 more_trbs_coming = true;
3852 more_trbs_coming = false;
3853 td->last_trb = ep_ring->enqueue;
3855 /* set BEI, except for the last TD */
3856 if (xhci->hci_version >= 0x100 &&
3857 !(xhci->quirks & XHCI_AVOID_BEI) &&
3861 /* Calculate TRB length */
3862 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3863 if (trb_buff_len > td_remain_len)
3864 trb_buff_len = td_remain_len;
3866 /* Set the TRB length, TD size, & interrupter fields. */
3867 remainder = xhci_td_remainder(xhci, running_total,
3868 trb_buff_len, td_len,
3869 urb, more_trbs_coming);
3871 length_field = TRB_LEN(trb_buff_len) |
3874 /* xhci 1.1 with ETE uses TD Size field for TBC */
3875 if (first_trb && xep->use_extended_tbc)
3876 length_field |= TRB_TD_SIZE_TBC(burst_count);
3878 length_field |= TRB_TD_SIZE(remainder);
3881 queue_trb(xhci, ep_ring, more_trbs_coming,
3882 lower_32_bits(addr),
3883 upper_32_bits(addr),
3886 running_total += trb_buff_len;
3888 addr += trb_buff_len;
3889 td_remain_len -= trb_buff_len;
3892 /* Check TD length */
3893 if (running_total != td_len) {
3894 xhci_err(xhci, "ISOC TD length unmatch\n");
3900 /* store the next frame id */
3901 if (HCC_CFC(xhci->hcc_params))
3902 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3904 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3905 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3906 usb_amd_quirk_pll_disable();
3908 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3910 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3911 start_cycle, start_trb);
3914 /* Clean up a partially enqueued isoc transfer. */
3916 for (i--; i >= 0; i--)
3917 list_del_init(&urb_priv->td[i].td_list);
3919 /* Use the first TD as a temporary variable to turn the TDs we've queued
3920 * into No-ops with a software-owned cycle bit. That way the hardware
3921 * won't accidentally start executing bogus TDs when we partially
3922 * overwrite them. td->first_trb and td->start_seg are already set.
3924 urb_priv->td[0].last_trb = ep_ring->enqueue;
3925 /* Every TRB except the first & last will have its cycle bit flipped. */
3926 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
3928 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3929 ep_ring->enqueue = urb_priv->td[0].first_trb;
3930 ep_ring->enq_seg = urb_priv->td[0].start_seg;
3931 ep_ring->cycle_state = start_cycle;
3932 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3933 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3938 * Check transfer ring to guarantee there is enough room for the urb.
3939 * Update ISO URB start_frame and interval.
3940 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3941 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3942 * Contiguous Frame ID is not supported by HC.
3944 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3945 struct urb *urb, int slot_id, unsigned int ep_index)
3947 struct xhci_virt_device *xdev;
3948 struct xhci_ring *ep_ring;
3949 struct xhci_ep_ctx *ep_ctx;
3951 int num_tds, num_trbs, i;
3953 struct xhci_virt_ep *xep;
3956 xdev = xhci->devs[slot_id];
3957 xep = &xhci->devs[slot_id]->eps[ep_index];
3958 ep_ring = xdev->eps[ep_index].ring;
3959 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3962 num_tds = urb->number_of_packets;
3963 for (i = 0; i < num_tds; i++)
3964 num_trbs += count_isoc_trbs_needed(urb, i);
3966 /* Check the ring to guarantee there is enough room for the whole urb.
3967 * Do not insert any td of the urb to the ring if the check failed.
3969 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3970 num_trbs, mem_flags);
3975 * Check interval value. This should be done before we start to
3976 * calculate the start frame value.
3978 check_interval(xhci, urb, ep_ctx);
3980 /* Calculate the start frame and put it in urb->start_frame. */
3981 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3982 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
3983 urb->start_frame = xep->next_frame_id;
3984 goto skip_start_over;
3988 start_frame = readl(&xhci->run_regs->microframe_index);
3989 start_frame &= 0x3fff;
3991 * Round up to the next frame and consider the time before trb really
3992 * gets scheduled by hardare.
3994 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3995 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3997 start_frame += ist + XHCI_CFC_DELAY;
3998 start_frame = roundup(start_frame, 8);
4001 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4002 * is greate than 8 microframes.
4004 if (urb->dev->speed == USB_SPEED_LOW ||
4005 urb->dev->speed == USB_SPEED_FULL) {
4006 start_frame = roundup(start_frame, urb->interval << 3);
4007 urb->start_frame = start_frame >> 3;
4009 start_frame = roundup(start_frame, urb->interval);
4010 urb->start_frame = start_frame;
4014 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4016 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4019 /**** Command Ring Operations ****/
4021 /* Generic function for queueing a command TRB on the command ring.
4022 * Check to make sure there's room on the command ring for one command TRB.
4023 * Also check that there's room reserved for commands that must not fail.
4024 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4025 * then only check for the number of reserved spots.
4026 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4027 * because the command event handler may want to resubmit a failed command.
4029 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4030 u32 field1, u32 field2,
4031 u32 field3, u32 field4, bool command_must_succeed)
4033 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4036 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4037 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4038 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4042 if (!command_must_succeed)
4045 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4046 reserved_trbs, GFP_ATOMIC);
4048 xhci_err(xhci, "ERR: No room for command on command ring\n");
4049 if (command_must_succeed)
4050 xhci_err(xhci, "ERR: Reserved TRB counting for "
4051 "unfailable commands failed.\n");
4055 cmd->command_trb = xhci->cmd_ring->enqueue;
4057 /* if there are no other commands queued we start the timeout timer */
4058 if (list_empty(&xhci->cmd_list)) {
4059 xhci->current_cmd = cmd;
4060 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4063 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4065 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4066 field4 | xhci->cmd_ring->cycle_state);
4070 /* Queue a slot enable or disable request on the command ring */
4071 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4072 u32 trb_type, u32 slot_id)
4074 return queue_command(xhci, cmd, 0, 0, 0,
4075 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4078 /* Queue an address device command TRB */
4079 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4080 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4082 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4083 upper_32_bits(in_ctx_ptr), 0,
4084 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4085 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4088 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4089 u32 field1, u32 field2, u32 field3, u32 field4)
4091 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4094 /* Queue a reset device command TRB */
4095 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4098 return queue_command(xhci, cmd, 0, 0, 0,
4099 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4103 /* Queue a configure endpoint command TRB */
4104 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4105 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4106 u32 slot_id, bool command_must_succeed)
4108 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4109 upper_32_bits(in_ctx_ptr), 0,
4110 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4111 command_must_succeed);
4114 /* Queue an evaluate context command TRB */
4115 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4116 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4118 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4119 upper_32_bits(in_ctx_ptr), 0,
4120 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4121 command_must_succeed);
4125 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4126 * activity on an endpoint that is about to be suspended.
4128 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4129 int slot_id, unsigned int ep_index, int suspend)
4131 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4132 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4133 u32 type = TRB_TYPE(TRB_STOP_RING);
4134 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4136 return queue_command(xhci, cmd, 0, 0, 0,
4137 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4140 /* Set Transfer Ring Dequeue Pointer command */
4141 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4142 unsigned int slot_id, unsigned int ep_index,
4143 struct xhci_dequeue_state *deq_state)
4146 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4147 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4148 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4150 u32 type = TRB_TYPE(TRB_SET_DEQ);
4151 struct xhci_virt_ep *ep;
4152 struct xhci_command *cmd;
4155 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4156 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4157 deq_state->new_deq_seg,
4158 (unsigned long long)deq_state->new_deq_seg->dma,
4159 deq_state->new_deq_ptr,
4160 (unsigned long long)xhci_trb_virt_to_dma(
4161 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4162 deq_state->new_cycle_state);
4164 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4165 deq_state->new_deq_ptr);
4167 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4168 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4169 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4172 ep = &xhci->devs[slot_id]->eps[ep_index];
4173 if ((ep->ep_state & SET_DEQ_PENDING)) {
4174 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4175 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4179 /* This function gets called from contexts where it cannot sleep */
4180 cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
4184 ep->queued_deq_seg = deq_state->new_deq_seg;
4185 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4186 if (deq_state->stream_id)
4187 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4188 ret = queue_command(xhci, cmd,
4189 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4190 upper_32_bits(addr), trb_stream_id,
4191 trb_slot_id | trb_ep_index | type, false);
4193 xhci_free_command(xhci, cmd);
4197 /* Stop the TD queueing code from ringing the doorbell until
4198 * this command completes. The HC won't set the dequeue pointer
4199 * if the ring is running, and ringing the doorbell starts the
4202 ep->ep_state |= SET_DEQ_PENDING;
4205 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4206 int slot_id, unsigned int ep_index,
4207 enum xhci_ep_reset_type reset_type)
4209 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4210 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4211 u32 type = TRB_TYPE(TRB_RESET_EP);
4213 if (reset_type == EP_SOFT_RESET)
4216 return queue_command(xhci, cmd, 0, 0, 0,
4217 trb_slot_id | trb_ep_index | type, false);