1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
59 #include "xhci-trace.h"
63 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
66 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
69 unsigned long segment_offset;
71 if (!seg || !trb || trb < seg->trbs)
74 segment_offset = trb - seg->trbs;
75 if (segment_offset >= TRBS_PER_SEGMENT)
77 return seg->dma + (segment_offset * sizeof(*trb));
80 static bool trb_is_noop(union xhci_trb *trb)
82 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
85 static bool trb_is_link(union xhci_trb *trb)
87 return TRB_TYPE_LINK_LE32(trb->link.control);
90 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
92 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
95 static bool last_trb_on_ring(struct xhci_ring *ring,
96 struct xhci_segment *seg, union xhci_trb *trb)
98 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
101 static bool link_trb_toggles_cycle(union xhci_trb *trb)
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
106 static bool last_td_in_urb(struct xhci_td *td)
108 struct urb_priv *urb_priv = td->urb->hcpriv;
110 return urb_priv->num_tds_done == urb_priv->num_tds;
113 static void inc_td_cnt(struct urb *urb)
115 struct urb_priv *urb_priv = urb->hcpriv;
117 urb_priv->num_tds_done++;
120 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
122 if (trb_is_link(trb)) {
123 /* unchain chained link TRBs */
124 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
126 trb->generic.field[0] = 0;
127 trb->generic.field[1] = 0;
128 trb->generic.field[2] = 0;
129 /* Preserve only the cycle bit of this TRB */
130 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
131 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
135 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
136 * TRB is in a new segment. This does not skip over link TRBs, and it does not
137 * effect the ring dequeue or enqueue pointers.
139 static void next_trb(struct xhci_hcd *xhci,
140 struct xhci_ring *ring,
141 struct xhci_segment **seg,
142 union xhci_trb **trb)
144 if (trb_is_link(*trb)) {
146 *trb = ((*seg)->trbs);
153 * See Cycle bit rules. SW is the consumer for the event ring only.
154 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
156 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
158 /* event ring doesn't have link trbs, check for last trb */
159 if (ring->type == TYPE_EVENT) {
160 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
164 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
165 ring->cycle_state ^= 1;
166 ring->deq_seg = ring->deq_seg->next;
167 ring->dequeue = ring->deq_seg->trbs;
171 /* All other rings have link trbs */
172 if (!trb_is_link(ring->dequeue)) {
174 ring->num_trbs_free++;
176 while (trb_is_link(ring->dequeue)) {
177 ring->deq_seg = ring->deq_seg->next;
178 ring->dequeue = ring->deq_seg->trbs;
182 trace_xhci_inc_deq(ring);
188 * See Cycle bit rules. SW is the consumer for the event ring only.
189 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
191 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
192 * chain bit is set), then set the chain bit in all the following link TRBs.
193 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
194 * have their chain bit cleared (so that each Link TRB is a separate TD).
196 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
197 * set, but other sections talk about dealing with the chain bit set. This was
198 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
199 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
201 * @more_trbs_coming: Will you enqueue more TRBs before calling
202 * prepare_transfer()?
204 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
205 bool more_trbs_coming)
208 union xhci_trb *next;
210 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
211 /* If this is not event ring, there is one less usable TRB */
212 if (!trb_is_link(ring->enqueue))
213 ring->num_trbs_free--;
214 next = ++(ring->enqueue);
216 /* Update the dequeue pointer further if that was a link TRB */
217 while (trb_is_link(next)) {
220 * If the caller doesn't plan on enqueueing more TDs before
221 * ringing the doorbell, then we don't want to give the link TRB
222 * to the hardware just yet. We'll give the link TRB back in
223 * prepare_ring() just before we enqueue the TD at the top of
226 if (!chain && !more_trbs_coming)
229 /* If we're not dealing with 0.95 hardware or isoc rings on
230 * AMD 0.96 host, carry over the chain bit of the previous TRB
231 * (which may mean the chain bit is cleared).
233 if (!(ring->type == TYPE_ISOC &&
234 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
235 !xhci_link_trb_quirk(xhci)) {
236 next->link.control &= cpu_to_le32(~TRB_CHAIN);
237 next->link.control |= cpu_to_le32(chain);
239 /* Give this link TRB to the hardware */
241 next->link.control ^= cpu_to_le32(TRB_CYCLE);
243 /* Toggle the cycle bit after the last ring segment. */
244 if (link_trb_toggles_cycle(next))
245 ring->cycle_state ^= 1;
247 ring->enq_seg = ring->enq_seg->next;
248 ring->enqueue = ring->enq_seg->trbs;
249 next = ring->enqueue;
252 trace_xhci_inc_enq(ring);
256 * Check to see if there's room to enqueue num_trbs on the ring and make sure
257 * enqueue pointer will not advance into dequeue segment. See rules above.
259 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
260 unsigned int num_trbs)
262 int num_trbs_in_deq_seg;
264 if (ring->num_trbs_free < num_trbs)
267 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
268 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
269 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
276 /* Ring the host controller doorbell after placing a command on the ring */
277 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
279 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
282 xhci_dbg(xhci, "// Ding dong!\n");
283 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
284 /* Flush PCI posted writes */
285 readl(&xhci->dba->doorbell[0]);
288 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
290 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
293 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
295 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
300 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
301 * If there are other commands waiting then restart the ring and kick the timer.
302 * This must be called with command ring stopped and xhci->lock held.
304 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
305 struct xhci_command *cur_cmd)
307 struct xhci_command *i_cmd;
309 /* Turn all aborted commands in list to no-ops, then restart */
310 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
312 if (i_cmd->status != COMP_COMMAND_ABORTED)
315 i_cmd->status = COMP_COMMAND_RING_STOPPED;
317 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
320 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
323 * caller waiting for completion is called when command
324 * completion event is received for these no-op commands
328 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
330 /* ring command ring doorbell to restart the command ring */
331 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
332 !(xhci->xhc_state & XHCI_STATE_DYING)) {
333 xhci->current_cmd = cur_cmd;
334 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
335 xhci_ring_cmd_db(xhci);
339 /* Must be called with xhci->lock held, releases and aquires lock back */
340 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
345 xhci_dbg(xhci, "Abort command ring\n");
347 reinit_completion(&xhci->cmd_ring_stop_completion);
349 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
350 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
351 &xhci->op_regs->cmd_ring);
353 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
354 * completion of the Command Abort operation. If CRR is not negated in 5
355 * seconds then driver handles it as if host died (-ENODEV).
356 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
357 * and try to recover a -ETIMEDOUT with a host controller reset.
359 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
360 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
362 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
368 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
369 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
370 * but the completion event in never sent. Wait 2 secs (arbitrary
371 * number) to handle those cases after negation of CMD_RING_RUNNING.
373 spin_unlock_irqrestore(&xhci->lock, flags);
374 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
375 msecs_to_jiffies(2000));
376 spin_lock_irqsave(&xhci->lock, flags);
378 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
379 xhci_cleanup_command_queue(xhci);
381 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
386 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
387 unsigned int slot_id,
388 unsigned int ep_index,
389 unsigned int stream_id)
391 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
392 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
393 unsigned int ep_state = ep->ep_state;
395 /* Don't ring the doorbell for this endpoint if there are pending
396 * cancellations because we don't want to interrupt processing.
397 * We don't want to restart any stream rings if there's a set dequeue
398 * pointer command pending because the device can choose to start any
399 * stream once the endpoint is on the HW schedule.
401 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
402 (ep_state & EP_HALTED))
404 writel(DB_VALUE(ep_index, stream_id), db_addr);
405 /* The CPU has better things to do at this point than wait for a
406 * write-posting flush. It'll get there soon enough.
410 /* Ring the doorbell for any rings with pending URBs */
411 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
412 unsigned int slot_id,
413 unsigned int ep_index)
415 unsigned int stream_id;
416 struct xhci_virt_ep *ep;
418 ep = &xhci->devs[slot_id]->eps[ep_index];
420 /* A ring has pending URBs if its TD list is not empty */
421 if (!(ep->ep_state & EP_HAS_STREAMS)) {
422 if (ep->ring && !(list_empty(&ep->ring->td_list)))
423 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
427 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
429 struct xhci_stream_info *stream_info = ep->stream_info;
430 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
431 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
436 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
437 unsigned int slot_id,
438 unsigned int ep_index)
440 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
441 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
444 if (ep_index >= EP_CTX_PER_DEV) {
445 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
448 if (!xhci->devs[slot_id]) {
449 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
453 return &xhci->devs[slot_id]->eps[ep_index];
456 /* Get the right ring for the given slot_id, ep_index and stream_id.
457 * If the endpoint supports streams, boundary check the URB's stream ID.
458 * If the endpoint doesn't support streams, return the singular endpoint ring.
460 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
461 unsigned int slot_id, unsigned int ep_index,
462 unsigned int stream_id)
464 struct xhci_virt_ep *ep;
466 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
470 /* Common case: no streams */
471 if (!(ep->ep_state & EP_HAS_STREAMS))
474 if (stream_id == 0) {
476 "WARN: Slot ID %u, ep index %u has streams, "
477 "but URB has no stream ID.\n",
482 if (stream_id < ep->stream_info->num_streams)
483 return ep->stream_info->stream_rings[stream_id];
486 "WARN: Slot ID %u, ep index %u has "
487 "stream IDs 1 to %u allocated, "
488 "but stream ID %u is requested.\n",
490 ep->stream_info->num_streams - 1,
497 * Get the hw dequeue pointer xHC stopped on, either directly from the
498 * endpoint context, or if streams are in use from the stream context.
499 * The returned hw_dequeue contains the lowest four bits with cycle state
500 * and possbile stream context type.
502 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
503 unsigned int ep_index, unsigned int stream_id)
505 struct xhci_ep_ctx *ep_ctx;
506 struct xhci_stream_ctx *st_ctx;
507 struct xhci_virt_ep *ep;
509 ep = &vdev->eps[ep_index];
511 if (ep->ep_state & EP_HAS_STREAMS) {
512 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
513 return le64_to_cpu(st_ctx->stream_ring);
515 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
516 return le64_to_cpu(ep_ctx->deq);
520 * Move the xHC's endpoint ring dequeue pointer past cur_td.
521 * Record the new state of the xHC's endpoint ring dequeue segment,
522 * dequeue pointer, stream id, and new consumer cycle state in state.
523 * Update our internal representation of the ring's dequeue pointer.
525 * We do this in three jumps:
526 * - First we update our new ring state to be the same as when the xHC stopped.
527 * - Then we traverse the ring to find the segment that contains
528 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
529 * any link TRBs with the toggle cycle bit set.
530 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
531 * if we've moved it past a link TRB with the toggle cycle bit set.
533 * Some of the uses of xhci_generic_trb are grotty, but if they're done
534 * with correct __le32 accesses they should work fine. Only users of this are
537 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
538 unsigned int slot_id, unsigned int ep_index,
539 unsigned int stream_id, struct xhci_td *cur_td,
540 struct xhci_dequeue_state *state)
542 struct xhci_virt_device *dev = xhci->devs[slot_id];
543 struct xhci_virt_ep *ep = &dev->eps[ep_index];
544 struct xhci_ring *ep_ring;
545 struct xhci_segment *new_seg;
546 union xhci_trb *new_deq;
549 bool cycle_found = false;
550 bool td_last_trb_found = false;
552 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
553 ep_index, stream_id);
555 xhci_warn(xhci, "WARN can't find new dequeue state "
556 "for invalid stream ID %u.\n",
560 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
561 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
562 "Finding endpoint context");
564 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
565 new_seg = ep_ring->deq_seg;
566 new_deq = ep_ring->dequeue;
567 state->new_cycle_state = hw_dequeue & 0x1;
568 state->stream_id = stream_id;
571 * We want to find the pointer, segment and cycle state of the new trb
572 * (the one after current TD's last_trb). We know the cycle state at
573 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
577 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
578 == (dma_addr_t)(hw_dequeue & ~0xf)) {
580 if (td_last_trb_found)
583 if (new_deq == cur_td->last_trb)
584 td_last_trb_found = true;
586 if (cycle_found && trb_is_link(new_deq) &&
587 link_trb_toggles_cycle(new_deq))
588 state->new_cycle_state ^= 0x1;
590 next_trb(xhci, ep_ring, &new_seg, &new_deq);
592 /* Search wrapped around, bail out */
593 if (new_deq == ep->ring->dequeue) {
594 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
595 state->new_deq_seg = NULL;
596 state->new_deq_ptr = NULL;
600 } while (!cycle_found || !td_last_trb_found);
602 state->new_deq_seg = new_seg;
603 state->new_deq_ptr = new_deq;
605 /* Don't update the ring cycle state for the producer (us). */
606 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
607 "Cycle state = 0x%x", state->new_cycle_state);
609 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
610 "New dequeue segment = %p (virtual)",
612 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
613 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
614 "New dequeue pointer = 0x%llx (DMA)",
615 (unsigned long long) addr);
618 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
619 * (The last TRB actually points to the ring enqueue pointer, which is not part
620 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
622 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
623 struct xhci_td *td, bool flip_cycle)
625 struct xhci_segment *seg = td->start_seg;
626 union xhci_trb *trb = td->first_trb;
629 trb_to_noop(trb, TRB_TR_NOOP);
631 /* flip cycle if asked to */
632 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
633 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
635 if (trb == td->last_trb)
638 next_trb(xhci, ep_ring, &seg, &trb);
642 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
643 struct xhci_virt_ep *ep)
645 ep->ep_state &= ~EP_STOP_CMD_PENDING;
646 /* Can't del_timer_sync in interrupt */
647 del_timer(&ep->stop_cmd_timer);
651 * Must be called with xhci->lock held in interrupt context,
652 * releases and re-acquires xhci->lock
654 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
655 struct xhci_td *cur_td, int status)
657 struct urb *urb = cur_td->urb;
658 struct urb_priv *urb_priv = urb->hcpriv;
659 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
661 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
662 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
663 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
664 if (xhci->quirks & XHCI_AMD_PLL_FIX)
665 usb_amd_quirk_pll_enable();
668 xhci_urb_free_priv(urb_priv);
669 usb_hcd_unlink_urb_from_ep(hcd, urb);
670 spin_unlock(&xhci->lock);
671 trace_xhci_urb_giveback(urb);
672 usb_hcd_giveback_urb(hcd, urb, status);
673 spin_lock(&xhci->lock);
676 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
677 struct xhci_ring *ring, struct xhci_td *td)
679 struct device *dev = xhci_to_hcd(xhci)->self.controller;
680 struct xhci_segment *seg = td->bounce_seg;
681 struct urb *urb = td->urb;
684 if (!ring || !seg || !urb)
687 if (usb_urb_dir_out(urb)) {
688 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
693 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
695 /* for in tranfers we need to copy the data from bounce to sg */
697 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
698 seg->bounce_len, seg->bounce_offs);
699 if (len != seg->bounce_len)
700 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
701 len, seg->bounce_len);
703 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
707 seg->bounce_offs = 0;
711 * When we get a command completion for a Stop Endpoint Command, we need to
712 * unlink any cancelled TDs from the ring. There are two ways to do that:
714 * 1. If the HW was in the middle of processing the TD that needs to be
715 * cancelled, then we must move the ring's dequeue pointer past the last TRB
716 * in the TD with a Set Dequeue Pointer Command.
717 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
718 * bit cleared) so that the HW will skip over them.
720 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
721 union xhci_trb *trb, struct xhci_event_cmd *event)
723 unsigned int ep_index;
724 struct xhci_ring *ep_ring;
725 struct xhci_virt_ep *ep;
726 struct xhci_td *cur_td = NULL;
727 struct xhci_td *last_unlinked_td;
728 struct xhci_ep_ctx *ep_ctx;
729 struct xhci_virt_device *vdev;
731 struct xhci_dequeue_state deq_state;
733 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
734 if (!xhci->devs[slot_id])
735 xhci_warn(xhci, "Stop endpoint command "
736 "completion for disabled slot %u\n",
741 memset(&deq_state, 0, sizeof(deq_state));
742 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
744 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
748 vdev = xhci->devs[slot_id];
749 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
750 trace_xhci_handle_cmd_stop_ep(ep_ctx);
752 last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
753 struct xhci_td, cancelled_td_list);
755 if (list_empty(&ep->cancelled_td_list)) {
756 xhci_stop_watchdog_timer_in_irq(xhci, ep);
757 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
761 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
762 * We have the xHCI lock, so nothing can modify this list until we drop
763 * it. We're also in the event handler, so we can't get re-interrupted
764 * if another Stop Endpoint command completes
766 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
767 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
768 "Removing canceled TD starting at 0x%llx (dma).",
769 (unsigned long long)xhci_trb_virt_to_dma(
770 cur_td->start_seg, cur_td->first_trb));
771 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
773 /* This shouldn't happen unless a driver is mucking
774 * with the stream ID after submission. This will
775 * leave the TD on the hardware ring, and the hardware
776 * will try to execute it, and may access a buffer
777 * that has already been freed. In the best case, the
778 * hardware will execute it, and the event handler will
779 * ignore the completion event for that TD, since it was
780 * removed from the td_list for that endpoint. In
781 * short, don't muck with the stream ID after
784 xhci_warn(xhci, "WARN Cancelled URB %p "
785 "has invalid stream ID %u.\n",
787 cur_td->urb->stream_id);
788 goto remove_finished_td;
791 * If we stopped on the TD we need to cancel, then we have to
792 * move the xHC endpoint ring dequeue pointer past this TD.
794 hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
795 cur_td->urb->stream_id);
798 if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
799 cur_td->last_trb, hw_deq, false)) {
800 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
801 cur_td->urb->stream_id,
804 td_to_noop(xhci, ep_ring, cur_td, false);
809 * The event handler won't see a completion for this TD anymore,
810 * so remove it from the endpoint ring's TD list. Keep it in
811 * the cancelled TD list for URB completion later.
813 list_del_init(&cur_td->td_list);
816 xhci_stop_watchdog_timer_in_irq(xhci, ep);
818 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
819 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
820 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
822 xhci_ring_cmd_db(xhci);
824 /* Otherwise ring the doorbell(s) to restart queued transfers */
825 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
829 * Drop the lock and complete the URBs in the cancelled TD list.
830 * New TDs to be cancelled might be added to the end of the list before
831 * we can complete all the URBs for the TDs we already unlinked.
832 * So stop when we've completed the URB for the last TD we unlinked.
835 cur_td = list_first_entry(&ep->cancelled_td_list,
836 struct xhci_td, cancelled_td_list);
837 list_del_init(&cur_td->cancelled_td_list);
839 /* Clean up the cancelled URB */
840 /* Doesn't matter what we pass for status, since the core will
841 * just overwrite it (because the URB has been unlinked).
843 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
844 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
845 inc_td_cnt(cur_td->urb);
846 if (last_td_in_urb(cur_td))
847 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
849 /* Stop processing the cancelled list if the watchdog timer is
852 if (xhci->xhc_state & XHCI_STATE_DYING)
854 } while (cur_td != last_unlinked_td);
856 /* Return to the event handler with xhci->lock re-acquired */
859 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
861 struct xhci_td *cur_td;
864 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
865 list_del_init(&cur_td->td_list);
867 if (!list_empty(&cur_td->cancelled_td_list))
868 list_del_init(&cur_td->cancelled_td_list);
870 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
872 inc_td_cnt(cur_td->urb);
873 if (last_td_in_urb(cur_td))
874 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
878 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
879 int slot_id, int ep_index)
881 struct xhci_td *cur_td;
883 struct xhci_virt_ep *ep;
884 struct xhci_ring *ring;
886 ep = &xhci->devs[slot_id]->eps[ep_index];
887 if ((ep->ep_state & EP_HAS_STREAMS) ||
888 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
891 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
893 ring = ep->stream_info->stream_rings[stream_id];
897 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
898 "Killing URBs for slot ID %u, ep index %u, stream %u",
899 slot_id, ep_index, stream_id);
900 xhci_kill_ring_urbs(xhci, ring);
906 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
907 "Killing URBs for slot ID %u, ep index %u",
909 xhci_kill_ring_urbs(xhci, ring);
912 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
914 list_del_init(&cur_td->cancelled_td_list);
915 inc_td_cnt(cur_td->urb);
917 if (last_td_in_urb(cur_td))
918 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
923 * host controller died, register read returns 0xffffffff
924 * Complete pending commands, mark them ABORTED.
925 * URBs need to be given back as usb core might be waiting with device locks
926 * held for the URBs to finish during device disconnect, blocking host remove.
928 * Call with xhci->lock held.
929 * lock is relased and re-acquired while giving back urb.
931 void xhci_hc_died(struct xhci_hcd *xhci)
935 if (xhci->xhc_state & XHCI_STATE_DYING)
938 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
939 xhci->xhc_state |= XHCI_STATE_DYING;
941 xhci_cleanup_command_queue(xhci);
943 /* return any pending urbs, remove may be waiting for them */
944 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
947 for (j = 0; j < 31; j++)
948 xhci_kill_endpoint_urbs(xhci, i, j);
951 /* inform usb core hc died if PCI remove isn't already handling it */
952 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
953 usb_hc_died(xhci_to_hcd(xhci));
956 /* Watchdog timer function for when a stop endpoint command fails to complete.
957 * In this case, we assume the host controller is broken or dying or dead. The
958 * host may still be completing some other events, so we have to be careful to
959 * let the event ring handler and the URB dequeueing/enqueueing functions know
960 * through xhci->state.
962 * The timer may also fire if the host takes a very long time to respond to the
963 * command, and the stop endpoint command completion handler cannot delete the
964 * timer before the timer function is called. Another endpoint cancellation may
965 * sneak in before the timer function can grab the lock, and that may queue
966 * another stop endpoint command and add the timer back. So we cannot use a
967 * simple flag to say whether there is a pending stop endpoint command for a
968 * particular endpoint.
970 * Instead we use a combination of that flag and checking if a new timer is
973 void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
975 struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
976 struct xhci_hcd *xhci = ep->xhci;
979 spin_lock_irqsave(&xhci->lock, flags);
981 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
982 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
983 timer_pending(&ep->stop_cmd_timer)) {
984 spin_unlock_irqrestore(&xhci->lock, flags);
985 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
989 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
990 ep->ep_state &= ~EP_STOP_CMD_PENDING;
995 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
996 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
997 * and try to recover a -ETIMEDOUT with a host controller reset
1001 spin_unlock_irqrestore(&xhci->lock, flags);
1002 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1003 "xHCI host controller is dead.");
1006 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1007 struct xhci_virt_device *dev,
1008 struct xhci_ring *ep_ring,
1009 unsigned int ep_index)
1011 union xhci_trb *dequeue_temp;
1012 int num_trbs_free_temp;
1013 bool revert = false;
1015 num_trbs_free_temp = ep_ring->num_trbs_free;
1016 dequeue_temp = ep_ring->dequeue;
1018 /* If we get two back-to-back stalls, and the first stalled transfer
1019 * ends just before a link TRB, the dequeue pointer will be left on
1020 * the link TRB by the code in the while loop. So we have to update
1021 * the dequeue pointer one segment further, or we'll jump off
1022 * the segment into la-la-land.
1024 if (trb_is_link(ep_ring->dequeue)) {
1025 ep_ring->deq_seg = ep_ring->deq_seg->next;
1026 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1029 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1030 /* We have more usable TRBs */
1031 ep_ring->num_trbs_free++;
1033 if (trb_is_link(ep_ring->dequeue)) {
1034 if (ep_ring->dequeue ==
1035 dev->eps[ep_index].queued_deq_ptr)
1037 ep_ring->deq_seg = ep_ring->deq_seg->next;
1038 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1040 if (ep_ring->dequeue == dequeue_temp) {
1047 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1048 ep_ring->num_trbs_free = num_trbs_free_temp;
1053 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1054 * we need to clear the set deq pending flag in the endpoint ring state, so that
1055 * the TD queueing code can ring the doorbell again. We also need to ring the
1056 * endpoint doorbell to restart the ring, but only if there aren't more
1057 * cancellations pending.
1059 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1060 union xhci_trb *trb, u32 cmd_comp_code)
1062 unsigned int ep_index;
1063 unsigned int stream_id;
1064 struct xhci_ring *ep_ring;
1065 struct xhci_virt_device *dev;
1066 struct xhci_virt_ep *ep;
1067 struct xhci_ep_ctx *ep_ctx;
1068 struct xhci_slot_ctx *slot_ctx;
1070 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1071 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1072 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1076 dev = xhci->devs[slot_id];
1077 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1079 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1081 /* XXX: Harmless??? */
1085 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1086 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1087 trace_xhci_handle_cmd_set_deq(slot_ctx);
1088 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1090 if (cmd_comp_code != COMP_SUCCESS) {
1091 unsigned int ep_state;
1092 unsigned int slot_state;
1094 switch (cmd_comp_code) {
1095 case COMP_TRB_ERROR:
1096 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1098 case COMP_CONTEXT_STATE_ERROR:
1099 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1100 ep_state = GET_EP_CTX_STATE(ep_ctx);
1101 slot_state = le32_to_cpu(slot_ctx->dev_state);
1102 slot_state = GET_SLOT_STATE(slot_state);
1103 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1104 "Slot state = %u, EP state = %u",
1105 slot_state, ep_state);
1107 case COMP_SLOT_NOT_ENABLED_ERROR:
1108 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1112 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1116 /* OK what do we do now? The endpoint state is hosed, and we
1117 * should never get to this point if the synchronization between
1118 * queueing, and endpoint state are correct. This might happen
1119 * if the device gets disconnected after we've finished
1120 * cancelling URBs, which might not be an error...
1124 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1125 if (ep->ep_state & EP_HAS_STREAMS) {
1126 struct xhci_stream_ctx *ctx =
1127 &ep->stream_info->stream_ctx_array[stream_id];
1128 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1130 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1132 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1133 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1134 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1135 ep->queued_deq_ptr) == deq) {
1136 /* Update the ring's dequeue segment and dequeue pointer
1137 * to reflect the new position.
1139 update_ring_for_set_deq_completion(xhci, dev,
1142 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1143 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1144 ep->queued_deq_seg, ep->queued_deq_ptr);
1149 ep->ep_state &= ~SET_DEQ_PENDING;
1150 ep->queued_deq_seg = NULL;
1151 ep->queued_deq_ptr = NULL;
1152 /* Restart any rings with pending URBs */
1153 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1156 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1157 union xhci_trb *trb, u32 cmd_comp_code)
1159 struct xhci_virt_device *vdev;
1160 struct xhci_virt_ep *ep;
1161 struct xhci_ep_ctx *ep_ctx;
1162 unsigned int ep_index;
1164 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1165 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1169 vdev = xhci->devs[slot_id];
1170 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1171 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1173 /* This command will only fail if the endpoint wasn't halted,
1174 * but we don't care.
1176 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1177 "Ignoring reset ep completion code of %u", cmd_comp_code);
1179 /* HW with the reset endpoint quirk needs to have a configure endpoint
1180 * command complete before the endpoint can be used. Queue that here
1181 * because the HW can't handle two commands being queued in a row.
1183 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1184 struct xhci_command *command;
1186 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1190 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1191 "Queueing configure endpoint command");
1192 xhci_queue_configure_endpoint(xhci, command,
1193 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1195 xhci_ring_cmd_db(xhci);
1197 /* Clear our internal halted state */
1198 ep->ep_state &= ~EP_HALTED;
1202 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1203 struct xhci_command *command, u32 cmd_comp_code)
1205 if (cmd_comp_code == COMP_SUCCESS)
1206 command->slot_id = slot_id;
1208 command->slot_id = 0;
1211 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1213 struct xhci_virt_device *virt_dev;
1214 struct xhci_slot_ctx *slot_ctx;
1216 virt_dev = xhci->devs[slot_id];
1220 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1221 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1223 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1224 /* Delete default control endpoint resources */
1225 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1226 xhci_free_virt_device(xhci, slot_id);
1229 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1230 struct xhci_event_cmd *event, u32 cmd_comp_code)
1232 struct xhci_virt_device *virt_dev;
1233 struct xhci_input_control_ctx *ctrl_ctx;
1234 struct xhci_ep_ctx *ep_ctx;
1235 unsigned int ep_index;
1236 unsigned int ep_state;
1237 u32 add_flags, drop_flags;
1240 * Configure endpoint commands can come from the USB core
1241 * configuration or alt setting changes, or because the HW
1242 * needed an extra configure endpoint command after a reset
1243 * endpoint command or streams were being configured.
1244 * If the command was for a halted endpoint, the xHCI driver
1245 * is not waiting on the configure endpoint command.
1247 virt_dev = xhci->devs[slot_id];
1248 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1250 xhci_warn(xhci, "Could not get input context, bad type.\n");
1254 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1255 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1256 /* Input ctx add_flags are the endpoint index plus one */
1257 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1259 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1260 trace_xhci_handle_cmd_config_ep(ep_ctx);
1262 /* A usb_set_interface() call directly after clearing a halted
1263 * condition may race on this quirky hardware. Not worth
1264 * worrying about, since this is prototype hardware. Not sure
1265 * if this will work for streams, but streams support was
1266 * untested on this prototype.
1268 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1269 ep_index != (unsigned int) -1 &&
1270 add_flags - SLOT_FLAG == drop_flags) {
1271 ep_state = virt_dev->eps[ep_index].ep_state;
1272 if (!(ep_state & EP_HALTED))
1274 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1275 "Completed config ep cmd - "
1276 "last ep index = %d, state = %d",
1277 ep_index, ep_state);
1278 /* Clear internal halted state and restart ring(s) */
1279 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1280 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1286 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1288 struct xhci_virt_device *vdev;
1289 struct xhci_slot_ctx *slot_ctx;
1291 vdev = xhci->devs[slot_id];
1292 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1293 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1296 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1297 struct xhci_event_cmd *event)
1299 struct xhci_virt_device *vdev;
1300 struct xhci_slot_ctx *slot_ctx;
1302 vdev = xhci->devs[slot_id];
1303 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1304 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1306 xhci_dbg(xhci, "Completed reset device command.\n");
1307 if (!xhci->devs[slot_id])
1308 xhci_warn(xhci, "Reset device command completion "
1309 "for disabled slot %u\n", slot_id);
1312 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1313 struct xhci_event_cmd *event)
1315 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1316 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1319 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1320 "NEC firmware version %2x.%02x",
1321 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1322 NEC_FW_MINOR(le32_to_cpu(event->status)));
1325 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1327 list_del(&cmd->cmd_list);
1329 if (cmd->completion) {
1330 cmd->status = status;
1331 complete(cmd->completion);
1337 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1339 struct xhci_command *cur_cmd, *tmp_cmd;
1340 xhci->current_cmd = NULL;
1341 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1342 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1345 void xhci_handle_command_timeout(struct work_struct *work)
1347 struct xhci_hcd *xhci;
1348 unsigned long flags;
1351 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1353 spin_lock_irqsave(&xhci->lock, flags);
1356 * If timeout work is pending, or current_cmd is NULL, it means we
1357 * raced with command completion. Command is handled so just return.
1359 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1360 spin_unlock_irqrestore(&xhci->lock, flags);
1363 /* mark this command to be cancelled */
1364 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1366 /* Make sure command ring is running before aborting it */
1367 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1368 if (hw_ring_state == ~(u64)0) {
1370 goto time_out_completed;
1373 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1374 (hw_ring_state & CMD_RING_RUNNING)) {
1375 /* Prevent new doorbell, and start command abort */
1376 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1377 xhci_dbg(xhci, "Command timeout\n");
1378 xhci_abort_cmd_ring(xhci, flags);
1379 goto time_out_completed;
1382 /* host removed. Bail out */
1383 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1384 xhci_dbg(xhci, "host removed, ring start fail?\n");
1385 xhci_cleanup_command_queue(xhci);
1387 goto time_out_completed;
1390 /* command timeout on stopped ring, ring can't be aborted */
1391 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1392 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1395 spin_unlock_irqrestore(&xhci->lock, flags);
1399 static void handle_cmd_completion(struct xhci_hcd *xhci,
1400 struct xhci_event_cmd *event)
1402 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1404 dma_addr_t cmd_dequeue_dma;
1406 union xhci_trb *cmd_trb;
1407 struct xhci_command *cmd;
1410 cmd_dma = le64_to_cpu(event->cmd_trb);
1411 cmd_trb = xhci->cmd_ring->dequeue;
1413 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1415 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1418 * Check whether the completion event is for our internal kept
1421 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1423 "ERROR mismatched command completion event\n");
1427 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1429 cancel_delayed_work(&xhci->cmd_timer);
1431 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1433 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1434 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1435 complete_all(&xhci->cmd_ring_stop_completion);
1439 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1441 "Command completion event does not match command\n");
1446 * Host aborted the command ring, check if the current command was
1447 * supposed to be aborted, otherwise continue normally.
1448 * The command ring is stopped now, but the xHC will issue a Command
1449 * Ring Stopped event which will cause us to restart it.
1451 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1452 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1453 if (cmd->status == COMP_COMMAND_ABORTED) {
1454 if (xhci->current_cmd == cmd)
1455 xhci->current_cmd = NULL;
1460 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1462 case TRB_ENABLE_SLOT:
1463 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1465 case TRB_DISABLE_SLOT:
1466 xhci_handle_cmd_disable_slot(xhci, slot_id);
1469 if (!cmd->completion)
1470 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1473 case TRB_EVAL_CONTEXT:
1476 xhci_handle_cmd_addr_dev(xhci, slot_id);
1479 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1480 le32_to_cpu(cmd_trb->generic.field[3])));
1481 if (!cmd->completion)
1482 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1485 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1486 le32_to_cpu(cmd_trb->generic.field[3])));
1487 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1490 /* Is this an aborted command turned to NO-OP? */
1491 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1492 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1495 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1496 le32_to_cpu(cmd_trb->generic.field[3])));
1497 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1500 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1501 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1503 slot_id = TRB_TO_SLOT_ID(
1504 le32_to_cpu(cmd_trb->generic.field[3]));
1505 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1507 case TRB_NEC_GET_FW:
1508 xhci_handle_cmd_nec_get_fw(xhci, event);
1511 /* Skip over unknown commands on the event ring */
1512 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1516 /* restart timer if this wasn't the last command */
1517 if (!list_is_singular(&xhci->cmd_list)) {
1518 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1519 struct xhci_command, cmd_list);
1520 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1521 } else if (xhci->current_cmd == cmd) {
1522 xhci->current_cmd = NULL;
1526 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1528 inc_deq(xhci, xhci->cmd_ring);
1531 static void handle_vendor_event(struct xhci_hcd *xhci,
1532 union xhci_trb *event)
1536 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1537 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1538 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1539 handle_cmd_completion(xhci, &event->event_cmd);
1542 static void handle_device_notification(struct xhci_hcd *xhci,
1543 union xhci_trb *event)
1546 struct usb_device *udev;
1548 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1549 if (!xhci->devs[slot_id]) {
1550 xhci_warn(xhci, "Device Notification event for "
1551 "unused slot %u\n", slot_id);
1555 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1557 udev = xhci->devs[slot_id]->udev;
1558 if (udev && udev->parent)
1559 usb_wakeup_notification(udev->parent, udev->portnum);
1563 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1565 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1566 * If a connection to a USB 1 device is followed by another connection
1567 * to a USB 2 device.
1569 * Reset the PHY after the USB device is disconnected if device speed
1570 * is less than HCD_USB3.
1571 * Retry the reset sequence max of 4 times checking the PLL lock status.
1574 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1576 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1578 u32 retry_count = 4;
1581 /* Assert PHY reset */
1582 writel(0x6F, hcd->regs + 0x1048);
1584 /* De-assert the PHY reset */
1585 writel(0x7F, hcd->regs + 0x1048);
1587 pll_lock_check = readl(hcd->regs + 0x1070);
1588 } while (!(pll_lock_check & 0x1) && --retry_count);
1591 static void handle_port_status(struct xhci_hcd *xhci,
1592 union xhci_trb *event)
1594 struct usb_hcd *hcd;
1596 u32 portsc, cmd_reg;
1599 unsigned int hcd_portnum;
1600 struct xhci_bus_state *bus_state;
1601 bool bogus_port_status = false;
1602 struct xhci_port *port;
1604 /* Port status change events always have a successful completion code */
1605 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1607 "WARN: xHC returned failed port status event\n");
1609 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1610 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1612 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1613 if ((port_id <= 0) || (port_id > max_ports)) {
1614 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1615 inc_deq(xhci, xhci->event_ring);
1619 port = &xhci->hw_ports[port_id - 1];
1620 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1621 xhci_warn(xhci, "Event for invalid port %u\n", port_id);
1622 bogus_port_status = true;
1626 /* We might get interrupts after shared_hcd is removed */
1627 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1628 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1629 bogus_port_status = true;
1633 hcd = port->rhub->hcd;
1634 bus_state = &xhci->bus_state[hcd_index(hcd)];
1635 hcd_portnum = port->hcd_portnum;
1636 portsc = readl(port->addr);
1638 trace_xhci_handle_port_status(hcd_portnum, portsc);
1640 if (hcd->state == HC_STATE_SUSPENDED) {
1641 xhci_dbg(xhci, "resume root hub\n");
1642 usb_hcd_resume_root_hub(hcd);
1645 if (hcd->speed >= HCD_USB3 &&
1646 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1647 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1648 if (slot_id && xhci->devs[slot_id])
1649 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1652 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1653 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1655 cmd_reg = readl(&xhci->op_regs->command);
1656 if (!(cmd_reg & CMD_RUN)) {
1657 xhci_warn(xhci, "xHC is not running.\n");
1661 if (DEV_SUPERSPEED_ANY(portsc)) {
1662 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1663 /* Set a flag to say the port signaled remote wakeup,
1664 * so we can tell the difference between the end of
1665 * device and host initiated resume.
1667 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1668 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1669 xhci_set_link_state(xhci, port, XDEV_U0);
1670 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1671 /* Need to wait until the next link state change
1672 * indicates the device is actually in U0.
1674 bogus_port_status = true;
1676 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1677 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1678 bus_state->resume_done[hcd_portnum] = jiffies +
1679 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1680 set_bit(hcd_portnum, &bus_state->resuming_ports);
1681 /* Do the rest in GetPortStatus after resume time delay.
1682 * Avoid polling roothub status before that so that a
1683 * usb device auto-resume latency around ~40ms.
1685 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1686 mod_timer(&hcd->rh_timer,
1687 bus_state->resume_done[hcd_portnum]);
1688 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1689 bogus_port_status = true;
1693 if ((portsc & PORT_PLC) &&
1694 DEV_SUPERSPEED_ANY(portsc) &&
1695 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1696 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1697 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1698 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1699 /* We've just brought the device into U0/1/2 through either the
1700 * Resume state after a device remote wakeup, or through the
1701 * U3Exit state after a host-initiated resume. If it's a device
1702 * initiated remote wake, don't pass up the link state change,
1703 * so the roothub behavior is consistent with external
1704 * USB 3.0 hub behavior.
1706 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1707 if (slot_id && xhci->devs[slot_id])
1708 xhci_ring_device(xhci, slot_id);
1709 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1710 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1711 usb_wakeup_notification(hcd->self.root_hub,
1713 bogus_port_status = true;
1719 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1720 * RExit to a disconnect state). If so, let the the driver know it's
1721 * out of the RExit state.
1723 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1724 test_and_clear_bit(hcd_portnum,
1725 &bus_state->rexit_ports)) {
1726 complete(&bus_state->rexit_done[hcd_portnum]);
1727 bogus_port_status = true;
1731 if (hcd->speed < HCD_USB3) {
1732 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1733 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1734 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1735 xhci_cavium_reset_phy_quirk(xhci);
1739 /* Update event ring dequeue pointer before dropping the lock */
1740 inc_deq(xhci, xhci->event_ring);
1742 /* Don't make the USB core poll the roothub if we got a bad port status
1743 * change event. Besides, at that point we can't tell which roothub
1744 * (USB 2.0 or USB 3.0) to kick.
1746 if (bogus_port_status)
1750 * xHCI port-status-change events occur when the "or" of all the
1751 * status-change bits in the portsc register changes from 0 to 1.
1752 * New status changes won't cause an event if any other change
1753 * bits are still set. When an event occurs, switch over to
1754 * polling to avoid losing status changes.
1756 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1757 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1758 spin_unlock(&xhci->lock);
1759 /* Pass this up to the core */
1760 usb_hcd_poll_rh_status(hcd);
1761 spin_lock(&xhci->lock);
1765 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1766 * at end_trb, which may be in another segment. If the suspect DMA address is a
1767 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1770 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1771 struct xhci_segment *start_seg,
1772 union xhci_trb *start_trb,
1773 union xhci_trb *end_trb,
1774 dma_addr_t suspect_dma,
1777 dma_addr_t start_dma;
1778 dma_addr_t end_seg_dma;
1779 dma_addr_t end_trb_dma;
1780 struct xhci_segment *cur_seg;
1782 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1783 cur_seg = start_seg;
1788 /* We may get an event for a Link TRB in the middle of a TD */
1789 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1790 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1791 /* If the end TRB isn't in this segment, this is set to 0 */
1792 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1796 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1797 (unsigned long long)suspect_dma,
1798 (unsigned long long)start_dma,
1799 (unsigned long long)end_trb_dma,
1800 (unsigned long long)cur_seg->dma,
1801 (unsigned long long)end_seg_dma);
1803 if (end_trb_dma > 0) {
1804 /* The end TRB is in this segment, so suspect should be here */
1805 if (start_dma <= end_trb_dma) {
1806 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1809 /* Case for one segment with
1810 * a TD wrapped around to the top
1812 if ((suspect_dma >= start_dma &&
1813 suspect_dma <= end_seg_dma) ||
1814 (suspect_dma >= cur_seg->dma &&
1815 suspect_dma <= end_trb_dma))
1820 /* Might still be somewhere in this segment */
1821 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1824 cur_seg = cur_seg->next;
1825 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1826 } while (cur_seg != start_seg);
1831 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1832 unsigned int slot_id, unsigned int ep_index,
1833 unsigned int stream_id, struct xhci_td *td,
1834 enum xhci_ep_reset_type reset_type)
1836 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1837 struct xhci_command *command;
1840 * Avoid resetting endpoint if link is inactive. Can cause host hang.
1841 * Device will be reset soon to recover the link so don't do anything
1843 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR)
1846 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1850 ep->ep_state |= EP_HALTED;
1852 xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
1854 if (reset_type == EP_HARD_RESET) {
1855 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
1856 xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td);
1858 xhci_ring_cmd_db(xhci);
1861 /* Check if an error has halted the endpoint ring. The class driver will
1862 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1863 * However, a babble and other errors also halt the endpoint ring, and the class
1864 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1865 * Ring Dequeue Pointer command manually.
1867 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1868 struct xhci_ep_ctx *ep_ctx,
1869 unsigned int trb_comp_code)
1871 /* TRB completion codes that may require a manual halt cleanup */
1872 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1873 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1874 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1875 /* The 0.95 spec says a babbling control endpoint
1876 * is not halted. The 0.96 spec says it is. Some HW
1877 * claims to be 0.95 compliant, but it halts the control
1878 * endpoint anyway. Check if a babble halted the
1881 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1887 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1889 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1890 /* Vendor defined "informational" completion code,
1891 * treat as not-an-error.
1893 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1895 xhci_dbg(xhci, "Treating code as success.\n");
1901 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1902 struct xhci_ring *ep_ring, int *status)
1904 struct urb *urb = NULL;
1906 /* Clean up the endpoint's TD list */
1909 /* if a bounce buffer was used to align this td then unmap it */
1910 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1912 /* Do one last check of the actual transfer length.
1913 * If the host controller said we transferred more data than the buffer
1914 * length, urb->actual_length will be a very big number (since it's
1915 * unsigned). Play it safe and say we didn't transfer anything.
1917 if (urb->actual_length > urb->transfer_buffer_length) {
1918 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
1919 urb->transfer_buffer_length, urb->actual_length);
1920 urb->actual_length = 0;
1923 list_del_init(&td->td_list);
1924 /* Was this TD slated to be cancelled but completed anyway? */
1925 if (!list_empty(&td->cancelled_td_list))
1926 list_del_init(&td->cancelled_td_list);
1929 /* Giveback the urb when all the tds are completed */
1930 if (last_td_in_urb(td)) {
1931 if ((urb->actual_length != urb->transfer_buffer_length &&
1932 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
1933 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
1934 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
1935 urb, urb->actual_length,
1936 urb->transfer_buffer_length, *status);
1938 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
1939 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
1941 xhci_giveback_urb_in_irq(xhci, td, *status);
1947 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1948 struct xhci_transfer_event *event,
1949 struct xhci_virt_ep *ep, int *status)
1951 struct xhci_virt_device *xdev;
1952 struct xhci_ep_ctx *ep_ctx;
1953 struct xhci_ring *ep_ring;
1954 unsigned int slot_id;
1958 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1959 xdev = xhci->devs[slot_id];
1960 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1961 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1962 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1963 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1965 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
1966 trb_comp_code == COMP_STOPPED ||
1967 trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
1968 /* The Endpoint Stop Command completion will take care of any
1969 * stopped TDs. A stopped TD may be restarted, so don't update
1970 * the ring dequeue pointer or take this TD off any lists yet.
1974 if (trb_comp_code == COMP_STALL_ERROR ||
1975 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1977 /* Issue a reset endpoint command to clear the host side
1978 * halt, followed by a set dequeue command to move the
1979 * dequeue pointer past the TD.
1980 * The class driver clears the device side halt later.
1982 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1983 ep_ring->stream_id, td, EP_HARD_RESET);
1985 /* Update ring dequeue pointer */
1986 while (ep_ring->dequeue != td->last_trb)
1987 inc_deq(xhci, ep_ring);
1988 inc_deq(xhci, ep_ring);
1991 return xhci_td_cleanup(xhci, td, ep_ring, status);
1994 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
1995 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
1996 union xhci_trb *stop_trb)
1999 union xhci_trb *trb = ring->dequeue;
2000 struct xhci_segment *seg = ring->deq_seg;
2002 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2003 if (!trb_is_noop(trb) && !trb_is_link(trb))
2004 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2010 * Process control tds, update urb status and actual_length.
2012 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2013 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2014 struct xhci_virt_ep *ep, int *status)
2016 struct xhci_virt_device *xdev;
2017 unsigned int slot_id;
2019 struct xhci_ep_ctx *ep_ctx;
2021 u32 remaining, requested;
2024 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2025 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2026 xdev = xhci->devs[slot_id];
2027 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2028 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2029 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2030 requested = td->urb->transfer_buffer_length;
2031 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2033 switch (trb_comp_code) {
2035 if (trb_type != TRB_STATUS) {
2036 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2037 (trb_type == TRB_DATA) ? "data" : "setup");
2038 *status = -ESHUTDOWN;
2043 case COMP_SHORT_PACKET:
2046 case COMP_STOPPED_SHORT_PACKET:
2047 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2048 td->urb->actual_length = remaining;
2050 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2055 td->urb->actual_length = 0;
2059 td->urb->actual_length = requested - remaining;
2062 td->urb->actual_length = requested;
2065 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2069 case COMP_STOPPED_LENGTH_INVALID:
2072 if (!xhci_requires_manual_halt_cleanup(xhci,
2073 ep_ctx, trb_comp_code))
2075 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2076 trb_comp_code, ep_index);
2077 /* else fall through */
2078 case COMP_STALL_ERROR:
2079 /* Did we transfer part of the data (middle) phase? */
2080 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2081 td->urb->actual_length = requested - remaining;
2082 else if (!td->urb_length_set)
2083 td->urb->actual_length = 0;
2087 /* stopped at setup stage, no data transferred */
2088 if (trb_type == TRB_SETUP)
2092 * if on data stage then update the actual_length of the URB and flag it
2093 * as set, so it won't be overwritten in the event for the last TRB.
2095 if (trb_type == TRB_DATA ||
2096 trb_type == TRB_NORMAL) {
2097 td->urb_length_set = true;
2098 td->urb->actual_length = requested - remaining;
2099 xhci_dbg(xhci, "Waiting for status stage event\n");
2103 /* at status stage */
2104 if (!td->urb_length_set)
2105 td->urb->actual_length = requested;
2108 return finish_td(xhci, td, event, ep, status);
2112 * Process isochronous tds, update urb packet status and actual_length.
2114 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2115 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2116 struct xhci_virt_ep *ep, int *status)
2118 struct xhci_ring *ep_ring;
2119 struct urb_priv *urb_priv;
2121 struct usb_iso_packet_descriptor *frame;
2123 bool sum_trbs_for_length = false;
2124 u32 remaining, requested, ep_trb_len;
2125 int short_framestatus;
2127 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2128 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2129 urb_priv = td->urb->hcpriv;
2130 idx = urb_priv->num_tds_done;
2131 frame = &td->urb->iso_frame_desc[idx];
2132 requested = frame->length;
2133 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2134 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2135 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2138 /* handle completion code */
2139 switch (trb_comp_code) {
2142 frame->status = short_framestatus;
2143 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2144 sum_trbs_for_length = true;
2149 case COMP_SHORT_PACKET:
2150 frame->status = short_framestatus;
2151 sum_trbs_for_length = true;
2153 case COMP_BANDWIDTH_OVERRUN_ERROR:
2154 frame->status = -ECOMM;
2156 case COMP_ISOCH_BUFFER_OVERRUN:
2157 case COMP_BABBLE_DETECTED_ERROR:
2158 frame->status = -EOVERFLOW;
2160 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2161 case COMP_STALL_ERROR:
2162 frame->status = -EPROTO;
2164 case COMP_USB_TRANSACTION_ERROR:
2165 frame->status = -EPROTO;
2166 if (ep_trb != td->last_trb)
2170 sum_trbs_for_length = true;
2172 case COMP_STOPPED_SHORT_PACKET:
2173 /* field normally containing residue now contains tranferred */
2174 frame->status = short_framestatus;
2175 requested = remaining;
2177 case COMP_STOPPED_LENGTH_INVALID:
2182 sum_trbs_for_length = true;
2187 if (sum_trbs_for_length)
2188 frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2189 ep_trb_len - remaining;
2191 frame->actual_length = requested;
2193 td->urb->actual_length += frame->actual_length;
2195 return finish_td(xhci, td, event, ep, status);
2198 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2199 struct xhci_transfer_event *event,
2200 struct xhci_virt_ep *ep, int *status)
2202 struct xhci_ring *ep_ring;
2203 struct urb_priv *urb_priv;
2204 struct usb_iso_packet_descriptor *frame;
2207 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2208 urb_priv = td->urb->hcpriv;
2209 idx = urb_priv->num_tds_done;
2210 frame = &td->urb->iso_frame_desc[idx];
2212 /* The transfer is partly done. */
2213 frame->status = -EXDEV;
2215 /* calc actual length */
2216 frame->actual_length = 0;
2218 /* Update ring dequeue pointer */
2219 while (ep_ring->dequeue != td->last_trb)
2220 inc_deq(xhci, ep_ring);
2221 inc_deq(xhci, ep_ring);
2223 return xhci_td_cleanup(xhci, td, ep_ring, status);
2227 * Process bulk and interrupt tds, update urb status and actual_length.
2229 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2230 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2231 struct xhci_virt_ep *ep, int *status)
2233 struct xhci_ring *ep_ring;
2235 u32 remaining, requested, ep_trb_len;
2237 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2238 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2239 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2240 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2241 requested = td->urb->transfer_buffer_length;
2243 switch (trb_comp_code) {
2245 /* handle success with untransferred data as short packet */
2246 if (ep_trb != td->last_trb || remaining) {
2247 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2248 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2249 td->urb->ep->desc.bEndpointAddress,
2250 requested, remaining);
2254 case COMP_SHORT_PACKET:
2255 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2256 td->urb->ep->desc.bEndpointAddress,
2257 requested, remaining);
2260 case COMP_STOPPED_SHORT_PACKET:
2261 td->urb->actual_length = remaining;
2263 case COMP_STOPPED_LENGTH_INVALID:
2264 /* stopped on ep trb with invalid length, exclude it */
2273 if (ep_trb == td->last_trb)
2274 td->urb->actual_length = requested - remaining;
2276 td->urb->actual_length =
2277 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2278 ep_trb_len - remaining;
2280 if (remaining > requested) {
2281 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2283 td->urb->actual_length = 0;
2285 return finish_td(xhci, td, event, ep, status);
2289 * If this function returns an error condition, it means it got a Transfer
2290 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2291 * At this point, the host controller is probably hosed and should be reset.
2293 static int handle_tx_event(struct xhci_hcd *xhci,
2294 struct xhci_transfer_event *event)
2296 struct xhci_virt_device *xdev;
2297 struct xhci_virt_ep *ep;
2298 struct xhci_ring *ep_ring;
2299 unsigned int slot_id;
2301 struct xhci_td *td = NULL;
2302 dma_addr_t ep_trb_dma;
2303 struct xhci_segment *ep_seg;
2304 union xhci_trb *ep_trb;
2305 int status = -EINPROGRESS;
2306 struct xhci_ep_ctx *ep_ctx;
2307 struct list_head *tmp;
2310 bool handling_skipped_tds = false;
2312 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2313 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2314 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2315 ep_trb_dma = le64_to_cpu(event->buffer);
2317 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2319 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2323 xdev = xhci->devs[slot_id];
2324 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2325 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2327 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2329 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2334 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2336 switch (trb_comp_code) {
2337 case COMP_STALL_ERROR:
2338 case COMP_USB_TRANSACTION_ERROR:
2339 case COMP_INVALID_STREAM_TYPE_ERROR:
2340 case COMP_INVALID_STREAM_ID_ERROR:
2341 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
2342 NULL, EP_SOFT_RESET);
2344 case COMP_RING_UNDERRUN:
2345 case COMP_RING_OVERRUN:
2346 case COMP_STOPPED_LENGTH_INVALID:
2349 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2355 /* Count current td numbers if ep->skip is set */
2357 list_for_each(tmp, &ep_ring->td_list)
2361 /* Look for common error cases */
2362 switch (trb_comp_code) {
2363 /* Skip codes that require special handling depending on
2367 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2369 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2370 ep_ring->last_td_was_short)
2371 trb_comp_code = COMP_SHORT_PACKET;
2373 xhci_warn_ratelimited(xhci,
2374 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2376 case COMP_SHORT_PACKET:
2378 /* Completion codes for endpoint stopped state */
2380 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2383 case COMP_STOPPED_LENGTH_INVALID:
2385 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2388 case COMP_STOPPED_SHORT_PACKET:
2390 "Stopped with short packet transfer detected for slot %u ep %u\n",
2393 /* Completion codes for endpoint halted state */
2394 case COMP_STALL_ERROR:
2395 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2397 ep->ep_state |= EP_HALTED;
2400 case COMP_SPLIT_TRANSACTION_ERROR:
2401 case COMP_USB_TRANSACTION_ERROR:
2402 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2406 case COMP_BABBLE_DETECTED_ERROR:
2407 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2409 status = -EOVERFLOW;
2411 /* Completion codes for endpoint error state */
2412 case COMP_TRB_ERROR:
2414 "WARN: TRB error for slot %u ep %u on endpoint\n",
2418 /* completion codes not indicating endpoint state change */
2419 case COMP_DATA_BUFFER_ERROR:
2421 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2425 case COMP_BANDWIDTH_OVERRUN_ERROR:
2427 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2430 case COMP_ISOCH_BUFFER_OVERRUN:
2432 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2435 case COMP_RING_UNDERRUN:
2437 * When the Isoch ring is empty, the xHC will generate
2438 * a Ring Overrun Event for IN Isoch endpoint or Ring
2439 * Underrun Event for OUT Isoch endpoint.
2441 xhci_dbg(xhci, "underrun event on endpoint\n");
2442 if (!list_empty(&ep_ring->td_list))
2443 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2444 "still with TDs queued?\n",
2445 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2448 case COMP_RING_OVERRUN:
2449 xhci_dbg(xhci, "overrun event on endpoint\n");
2450 if (!list_empty(&ep_ring->td_list))
2451 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2452 "still with TDs queued?\n",
2453 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2456 case COMP_MISSED_SERVICE_ERROR:
2458 * When encounter missed service error, one or more isoc tds
2459 * may be missed by xHC.
2460 * Set skip flag of the ep_ring; Complete the missed tds as
2461 * short transfer when process the ep_ring next time.
2465 "Miss service interval error for slot %u ep %u, set skip flag\n",
2468 case COMP_NO_PING_RESPONSE_ERROR:
2471 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2475 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2476 /* needs disable slot command to recover */
2478 "WARN: detect an incompatible device for slot %u ep %u",
2483 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2488 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2489 trb_comp_code, slot_id, ep_index);
2494 /* This TRB should be in the TD at the head of this ring's
2497 if (list_empty(&ep_ring->td_list)) {
2499 * Don't print wanings if it's due to a stopped endpoint
2500 * generating an extra completion event if the device
2501 * was suspended. Or, a event for the last TRB of a
2502 * short TD we already got a short event for.
2503 * The short TD is already removed from the TD list.
2506 if (!(trb_comp_code == COMP_STOPPED ||
2507 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2508 ep_ring->last_td_was_short)) {
2509 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2510 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2515 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2521 /* We've skipped all the TDs on the ep ring when ep->skip set */
2522 if (ep->skip && td_num == 0) {
2524 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2529 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2534 /* Is this a TRB in the currently executing TD? */
2535 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2536 td->last_trb, ep_trb_dma, false);
2539 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2540 * is not in the current TD pointed by ep_ring->dequeue because
2541 * that the hardware dequeue pointer still at the previous TRB
2542 * of the current TD. The previous TRB maybe a Link TD or the
2543 * last TRB of the previous TD. The command completion handle
2544 * will take care the rest.
2546 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2547 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2553 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2554 /* Some host controllers give a spurious
2555 * successful event after a short transfer.
2558 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2559 ep_ring->last_td_was_short) {
2560 ep_ring->last_td_was_short = false;
2563 /* HC is busted, give up! */
2565 "ERROR Transfer event TRB DMA ptr not "
2566 "part of current TD ep_index %d "
2567 "comp_code %u\n", ep_index,
2569 trb_in_td(xhci, ep_ring->deq_seg,
2570 ep_ring->dequeue, td->last_trb,
2575 skip_isoc_td(xhci, td, event, ep, &status);
2578 if (trb_comp_code == COMP_SHORT_PACKET)
2579 ep_ring->last_td_was_short = true;
2581 ep_ring->last_td_was_short = false;
2585 "Found td. Clear skip flag for slot %u ep %u.\n",
2590 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2593 trace_xhci_handle_transfer(ep_ring,
2594 (struct xhci_generic_trb *) ep_trb);
2597 * No-op TRB could trigger interrupts in a case where
2598 * a URB was killed and a STALL_ERROR happens right
2599 * after the endpoint ring stopped. Reset the halted
2600 * endpoint. Otherwise, the endpoint remains stalled
2603 if (trb_is_noop(ep_trb)) {
2604 if (trb_comp_code == COMP_STALL_ERROR ||
2605 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2607 xhci_cleanup_halted_endpoint(xhci, slot_id,
2614 /* update the urb's actual_length and give back to the core */
2615 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2616 process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2617 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2618 process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2620 process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2623 handling_skipped_tds = ep->skip &&
2624 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2625 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2628 * Do not update event ring dequeue pointer if we're in a loop
2629 * processing missed tds.
2631 if (!handling_skipped_tds)
2632 inc_deq(xhci, xhci->event_ring);
2635 * If ep->skip is set, it means there are missed tds on the
2636 * endpoint ring need to take care of.
2637 * Process them as short transfer until reach the td pointed by
2640 } while (handling_skipped_tds);
2645 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2646 (unsigned long long) xhci_trb_virt_to_dma(
2647 xhci->event_ring->deq_seg,
2648 xhci->event_ring->dequeue),
2649 lower_32_bits(le64_to_cpu(event->buffer)),
2650 upper_32_bits(le64_to_cpu(event->buffer)),
2651 le32_to_cpu(event->transfer_len),
2652 le32_to_cpu(event->flags));
2657 * This function handles all OS-owned events on the event ring. It may drop
2658 * xhci->lock between event processing (e.g. to pass up port status changes).
2659 * Returns >0 for "possibly more events to process" (caller should call again),
2660 * otherwise 0 if done. In future, <0 returns should indicate error code.
2662 static int xhci_handle_event(struct xhci_hcd *xhci)
2664 union xhci_trb *event;
2665 int update_ptrs = 1;
2668 /* Event ring hasn't been allocated yet. */
2669 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2670 xhci_err(xhci, "ERROR event ring not ready\n");
2674 event = xhci->event_ring->dequeue;
2675 /* Does the HC or OS own the TRB? */
2676 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2677 xhci->event_ring->cycle_state)
2680 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2683 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2684 * speculative reads of the event's flags/data below.
2687 /* FIXME: Handle more event types. */
2688 switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2689 case TRB_TYPE(TRB_COMPLETION):
2690 handle_cmd_completion(xhci, &event->event_cmd);
2692 case TRB_TYPE(TRB_PORT_STATUS):
2693 handle_port_status(xhci, event);
2696 case TRB_TYPE(TRB_TRANSFER):
2697 ret = handle_tx_event(xhci, &event->trans_event);
2701 case TRB_TYPE(TRB_DEV_NOTE):
2702 handle_device_notification(xhci, event);
2705 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2707 handle_vendor_event(xhci, event);
2709 xhci_warn(xhci, "ERROR unknown event type %d\n",
2711 le32_to_cpu(event->event_cmd.flags)));
2713 /* Any of the above functions may drop and re-acquire the lock, so check
2714 * to make sure a watchdog timer didn't mark the host as non-responsive.
2716 if (xhci->xhc_state & XHCI_STATE_DYING) {
2717 xhci_dbg(xhci, "xHCI host dying, returning from "
2718 "event handler.\n");
2723 /* Update SW event ring dequeue pointer */
2724 inc_deq(xhci, xhci->event_ring);
2726 /* Are there more items on the event ring? Caller will call us again to
2733 * Update Event Ring Dequeue Pointer:
2734 * - When all events have finished
2735 * - To avoid "Event Ring Full Error" condition
2737 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2738 union xhci_trb *event_ring_deq)
2743 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2744 /* If necessary, update the HW's version of the event ring deq ptr. */
2745 if (event_ring_deq != xhci->event_ring->dequeue) {
2746 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2747 xhci->event_ring->dequeue);
2749 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
2751 * Per 4.9.4, Software writes to the ERDP register shall
2752 * always advance the Event Ring Dequeue Pointer value.
2754 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
2755 ((u64) deq & (u64) ~ERST_PTR_MASK))
2758 /* Update HC event ring dequeue pointer */
2759 temp_64 &= ERST_PTR_MASK;
2760 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2763 /* Clear the event handler busy flag (RW1C) */
2764 temp_64 |= ERST_EHB;
2765 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2769 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2770 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2771 * indicators of an event TRB error, but we check the status *first* to be safe.
2773 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2775 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2776 union xhci_trb *event_ring_deq;
2777 irqreturn_t ret = IRQ_NONE;
2778 unsigned long flags;
2783 spin_lock_irqsave(&xhci->lock, flags);
2784 /* Check if the xHC generated the interrupt, or the irq is shared */
2785 status = readl(&xhci->op_regs->status);
2786 if (status == ~(u32)0) {
2792 if (!(status & STS_EINT))
2795 if (status & STS_FATAL) {
2796 xhci_warn(xhci, "WARNING: Host System Error\n");
2803 * Clear the op reg interrupt status first,
2804 * so we can receive interrupts from other MSI-X interrupters.
2805 * Write 1 to clear the interrupt status.
2808 writel(status, &xhci->op_regs->status);
2810 if (!hcd->msi_enabled) {
2812 irq_pending = readl(&xhci->ir_set->irq_pending);
2813 irq_pending |= IMAN_IP;
2814 writel(irq_pending, &xhci->ir_set->irq_pending);
2817 if (xhci->xhc_state & XHCI_STATE_DYING ||
2818 xhci->xhc_state & XHCI_STATE_HALTED) {
2819 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2820 "Shouldn't IRQs be disabled?\n");
2821 /* Clear the event handler busy flag (RW1C);
2822 * the event ring should be empty.
2824 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2825 xhci_write_64(xhci, temp_64 | ERST_EHB,
2826 &xhci->ir_set->erst_dequeue);
2831 event_ring_deq = xhci->event_ring->dequeue;
2832 /* FIXME this should be a delayed service routine
2833 * that clears the EHB.
2835 while (xhci_handle_event(xhci) > 0) {
2836 if (event_loop++ < TRBS_PER_SEGMENT / 2)
2838 xhci_update_erst_dequeue(xhci, event_ring_deq);
2842 xhci_update_erst_dequeue(xhci, event_ring_deq);
2846 spin_unlock_irqrestore(&xhci->lock, flags);
2851 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2853 return xhci_irq(hcd);
2856 /**** Endpoint Ring Operations ****/
2859 * Generic function for queueing a TRB on a ring.
2860 * The caller must have checked to make sure there's room on the ring.
2862 * @more_trbs_coming: Will you enqueue more TRBs before calling
2863 * prepare_transfer()?
2865 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2866 bool more_trbs_coming,
2867 u32 field1, u32 field2, u32 field3, u32 field4)
2869 struct xhci_generic_trb *trb;
2871 trb = &ring->enqueue->generic;
2872 trb->field[0] = cpu_to_le32(field1);
2873 trb->field[1] = cpu_to_le32(field2);
2874 trb->field[2] = cpu_to_le32(field3);
2875 /* make sure TRB is fully written before giving it to the controller */
2877 trb->field[3] = cpu_to_le32(field4);
2879 trace_xhci_queue_trb(ring, trb);
2881 inc_enq(xhci, ring, more_trbs_coming);
2885 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2886 * FIXME allocate segments if the ring is full.
2888 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2889 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2891 unsigned int num_trbs_needed;
2893 /* Make sure the endpoint has been added to xHC schedule */
2895 case EP_STATE_DISABLED:
2897 * USB core changed config/interfaces without notifying us,
2898 * or hardware is reporting the wrong state.
2900 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2902 case EP_STATE_ERROR:
2903 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2904 /* FIXME event handling code for error needs to clear it */
2905 /* XXX not sure if this should be -ENOENT or not */
2907 case EP_STATE_HALTED:
2908 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2909 case EP_STATE_STOPPED:
2910 case EP_STATE_RUNNING:
2913 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2915 * FIXME issue Configure Endpoint command to try to get the HC
2916 * back into a known state.
2922 if (room_on_ring(xhci, ep_ring, num_trbs))
2925 if (ep_ring == xhci->cmd_ring) {
2926 xhci_err(xhci, "Do not support expand command ring\n");
2930 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2931 "ERROR no room on ep ring, try ring expansion");
2932 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2933 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2935 xhci_err(xhci, "Ring expansion failed\n");
2940 while (trb_is_link(ep_ring->enqueue)) {
2941 /* If we're not dealing with 0.95 hardware or isoc rings
2942 * on AMD 0.96 host, clear the chain bit.
2944 if (!xhci_link_trb_quirk(xhci) &&
2945 !(ep_ring->type == TYPE_ISOC &&
2946 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2947 ep_ring->enqueue->link.control &=
2948 cpu_to_le32(~TRB_CHAIN);
2950 ep_ring->enqueue->link.control |=
2951 cpu_to_le32(TRB_CHAIN);
2954 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
2956 /* Toggle the cycle bit after the last ring segment. */
2957 if (link_trb_toggles_cycle(ep_ring->enqueue))
2958 ep_ring->cycle_state ^= 1;
2960 ep_ring->enq_seg = ep_ring->enq_seg->next;
2961 ep_ring->enqueue = ep_ring->enq_seg->trbs;
2966 static int prepare_transfer(struct xhci_hcd *xhci,
2967 struct xhci_virt_device *xdev,
2968 unsigned int ep_index,
2969 unsigned int stream_id,
2970 unsigned int num_trbs,
2972 unsigned int td_index,
2976 struct urb_priv *urb_priv;
2978 struct xhci_ring *ep_ring;
2979 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2981 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2983 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2988 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
2989 num_trbs, mem_flags);
2993 urb_priv = urb->hcpriv;
2994 td = &urb_priv->td[td_index];
2996 INIT_LIST_HEAD(&td->td_list);
2997 INIT_LIST_HEAD(&td->cancelled_td_list);
2999 if (td_index == 0) {
3000 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3006 /* Add this TD to the tail of the endpoint ring's TD list */
3007 list_add_tail(&td->td_list, &ep_ring->td_list);
3008 td->start_seg = ep_ring->enq_seg;
3009 td->first_trb = ep_ring->enqueue;
3014 unsigned int count_trbs(u64 addr, u64 len)
3016 unsigned int num_trbs;
3018 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3026 static inline unsigned int count_trbs_needed(struct urb *urb)
3028 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3031 static unsigned int count_sg_trbs_needed(struct urb *urb)
3033 struct scatterlist *sg;
3034 unsigned int i, len, full_len, num_trbs = 0;
3036 full_len = urb->transfer_buffer_length;
3038 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3039 len = sg_dma_len(sg);
3040 num_trbs += count_trbs(sg_dma_address(sg), len);
3041 len = min_t(unsigned int, len, full_len);
3050 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3054 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3055 len = urb->iso_frame_desc[i].length;
3057 return count_trbs(addr, len);
3060 static void check_trb_math(struct urb *urb, int running_total)
3062 if (unlikely(running_total != urb->transfer_buffer_length))
3063 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3064 "queued %#x (%d), asked for %#x (%d)\n",
3066 urb->ep->desc.bEndpointAddress,
3067 running_total, running_total,
3068 urb->transfer_buffer_length,
3069 urb->transfer_buffer_length);
3072 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3073 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3074 struct xhci_generic_trb *start_trb)
3077 * Pass all the TRBs to the hardware at once and make sure this write
3082 start_trb->field[3] |= cpu_to_le32(start_cycle);
3084 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3085 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3088 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3089 struct xhci_ep_ctx *ep_ctx)
3094 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3095 ep_interval = urb->interval;
3097 /* Convert to microframes */
3098 if (urb->dev->speed == USB_SPEED_LOW ||
3099 urb->dev->speed == USB_SPEED_FULL)
3102 /* FIXME change this to a warning and a suggestion to use the new API
3103 * to set the polling interval (once the API is added).
3105 if (xhci_interval != ep_interval) {
3106 dev_dbg_ratelimited(&urb->dev->dev,
3107 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3108 ep_interval, ep_interval == 1 ? "" : "s",
3109 xhci_interval, xhci_interval == 1 ? "" : "s");
3110 urb->interval = xhci_interval;
3111 /* Convert back to frames for LS/FS devices */
3112 if (urb->dev->speed == USB_SPEED_LOW ||
3113 urb->dev->speed == USB_SPEED_FULL)
3119 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3120 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3121 * (comprised of sg list entries) can take several service intervals to
3124 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3125 struct urb *urb, int slot_id, unsigned int ep_index)
3127 struct xhci_ep_ctx *ep_ctx;
3129 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3130 check_interval(xhci, urb, ep_ctx);
3132 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3136 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3137 * packets remaining in the TD (*not* including this TRB).
3139 * Total TD packet count = total_packet_count =
3140 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3142 * Packets transferred up to and including this TRB = packets_transferred =
3143 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3145 * TD size = total_packet_count - packets_transferred
3147 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3148 * including this TRB, right shifted by 10
3150 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3151 * This is taken care of in the TRB_TD_SIZE() macro
3153 * The last TRB in a TD must have the TD size set to zero.
3155 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3156 int trb_buff_len, unsigned int td_total_len,
3157 struct urb *urb, bool more_trbs_coming)
3159 u32 maxp, total_packet_count;
3161 /* MTK xHCI 0.96 contains some features from 1.0 */
3162 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3163 return ((td_total_len - transferred) >> 10);
3165 /* One TRB with a zero-length data packet. */
3166 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3167 trb_buff_len == td_total_len)
3170 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3171 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3174 maxp = usb_endpoint_maxp(&urb->ep->desc);
3175 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3177 /* Queueing functions don't count the current TRB into transferred */
3178 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3182 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3183 u32 *trb_buff_len, struct xhci_segment *seg)
3185 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3186 unsigned int unalign;
3187 unsigned int max_pkt;
3191 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3192 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3194 /* we got lucky, last normal TRB data on segment is packet aligned */
3198 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3199 unalign, *trb_buff_len);
3201 /* is the last nornal TRB alignable by splitting it */
3202 if (*trb_buff_len > unalign) {
3203 *trb_buff_len -= unalign;
3204 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3209 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3210 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3211 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3213 new_buff_len = max_pkt - (enqd_len % max_pkt);
3215 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3216 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3218 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3219 if (usb_urb_dir_out(urb)) {
3221 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3222 seg->bounce_buf, new_buff_len, enqd_len);
3223 if (len != new_buff_len)
3224 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3227 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3230 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3231 max_pkt, DMA_TO_DEVICE);
3233 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3234 max_pkt, DMA_FROM_DEVICE);
3237 if (dma_mapping_error(dev, seg->bounce_dma)) {
3238 /* try without aligning. Some host controllers survive */
3239 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3242 *trb_buff_len = new_buff_len;
3243 seg->bounce_len = new_buff_len;
3244 seg->bounce_offs = enqd_len;
3246 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3251 /* This is very similar to what ehci-q.c qtd_fill() does */
3252 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3253 struct urb *urb, int slot_id, unsigned int ep_index)
3255 struct xhci_ring *ring;
3256 struct urb_priv *urb_priv;
3258 struct xhci_generic_trb *start_trb;
3259 struct scatterlist *sg = NULL;
3260 bool more_trbs_coming = true;
3261 bool need_zero_pkt = false;
3262 bool first_trb = true;
3263 unsigned int num_trbs;
3264 unsigned int start_cycle, num_sgs = 0;
3265 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3267 u32 field, length_field, remainder;
3268 u64 addr, send_addr;
3270 ring = xhci_urb_to_transfer_ring(xhci, urb);
3274 full_len = urb->transfer_buffer_length;
3275 /* If we have scatter/gather list, we use it. */
3277 num_sgs = urb->num_mapped_sgs;
3279 addr = (u64) sg_dma_address(sg);
3280 block_len = sg_dma_len(sg);
3281 num_trbs = count_sg_trbs_needed(urb);
3283 num_trbs = count_trbs_needed(urb);
3284 addr = (u64) urb->transfer_dma;
3285 block_len = full_len;
3287 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3288 ep_index, urb->stream_id,
3289 num_trbs, urb, 0, mem_flags);
3290 if (unlikely(ret < 0))
3293 urb_priv = urb->hcpriv;
3295 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3296 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3297 need_zero_pkt = true;
3299 td = &urb_priv->td[0];
3302 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3303 * until we've finished creating all the other TRBs. The ring's cycle
3304 * state may change as we enqueue the other TRBs, so save it too.
3306 start_trb = &ring->enqueue->generic;
3307 start_cycle = ring->cycle_state;
3310 /* Queue the TRBs, even if they are zero-length */
3311 for (enqd_len = 0; first_trb || enqd_len < full_len;
3312 enqd_len += trb_buff_len) {
3313 field = TRB_TYPE(TRB_NORMAL);
3315 /* TRB buffer should not cross 64KB boundaries */
3316 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3317 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3319 if (enqd_len + trb_buff_len > full_len)
3320 trb_buff_len = full_len - enqd_len;
3322 /* Don't change the cycle bit of the first TRB until later */
3325 if (start_cycle == 0)
3328 field |= ring->cycle_state;
3330 /* Chain all the TRBs together; clear the chain bit in the last
3331 * TRB to indicate it's the last TRB in the chain.
3333 if (enqd_len + trb_buff_len < full_len) {
3335 if (trb_is_link(ring->enqueue + 1)) {
3336 if (xhci_align_td(xhci, urb, enqd_len,
3339 send_addr = ring->enq_seg->bounce_dma;
3340 /* assuming TD won't span 2 segs */
3341 td->bounce_seg = ring->enq_seg;
3345 if (enqd_len + trb_buff_len >= full_len) {
3346 field &= ~TRB_CHAIN;
3348 more_trbs_coming = false;
3349 td->last_trb = ring->enqueue;
3352 /* Only set interrupt on short packet for IN endpoints */
3353 if (usb_urb_dir_in(urb))
3356 /* Set the TRB length, TD size, and interrupter fields. */
3357 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3358 full_len, urb, more_trbs_coming);
3360 length_field = TRB_LEN(trb_buff_len) |
3361 TRB_TD_SIZE(remainder) |
3364 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3365 lower_32_bits(send_addr),
3366 upper_32_bits(send_addr),
3370 addr += trb_buff_len;
3371 sent_len = trb_buff_len;
3373 while (sg && sent_len >= block_len) {
3376 sent_len -= block_len;
3378 if (num_sgs != 0 && sg) {
3379 block_len = sg_dma_len(sg);
3380 addr = (u64) sg_dma_address(sg);
3384 block_len -= sent_len;
3388 if (need_zero_pkt) {
3389 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3390 ep_index, urb->stream_id,
3391 1, urb, 1, mem_flags);
3392 urb_priv->td[1].last_trb = ring->enqueue;
3393 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3394 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3397 check_trb_math(urb, enqd_len);
3398 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3399 start_cycle, start_trb);
3403 /* Caller must have locked xhci->lock */
3404 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3405 struct urb *urb, int slot_id, unsigned int ep_index)
3407 struct xhci_ring *ep_ring;
3410 struct usb_ctrlrequest *setup;
3411 struct xhci_generic_trb *start_trb;
3414 struct urb_priv *urb_priv;
3417 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3422 * Need to copy setup packet into setup TRB, so we can't use the setup
3425 if (!urb->setup_packet)
3428 /* 1 TRB for setup, 1 for status */
3431 * Don't need to check if we need additional event data and normal TRBs,
3432 * since data in control transfers will never get bigger than 16MB
3433 * XXX: can we get a buffer that crosses 64KB boundaries?
3435 if (urb->transfer_buffer_length > 0)
3437 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3438 ep_index, urb->stream_id,
3439 num_trbs, urb, 0, mem_flags);
3443 urb_priv = urb->hcpriv;
3444 td = &urb_priv->td[0];
3447 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3448 * until we've finished creating all the other TRBs. The ring's cycle
3449 * state may change as we enqueue the other TRBs, so save it too.
3451 start_trb = &ep_ring->enqueue->generic;
3452 start_cycle = ep_ring->cycle_state;
3454 /* Queue setup TRB - see section 6.4.1.2.1 */
3455 /* FIXME better way to translate setup_packet into two u32 fields? */
3456 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3458 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3459 if (start_cycle == 0)
3462 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3463 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3464 if (urb->transfer_buffer_length > 0) {
3465 if (setup->bRequestType & USB_DIR_IN)
3466 field |= TRB_TX_TYPE(TRB_DATA_IN);
3468 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3472 queue_trb(xhci, ep_ring, true,
3473 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3474 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3475 TRB_LEN(8) | TRB_INTR_TARGET(0),
3476 /* Immediate data in pointer */
3479 /* If there's data, queue data TRBs */
3480 /* Only set interrupt on short packet for IN endpoints */
3481 if (usb_urb_dir_in(urb))
3482 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3484 field = TRB_TYPE(TRB_DATA);
3486 if (urb->transfer_buffer_length > 0) {
3487 u32 length_field, remainder;
3489 remainder = xhci_td_remainder(xhci, 0,
3490 urb->transfer_buffer_length,
3491 urb->transfer_buffer_length,
3493 length_field = TRB_LEN(urb->transfer_buffer_length) |
3494 TRB_TD_SIZE(remainder) |
3496 if (setup->bRequestType & USB_DIR_IN)
3497 field |= TRB_DIR_IN;
3498 queue_trb(xhci, ep_ring, true,
3499 lower_32_bits(urb->transfer_dma),
3500 upper_32_bits(urb->transfer_dma),
3502 field | ep_ring->cycle_state);
3505 /* Save the DMA address of the last TRB in the TD */
3506 td->last_trb = ep_ring->enqueue;
3508 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3509 /* If the device sent data, the status stage is an OUT transfer */
3510 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3514 queue_trb(xhci, ep_ring, false,
3518 /* Event on completion */
3519 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3521 giveback_first_trb(xhci, slot_id, ep_index, 0,
3522 start_cycle, start_trb);
3527 * The transfer burst count field of the isochronous TRB defines the number of
3528 * bursts that are required to move all packets in this TD. Only SuperSpeed
3529 * devices can burst up to bMaxBurst number of packets per service interval.
3530 * This field is zero based, meaning a value of zero in the field means one
3531 * burst. Basically, for everything but SuperSpeed devices, this field will be
3532 * zero. Only xHCI 1.0 host controllers support this field.
3534 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3535 struct urb *urb, unsigned int total_packet_count)
3537 unsigned int max_burst;
3539 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3542 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3543 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3547 * Returns the number of packets in the last "burst" of packets. This field is
3548 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3549 * the last burst packet count is equal to the total number of packets in the
3550 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3551 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3552 * contain 1 to (bMaxBurst + 1) packets.
3554 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3555 struct urb *urb, unsigned int total_packet_count)
3557 unsigned int max_burst;
3558 unsigned int residue;
3560 if (xhci->hci_version < 0x100)
3563 if (urb->dev->speed >= USB_SPEED_SUPER) {
3564 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3565 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3566 residue = total_packet_count % (max_burst + 1);
3567 /* If residue is zero, the last burst contains (max_burst + 1)
3568 * number of packets, but the TLBPC field is zero-based.
3574 if (total_packet_count == 0)
3576 return total_packet_count - 1;
3580 * Calculates Frame ID field of the isochronous TRB identifies the
3581 * target frame that the Interval associated with this Isochronous
3582 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3584 * Returns actual frame id on success, negative value on error.
3586 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3587 struct urb *urb, int index)
3589 int start_frame, ist, ret = 0;
3590 int start_frame_id, end_frame_id, current_frame_id;
3592 if (urb->dev->speed == USB_SPEED_LOW ||
3593 urb->dev->speed == USB_SPEED_FULL)
3594 start_frame = urb->start_frame + index * urb->interval;
3596 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3598 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3600 * If bit [3] of IST is cleared to '0', software can add a TRB no
3601 * later than IST[2:0] Microframes before that TRB is scheduled to
3603 * If bit [3] of IST is set to '1', software can add a TRB no later
3604 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3606 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3607 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3610 /* Software shall not schedule an Isoch TD with a Frame ID value that
3611 * is less than the Start Frame ID or greater than the End Frame ID,
3614 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3615 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3617 * Both the End Frame ID and Start Frame ID values are calculated
3618 * in microframes. When software determines the valid Frame ID value;
3619 * The End Frame ID value should be rounded down to the nearest Frame
3620 * boundary, and the Start Frame ID value should be rounded up to the
3621 * nearest Frame boundary.
3623 current_frame_id = readl(&xhci->run_regs->microframe_index);
3624 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3625 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3627 start_frame &= 0x7ff;
3628 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3629 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3631 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3632 __func__, index, readl(&xhci->run_regs->microframe_index),
3633 start_frame_id, end_frame_id, start_frame);
3635 if (start_frame_id < end_frame_id) {
3636 if (start_frame > end_frame_id ||
3637 start_frame < start_frame_id)
3639 } else if (start_frame_id > end_frame_id) {
3640 if ((start_frame > end_frame_id &&
3641 start_frame < start_frame_id))
3648 if (ret == -EINVAL || start_frame == start_frame_id) {
3649 start_frame = start_frame_id + 1;
3650 if (urb->dev->speed == USB_SPEED_LOW ||
3651 urb->dev->speed == USB_SPEED_FULL)
3652 urb->start_frame = start_frame;
3654 urb->start_frame = start_frame << 3;
3660 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3661 start_frame, current_frame_id, index,
3662 start_frame_id, end_frame_id);
3663 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3670 /* This is for isoc transfer */
3671 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3672 struct urb *urb, int slot_id, unsigned int ep_index)
3674 struct xhci_ring *ep_ring;
3675 struct urb_priv *urb_priv;
3677 int num_tds, trbs_per_td;
3678 struct xhci_generic_trb *start_trb;
3681 u32 field, length_field;
3682 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3683 u64 start_addr, addr;
3685 bool more_trbs_coming;
3686 struct xhci_virt_ep *xep;
3689 xep = &xhci->devs[slot_id]->eps[ep_index];
3690 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3692 num_tds = urb->number_of_packets;
3694 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3697 start_addr = (u64) urb->transfer_dma;
3698 start_trb = &ep_ring->enqueue->generic;
3699 start_cycle = ep_ring->cycle_state;
3701 urb_priv = urb->hcpriv;
3702 /* Queue the TRBs for each TD, even if they are zero-length */
3703 for (i = 0; i < num_tds; i++) {
3704 unsigned int total_pkt_count, max_pkt;
3705 unsigned int burst_count, last_burst_pkt_count;
3710 addr = start_addr + urb->iso_frame_desc[i].offset;
3711 td_len = urb->iso_frame_desc[i].length;
3712 td_remain_len = td_len;
3713 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3714 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3716 /* A zero-length transfer still involves at least one packet. */
3717 if (total_pkt_count == 0)
3719 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3720 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3721 urb, total_pkt_count);
3723 trbs_per_td = count_isoc_trbs_needed(urb, i);
3725 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3726 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3732 td = &urb_priv->td[i];
3734 /* use SIA as default, if frame id is used overwrite it */
3735 sia_frame_id = TRB_SIA;
3736 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3737 HCC_CFC(xhci->hcc_params)) {
3738 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3740 sia_frame_id = TRB_FRAME_ID(frame_id);
3743 * Set isoc specific data for the first TRB in a TD.
3744 * Prevent HW from getting the TRBs by keeping the cycle state
3745 * inverted in the first TDs isoc TRB.
3747 field = TRB_TYPE(TRB_ISOC) |
3748 TRB_TLBPC(last_burst_pkt_count) |
3750 (i ? ep_ring->cycle_state : !start_cycle);
3752 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3753 if (!xep->use_extended_tbc)
3754 field |= TRB_TBC(burst_count);
3756 /* fill the rest of the TRB fields, and remaining normal TRBs */
3757 for (j = 0; j < trbs_per_td; j++) {
3760 /* only first TRB is isoc, overwrite otherwise */
3762 field = TRB_TYPE(TRB_NORMAL) |
3763 ep_ring->cycle_state;
3765 /* Only set interrupt on short packet for IN EPs */
3766 if (usb_urb_dir_in(urb))
3769 /* Set the chain bit for all except the last TRB */
3770 if (j < trbs_per_td - 1) {
3771 more_trbs_coming = true;
3774 more_trbs_coming = false;
3775 td->last_trb = ep_ring->enqueue;
3777 /* set BEI, except for the last TD */
3778 if (xhci->hci_version >= 0x100 &&
3779 !(xhci->quirks & XHCI_AVOID_BEI) &&
3783 /* Calculate TRB length */
3784 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3785 if (trb_buff_len > td_remain_len)
3786 trb_buff_len = td_remain_len;
3788 /* Set the TRB length, TD size, & interrupter fields. */
3789 remainder = xhci_td_remainder(xhci, running_total,
3790 trb_buff_len, td_len,
3791 urb, more_trbs_coming);
3793 length_field = TRB_LEN(trb_buff_len) |
3796 /* xhci 1.1 with ETE uses TD Size field for TBC */
3797 if (first_trb && xep->use_extended_tbc)
3798 length_field |= TRB_TD_SIZE_TBC(burst_count);
3800 length_field |= TRB_TD_SIZE(remainder);
3803 queue_trb(xhci, ep_ring, more_trbs_coming,
3804 lower_32_bits(addr),
3805 upper_32_bits(addr),
3808 running_total += trb_buff_len;
3810 addr += trb_buff_len;
3811 td_remain_len -= trb_buff_len;
3814 /* Check TD length */
3815 if (running_total != td_len) {
3816 xhci_err(xhci, "ISOC TD length unmatch\n");
3822 /* store the next frame id */
3823 if (HCC_CFC(xhci->hcc_params))
3824 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3826 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3827 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3828 usb_amd_quirk_pll_disable();
3830 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3832 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3833 start_cycle, start_trb);
3836 /* Clean up a partially enqueued isoc transfer. */
3838 for (i--; i >= 0; i--)
3839 list_del_init(&urb_priv->td[i].td_list);
3841 /* Use the first TD as a temporary variable to turn the TDs we've queued
3842 * into No-ops with a software-owned cycle bit. That way the hardware
3843 * won't accidentally start executing bogus TDs when we partially
3844 * overwrite them. td->first_trb and td->start_seg are already set.
3846 urb_priv->td[0].last_trb = ep_ring->enqueue;
3847 /* Every TRB except the first & last will have its cycle bit flipped. */
3848 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
3850 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3851 ep_ring->enqueue = urb_priv->td[0].first_trb;
3852 ep_ring->enq_seg = urb_priv->td[0].start_seg;
3853 ep_ring->cycle_state = start_cycle;
3854 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3855 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3860 * Check transfer ring to guarantee there is enough room for the urb.
3861 * Update ISO URB start_frame and interval.
3862 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3863 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3864 * Contiguous Frame ID is not supported by HC.
3866 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3867 struct urb *urb, int slot_id, unsigned int ep_index)
3869 struct xhci_virt_device *xdev;
3870 struct xhci_ring *ep_ring;
3871 struct xhci_ep_ctx *ep_ctx;
3873 int num_tds, num_trbs, i;
3875 struct xhci_virt_ep *xep;
3878 xdev = xhci->devs[slot_id];
3879 xep = &xhci->devs[slot_id]->eps[ep_index];
3880 ep_ring = xdev->eps[ep_index].ring;
3881 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3884 num_tds = urb->number_of_packets;
3885 for (i = 0; i < num_tds; i++)
3886 num_trbs += count_isoc_trbs_needed(urb, i);
3888 /* Check the ring to guarantee there is enough room for the whole urb.
3889 * Do not insert any td of the urb to the ring if the check failed.
3891 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3892 num_trbs, mem_flags);
3897 * Check interval value. This should be done before we start to
3898 * calculate the start frame value.
3900 check_interval(xhci, urb, ep_ctx);
3902 /* Calculate the start frame and put it in urb->start_frame. */
3903 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3904 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
3905 urb->start_frame = xep->next_frame_id;
3906 goto skip_start_over;
3910 start_frame = readl(&xhci->run_regs->microframe_index);
3911 start_frame &= 0x3fff;
3913 * Round up to the next frame and consider the time before trb really
3914 * gets scheduled by hardare.
3916 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3917 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3919 start_frame += ist + XHCI_CFC_DELAY;
3920 start_frame = roundup(start_frame, 8);
3923 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
3924 * is greate than 8 microframes.
3926 if (urb->dev->speed == USB_SPEED_LOW ||
3927 urb->dev->speed == USB_SPEED_FULL) {
3928 start_frame = roundup(start_frame, urb->interval << 3);
3929 urb->start_frame = start_frame >> 3;
3931 start_frame = roundup(start_frame, urb->interval);
3932 urb->start_frame = start_frame;
3936 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3938 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3941 /**** Command Ring Operations ****/
3943 /* Generic function for queueing a command TRB on the command ring.
3944 * Check to make sure there's room on the command ring for one command TRB.
3945 * Also check that there's room reserved for commands that must not fail.
3946 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3947 * then only check for the number of reserved spots.
3948 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3949 * because the command event handler may want to resubmit a failed command.
3951 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3952 u32 field1, u32 field2,
3953 u32 field3, u32 field4, bool command_must_succeed)
3955 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3958 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3959 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3960 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
3964 if (!command_must_succeed)
3967 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3968 reserved_trbs, GFP_ATOMIC);
3970 xhci_err(xhci, "ERR: No room for command on command ring\n");
3971 if (command_must_succeed)
3972 xhci_err(xhci, "ERR: Reserved TRB counting for "
3973 "unfailable commands failed.\n");
3977 cmd->command_trb = xhci->cmd_ring->enqueue;
3979 /* if there are no other commands queued we start the timeout timer */
3980 if (list_empty(&xhci->cmd_list)) {
3981 xhci->current_cmd = cmd;
3982 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
3985 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3987 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3988 field4 | xhci->cmd_ring->cycle_state);
3992 /* Queue a slot enable or disable request on the command ring */
3993 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3994 u32 trb_type, u32 slot_id)
3996 return queue_command(xhci, cmd, 0, 0, 0,
3997 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4000 /* Queue an address device command TRB */
4001 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4002 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4004 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4005 upper_32_bits(in_ctx_ptr), 0,
4006 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4007 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4010 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4011 u32 field1, u32 field2, u32 field3, u32 field4)
4013 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4016 /* Queue a reset device command TRB */
4017 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4020 return queue_command(xhci, cmd, 0, 0, 0,
4021 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4025 /* Queue a configure endpoint command TRB */
4026 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4027 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4028 u32 slot_id, bool command_must_succeed)
4030 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4031 upper_32_bits(in_ctx_ptr), 0,
4032 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4033 command_must_succeed);
4036 /* Queue an evaluate context command TRB */
4037 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4038 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4040 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4041 upper_32_bits(in_ctx_ptr), 0,
4042 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4043 command_must_succeed);
4047 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4048 * activity on an endpoint that is about to be suspended.
4050 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4051 int slot_id, unsigned int ep_index, int suspend)
4053 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4054 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4055 u32 type = TRB_TYPE(TRB_STOP_RING);
4056 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4058 return queue_command(xhci, cmd, 0, 0, 0,
4059 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4062 /* Set Transfer Ring Dequeue Pointer command */
4063 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4064 unsigned int slot_id, unsigned int ep_index,
4065 struct xhci_dequeue_state *deq_state)
4068 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4069 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4070 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4072 u32 type = TRB_TYPE(TRB_SET_DEQ);
4073 struct xhci_virt_ep *ep;
4074 struct xhci_command *cmd;
4077 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4078 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4079 deq_state->new_deq_seg,
4080 (unsigned long long)deq_state->new_deq_seg->dma,
4081 deq_state->new_deq_ptr,
4082 (unsigned long long)xhci_trb_virt_to_dma(
4083 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4084 deq_state->new_cycle_state);
4086 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4087 deq_state->new_deq_ptr);
4089 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4090 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4091 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4094 ep = &xhci->devs[slot_id]->eps[ep_index];
4095 if ((ep->ep_state & SET_DEQ_PENDING)) {
4096 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4097 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4101 /* This function gets called from contexts where it cannot sleep */
4102 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
4106 ep->queued_deq_seg = deq_state->new_deq_seg;
4107 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4108 if (deq_state->stream_id)
4109 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4110 ret = queue_command(xhci, cmd,
4111 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4112 upper_32_bits(addr), trb_stream_id,
4113 trb_slot_id | trb_ep_index | type, false);
4115 xhci_free_command(xhci, cmd);
4119 /* Stop the TD queueing code from ringing the doorbell until
4120 * this command completes. The HC won't set the dequeue pointer
4121 * if the ring is running, and ringing the doorbell starts the
4124 ep->ep_state |= SET_DEQ_PENDING;
4127 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4128 int slot_id, unsigned int ep_index,
4129 enum xhci_ep_reset_type reset_type)
4131 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4132 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4133 u32 type = TRB_TYPE(TRB_RESET_EP);
4135 if (reset_type == EP_SOFT_RESET)
4138 return queue_command(xhci, cmd, 0, 0, 0,
4139 trb_slot_id | trb_ep_index | type, false);