2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
69 #include <linux/dma-mapping.h>
71 #include "xhci-trace.h"
75 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
78 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
81 unsigned long segment_offset;
83 if (!seg || !trb || trb < seg->trbs)
86 segment_offset = trb - seg->trbs;
87 if (segment_offset >= TRBS_PER_SEGMENT)
89 return seg->dma + (segment_offset * sizeof(*trb));
92 static bool trb_is_link(union xhci_trb *trb)
94 return TRB_TYPE_LINK_LE32(trb->link.control);
97 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
99 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
102 static bool last_trb_on_ring(struct xhci_ring *ring,
103 struct xhci_segment *seg, union xhci_trb *trb)
105 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
108 static bool link_trb_toggles_cycle(union xhci_trb *trb)
110 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
113 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
114 * TRB is in a new segment. This does not skip over link TRBs, and it does not
115 * effect the ring dequeue or enqueue pointers.
117 static void next_trb(struct xhci_hcd *xhci,
118 struct xhci_ring *ring,
119 struct xhci_segment **seg,
120 union xhci_trb **trb)
122 if (trb_is_link(*trb)) {
124 *trb = ((*seg)->trbs);
131 * See Cycle bit rules. SW is the consumer for the event ring only.
132 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
134 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
138 /* event ring doesn't have link trbs, check for last trb */
139 if (ring->type == TYPE_EVENT) {
140 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
144 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
145 ring->cycle_state ^= 1;
146 ring->deq_seg = ring->deq_seg->next;
147 ring->dequeue = ring->deq_seg->trbs;
151 /* All other rings have link trbs */
152 if (!trb_is_link(ring->dequeue)) {
154 ring->num_trbs_free++;
156 while (trb_is_link(ring->dequeue)) {
157 ring->deq_seg = ring->deq_seg->next;
158 ring->dequeue = ring->deq_seg->trbs;
164 * See Cycle bit rules. SW is the consumer for the event ring only.
165 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
167 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
168 * chain bit is set), then set the chain bit in all the following link TRBs.
169 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
170 * have their chain bit cleared (so that each Link TRB is a separate TD).
172 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
173 * set, but other sections talk about dealing with the chain bit set. This was
174 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
175 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
177 * @more_trbs_coming: Will you enqueue more TRBs before calling
178 * prepare_transfer()?
180 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
181 bool more_trbs_coming)
184 union xhci_trb *next;
186 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
187 /* If this is not event ring, there is one less usable TRB */
188 if (!trb_is_link(ring->enqueue))
189 ring->num_trbs_free--;
190 next = ++(ring->enqueue);
193 /* Update the dequeue pointer further if that was a link TRB */
194 while (trb_is_link(next)) {
197 * If the caller doesn't plan on enqueueing more TDs before
198 * ringing the doorbell, then we don't want to give the link TRB
199 * to the hardware just yet. We'll give the link TRB back in
200 * prepare_ring() just before we enqueue the TD at the top of
203 if (!chain && !more_trbs_coming)
206 /* If we're not dealing with 0.95 hardware or isoc rings on
207 * AMD 0.96 host, carry over the chain bit of the previous TRB
208 * (which may mean the chain bit is cleared).
210 if (!(ring->type == TYPE_ISOC &&
211 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
212 !xhci_link_trb_quirk(xhci)) {
213 next->link.control &= cpu_to_le32(~TRB_CHAIN);
214 next->link.control |= cpu_to_le32(chain);
216 /* Give this link TRB to the hardware */
218 next->link.control ^= cpu_to_le32(TRB_CYCLE);
220 /* Toggle the cycle bit after the last ring segment. */
221 if (link_trb_toggles_cycle(next))
222 ring->cycle_state ^= 1;
224 ring->enq_seg = ring->enq_seg->next;
225 ring->enqueue = ring->enq_seg->trbs;
226 next = ring->enqueue;
231 * Check to see if there's room to enqueue num_trbs on the ring and make sure
232 * enqueue pointer will not advance into dequeue segment. See rules above.
234 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
235 unsigned int num_trbs)
237 int num_trbs_in_deq_seg;
239 if (ring->num_trbs_free < num_trbs)
242 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
243 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
244 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
251 /* Ring the host controller doorbell after placing a command on the ring */
252 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
254 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
257 xhci_dbg(xhci, "// Ding dong!\n");
258 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
259 /* Flush PCI posted writes */
260 readl(&xhci->dba->doorbell[0]);
263 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
265 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
268 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
270 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
275 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
276 * If there are other commands waiting then restart the ring and kick the timer.
277 * This must be called with command ring stopped and xhci->lock held.
279 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
280 struct xhci_command *cur_cmd)
282 struct xhci_command *i_cmd;
285 /* Turn all aborted commands in list to no-ops, then restart */
286 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
288 if (i_cmd->status != COMP_CMD_ABORT)
291 i_cmd->status = COMP_CMD_STOP;
293 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
295 /* get cycle state from the original cmd trb */
296 cycle_state = le32_to_cpu(
297 i_cmd->command_trb->generic.field[3]) & TRB_CYCLE;
298 /* modify the command trb to no-op command */
299 i_cmd->command_trb->generic.field[0] = 0;
300 i_cmd->command_trb->generic.field[1] = 0;
301 i_cmd->command_trb->generic.field[2] = 0;
302 i_cmd->command_trb->generic.field[3] = cpu_to_le32(
303 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
306 * caller waiting for completion is called when command
307 * completion event is received for these no-op commands
311 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
313 /* ring command ring doorbell to restart the command ring */
314 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
315 !(xhci->xhc_state & XHCI_STATE_DYING)) {
316 xhci->current_cmd = cur_cmd;
317 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
318 xhci_ring_cmd_db(xhci);
322 /* Must be called with xhci->lock held, releases and aquires lock back */
323 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
328 xhci_dbg(xhci, "Abort command ring\n");
330 reinit_completion(&xhci->cmd_ring_stop_completion);
332 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
333 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
334 &xhci->op_regs->cmd_ring);
336 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
337 * time the completion od all xHCI commands, including
338 * the Command Abort operation. If software doesn't see
339 * CRR negated in a timely manner (e.g. longer than 5
340 * seconds), then it should assume that the there are
341 * larger problems with the xHC and assert HCRST.
343 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
344 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
346 /* we are about to kill xhci, give it one more chance */
347 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
348 &xhci->op_regs->cmd_ring);
350 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
351 CMD_RING_RUNNING, 0, 3 * 1000 * 1000);
353 xhci_err(xhci, "Stopped the command ring failed, "
354 "maybe the host is dead\n");
355 xhci->xhc_state |= XHCI_STATE_DYING;
362 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
363 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
364 * but the completion event in never sent. Wait 2 secs (arbitrary
365 * number) to handle those cases after negation of CMD_RING_RUNNING.
367 spin_unlock_irqrestore(&xhci->lock, flags);
368 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
369 msecs_to_jiffies(2000));
370 spin_lock_irqsave(&xhci->lock, flags);
372 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
373 xhci_cleanup_command_queue(xhci);
375 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
381 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
382 unsigned int slot_id,
383 unsigned int ep_index,
384 unsigned int stream_id)
386 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
387 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
388 unsigned int ep_state = ep->ep_state;
390 /* Don't ring the doorbell for this endpoint if there are pending
391 * cancellations because we don't want to interrupt processing.
392 * We don't want to restart any stream rings if there's a set dequeue
393 * pointer command pending because the device can choose to start any
394 * stream once the endpoint is on the HW schedule.
396 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
397 (ep_state & EP_HALTED))
399 writel(DB_VALUE(ep_index, stream_id), db_addr);
400 /* The CPU has better things to do at this point than wait for a
401 * write-posting flush. It'll get there soon enough.
405 /* Ring the doorbell for any rings with pending URBs */
406 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
407 unsigned int slot_id,
408 unsigned int ep_index)
410 unsigned int stream_id;
411 struct xhci_virt_ep *ep;
413 ep = &xhci->devs[slot_id]->eps[ep_index];
415 /* A ring has pending URBs if its TD list is not empty */
416 if (!(ep->ep_state & EP_HAS_STREAMS)) {
417 if (ep->ring && !(list_empty(&ep->ring->td_list)))
418 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
422 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
424 struct xhci_stream_info *stream_info = ep->stream_info;
425 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
426 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
431 /* Get the right ring for the given slot_id, ep_index and stream_id.
432 * If the endpoint supports streams, boundary check the URB's stream ID.
433 * If the endpoint doesn't support streams, return the singular endpoint ring.
435 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
436 unsigned int slot_id, unsigned int ep_index,
437 unsigned int stream_id)
439 struct xhci_virt_ep *ep;
441 ep = &xhci->devs[slot_id]->eps[ep_index];
442 /* Common case: no streams */
443 if (!(ep->ep_state & EP_HAS_STREAMS))
446 if (stream_id == 0) {
448 "WARN: Slot ID %u, ep index %u has streams, "
449 "but URB has no stream ID.\n",
454 if (stream_id < ep->stream_info->num_streams)
455 return ep->stream_info->stream_rings[stream_id];
458 "WARN: Slot ID %u, ep index %u has "
459 "stream IDs 1 to %u allocated, "
460 "but stream ID %u is requested.\n",
462 ep->stream_info->num_streams - 1,
468 * Move the xHC's endpoint ring dequeue pointer past cur_td.
469 * Record the new state of the xHC's endpoint ring dequeue segment,
470 * dequeue pointer, and new consumer cycle state in state.
471 * Update our internal representation of the ring's dequeue pointer.
473 * We do this in three jumps:
474 * - First we update our new ring state to be the same as when the xHC stopped.
475 * - Then we traverse the ring to find the segment that contains
476 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
477 * any link TRBs with the toggle cycle bit set.
478 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
479 * if we've moved it past a link TRB with the toggle cycle bit set.
481 * Some of the uses of xhci_generic_trb are grotty, but if they're done
482 * with correct __le32 accesses they should work fine. Only users of this are
485 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
486 unsigned int slot_id, unsigned int ep_index,
487 unsigned int stream_id, struct xhci_td *cur_td,
488 struct xhci_dequeue_state *state)
490 struct xhci_virt_device *dev = xhci->devs[slot_id];
491 struct xhci_virt_ep *ep = &dev->eps[ep_index];
492 struct xhci_ring *ep_ring;
493 struct xhci_segment *new_seg;
494 union xhci_trb *new_deq;
497 bool cycle_found = false;
498 bool td_last_trb_found = false;
500 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
501 ep_index, stream_id);
503 xhci_warn(xhci, "WARN can't find new dequeue state "
504 "for invalid stream ID %u.\n",
509 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
510 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
511 "Finding endpoint context");
512 /* 4.6.9 the css flag is written to the stream context for streams */
513 if (ep->ep_state & EP_HAS_STREAMS) {
514 struct xhci_stream_ctx *ctx =
515 &ep->stream_info->stream_ctx_array[stream_id];
516 hw_dequeue = le64_to_cpu(ctx->stream_ring);
518 struct xhci_ep_ctx *ep_ctx
519 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
520 hw_dequeue = le64_to_cpu(ep_ctx->deq);
523 new_seg = ep_ring->deq_seg;
524 new_deq = ep_ring->dequeue;
525 state->new_cycle_state = hw_dequeue & 0x1;
528 * We want to find the pointer, segment and cycle state of the new trb
529 * (the one after current TD's last_trb). We know the cycle state at
530 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
534 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
535 == (dma_addr_t)(hw_dequeue & ~0xf)) {
537 if (td_last_trb_found)
540 if (new_deq == cur_td->last_trb)
541 td_last_trb_found = true;
544 TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
545 new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
546 state->new_cycle_state ^= 0x1;
548 next_trb(xhci, ep_ring, &new_seg, &new_deq);
550 /* Search wrapped around, bail out */
551 if (new_deq == ep->ring->dequeue) {
552 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
553 state->new_deq_seg = NULL;
554 state->new_deq_ptr = NULL;
558 } while (!cycle_found || !td_last_trb_found);
560 state->new_deq_seg = new_seg;
561 state->new_deq_ptr = new_deq;
563 /* Don't update the ring cycle state for the producer (us). */
564 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
565 "Cycle state = 0x%x", state->new_cycle_state);
567 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
568 "New dequeue segment = %p (virtual)",
570 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
571 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
572 "New dequeue pointer = 0x%llx (DMA)",
573 (unsigned long long) addr);
576 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
577 * (The last TRB actually points to the ring enqueue pointer, which is not part
578 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
580 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
581 struct xhci_td *cur_td, bool flip_cycle)
583 struct xhci_segment *cur_seg;
584 union xhci_trb *cur_trb;
586 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
588 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
589 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
590 /* Unchain any chained Link TRBs, but
591 * leave the pointers intact.
593 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
594 /* Flip the cycle bit (link TRBs can't be the first
598 cur_trb->generic.field[3] ^=
599 cpu_to_le32(TRB_CYCLE);
600 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
601 "Cancel (unchain) link TRB");
602 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
603 "Address = %p (0x%llx dma); "
604 "in seg %p (0x%llx dma)",
606 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
608 (unsigned long long)cur_seg->dma);
610 cur_trb->generic.field[0] = 0;
611 cur_trb->generic.field[1] = 0;
612 cur_trb->generic.field[2] = 0;
613 /* Preserve only the cycle bit of this TRB */
614 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
615 /* Flip the cycle bit except on the first or last TRB */
616 if (flip_cycle && cur_trb != cur_td->first_trb &&
617 cur_trb != cur_td->last_trb)
618 cur_trb->generic.field[3] ^=
619 cpu_to_le32(TRB_CYCLE);
620 cur_trb->generic.field[3] |= cpu_to_le32(
621 TRB_TYPE(TRB_TR_NOOP));
622 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
623 "TRB to noop at offset 0x%llx",
625 xhci_trb_virt_to_dma(cur_seg, cur_trb));
627 if (cur_trb == cur_td->last_trb)
632 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
633 struct xhci_virt_ep *ep)
635 ep->ep_state &= ~EP_HALT_PENDING;
636 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
637 * timer is running on another CPU, we don't decrement stop_cmds_pending
638 * (since we didn't successfully stop the watchdog timer).
640 if (del_timer(&ep->stop_cmd_timer))
641 ep->stop_cmds_pending--;
644 /* Must be called with xhci->lock held in interrupt context */
645 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
646 struct xhci_td *cur_td, int status)
650 struct urb_priv *urb_priv;
653 urb_priv = urb->hcpriv;
655 hcd = bus_to_hcd(urb->dev->bus);
657 /* Only giveback urb when this is the last td in urb */
658 if (urb_priv->td_cnt == urb_priv->length) {
659 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
660 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
661 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
662 if (xhci->quirks & XHCI_AMD_PLL_FIX)
663 usb_amd_quirk_pll_enable();
666 usb_hcd_unlink_urb_from_ep(hcd, urb);
668 spin_unlock(&xhci->lock);
669 usb_hcd_giveback_urb(hcd, urb, status);
670 xhci_urb_free_priv(urb_priv);
671 spin_lock(&xhci->lock);
675 void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, struct xhci_ring *ring,
678 struct device *dev = xhci_to_hcd(xhci)->self.controller;
679 struct xhci_segment *seg = td->bounce_seg;
680 struct urb *urb = td->urb;
686 if (usb_urb_dir_out(urb)) {
687 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
692 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
694 /* for in tranfers we need to copy the data from bounce to sg */
696 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
697 seg->bounce_len, seg->bounce_offs);
698 if (len != seg->bounce_len)
699 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
700 len, seg->bounce_len);
702 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
706 seg->bounce_offs = 0;
710 * When we get a command completion for a Stop Endpoint Command, we need to
711 * unlink any cancelled TDs from the ring. There are two ways to do that:
713 * 1. If the HW was in the middle of processing the TD that needs to be
714 * cancelled, then we must move the ring's dequeue pointer past the last TRB
715 * in the TD with a Set Dequeue Pointer Command.
716 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
717 * bit cleared) so that the HW will skip over them.
719 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
720 union xhci_trb *trb, struct xhci_event_cmd *event)
722 unsigned int ep_index;
723 struct xhci_ring *ep_ring;
724 struct xhci_virt_ep *ep;
725 struct list_head *entry;
726 struct xhci_td *cur_td = NULL;
727 struct xhci_td *last_unlinked_td;
729 struct xhci_dequeue_state deq_state;
731 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
732 if (!xhci->devs[slot_id])
733 xhci_warn(xhci, "Stop endpoint command "
734 "completion for disabled slot %u\n",
739 memset(&deq_state, 0, sizeof(deq_state));
740 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
741 ep = &xhci->devs[slot_id]->eps[ep_index];
743 if (list_empty(&ep->cancelled_td_list)) {
744 xhci_stop_watchdog_timer_in_irq(xhci, ep);
745 ep->stopped_td = NULL;
746 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
750 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
751 * We have the xHCI lock, so nothing can modify this list until we drop
752 * it. We're also in the event handler, so we can't get re-interrupted
753 * if another Stop Endpoint command completes
755 list_for_each(entry, &ep->cancelled_td_list) {
756 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
757 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
758 "Removing canceled TD starting at 0x%llx (dma).",
759 (unsigned long long)xhci_trb_virt_to_dma(
760 cur_td->start_seg, cur_td->first_trb));
761 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
763 /* This shouldn't happen unless a driver is mucking
764 * with the stream ID after submission. This will
765 * leave the TD on the hardware ring, and the hardware
766 * will try to execute it, and may access a buffer
767 * that has already been freed. In the best case, the
768 * hardware will execute it, and the event handler will
769 * ignore the completion event for that TD, since it was
770 * removed from the td_list for that endpoint. In
771 * short, don't muck with the stream ID after
774 xhci_warn(xhci, "WARN Cancelled URB %p "
775 "has invalid stream ID %u.\n",
777 cur_td->urb->stream_id);
778 goto remove_finished_td;
781 * If we stopped on the TD we need to cancel, then we have to
782 * move the xHC endpoint ring dequeue pointer past this TD.
784 if (cur_td == ep->stopped_td)
785 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
786 cur_td->urb->stream_id,
789 td_to_noop(xhci, ep_ring, cur_td, false);
792 * The event handler won't see a completion for this TD anymore,
793 * so remove it from the endpoint ring's TD list. Keep it in
794 * the cancelled TD list for URB completion later.
796 list_del_init(&cur_td->td_list);
798 last_unlinked_td = cur_td;
799 xhci_stop_watchdog_timer_in_irq(xhci, ep);
801 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
802 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
803 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
804 ep->stopped_td->urb->stream_id, &deq_state);
805 xhci_ring_cmd_db(xhci);
807 /* Otherwise ring the doorbell(s) to restart queued transfers */
808 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
811 ep->stopped_td = NULL;
814 * Drop the lock and complete the URBs in the cancelled TD list.
815 * New TDs to be cancelled might be added to the end of the list before
816 * we can complete all the URBs for the TDs we already unlinked.
817 * So stop when we've completed the URB for the last TD we unlinked.
820 cur_td = list_entry(ep->cancelled_td_list.next,
821 struct xhci_td, cancelled_td_list);
822 list_del_init(&cur_td->cancelled_td_list);
824 /* Clean up the cancelled URB */
825 /* Doesn't matter what we pass for status, since the core will
826 * just overwrite it (because the URB has been unlinked).
828 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
829 if (ep_ring && cur_td->bounce_seg)
830 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
831 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
833 /* Stop processing the cancelled list if the watchdog timer is
836 if (xhci->xhc_state & XHCI_STATE_DYING)
838 } while (cur_td != last_unlinked_td);
840 /* Return to the event handler with xhci->lock re-acquired */
843 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
845 struct xhci_td *cur_td;
847 while (!list_empty(&ring->td_list)) {
848 cur_td = list_first_entry(&ring->td_list,
849 struct xhci_td, td_list);
850 list_del_init(&cur_td->td_list);
851 if (!list_empty(&cur_td->cancelled_td_list))
852 list_del_init(&cur_td->cancelled_td_list);
854 if (cur_td->bounce_seg)
855 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
856 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
860 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
861 int slot_id, int ep_index)
863 struct xhci_td *cur_td;
864 struct xhci_virt_ep *ep;
865 struct xhci_ring *ring;
867 ep = &xhci->devs[slot_id]->eps[ep_index];
868 if ((ep->ep_state & EP_HAS_STREAMS) ||
869 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
872 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
874 ring = ep->stream_info->stream_rings[stream_id];
878 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
879 "Killing URBs for slot ID %u, ep index %u, stream %u",
880 slot_id, ep_index, stream_id);
881 xhci_kill_ring_urbs(xhci, ring);
887 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
888 "Killing URBs for slot ID %u, ep index %u",
890 xhci_kill_ring_urbs(xhci, ring);
892 while (!list_empty(&ep->cancelled_td_list)) {
893 cur_td = list_first_entry(&ep->cancelled_td_list,
894 struct xhci_td, cancelled_td_list);
895 list_del_init(&cur_td->cancelled_td_list);
896 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
900 /* Watchdog timer function for when a stop endpoint command fails to complete.
901 * In this case, we assume the host controller is broken or dying or dead. The
902 * host may still be completing some other events, so we have to be careful to
903 * let the event ring handler and the URB dequeueing/enqueueing functions know
904 * through xhci->state.
906 * The timer may also fire if the host takes a very long time to respond to the
907 * command, and the stop endpoint command completion handler cannot delete the
908 * timer before the timer function is called. Another endpoint cancellation may
909 * sneak in before the timer function can grab the lock, and that may queue
910 * another stop endpoint command and add the timer back. So we cannot use a
911 * simple flag to say whether there is a pending stop endpoint command for a
912 * particular endpoint.
914 * Instead we use a combination of that flag and a counter for the number of
915 * pending stop endpoint commands. If the timer is the tail end of the last
916 * stop endpoint command, and the endpoint's command is still pending, we assume
919 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
921 struct xhci_hcd *xhci;
922 struct xhci_virt_ep *ep;
926 ep = (struct xhci_virt_ep *) arg;
929 spin_lock_irqsave(&xhci->lock, flags);
931 ep->stop_cmds_pending--;
932 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
933 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
934 "Stop EP timer ran, but no command pending, "
936 spin_unlock_irqrestore(&xhci->lock, flags);
940 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
941 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
942 /* Oops, HC is dead or dying or at least not responding to the stop
945 xhci->xhc_state |= XHCI_STATE_DYING;
946 /* Disable interrupts from the host controller and start halting it */
948 spin_unlock_irqrestore(&xhci->lock, flags);
950 ret = xhci_halt(xhci);
952 spin_lock_irqsave(&xhci->lock, flags);
954 /* This is bad; the host is not responding to commands and it's
955 * not allowing itself to be halted. At least interrupts are
956 * disabled. If we call usb_hc_died(), it will attempt to
957 * disconnect all device drivers under this host. Those
958 * disconnect() methods will wait for all URBs to be unlinked,
959 * so we must complete them.
961 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
962 xhci_warn(xhci, "Completing active URBs anyway.\n");
963 /* We could turn all TDs on the rings to no-ops. This won't
964 * help if the host has cached part of the ring, and is slow if
965 * we want to preserve the cycle bit. Skip it and hope the host
966 * doesn't touch the memory.
969 for (i = 0; i < MAX_HC_SLOTS; i++) {
972 for (j = 0; j < 31; j++)
973 xhci_kill_endpoint_urbs(xhci, i, j);
975 spin_unlock_irqrestore(&xhci->lock, flags);
976 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
977 "Calling usb_hc_died()");
978 usb_hc_died(xhci_to_hcd(xhci));
979 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
980 "xHCI host controller is dead.");
984 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
985 struct xhci_virt_device *dev,
986 struct xhci_ring *ep_ring,
987 unsigned int ep_index)
989 union xhci_trb *dequeue_temp;
990 int num_trbs_free_temp;
993 num_trbs_free_temp = ep_ring->num_trbs_free;
994 dequeue_temp = ep_ring->dequeue;
996 /* If we get two back-to-back stalls, and the first stalled transfer
997 * ends just before a link TRB, the dequeue pointer will be left on
998 * the link TRB by the code in the while loop. So we have to update
999 * the dequeue pointer one segment further, or we'll jump off
1000 * the segment into la-la-land.
1002 if (trb_is_link(ep_ring->dequeue)) {
1003 ep_ring->deq_seg = ep_ring->deq_seg->next;
1004 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1007 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1008 /* We have more usable TRBs */
1009 ep_ring->num_trbs_free++;
1011 if (trb_is_link(ep_ring->dequeue)) {
1012 if (ep_ring->dequeue ==
1013 dev->eps[ep_index].queued_deq_ptr)
1015 ep_ring->deq_seg = ep_ring->deq_seg->next;
1016 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1018 if (ep_ring->dequeue == dequeue_temp) {
1025 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1026 ep_ring->num_trbs_free = num_trbs_free_temp;
1031 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1032 * we need to clear the set deq pending flag in the endpoint ring state, so that
1033 * the TD queueing code can ring the doorbell again. We also need to ring the
1034 * endpoint doorbell to restart the ring, but only if there aren't more
1035 * cancellations pending.
1037 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1038 union xhci_trb *trb, u32 cmd_comp_code)
1040 unsigned int ep_index;
1041 unsigned int stream_id;
1042 struct xhci_ring *ep_ring;
1043 struct xhci_virt_device *dev;
1044 struct xhci_virt_ep *ep;
1045 struct xhci_ep_ctx *ep_ctx;
1046 struct xhci_slot_ctx *slot_ctx;
1048 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1049 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1050 dev = xhci->devs[slot_id];
1051 ep = &dev->eps[ep_index];
1053 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1055 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1057 /* XXX: Harmless??? */
1061 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1062 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1064 if (cmd_comp_code != COMP_SUCCESS) {
1065 unsigned int ep_state;
1066 unsigned int slot_state;
1068 switch (cmd_comp_code) {
1070 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1072 case COMP_CTX_STATE:
1073 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1074 ep_state = le32_to_cpu(ep_ctx->ep_info);
1075 ep_state &= EP_STATE_MASK;
1076 slot_state = le32_to_cpu(slot_ctx->dev_state);
1077 slot_state = GET_SLOT_STATE(slot_state);
1078 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1079 "Slot state = %u, EP state = %u",
1080 slot_state, ep_state);
1083 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1087 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1091 /* OK what do we do now? The endpoint state is hosed, and we
1092 * should never get to this point if the synchronization between
1093 * queueing, and endpoint state are correct. This might happen
1094 * if the device gets disconnected after we've finished
1095 * cancelling URBs, which might not be an error...
1099 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1100 if (ep->ep_state & EP_HAS_STREAMS) {
1101 struct xhci_stream_ctx *ctx =
1102 &ep->stream_info->stream_ctx_array[stream_id];
1103 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1105 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1107 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1108 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1109 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1110 ep->queued_deq_ptr) == deq) {
1111 /* Update the ring's dequeue segment and dequeue pointer
1112 * to reflect the new position.
1114 update_ring_for_set_deq_completion(xhci, dev,
1117 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1118 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1119 ep->queued_deq_seg, ep->queued_deq_ptr);
1124 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1125 dev->eps[ep_index].queued_deq_seg = NULL;
1126 dev->eps[ep_index].queued_deq_ptr = NULL;
1127 /* Restart any rings with pending URBs */
1128 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1131 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1132 union xhci_trb *trb, u32 cmd_comp_code)
1134 unsigned int ep_index;
1136 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1137 /* This command will only fail if the endpoint wasn't halted,
1138 * but we don't care.
1140 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1141 "Ignoring reset ep completion code of %u", cmd_comp_code);
1143 /* HW with the reset endpoint quirk needs to have a configure endpoint
1144 * command complete before the endpoint can be used. Queue that here
1145 * because the HW can't handle two commands being queued in a row.
1147 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1148 struct xhci_command *command;
1149 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1151 xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n");
1154 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1155 "Queueing configure endpoint command");
1156 xhci_queue_configure_endpoint(xhci, command,
1157 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1159 xhci_ring_cmd_db(xhci);
1161 /* Clear our internal halted state */
1162 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1166 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1169 if (cmd_comp_code == COMP_SUCCESS)
1170 xhci->slot_id = slot_id;
1175 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1177 struct xhci_virt_device *virt_dev;
1179 virt_dev = xhci->devs[slot_id];
1182 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1183 /* Delete default control endpoint resources */
1184 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1185 xhci_free_virt_device(xhci, slot_id);
1188 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1189 struct xhci_event_cmd *event, u32 cmd_comp_code)
1191 struct xhci_virt_device *virt_dev;
1192 struct xhci_input_control_ctx *ctrl_ctx;
1193 unsigned int ep_index;
1194 unsigned int ep_state;
1195 u32 add_flags, drop_flags;
1198 * Configure endpoint commands can come from the USB core
1199 * configuration or alt setting changes, or because the HW
1200 * needed an extra configure endpoint command after a reset
1201 * endpoint command or streams were being configured.
1202 * If the command was for a halted endpoint, the xHCI driver
1203 * is not waiting on the configure endpoint command.
1205 virt_dev = xhci->devs[slot_id];
1206 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1208 xhci_warn(xhci, "Could not get input context, bad type.\n");
1212 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1213 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1214 /* Input ctx add_flags are the endpoint index plus one */
1215 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1217 /* A usb_set_interface() call directly after clearing a halted
1218 * condition may race on this quirky hardware. Not worth
1219 * worrying about, since this is prototype hardware. Not sure
1220 * if this will work for streams, but streams support was
1221 * untested on this prototype.
1223 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1224 ep_index != (unsigned int) -1 &&
1225 add_flags - SLOT_FLAG == drop_flags) {
1226 ep_state = virt_dev->eps[ep_index].ep_state;
1227 if (!(ep_state & EP_HALTED))
1229 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1230 "Completed config ep cmd - "
1231 "last ep index = %d, state = %d",
1232 ep_index, ep_state);
1233 /* Clear internal halted state and restart ring(s) */
1234 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1235 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1241 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1242 struct xhci_event_cmd *event)
1244 xhci_dbg(xhci, "Completed reset device command.\n");
1245 if (!xhci->devs[slot_id])
1246 xhci_warn(xhci, "Reset device command completion "
1247 "for disabled slot %u\n", slot_id);
1250 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1251 struct xhci_event_cmd *event)
1253 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1254 xhci->error_bitmask |= 1 << 6;
1257 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1258 "NEC firmware version %2x.%02x",
1259 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1260 NEC_FW_MINOR(le32_to_cpu(event->status)));
1263 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1265 list_del(&cmd->cmd_list);
1267 if (cmd->completion) {
1268 cmd->status = status;
1269 complete(cmd->completion);
1275 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1277 struct xhci_command *cur_cmd, *tmp_cmd;
1278 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1279 xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT);
1282 void xhci_handle_command_timeout(struct work_struct *work)
1284 struct xhci_hcd *xhci;
1286 unsigned long flags;
1289 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1291 spin_lock_irqsave(&xhci->lock, flags);
1294 * If timeout work is pending, or current_cmd is NULL, it means we
1295 * raced with command completion. Command is handled so just return.
1297 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1298 spin_unlock_irqrestore(&xhci->lock, flags);
1301 /* mark this command to be cancelled */
1302 xhci->current_cmd->status = COMP_CMD_ABORT;
1304 /* Make sure command ring is running before aborting it */
1305 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1306 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1307 (hw_ring_state & CMD_RING_RUNNING)) {
1308 /* Prevent new doorbell, and start command abort */
1309 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1310 xhci_dbg(xhci, "Command timeout\n");
1311 ret = xhci_abort_cmd_ring(xhci, flags);
1312 if (unlikely(ret == -ESHUTDOWN)) {
1313 xhci_err(xhci, "Abort command ring failed\n");
1314 xhci_cleanup_command_queue(xhci);
1315 spin_unlock_irqrestore(&xhci->lock, flags);
1316 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1317 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1322 goto time_out_completed;
1325 /* host removed. Bail out */
1326 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1327 xhci_dbg(xhci, "host removed, ring start fail?\n");
1328 xhci_cleanup_command_queue(xhci);
1330 goto time_out_completed;
1333 /* command timeout on stopped ring, ring can't be aborted */
1334 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1335 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1338 spin_unlock_irqrestore(&xhci->lock, flags);
1342 static void handle_cmd_completion(struct xhci_hcd *xhci,
1343 struct xhci_event_cmd *event)
1345 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1347 dma_addr_t cmd_dequeue_dma;
1349 union xhci_trb *cmd_trb;
1350 struct xhci_command *cmd;
1353 cmd_dma = le64_to_cpu(event->cmd_trb);
1354 cmd_trb = xhci->cmd_ring->dequeue;
1355 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1357 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1358 if (cmd_dequeue_dma == 0) {
1359 xhci->error_bitmask |= 1 << 4;
1362 /* Does the DMA address match our internal dequeue pointer address? */
1363 if (cmd_dma != (u64) cmd_dequeue_dma) {
1364 xhci->error_bitmask |= 1 << 5;
1368 cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list);
1370 cancel_delayed_work(&xhci->cmd_timer);
1372 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1374 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1376 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1377 if (cmd_comp_code == COMP_CMD_STOP) {
1378 complete_all(&xhci->cmd_ring_stop_completion);
1382 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1384 "Command completion event does not match command\n");
1389 * Host aborted the command ring, check if the current command was
1390 * supposed to be aborted, otherwise continue normally.
1391 * The command ring is stopped now, but the xHC will issue a Command
1392 * Ring Stopped event which will cause us to restart it.
1394 if (cmd_comp_code == COMP_CMD_ABORT) {
1395 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1396 if (cmd->status == COMP_CMD_ABORT) {
1397 if (xhci->current_cmd == cmd)
1398 xhci->current_cmd = NULL;
1403 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1405 case TRB_ENABLE_SLOT:
1406 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1408 case TRB_DISABLE_SLOT:
1409 xhci_handle_cmd_disable_slot(xhci, slot_id);
1412 if (!cmd->completion)
1413 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1416 case TRB_EVAL_CONTEXT:
1421 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1422 le32_to_cpu(cmd_trb->generic.field[3])));
1423 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1426 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1427 le32_to_cpu(cmd_trb->generic.field[3])));
1428 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1431 /* Is this an aborted command turned to NO-OP? */
1432 if (cmd->status == COMP_CMD_STOP)
1433 cmd_comp_code = COMP_CMD_STOP;
1436 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1437 le32_to_cpu(cmd_trb->generic.field[3])));
1438 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1441 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1442 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1444 slot_id = TRB_TO_SLOT_ID(
1445 le32_to_cpu(cmd_trb->generic.field[3]));
1446 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1448 case TRB_NEC_GET_FW:
1449 xhci_handle_cmd_nec_get_fw(xhci, event);
1452 /* Skip over unknown commands on the event ring */
1453 xhci->error_bitmask |= 1 << 6;
1457 /* restart timer if this wasn't the last command */
1458 if (cmd->cmd_list.next != &xhci->cmd_list) {
1459 xhci->current_cmd = list_entry(cmd->cmd_list.next,
1460 struct xhci_command, cmd_list);
1461 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1462 } else if (xhci->current_cmd == cmd) {
1463 xhci->current_cmd = NULL;
1467 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1469 inc_deq(xhci, xhci->cmd_ring);
1472 static void handle_vendor_event(struct xhci_hcd *xhci,
1473 union xhci_trb *event)
1477 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1478 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1479 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1480 handle_cmd_completion(xhci, &event->event_cmd);
1483 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1484 * port registers -- USB 3.0 and USB 2.0).
1486 * Returns a zero-based port number, which is suitable for indexing into each of
1487 * the split roothubs' port arrays and bus state arrays.
1488 * Add one to it in order to call xhci_find_slot_id_by_port.
1490 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1491 struct xhci_hcd *xhci, u32 port_id)
1494 unsigned int num_similar_speed_ports = 0;
1496 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1497 * and usb2_ports are 0-based indexes. Count the number of similar
1498 * speed ports, up to 1 port before this port.
1500 for (i = 0; i < (port_id - 1); i++) {
1501 u8 port_speed = xhci->port_array[i];
1504 * Skip ports that don't have known speeds, or have duplicate
1505 * Extended Capabilities port speed entries.
1507 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1511 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1512 * 1.1 ports are under the USB 2.0 hub. If the port speed
1513 * matches the device speed, it's a similar speed port.
1515 if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3))
1516 num_similar_speed_ports++;
1518 return num_similar_speed_ports;
1521 static void handle_device_notification(struct xhci_hcd *xhci,
1522 union xhci_trb *event)
1525 struct usb_device *udev;
1527 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1528 if (!xhci->devs[slot_id]) {
1529 xhci_warn(xhci, "Device Notification event for "
1530 "unused slot %u\n", slot_id);
1534 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1536 udev = xhci->devs[slot_id]->udev;
1537 if (udev && udev->parent)
1538 usb_wakeup_notification(udev->parent, udev->portnum);
1541 static void handle_port_status(struct xhci_hcd *xhci,
1542 union xhci_trb *event)
1544 struct usb_hcd *hcd;
1549 unsigned int faked_port_index;
1551 struct xhci_bus_state *bus_state;
1552 __le32 __iomem **port_array;
1553 bool bogus_port_status = false;
1555 /* Port status change events always have a successful completion code */
1556 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1557 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1558 xhci->error_bitmask |= 1 << 8;
1560 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1561 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1563 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1564 if ((port_id <= 0) || (port_id > max_ports)) {
1565 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1566 inc_deq(xhci, xhci->event_ring);
1570 /* Figure out which usb_hcd this port is attached to:
1571 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1573 major_revision = xhci->port_array[port_id - 1];
1575 /* Find the right roothub. */
1576 hcd = xhci_to_hcd(xhci);
1577 if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3))
1578 hcd = xhci->shared_hcd;
1580 if (major_revision == 0) {
1581 xhci_warn(xhci, "Event for port %u not in "
1582 "Extended Capabilities, ignoring.\n",
1584 bogus_port_status = true;
1587 if (major_revision == DUPLICATE_ENTRY) {
1588 xhci_warn(xhci, "Event for port %u duplicated in"
1589 "Extended Capabilities, ignoring.\n",
1591 bogus_port_status = true;
1596 * Hardware port IDs reported by a Port Status Change Event include USB
1597 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1598 * resume event, but we first need to translate the hardware port ID
1599 * into the index into the ports on the correct split roothub, and the
1600 * correct bus_state structure.
1602 bus_state = &xhci->bus_state[hcd_index(hcd)];
1603 if (hcd->speed >= HCD_USB3)
1604 port_array = xhci->usb3_ports;
1606 port_array = xhci->usb2_ports;
1607 /* Find the faked port hub number */
1608 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1611 temp = readl(port_array[faked_port_index]);
1612 if (hcd->state == HC_STATE_SUSPENDED) {
1613 xhci_dbg(xhci, "resume root hub\n");
1614 usb_hcd_resume_root_hub(hcd);
1617 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1618 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1620 temp1 = readl(&xhci->op_regs->command);
1621 if (!(temp1 & CMD_RUN)) {
1622 xhci_warn(xhci, "xHC is not running.\n");
1626 if (DEV_SUPERSPEED_ANY(temp)) {
1627 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1628 /* Set a flag to say the port signaled remote wakeup,
1629 * so we can tell the difference between the end of
1630 * device and host initiated resume.
1632 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1633 xhci_test_and_clear_bit(xhci, port_array,
1634 faked_port_index, PORT_PLC);
1635 usb_hcd_start_port_resume(&hcd->self, faked_port_index);
1636 xhci_set_link_state(xhci, port_array, faked_port_index,
1638 /* Need to wait until the next link state change
1639 * indicates the device is actually in U0.
1641 bogus_port_status = true;
1643 } else if (!test_bit(faked_port_index,
1644 &bus_state->resuming_ports)) {
1645 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1646 bus_state->resume_done[faked_port_index] = jiffies +
1647 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1648 set_bit(faked_port_index, &bus_state->resuming_ports);
1649 mod_timer(&hcd->rh_timer,
1650 bus_state->resume_done[faked_port_index]);
1651 /* Do the rest in GetPortStatus */
1655 if ((temp & PORT_PLC) &&
1656 DEV_SUPERSPEED_ANY(temp) &&
1657 ((temp & PORT_PLS_MASK) == XDEV_U0 ||
1658 (temp & PORT_PLS_MASK) == XDEV_U1 ||
1659 (temp & PORT_PLS_MASK) == XDEV_U2)) {
1660 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1661 /* We've just brought the device into U0/1/2 through either the
1662 * Resume state after a device remote wakeup, or through the
1663 * U3Exit state after a host-initiated resume. If it's a device
1664 * initiated remote wake, don't pass up the link state change,
1665 * so the roothub behavior is consistent with external
1666 * USB 3.0 hub behavior.
1668 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1669 faked_port_index + 1);
1670 if (slot_id && xhci->devs[slot_id])
1671 xhci_ring_device(xhci, slot_id);
1672 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1673 xhci_test_and_clear_bit(xhci, port_array,
1674 faked_port_index, PORT_PLC);
1675 usb_wakeup_notification(hcd->self.root_hub,
1676 faked_port_index + 1);
1677 bogus_port_status = true;
1683 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1684 * RExit to a disconnect state). If so, let the the driver know it's
1685 * out of the RExit state.
1687 if (!DEV_SUPERSPEED_ANY(temp) && hcd->speed < HCD_USB3 &&
1688 test_and_clear_bit(faked_port_index,
1689 &bus_state->rexit_ports)) {
1690 complete(&bus_state->rexit_done[faked_port_index]);
1691 bogus_port_status = true;
1695 if (hcd->speed < HCD_USB3)
1696 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1700 /* Update event ring dequeue pointer before dropping the lock */
1701 inc_deq(xhci, xhci->event_ring);
1703 /* Don't make the USB core poll the roothub if we got a bad port status
1704 * change event. Besides, at that point we can't tell which roothub
1705 * (USB 2.0 or USB 3.0) to kick.
1707 if (bogus_port_status)
1711 * xHCI port-status-change events occur when the "or" of all the
1712 * status-change bits in the portsc register changes from 0 to 1.
1713 * New status changes won't cause an event if any other change
1714 * bits are still set. When an event occurs, switch over to
1715 * polling to avoid losing status changes.
1717 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1718 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1719 spin_unlock(&xhci->lock);
1720 /* Pass this up to the core */
1721 usb_hcd_poll_rh_status(hcd);
1722 spin_lock(&xhci->lock);
1726 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1727 * at end_trb, which may be in another segment. If the suspect DMA address is a
1728 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1731 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1732 struct xhci_segment *start_seg,
1733 union xhci_trb *start_trb,
1734 union xhci_trb *end_trb,
1735 dma_addr_t suspect_dma,
1738 dma_addr_t start_dma;
1739 dma_addr_t end_seg_dma;
1740 dma_addr_t end_trb_dma;
1741 struct xhci_segment *cur_seg;
1743 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1744 cur_seg = start_seg;
1749 /* We may get an event for a Link TRB in the middle of a TD */
1750 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1751 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1752 /* If the end TRB isn't in this segment, this is set to 0 */
1753 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1757 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1758 (unsigned long long)suspect_dma,
1759 (unsigned long long)start_dma,
1760 (unsigned long long)end_trb_dma,
1761 (unsigned long long)cur_seg->dma,
1762 (unsigned long long)end_seg_dma);
1764 if (end_trb_dma > 0) {
1765 /* The end TRB is in this segment, so suspect should be here */
1766 if (start_dma <= end_trb_dma) {
1767 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1770 /* Case for one segment with
1771 * a TD wrapped around to the top
1773 if ((suspect_dma >= start_dma &&
1774 suspect_dma <= end_seg_dma) ||
1775 (suspect_dma >= cur_seg->dma &&
1776 suspect_dma <= end_trb_dma))
1781 /* Might still be somewhere in this segment */
1782 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1785 cur_seg = cur_seg->next;
1786 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1787 } while (cur_seg != start_seg);
1792 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1793 unsigned int slot_id, unsigned int ep_index,
1794 unsigned int stream_id,
1795 struct xhci_td *td, union xhci_trb *event_trb)
1797 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1798 struct xhci_command *command;
1799 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1803 ep->ep_state |= EP_HALTED;
1804 ep->stopped_stream = stream_id;
1806 xhci_queue_reset_ep(xhci, command, slot_id, ep_index);
1807 xhci_cleanup_stalled_ring(xhci, ep_index, td);
1809 ep->stopped_stream = 0;
1811 xhci_ring_cmd_db(xhci);
1814 /* Check if an error has halted the endpoint ring. The class driver will
1815 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1816 * However, a babble and other errors also halt the endpoint ring, and the class
1817 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1818 * Ring Dequeue Pointer command manually.
1820 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1821 struct xhci_ep_ctx *ep_ctx,
1822 unsigned int trb_comp_code)
1824 /* TRB completion codes that may require a manual halt cleanup */
1825 if (trb_comp_code == COMP_TX_ERR ||
1826 trb_comp_code == COMP_BABBLE ||
1827 trb_comp_code == COMP_SPLIT_ERR)
1828 /* The 0.95 spec says a babbling control endpoint
1829 * is not halted. The 0.96 spec says it is. Some HW
1830 * claims to be 0.95 compliant, but it halts the control
1831 * endpoint anyway. Check if a babble halted the
1834 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1835 cpu_to_le32(EP_STATE_HALTED))
1841 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1843 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1844 /* Vendor defined "informational" completion code,
1845 * treat as not-an-error.
1847 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1849 xhci_dbg(xhci, "Treating code as success.\n");
1856 * Finish the td processing, remove the td from td list;
1857 * Return 1 if the urb can be given back.
1859 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1860 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1861 struct xhci_virt_ep *ep, int *status, bool skip)
1863 struct xhci_virt_device *xdev;
1864 struct xhci_ring *ep_ring;
1865 unsigned int slot_id;
1867 struct urb *urb = NULL;
1868 struct xhci_ep_ctx *ep_ctx;
1870 struct urb_priv *urb_priv;
1873 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1874 xdev = xhci->devs[slot_id];
1875 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1876 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1877 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1878 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1883 if (trb_comp_code == COMP_STOP_INVAL ||
1884 trb_comp_code == COMP_STOP ||
1885 trb_comp_code == COMP_STOP_SHORT) {
1886 /* The Endpoint Stop Command completion will take care of any
1887 * stopped TDs. A stopped TD may be restarted, so don't update
1888 * the ring dequeue pointer or take this TD off any lists yet.
1890 ep->stopped_td = td;
1893 if (trb_comp_code == COMP_STALL ||
1894 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1896 /* Issue a reset endpoint command to clear the host side
1897 * halt, followed by a set dequeue command to move the
1898 * dequeue pointer past the TD.
1899 * The class driver clears the device side halt later.
1901 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1902 ep_ring->stream_id, td, event_trb);
1904 /* Update ring dequeue pointer */
1905 while (ep_ring->dequeue != td->last_trb)
1906 inc_deq(xhci, ep_ring);
1907 inc_deq(xhci, ep_ring);
1911 /* Clean up the endpoint's TD list */
1913 urb_priv = urb->hcpriv;
1915 /* if a bounce buffer was used to align this td then unmap it */
1917 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1919 /* Do one last check of the actual transfer length.
1920 * If the host controller said we transferred more data than the buffer
1921 * length, urb->actual_length will be a very big number (since it's
1922 * unsigned). Play it safe and say we didn't transfer anything.
1924 if (urb->actual_length > urb->transfer_buffer_length) {
1925 xhci_warn(xhci, "URB transfer length is wrong, xHC issue? req. len = %u, act. len = %u\n",
1926 urb->transfer_buffer_length,
1927 urb->actual_length);
1928 urb->actual_length = 0;
1929 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1930 *status = -EREMOTEIO;
1934 list_del_init(&td->td_list);
1935 /* Was this TD slated to be cancelled but completed anyway? */
1936 if (!list_empty(&td->cancelled_td_list))
1937 list_del_init(&td->cancelled_td_list);
1940 /* Giveback the urb when all the tds are completed */
1941 if (urb_priv->td_cnt == urb_priv->length) {
1943 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1944 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1945 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
1946 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1947 usb_amd_quirk_pll_enable();
1956 * Process control tds, update urb status and actual_length.
1958 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1959 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1960 struct xhci_virt_ep *ep, int *status)
1962 struct xhci_virt_device *xdev;
1963 struct xhci_ring *ep_ring;
1964 unsigned int slot_id;
1966 struct xhci_ep_ctx *ep_ctx;
1969 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1970 xdev = xhci->devs[slot_id];
1971 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1972 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1973 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1974 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1976 switch (trb_comp_code) {
1978 if (event_trb == ep_ring->dequeue) {
1979 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1980 "without IOC set??\n");
1981 *status = -ESHUTDOWN;
1982 } else if (event_trb != td->last_trb) {
1983 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1984 "without IOC set??\n");
1985 *status = -ESHUTDOWN;
1991 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1992 *status = -EREMOTEIO;
1996 case COMP_STOP_SHORT:
1997 if (event_trb == ep_ring->dequeue || event_trb == td->last_trb)
1998 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2000 td->urb->actual_length =
2001 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2003 return finish_td(xhci, td, event_trb, event, ep, status, false);
2005 /* Did we stop at data stage? */
2006 if (event_trb != ep_ring->dequeue && event_trb != td->last_trb)
2007 td->urb->actual_length =
2008 td->urb->transfer_buffer_length -
2009 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2011 case COMP_STOP_INVAL:
2012 return finish_td(xhci, td, event_trb, event, ep, status, false);
2014 if (!xhci_requires_manual_halt_cleanup(xhci,
2015 ep_ctx, trb_comp_code))
2017 xhci_dbg(xhci, "TRB error code %u, "
2018 "halted endpoint index = %u\n",
2019 trb_comp_code, ep_index);
2020 /* else fall through */
2022 /* Did we transfer part of the data (middle) phase? */
2023 if (event_trb != ep_ring->dequeue &&
2024 event_trb != td->last_trb)
2025 td->urb->actual_length =
2026 td->urb->transfer_buffer_length -
2027 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2028 else if (!td->urb_length_set)
2029 td->urb->actual_length = 0;
2031 return finish_td(xhci, td, event_trb, event, ep, status, false);
2034 * Did we transfer any data, despite the errors that might have
2035 * happened? I.e. did we get past the setup stage?
2037 if (event_trb != ep_ring->dequeue) {
2038 /* The event was for the status stage */
2039 if (event_trb == td->last_trb) {
2040 if (td->urb_length_set) {
2041 /* Don't overwrite a previously set error code
2043 if ((*status == -EINPROGRESS || *status == 0) &&
2044 (td->urb->transfer_flags
2045 & URB_SHORT_NOT_OK))
2046 /* Did we already see a short data
2048 *status = -EREMOTEIO;
2050 td->urb->actual_length =
2051 td->urb->transfer_buffer_length;
2055 * Maybe the event was for the data stage? If so, update
2056 * already the actual_length of the URB and flag it as
2057 * set, so that it is not overwritten in the event for
2060 td->urb_length_set = true;
2061 td->urb->actual_length =
2062 td->urb->transfer_buffer_length -
2063 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2064 xhci_dbg(xhci, "Waiting for status "
2070 return finish_td(xhci, td, event_trb, event, ep, status, false);
2074 * Process isochronous tds, update urb packet status and actual_length.
2076 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2077 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2078 struct xhci_virt_ep *ep, int *status)
2080 struct xhci_ring *ep_ring;
2081 struct urb_priv *urb_priv;
2084 union xhci_trb *cur_trb;
2085 struct xhci_segment *cur_seg;
2086 struct usb_iso_packet_descriptor *frame;
2088 bool skip_td = false;
2090 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2091 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2092 urb_priv = td->urb->hcpriv;
2093 idx = urb_priv->td_cnt;
2094 frame = &td->urb->iso_frame_desc[idx];
2096 /* handle completion code */
2097 switch (trb_comp_code) {
2099 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2103 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2104 trb_comp_code = COMP_SHORT_TX;
2106 case COMP_STOP_SHORT:
2108 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2112 frame->status = -ECOMM;
2115 case COMP_BUFF_OVER:
2117 frame->status = -EOVERFLOW;
2122 frame->status = -EPROTO;
2126 frame->status = -EPROTO;
2127 if (event_trb != td->last_trb)
2132 case COMP_STOP_INVAL:
2139 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2140 frame->actual_length = frame->length;
2141 td->urb->actual_length += frame->length;
2142 } else if (trb_comp_code == COMP_STOP_SHORT) {
2143 frame->actual_length =
2144 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2145 td->urb->actual_length += frame->actual_length;
2147 for (cur_trb = ep_ring->dequeue,
2148 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2149 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2150 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2151 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2152 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2154 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2155 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2157 if (trb_comp_code != COMP_STOP_INVAL) {
2158 frame->actual_length = len;
2159 td->urb->actual_length += len;
2163 return finish_td(xhci, td, event_trb, event, ep, status, false);
2166 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2167 struct xhci_transfer_event *event,
2168 struct xhci_virt_ep *ep, int *status)
2170 struct xhci_ring *ep_ring;
2171 struct urb_priv *urb_priv;
2172 struct usb_iso_packet_descriptor *frame;
2175 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2176 urb_priv = td->urb->hcpriv;
2177 idx = urb_priv->td_cnt;
2178 frame = &td->urb->iso_frame_desc[idx];
2180 /* The transfer is partly done. */
2181 frame->status = -EXDEV;
2183 /* calc actual length */
2184 frame->actual_length = 0;
2186 /* Update ring dequeue pointer */
2187 while (ep_ring->dequeue != td->last_trb)
2188 inc_deq(xhci, ep_ring);
2189 inc_deq(xhci, ep_ring);
2191 return finish_td(xhci, td, NULL, event, ep, status, true);
2195 * Process bulk and interrupt tds, update urb status and actual_length.
2197 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2198 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2199 struct xhci_virt_ep *ep, int *status)
2201 struct xhci_ring *ep_ring;
2202 union xhci_trb *cur_trb;
2203 struct xhci_segment *cur_seg;
2206 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2207 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2209 switch (trb_comp_code) {
2211 /* Double check that the HW transferred everything. */
2212 if (event_trb != td->last_trb ||
2213 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2214 xhci_warn(xhci, "WARN Successful completion "
2216 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2217 *status = -EREMOTEIO;
2220 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2221 trb_comp_code = COMP_SHORT_TX;
2226 case COMP_STOP_SHORT:
2228 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2229 *status = -EREMOTEIO;
2234 /* Others already handled above */
2237 if (trb_comp_code == COMP_SHORT_TX)
2238 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2239 "%d bytes untransferred\n",
2240 td->urb->ep->desc.bEndpointAddress,
2241 td->urb->transfer_buffer_length,
2242 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2243 /* Stopped - short packet completion */
2244 if (trb_comp_code == COMP_STOP_SHORT) {
2245 td->urb->actual_length =
2246 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2248 if (td->urb->transfer_buffer_length <
2249 td->urb->actual_length) {
2250 xhci_warn(xhci, "HC gave bad length of %d bytes txed\n",
2251 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2252 td->urb->actual_length = 0;
2253 /* status will be set by usb core for canceled urbs */
2255 /* Fast path - was this the last TRB in the TD for this URB? */
2256 } else if (event_trb == td->last_trb) {
2257 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2258 td->urb->actual_length =
2259 td->urb->transfer_buffer_length -
2260 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2261 if (td->urb->transfer_buffer_length <
2262 td->urb->actual_length) {
2263 xhci_warn(xhci, "HC gave bad length "
2264 "of %d bytes left\n",
2265 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2266 td->urb->actual_length = 0;
2267 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2268 *status = -EREMOTEIO;
2272 /* Don't overwrite a previously set error code */
2273 if (*status == -EINPROGRESS) {
2274 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2275 *status = -EREMOTEIO;
2280 td->urb->actual_length =
2281 td->urb->transfer_buffer_length;
2282 /* Ignore a short packet completion if the
2283 * untransferred length was zero.
2285 if (*status == -EREMOTEIO)
2289 /* Slow path - walk the list, starting from the dequeue
2290 * pointer, to get the actual length transferred.
2292 td->urb->actual_length = 0;
2293 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2294 cur_trb != event_trb;
2295 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2296 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2297 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2298 td->urb->actual_length +=
2299 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2301 /* If the ring didn't stop on a Link or No-op TRB, add
2302 * in the actual bytes transferred from the Normal TRB
2304 if (trb_comp_code != COMP_STOP_INVAL)
2305 td->urb->actual_length +=
2306 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2307 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2310 return finish_td(xhci, td, event_trb, event, ep, status, false);
2314 * If this function returns an error condition, it means it got a Transfer
2315 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2316 * At this point, the host controller is probably hosed and should be reset.
2318 static int handle_tx_event(struct xhci_hcd *xhci,
2319 struct xhci_transfer_event *event)
2320 __releases(&xhci->lock)
2321 __acquires(&xhci->lock)
2323 struct xhci_virt_device *xdev;
2324 struct xhci_virt_ep *ep;
2325 struct xhci_ring *ep_ring;
2326 unsigned int slot_id;
2328 struct xhci_td *td = NULL;
2329 dma_addr_t event_dma;
2330 struct xhci_segment *event_seg;
2331 union xhci_trb *event_trb;
2332 struct urb *urb = NULL;
2333 int status = -EINPROGRESS;
2334 struct urb_priv *urb_priv;
2335 struct xhci_ep_ctx *ep_ctx;
2336 struct list_head *tmp;
2340 bool handling_skipped_tds = false;
2342 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2343 xdev = xhci->devs[slot_id];
2345 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2346 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2347 (unsigned long long) xhci_trb_virt_to_dma(
2348 xhci->event_ring->deq_seg,
2349 xhci->event_ring->dequeue),
2350 lower_32_bits(le64_to_cpu(event->buffer)),
2351 upper_32_bits(le64_to_cpu(event->buffer)),
2352 le32_to_cpu(event->transfer_len),
2353 le32_to_cpu(event->flags));
2354 xhci_dbg(xhci, "Event ring:\n");
2355 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2359 /* Endpoint ID is 1 based, our index is zero based */
2360 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2361 ep = &xdev->eps[ep_index];
2362 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2363 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2365 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2366 EP_STATE_DISABLED) {
2367 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2368 "or incorrect stream ring\n");
2369 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2370 (unsigned long long) xhci_trb_virt_to_dma(
2371 xhci->event_ring->deq_seg,
2372 xhci->event_ring->dequeue),
2373 lower_32_bits(le64_to_cpu(event->buffer)),
2374 upper_32_bits(le64_to_cpu(event->buffer)),
2375 le32_to_cpu(event->transfer_len),
2376 le32_to_cpu(event->flags));
2377 xhci_dbg(xhci, "Event ring:\n");
2378 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2382 /* Count current td numbers if ep->skip is set */
2384 list_for_each(tmp, &ep_ring->td_list)
2388 event_dma = le64_to_cpu(event->buffer);
2389 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2390 /* Look for common error cases */
2391 switch (trb_comp_code) {
2392 /* Skip codes that require special handling depending on
2396 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2398 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2399 trb_comp_code = COMP_SHORT_TX;
2401 xhci_warn_ratelimited(xhci,
2402 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2406 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2408 case COMP_STOP_INVAL:
2409 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2411 case COMP_STOP_SHORT:
2412 xhci_dbg(xhci, "Stopped with short packet transfer detected\n");
2415 xhci_dbg(xhci, "Stalled endpoint\n");
2416 ep->ep_state |= EP_HALTED;
2420 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2423 case COMP_SPLIT_ERR:
2425 xhci_dbg(xhci, "Transfer error on endpoint\n");
2429 xhci_dbg(xhci, "Babble error on endpoint\n");
2430 status = -EOVERFLOW;
2433 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2437 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2439 case COMP_BUFF_OVER:
2440 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2444 * When the Isoch ring is empty, the xHC will generate
2445 * a Ring Overrun Event for IN Isoch endpoint or Ring
2446 * Underrun Event for OUT Isoch endpoint.
2448 xhci_dbg(xhci, "underrun event on endpoint\n");
2449 if (!list_empty(&ep_ring->td_list))
2450 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2451 "still with TDs queued?\n",
2452 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2456 xhci_dbg(xhci, "overrun event on endpoint\n");
2457 if (!list_empty(&ep_ring->td_list))
2458 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2459 "still with TDs queued?\n",
2460 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2464 xhci_warn(xhci, "WARN: detect an incompatible device");
2467 case COMP_MISSED_INT:
2469 * When encounter missed service error, one or more isoc tds
2470 * may be missed by xHC.
2471 * Set skip flag of the ep_ring; Complete the missed tds as
2472 * short transfer when process the ep_ring next time.
2475 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2479 xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n");
2482 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2486 xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n",
2492 /* This TRB should be in the TD at the head of this ring's
2495 if (list_empty(&ep_ring->td_list)) {
2497 * A stopped endpoint may generate an extra completion
2498 * event if the device was suspended. Don't print
2501 if (!(trb_comp_code == COMP_STOP ||
2502 trb_comp_code == COMP_STOP_INVAL)) {
2503 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2504 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2506 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2507 (le32_to_cpu(event->flags) &
2508 TRB_TYPE_BITMASK)>>10);
2509 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2513 xhci_dbg(xhci, "td_list is empty while skip "
2514 "flag set. Clear skip flag.\n");
2520 /* We've skipped all the TDs on the ep ring when ep->skip set */
2521 if (ep->skip && td_num == 0) {
2523 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2524 "Clear skip flag.\n");
2529 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2533 /* Is this a TRB in the currently executing TD? */
2534 event_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2535 td->last_trb, event_dma, false);
2538 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2539 * is not in the current TD pointed by ep_ring->dequeue because
2540 * that the hardware dequeue pointer still at the previous TRB
2541 * of the current TD. The previous TRB maybe a Link TD or the
2542 * last TRB of the previous TD. The command completion handle
2543 * will take care the rest.
2545 if (!event_seg && (trb_comp_code == COMP_STOP ||
2546 trb_comp_code == COMP_STOP_INVAL)) {
2553 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2554 /* Some host controllers give a spurious
2555 * successful event after a short transfer.
2558 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2559 ep_ring->last_td_was_short) {
2560 ep_ring->last_td_was_short = false;
2564 /* HC is busted, give up! */
2566 "ERROR Transfer event TRB DMA ptr not "
2567 "part of current TD ep_index %d "
2568 "comp_code %u\n", ep_index,
2570 trb_in_td(xhci, ep_ring->deq_seg,
2571 ep_ring->dequeue, td->last_trb,
2576 ret = skip_isoc_td(xhci, td, event, ep, &status);
2579 if (trb_comp_code == COMP_SHORT_TX)
2580 ep_ring->last_td_was_short = true;
2582 ep_ring->last_td_was_short = false;
2585 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2589 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2590 sizeof(*event_trb)];
2592 * No-op TRB should not trigger interrupts.
2593 * If event_trb is a no-op TRB, it means the
2594 * corresponding TD has been cancelled. Just ignore
2597 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2599 "event_trb is a no-op TRB. Skip it\n");
2603 /* Now update the urb's actual_length and give back to
2606 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2607 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2609 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2610 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2613 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2619 handling_skipped_tds = ep->skip &&
2620 trb_comp_code != COMP_MISSED_INT &&
2621 trb_comp_code != COMP_PING_ERR;
2624 * Do not update event ring dequeue pointer if we're in a loop
2625 * processing missed tds.
2627 if (!handling_skipped_tds)
2628 inc_deq(xhci, xhci->event_ring);
2632 urb_priv = urb->hcpriv;
2634 xhci_urb_free_priv(urb_priv);
2636 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2637 if ((urb->actual_length != urb->transfer_buffer_length &&
2638 (urb->transfer_flags &
2639 URB_SHORT_NOT_OK)) ||
2641 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2642 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2643 "expected = %d, status = %d\n",
2644 urb, urb->actual_length,
2645 urb->transfer_buffer_length,
2647 spin_unlock(&xhci->lock);
2648 /* EHCI, UHCI, and OHCI always unconditionally set the
2649 * urb->status of an isochronous endpoint to 0.
2651 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2653 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2654 spin_lock(&xhci->lock);
2658 * If ep->skip is set, it means there are missed tds on the
2659 * endpoint ring need to take care of.
2660 * Process them as short transfer until reach the td pointed by
2663 } while (handling_skipped_tds);
2669 * This function handles all OS-owned events on the event ring. It may drop
2670 * xhci->lock between event processing (e.g. to pass up port status changes).
2671 * Returns >0 for "possibly more events to process" (caller should call again),
2672 * otherwise 0 if done. In future, <0 returns should indicate error code.
2674 static int xhci_handle_event(struct xhci_hcd *xhci)
2676 union xhci_trb *event;
2677 int update_ptrs = 1;
2680 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2681 xhci->error_bitmask |= 1 << 1;
2685 event = xhci->event_ring->dequeue;
2686 /* Does the HC or OS own the TRB? */
2687 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2688 xhci->event_ring->cycle_state) {
2689 xhci->error_bitmask |= 1 << 2;
2694 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2695 * speculative reads of the event's flags/data below.
2698 /* FIXME: Handle more event types. */
2699 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2700 case TRB_TYPE(TRB_COMPLETION):
2701 handle_cmd_completion(xhci, &event->event_cmd);
2703 case TRB_TYPE(TRB_PORT_STATUS):
2704 handle_port_status(xhci, event);
2707 case TRB_TYPE(TRB_TRANSFER):
2708 ret = handle_tx_event(xhci, &event->trans_event);
2710 xhci->error_bitmask |= 1 << 9;
2714 case TRB_TYPE(TRB_DEV_NOTE):
2715 handle_device_notification(xhci, event);
2718 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2720 handle_vendor_event(xhci, event);
2722 xhci->error_bitmask |= 1 << 3;
2724 /* Any of the above functions may drop and re-acquire the lock, so check
2725 * to make sure a watchdog timer didn't mark the host as non-responsive.
2727 if (xhci->xhc_state & XHCI_STATE_DYING) {
2728 xhci_dbg(xhci, "xHCI host dying, returning from "
2729 "event handler.\n");
2734 /* Update SW event ring dequeue pointer */
2735 inc_deq(xhci, xhci->event_ring);
2737 /* Are there more items on the event ring? Caller will call us again to
2744 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2745 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2746 * indicators of an event TRB error, but we check the status *first* to be safe.
2748 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2750 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2753 union xhci_trb *event_ring_deq;
2756 spin_lock(&xhci->lock);
2757 /* Check if the xHC generated the interrupt, or the irq is shared */
2758 status = readl(&xhci->op_regs->status);
2759 if (status == 0xffffffff)
2762 if (!(status & STS_EINT)) {
2763 spin_unlock(&xhci->lock);
2766 if (status & STS_FATAL) {
2767 xhci_warn(xhci, "WARNING: Host System Error\n");
2770 spin_unlock(&xhci->lock);
2775 * Clear the op reg interrupt status first,
2776 * so we can receive interrupts from other MSI-X interrupters.
2777 * Write 1 to clear the interrupt status.
2780 writel(status, &xhci->op_regs->status);
2781 /* FIXME when MSI-X is supported and there are multiple vectors */
2782 /* Clear the MSI-X event interrupt status */
2786 /* Acknowledge the PCI interrupt */
2787 irq_pending = readl(&xhci->ir_set->irq_pending);
2788 irq_pending |= IMAN_IP;
2789 writel(irq_pending, &xhci->ir_set->irq_pending);
2792 if (xhci->xhc_state & XHCI_STATE_DYING ||
2793 xhci->xhc_state & XHCI_STATE_HALTED) {
2794 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2795 "Shouldn't IRQs be disabled?\n");
2796 /* Clear the event handler busy flag (RW1C);
2797 * the event ring should be empty.
2799 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2800 xhci_write_64(xhci, temp_64 | ERST_EHB,
2801 &xhci->ir_set->erst_dequeue);
2802 spin_unlock(&xhci->lock);
2807 event_ring_deq = xhci->event_ring->dequeue;
2808 /* FIXME this should be a delayed service routine
2809 * that clears the EHB.
2811 while (xhci_handle_event(xhci) > 0) {}
2813 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2814 /* If necessary, update the HW's version of the event ring deq ptr. */
2815 if (event_ring_deq != xhci->event_ring->dequeue) {
2816 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2817 xhci->event_ring->dequeue);
2819 xhci_warn(xhci, "WARN something wrong with SW event "
2820 "ring dequeue ptr.\n");
2821 /* Update HC event ring dequeue pointer */
2822 temp_64 &= ERST_PTR_MASK;
2823 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2826 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2827 temp_64 |= ERST_EHB;
2828 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2830 spin_unlock(&xhci->lock);
2835 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2837 return xhci_irq(hcd);
2840 /**** Endpoint Ring Operations ****/
2843 * Generic function for queueing a TRB on a ring.
2844 * The caller must have checked to make sure there's room on the ring.
2846 * @more_trbs_coming: Will you enqueue more TRBs before calling
2847 * prepare_transfer()?
2849 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2850 bool more_trbs_coming,
2851 u32 field1, u32 field2, u32 field3, u32 field4)
2853 struct xhci_generic_trb *trb;
2855 trb = &ring->enqueue->generic;
2856 trb->field[0] = cpu_to_le32(field1);
2857 trb->field[1] = cpu_to_le32(field2);
2858 trb->field[2] = cpu_to_le32(field3);
2859 /* make sure TRB is fully written before giving it to the controller */
2861 trb->field[3] = cpu_to_le32(field4);
2862 inc_enq(xhci, ring, more_trbs_coming);
2866 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2867 * FIXME allocate segments if the ring is full.
2869 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2870 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2872 unsigned int num_trbs_needed;
2874 /* Make sure the endpoint has been added to xHC schedule */
2876 case EP_STATE_DISABLED:
2878 * USB core changed config/interfaces without notifying us,
2879 * or hardware is reporting the wrong state.
2881 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2883 case EP_STATE_ERROR:
2884 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2885 /* FIXME event handling code for error needs to clear it */
2886 /* XXX not sure if this should be -ENOENT or not */
2888 case EP_STATE_HALTED:
2889 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2890 case EP_STATE_STOPPED:
2891 case EP_STATE_RUNNING:
2894 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2896 * FIXME issue Configure Endpoint command to try to get the HC
2897 * back into a known state.
2903 if (room_on_ring(xhci, ep_ring, num_trbs))
2906 if (ep_ring == xhci->cmd_ring) {
2907 xhci_err(xhci, "Do not support expand command ring\n");
2911 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2912 "ERROR no room on ep ring, try ring expansion");
2913 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2914 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2916 xhci_err(xhci, "Ring expansion failed\n");
2921 while (trb_is_link(ep_ring->enqueue)) {
2922 /* If we're not dealing with 0.95 hardware or isoc rings
2923 * on AMD 0.96 host, clear the chain bit.
2925 if (!xhci_link_trb_quirk(xhci) &&
2926 !(ep_ring->type == TYPE_ISOC &&
2927 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2928 ep_ring->enqueue->link.control &=
2929 cpu_to_le32(~TRB_CHAIN);
2931 ep_ring->enqueue->link.control |=
2932 cpu_to_le32(TRB_CHAIN);
2935 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
2937 /* Toggle the cycle bit after the last ring segment. */
2938 if (link_trb_toggles_cycle(ep_ring->enqueue))
2939 ep_ring->cycle_state ^= 1;
2941 ep_ring->enq_seg = ep_ring->enq_seg->next;
2942 ep_ring->enqueue = ep_ring->enq_seg->trbs;
2947 static int prepare_transfer(struct xhci_hcd *xhci,
2948 struct xhci_virt_device *xdev,
2949 unsigned int ep_index,
2950 unsigned int stream_id,
2951 unsigned int num_trbs,
2953 unsigned int td_index,
2957 struct urb_priv *urb_priv;
2959 struct xhci_ring *ep_ring;
2960 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2962 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2964 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2969 ret = prepare_ring(xhci, ep_ring,
2970 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2971 num_trbs, mem_flags);
2975 urb_priv = urb->hcpriv;
2976 td = urb_priv->td[td_index];
2978 INIT_LIST_HEAD(&td->td_list);
2979 INIT_LIST_HEAD(&td->cancelled_td_list);
2981 if (td_index == 0) {
2982 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2988 /* Add this TD to the tail of the endpoint ring's TD list */
2989 list_add_tail(&td->td_list, &ep_ring->td_list);
2990 td->start_seg = ep_ring->enq_seg;
2991 td->first_trb = ep_ring->enqueue;
2993 urb_priv->td[td_index] = td;
2998 static unsigned int count_trbs(u64 addr, u64 len)
3000 unsigned int num_trbs;
3002 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3010 static inline unsigned int count_trbs_needed(struct urb *urb)
3012 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3015 static unsigned int count_sg_trbs_needed(struct urb *urb)
3017 struct scatterlist *sg;
3018 unsigned int i, len, full_len, num_trbs = 0;
3020 full_len = urb->transfer_buffer_length;
3022 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3023 len = sg_dma_len(sg);
3024 num_trbs += count_trbs(sg_dma_address(sg), len);
3025 len = min_t(unsigned int, len, full_len);
3034 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3038 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3039 len = urb->iso_frame_desc[i].length;
3041 return count_trbs(addr, len);
3044 static void check_trb_math(struct urb *urb, int running_total)
3046 if (unlikely(running_total != urb->transfer_buffer_length))
3047 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3048 "queued %#x (%d), asked for %#x (%d)\n",
3050 urb->ep->desc.bEndpointAddress,
3051 running_total, running_total,
3052 urb->transfer_buffer_length,
3053 urb->transfer_buffer_length);
3056 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3057 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3058 struct xhci_generic_trb *start_trb)
3061 * Pass all the TRBs to the hardware at once and make sure this write
3066 start_trb->field[3] |= cpu_to_le32(start_cycle);
3068 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3069 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3072 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3073 struct xhci_ep_ctx *ep_ctx)
3078 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3079 ep_interval = urb->interval;
3081 /* Convert to microframes */
3082 if (urb->dev->speed == USB_SPEED_LOW ||
3083 urb->dev->speed == USB_SPEED_FULL)
3086 /* FIXME change this to a warning and a suggestion to use the new API
3087 * to set the polling interval (once the API is added).
3089 if (xhci_interval != ep_interval) {
3090 dev_dbg_ratelimited(&urb->dev->dev,
3091 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3092 ep_interval, ep_interval == 1 ? "" : "s",
3093 xhci_interval, xhci_interval == 1 ? "" : "s");
3094 urb->interval = xhci_interval;
3095 /* Convert back to frames for LS/FS devices */
3096 if (urb->dev->speed == USB_SPEED_LOW ||
3097 urb->dev->speed == USB_SPEED_FULL)
3103 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3104 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3105 * (comprised of sg list entries) can take several service intervals to
3108 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3109 struct urb *urb, int slot_id, unsigned int ep_index)
3111 struct xhci_ep_ctx *ep_ctx;
3113 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3114 check_interval(xhci, urb, ep_ctx);
3116 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3120 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3121 * packets remaining in the TD (*not* including this TRB).
3123 * Total TD packet count = total_packet_count =
3124 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3126 * Packets transferred up to and including this TRB = packets_transferred =
3127 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3129 * TD size = total_packet_count - packets_transferred
3131 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3132 * including this TRB, right shifted by 10
3134 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3135 * This is taken care of in the TRB_TD_SIZE() macro
3137 * The last TRB in a TD must have the TD size set to zero.
3139 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3140 int trb_buff_len, unsigned int td_total_len,
3141 struct urb *urb, bool more_trbs_coming)
3143 u32 maxp, total_packet_count;
3145 /* MTK xHCI 0.96 contains some features from 1.0 */
3146 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3147 return ((td_total_len - transferred) >> 10);
3149 /* One TRB with a zero-length data packet. */
3150 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3151 trb_buff_len == td_total_len)
3154 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3155 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3158 maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3159 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3161 /* Queueing functions don't count the current TRB into transferred */
3162 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3166 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3167 u32 *trb_buff_len, struct xhci_segment *seg)
3169 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3170 unsigned int unalign;
3171 unsigned int max_pkt;
3175 max_pkt = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3176 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3178 /* we got lucky, last normal TRB data on segment is packet aligned */
3182 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3183 unalign, *trb_buff_len);
3185 /* is the last nornal TRB alignable by splitting it */
3186 if (*trb_buff_len > unalign) {
3187 *trb_buff_len -= unalign;
3188 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3193 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3194 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3195 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3197 new_buff_len = max_pkt - (enqd_len % max_pkt);
3199 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3200 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3202 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3203 if (usb_urb_dir_out(urb)) {
3205 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3206 seg->bounce_buf, new_buff_len, enqd_len);
3207 if (len != new_buff_len)
3208 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3211 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3214 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3215 max_pkt, DMA_TO_DEVICE);
3217 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3218 max_pkt, DMA_FROM_DEVICE);
3221 if (dma_mapping_error(dev, seg->bounce_dma)) {
3222 /* try without aligning. Some host controllers survive */
3223 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3226 *trb_buff_len = new_buff_len;
3227 seg->bounce_len = new_buff_len;
3228 seg->bounce_offs = enqd_len;
3230 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3235 /* This is very similar to what ehci-q.c qtd_fill() does */
3236 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3237 struct urb *urb, int slot_id, unsigned int ep_index)
3239 struct xhci_ring *ring;
3240 struct urb_priv *urb_priv;
3242 struct xhci_generic_trb *start_trb;
3243 struct scatterlist *sg = NULL;
3244 bool more_trbs_coming = true;
3245 bool need_zero_pkt = false;
3246 bool first_trb = true;
3247 unsigned int num_trbs;
3248 unsigned int start_cycle, num_sgs = 0;
3249 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3251 u32 field, length_field, remainder;
3252 u64 addr, send_addr;
3254 ring = xhci_urb_to_transfer_ring(xhci, urb);
3258 full_len = urb->transfer_buffer_length;
3259 /* If we have scatter/gather list, we use it. */
3261 num_sgs = urb->num_mapped_sgs;
3263 addr = (u64) sg_dma_address(sg);
3264 block_len = sg_dma_len(sg);
3265 num_trbs = count_sg_trbs_needed(urb);
3267 num_trbs = count_trbs_needed(urb);
3268 addr = (u64) urb->transfer_dma;
3269 block_len = full_len;
3271 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3272 ep_index, urb->stream_id,
3273 num_trbs, urb, 0, mem_flags);
3274 if (unlikely(ret < 0))
3277 urb_priv = urb->hcpriv;
3279 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3280 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->length > 1)
3281 need_zero_pkt = true;
3283 td = urb_priv->td[0];
3286 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3287 * until we've finished creating all the other TRBs. The ring's cycle
3288 * state may change as we enqueue the other TRBs, so save it too.
3290 start_trb = &ring->enqueue->generic;
3291 start_cycle = ring->cycle_state;
3294 /* Queue the TRBs, even if they are zero-length */
3295 for (enqd_len = 0; first_trb || enqd_len < full_len;
3296 enqd_len += trb_buff_len) {
3297 field = TRB_TYPE(TRB_NORMAL);
3299 /* TRB buffer should not cross 64KB boundaries */
3300 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3301 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3303 if (enqd_len + trb_buff_len > full_len)
3304 trb_buff_len = full_len - enqd_len;
3306 /* Don't change the cycle bit of the first TRB until later */
3309 if (start_cycle == 0)
3312 field |= ring->cycle_state;
3314 /* Chain all the TRBs together; clear the chain bit in the last
3315 * TRB to indicate it's the last TRB in the chain.
3317 if (enqd_len + trb_buff_len < full_len) {
3319 if (trb_is_link(ring->enqueue + 1)) {
3320 if (xhci_align_td(xhci, urb, enqd_len,
3323 send_addr = ring->enq_seg->bounce_dma;
3324 /* assuming TD won't span 2 segs */
3325 td->bounce_seg = ring->enq_seg;
3329 if (enqd_len + trb_buff_len >= full_len) {
3330 field &= ~TRB_CHAIN;
3332 more_trbs_coming = false;
3333 td->last_trb = ring->enqueue;
3336 /* Only set interrupt on short packet for IN endpoints */
3337 if (usb_urb_dir_in(urb))
3340 /* Set the TRB length, TD size, and interrupter fields. */
3341 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3342 full_len, urb, more_trbs_coming);
3344 length_field = TRB_LEN(trb_buff_len) |
3345 TRB_TD_SIZE(remainder) |
3348 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3349 lower_32_bits(send_addr),
3350 upper_32_bits(send_addr),
3354 addr += trb_buff_len;
3355 sent_len = trb_buff_len;
3357 while (sg && sent_len >= block_len) {
3360 sent_len -= block_len;
3362 if (num_sgs != 0 && sg) {
3363 block_len = sg_dma_len(sg);
3364 addr = (u64) sg_dma_address(sg);
3368 block_len -= sent_len;
3372 if (need_zero_pkt) {
3373 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3374 ep_index, urb->stream_id,
3375 1, urb, 1, mem_flags);
3376 urb_priv->td[1]->last_trb = ring->enqueue;
3377 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3378 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3381 check_trb_math(urb, enqd_len);
3382 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3383 start_cycle, start_trb);
3387 /* Caller must have locked xhci->lock */
3388 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3389 struct urb *urb, int slot_id, unsigned int ep_index)
3391 struct xhci_ring *ep_ring;
3394 struct usb_ctrlrequest *setup;
3395 struct xhci_generic_trb *start_trb;
3397 u32 field, length_field, remainder;
3398 struct urb_priv *urb_priv;
3401 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3406 * Need to copy setup packet into setup TRB, so we can't use the setup
3409 if (!urb->setup_packet)
3412 /* 1 TRB for setup, 1 for status */
3415 * Don't need to check if we need additional event data and normal TRBs,
3416 * since data in control transfers will never get bigger than 16MB
3417 * XXX: can we get a buffer that crosses 64KB boundaries?
3419 if (urb->transfer_buffer_length > 0)
3421 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3422 ep_index, urb->stream_id,
3423 num_trbs, urb, 0, mem_flags);
3427 urb_priv = urb->hcpriv;
3428 td = urb_priv->td[0];
3431 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3432 * until we've finished creating all the other TRBs. The ring's cycle
3433 * state may change as we enqueue the other TRBs, so save it too.
3435 start_trb = &ep_ring->enqueue->generic;
3436 start_cycle = ep_ring->cycle_state;
3438 /* Queue setup TRB - see section 6.4.1.2.1 */
3439 /* FIXME better way to translate setup_packet into two u32 fields? */
3440 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3442 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3443 if (start_cycle == 0)
3446 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3447 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3448 if (urb->transfer_buffer_length > 0) {
3449 if (setup->bRequestType & USB_DIR_IN)
3450 field |= TRB_TX_TYPE(TRB_DATA_IN);
3452 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3456 queue_trb(xhci, ep_ring, true,
3457 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3458 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3459 TRB_LEN(8) | TRB_INTR_TARGET(0),
3460 /* Immediate data in pointer */
3463 /* If there's data, queue data TRBs */
3464 /* Only set interrupt on short packet for IN endpoints */
3465 if (usb_urb_dir_in(urb))
3466 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3468 field = TRB_TYPE(TRB_DATA);
3470 remainder = xhci_td_remainder(xhci, 0,
3471 urb->transfer_buffer_length,
3472 urb->transfer_buffer_length,
3475 length_field = TRB_LEN(urb->transfer_buffer_length) |
3476 TRB_TD_SIZE(remainder) |
3479 if (urb->transfer_buffer_length > 0) {
3480 if (setup->bRequestType & USB_DIR_IN)
3481 field |= TRB_DIR_IN;
3482 queue_trb(xhci, ep_ring, true,
3483 lower_32_bits(urb->transfer_dma),
3484 upper_32_bits(urb->transfer_dma),
3486 field | ep_ring->cycle_state);
3489 /* Save the DMA address of the last TRB in the TD */
3490 td->last_trb = ep_ring->enqueue;
3492 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3493 /* If the device sent data, the status stage is an OUT transfer */
3494 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3498 queue_trb(xhci, ep_ring, false,
3502 /* Event on completion */
3503 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3505 giveback_first_trb(xhci, slot_id, ep_index, 0,
3506 start_cycle, start_trb);
3511 * The transfer burst count field of the isochronous TRB defines the number of
3512 * bursts that are required to move all packets in this TD. Only SuperSpeed
3513 * devices can burst up to bMaxBurst number of packets per service interval.
3514 * This field is zero based, meaning a value of zero in the field means one
3515 * burst. Basically, for everything but SuperSpeed devices, this field will be
3516 * zero. Only xHCI 1.0 host controllers support this field.
3518 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3519 struct urb *urb, unsigned int total_packet_count)
3521 unsigned int max_burst;
3523 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3526 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3527 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3531 * Returns the number of packets in the last "burst" of packets. This field is
3532 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3533 * the last burst packet count is equal to the total number of packets in the
3534 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3535 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3536 * contain 1 to (bMaxBurst + 1) packets.
3538 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3539 struct urb *urb, unsigned int total_packet_count)
3541 unsigned int max_burst;
3542 unsigned int residue;
3544 if (xhci->hci_version < 0x100)
3547 if (urb->dev->speed >= USB_SPEED_SUPER) {
3548 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3549 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3550 residue = total_packet_count % (max_burst + 1);
3551 /* If residue is zero, the last burst contains (max_burst + 1)
3552 * number of packets, but the TLBPC field is zero-based.
3558 if (total_packet_count == 0)
3560 return total_packet_count - 1;
3564 * Calculates Frame ID field of the isochronous TRB identifies the
3565 * target frame that the Interval associated with this Isochronous
3566 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3568 * Returns actual frame id on success, negative value on error.
3570 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3571 struct urb *urb, int index)
3573 int start_frame, ist, ret = 0;
3574 int start_frame_id, end_frame_id, current_frame_id;
3576 if (urb->dev->speed == USB_SPEED_LOW ||
3577 urb->dev->speed == USB_SPEED_FULL)
3578 start_frame = urb->start_frame + index * urb->interval;
3580 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3582 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3584 * If bit [3] of IST is cleared to '0', software can add a TRB no
3585 * later than IST[2:0] Microframes before that TRB is scheduled to
3587 * If bit [3] of IST is set to '1', software can add a TRB no later
3588 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3590 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3591 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3594 /* Software shall not schedule an Isoch TD with a Frame ID value that
3595 * is less than the Start Frame ID or greater than the End Frame ID,
3598 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3599 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3601 * Both the End Frame ID and Start Frame ID values are calculated
3602 * in microframes. When software determines the valid Frame ID value;
3603 * The End Frame ID value should be rounded down to the nearest Frame
3604 * boundary, and the Start Frame ID value should be rounded up to the
3605 * nearest Frame boundary.
3607 current_frame_id = readl(&xhci->run_regs->microframe_index);
3608 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3609 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3611 start_frame &= 0x7ff;
3612 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3613 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3615 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3616 __func__, index, readl(&xhci->run_regs->microframe_index),
3617 start_frame_id, end_frame_id, start_frame);
3619 if (start_frame_id < end_frame_id) {
3620 if (start_frame > end_frame_id ||
3621 start_frame < start_frame_id)
3623 } else if (start_frame_id > end_frame_id) {
3624 if ((start_frame > end_frame_id &&
3625 start_frame < start_frame_id))
3632 if (ret == -EINVAL || start_frame == start_frame_id) {
3633 start_frame = start_frame_id + 1;
3634 if (urb->dev->speed == USB_SPEED_LOW ||
3635 urb->dev->speed == USB_SPEED_FULL)
3636 urb->start_frame = start_frame;
3638 urb->start_frame = start_frame << 3;
3644 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3645 start_frame, current_frame_id, index,
3646 start_frame_id, end_frame_id);
3647 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3654 /* This is for isoc transfer */
3655 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3656 struct urb *urb, int slot_id, unsigned int ep_index)
3658 struct xhci_ring *ep_ring;
3659 struct urb_priv *urb_priv;
3661 int num_tds, trbs_per_td;
3662 struct xhci_generic_trb *start_trb;
3665 u32 field, length_field;
3666 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3667 u64 start_addr, addr;
3669 bool more_trbs_coming;
3670 struct xhci_virt_ep *xep;
3673 xep = &xhci->devs[slot_id]->eps[ep_index];
3674 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3676 num_tds = urb->number_of_packets;
3678 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3681 start_addr = (u64) urb->transfer_dma;
3682 start_trb = &ep_ring->enqueue->generic;
3683 start_cycle = ep_ring->cycle_state;
3685 urb_priv = urb->hcpriv;
3686 /* Queue the TRBs for each TD, even if they are zero-length */
3687 for (i = 0; i < num_tds; i++) {
3688 unsigned int total_pkt_count, max_pkt;
3689 unsigned int burst_count, last_burst_pkt_count;
3694 addr = start_addr + urb->iso_frame_desc[i].offset;
3695 td_len = urb->iso_frame_desc[i].length;
3696 td_remain_len = td_len;
3697 max_pkt = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3698 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3700 /* A zero-length transfer still involves at least one packet. */
3701 if (total_pkt_count == 0)
3703 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3704 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3705 urb, total_pkt_count);
3707 trbs_per_td = count_isoc_trbs_needed(urb, i);
3709 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3710 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3716 td = urb_priv->td[i];
3718 /* use SIA as default, if frame id is used overwrite it */
3719 sia_frame_id = TRB_SIA;
3720 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3721 HCC_CFC(xhci->hcc_params)) {
3722 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3724 sia_frame_id = TRB_FRAME_ID(frame_id);
3727 * Set isoc specific data for the first TRB in a TD.
3728 * Prevent HW from getting the TRBs by keeping the cycle state
3729 * inverted in the first TDs isoc TRB.
3731 field = TRB_TYPE(TRB_ISOC) |
3732 TRB_TLBPC(last_burst_pkt_count) |
3734 (i ? ep_ring->cycle_state : !start_cycle);
3736 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3737 if (!xep->use_extended_tbc)
3738 field |= TRB_TBC(burst_count);
3740 /* fill the rest of the TRB fields, and remaining normal TRBs */
3741 for (j = 0; j < trbs_per_td; j++) {
3744 /* only first TRB is isoc, overwrite otherwise */
3746 field = TRB_TYPE(TRB_NORMAL) |
3747 ep_ring->cycle_state;
3749 /* Only set interrupt on short packet for IN EPs */
3750 if (usb_urb_dir_in(urb))
3753 /* Set the chain bit for all except the last TRB */
3754 if (j < trbs_per_td - 1) {
3755 more_trbs_coming = true;
3758 more_trbs_coming = false;
3759 td->last_trb = ep_ring->enqueue;
3761 /* set BEI, except for the last TD */
3762 if (xhci->hci_version >= 0x100 &&
3763 !(xhci->quirks & XHCI_AVOID_BEI) &&
3767 /* Calculate TRB length */
3768 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3769 if (trb_buff_len > td_remain_len)
3770 trb_buff_len = td_remain_len;
3772 /* Set the TRB length, TD size, & interrupter fields. */
3773 remainder = xhci_td_remainder(xhci, running_total,
3774 trb_buff_len, td_len,
3775 urb, more_trbs_coming);
3777 length_field = TRB_LEN(trb_buff_len) |
3780 /* xhci 1.1 with ETE uses TD Size field for TBC */
3781 if (first_trb && xep->use_extended_tbc)
3782 length_field |= TRB_TD_SIZE_TBC(burst_count);
3784 length_field |= TRB_TD_SIZE(remainder);
3787 queue_trb(xhci, ep_ring, more_trbs_coming,
3788 lower_32_bits(addr),
3789 upper_32_bits(addr),
3792 running_total += trb_buff_len;
3794 addr += trb_buff_len;
3795 td_remain_len -= trb_buff_len;
3798 /* Check TD length */
3799 if (running_total != td_len) {
3800 xhci_err(xhci, "ISOC TD length unmatch\n");
3806 /* store the next frame id */
3807 if (HCC_CFC(xhci->hcc_params))
3808 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3810 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3811 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3812 usb_amd_quirk_pll_disable();
3814 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3816 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3817 start_cycle, start_trb);
3820 /* Clean up a partially enqueued isoc transfer. */
3822 for (i--; i >= 0; i--)
3823 list_del_init(&urb_priv->td[i]->td_list);
3825 /* Use the first TD as a temporary variable to turn the TDs we've queued
3826 * into No-ops with a software-owned cycle bit. That way the hardware
3827 * won't accidentally start executing bogus TDs when we partially
3828 * overwrite them. td->first_trb and td->start_seg are already set.
3830 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3831 /* Every TRB except the first & last will have its cycle bit flipped. */
3832 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3834 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3835 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3836 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3837 ep_ring->cycle_state = start_cycle;
3838 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3839 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3844 * Check transfer ring to guarantee there is enough room for the urb.
3845 * Update ISO URB start_frame and interval.
3846 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3847 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3848 * Contiguous Frame ID is not supported by HC.
3850 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3851 struct urb *urb, int slot_id, unsigned int ep_index)
3853 struct xhci_virt_device *xdev;
3854 struct xhci_ring *ep_ring;
3855 struct xhci_ep_ctx *ep_ctx;
3857 int num_tds, num_trbs, i;
3859 struct xhci_virt_ep *xep;
3862 xdev = xhci->devs[slot_id];
3863 xep = &xhci->devs[slot_id]->eps[ep_index];
3864 ep_ring = xdev->eps[ep_index].ring;
3865 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3868 num_tds = urb->number_of_packets;
3869 for (i = 0; i < num_tds; i++)
3870 num_trbs += count_isoc_trbs_needed(urb, i);
3872 /* Check the ring to guarantee there is enough room for the whole urb.
3873 * Do not insert any td of the urb to the ring if the check failed.
3875 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3876 num_trbs, mem_flags);
3881 * Check interval value. This should be done before we start to
3882 * calculate the start frame value.
3884 check_interval(xhci, urb, ep_ctx);
3886 /* Calculate the start frame and put it in urb->start_frame. */
3887 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3888 if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
3890 urb->start_frame = xep->next_frame_id;
3891 goto skip_start_over;
3895 start_frame = readl(&xhci->run_regs->microframe_index);
3896 start_frame &= 0x3fff;
3898 * Round up to the next frame and consider the time before trb really
3899 * gets scheduled by hardare.
3901 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3902 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3904 start_frame += ist + XHCI_CFC_DELAY;
3905 start_frame = roundup(start_frame, 8);
3908 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
3909 * is greate than 8 microframes.
3911 if (urb->dev->speed == USB_SPEED_LOW ||
3912 urb->dev->speed == USB_SPEED_FULL) {
3913 start_frame = roundup(start_frame, urb->interval << 3);
3914 urb->start_frame = start_frame >> 3;
3916 start_frame = roundup(start_frame, urb->interval);
3917 urb->start_frame = start_frame;
3921 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3923 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3926 /**** Command Ring Operations ****/
3928 /* Generic function for queueing a command TRB on the command ring.
3929 * Check to make sure there's room on the command ring for one command TRB.
3930 * Also check that there's room reserved for commands that must not fail.
3931 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3932 * then only check for the number of reserved spots.
3933 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3934 * because the command event handler may want to resubmit a failed command.
3936 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3937 u32 field1, u32 field2,
3938 u32 field3, u32 field4, bool command_must_succeed)
3940 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3943 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3944 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3945 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
3949 if (!command_must_succeed)
3952 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3953 reserved_trbs, GFP_ATOMIC);
3955 xhci_err(xhci, "ERR: No room for command on command ring\n");
3956 if (command_must_succeed)
3957 xhci_err(xhci, "ERR: Reserved TRB counting for "
3958 "unfailable commands failed.\n");
3962 cmd->command_trb = xhci->cmd_ring->enqueue;
3963 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3965 /* if there are no other commands queued we start the timeout timer */
3966 if (xhci->cmd_list.next == &cmd->cmd_list &&
3967 !delayed_work_pending(&xhci->cmd_timer)) {
3968 xhci->current_cmd = cmd;
3969 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
3972 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3973 field4 | xhci->cmd_ring->cycle_state);
3977 /* Queue a slot enable or disable request on the command ring */
3978 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3979 u32 trb_type, u32 slot_id)
3981 return queue_command(xhci, cmd, 0, 0, 0,
3982 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3985 /* Queue an address device command TRB */
3986 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3987 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3989 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3990 upper_32_bits(in_ctx_ptr), 0,
3991 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3992 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
3995 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3996 u32 field1, u32 field2, u32 field3, u32 field4)
3998 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4001 /* Queue a reset device command TRB */
4002 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4005 return queue_command(xhci, cmd, 0, 0, 0,
4006 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4010 /* Queue a configure endpoint command TRB */
4011 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4012 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4013 u32 slot_id, bool command_must_succeed)
4015 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4016 upper_32_bits(in_ctx_ptr), 0,
4017 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4018 command_must_succeed);
4021 /* Queue an evaluate context command TRB */
4022 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4023 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4025 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4026 upper_32_bits(in_ctx_ptr), 0,
4027 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4028 command_must_succeed);
4032 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4033 * activity on an endpoint that is about to be suspended.
4035 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4036 int slot_id, unsigned int ep_index, int suspend)
4038 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4039 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4040 u32 type = TRB_TYPE(TRB_STOP_RING);
4041 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4043 return queue_command(xhci, cmd, 0, 0, 0,
4044 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4047 /* Set Transfer Ring Dequeue Pointer command */
4048 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4049 unsigned int slot_id, unsigned int ep_index,
4050 unsigned int stream_id,
4051 struct xhci_dequeue_state *deq_state)
4054 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4055 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4056 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4058 u32 type = TRB_TYPE(TRB_SET_DEQ);
4059 struct xhci_virt_ep *ep;
4060 struct xhci_command *cmd;
4063 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4064 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4065 deq_state->new_deq_seg,
4066 (unsigned long long)deq_state->new_deq_seg->dma,
4067 deq_state->new_deq_ptr,
4068 (unsigned long long)xhci_trb_virt_to_dma(
4069 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4070 deq_state->new_cycle_state);
4072 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4073 deq_state->new_deq_ptr);
4075 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4076 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4077 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4080 ep = &xhci->devs[slot_id]->eps[ep_index];
4081 if ((ep->ep_state & SET_DEQ_PENDING)) {
4082 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4083 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4087 /* This function gets called from contexts where it cannot sleep */
4088 cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
4090 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n");
4094 ep->queued_deq_seg = deq_state->new_deq_seg;
4095 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4097 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4098 ret = queue_command(xhci, cmd,
4099 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4100 upper_32_bits(addr), trb_stream_id,
4101 trb_slot_id | trb_ep_index | type, false);
4103 xhci_free_command(xhci, cmd);
4107 /* Stop the TD queueing code from ringing the doorbell until
4108 * this command completes. The HC won't set the dequeue pointer
4109 * if the ring is running, and ringing the doorbell starts the
4112 ep->ep_state |= SET_DEQ_PENDING;
4115 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4116 int slot_id, unsigned int ep_index)
4118 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4119 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4120 u32 type = TRB_TYPE(TRB_RESET_EP);
4122 return queue_command(xhci, cmd, 0, 0, 0,
4123 trb_slot_id | trb_ep_index | type, false);