1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
59 #include "xhci-trace.h"
61 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
62 u32 field1, u32 field2,
63 u32 field3, u32 field4, bool command_must_succeed);
66 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
69 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
72 unsigned long segment_offset;
74 if (!seg || !trb || trb < seg->trbs)
77 segment_offset = trb - seg->trbs;
78 if (segment_offset >= TRBS_PER_SEGMENT)
80 return seg->dma + (segment_offset * sizeof(*trb));
83 static bool trb_is_noop(union xhci_trb *trb)
85 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
88 static bool trb_is_link(union xhci_trb *trb)
90 return TRB_TYPE_LINK_LE32(trb->link.control);
93 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
95 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
98 static bool last_trb_on_ring(struct xhci_ring *ring,
99 struct xhci_segment *seg, union xhci_trb *trb)
101 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
104 static bool link_trb_toggles_cycle(union xhci_trb *trb)
106 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
109 static bool last_td_in_urb(struct xhci_td *td)
111 struct urb_priv *urb_priv = td->urb->hcpriv;
113 return urb_priv->num_tds_done == urb_priv->num_tds;
116 static void inc_td_cnt(struct urb *urb)
118 struct urb_priv *urb_priv = urb->hcpriv;
120 urb_priv->num_tds_done++;
123 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
125 if (trb_is_link(trb)) {
126 /* unchain chained link TRBs */
127 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
129 trb->generic.field[0] = 0;
130 trb->generic.field[1] = 0;
131 trb->generic.field[2] = 0;
132 /* Preserve only the cycle bit of this TRB */
133 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
134 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
138 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
139 * TRB is in a new segment. This does not skip over link TRBs, and it does not
140 * effect the ring dequeue or enqueue pointers.
142 static void next_trb(struct xhci_hcd *xhci,
143 struct xhci_ring *ring,
144 struct xhci_segment **seg,
145 union xhci_trb **trb)
147 if (trb_is_link(*trb) || last_trb_on_seg(*seg, *trb)) {
149 *trb = ((*seg)->trbs);
156 * See Cycle bit rules. SW is the consumer for the event ring only.
158 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
160 unsigned int link_trb_count = 0;
162 /* event ring doesn't have link trbs, check for last trb */
163 if (ring->type == TYPE_EVENT) {
164 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
168 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
169 ring->cycle_state ^= 1;
170 ring->deq_seg = ring->deq_seg->next;
171 ring->dequeue = ring->deq_seg->trbs;
175 /* All other rings have link trbs */
176 if (!trb_is_link(ring->dequeue)) {
177 if (last_trb_on_seg(ring->deq_seg, ring->dequeue))
178 xhci_warn(xhci, "Missing link TRB at end of segment\n");
183 while (trb_is_link(ring->dequeue)) {
184 ring->deq_seg = ring->deq_seg->next;
185 ring->dequeue = ring->deq_seg->trbs;
187 if (link_trb_count++ > ring->num_segs) {
188 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
193 trace_xhci_inc_deq(ring);
199 * See Cycle bit rules. SW is the consumer for the event ring only.
201 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
202 * chain bit is set), then set the chain bit in all the following link TRBs.
203 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
204 * have their chain bit cleared (so that each Link TRB is a separate TD).
206 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
207 * set, but other sections talk about dealing with the chain bit set. This was
208 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
209 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
211 * @more_trbs_coming: Will you enqueue more TRBs before calling
212 * prepare_transfer()?
214 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
215 bool more_trbs_coming)
218 union xhci_trb *next;
219 unsigned int link_trb_count = 0;
221 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
223 if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
224 xhci_err(xhci, "Tried to move enqueue past ring segment\n");
228 next = ++(ring->enqueue);
230 /* Update the dequeue pointer further if that was a link TRB */
231 while (trb_is_link(next)) {
234 * If the caller doesn't plan on enqueueing more TDs before
235 * ringing the doorbell, then we don't want to give the link TRB
236 * to the hardware just yet. We'll give the link TRB back in
237 * prepare_ring() just before we enqueue the TD at the top of
240 if (!chain && !more_trbs_coming)
243 /* If we're not dealing with 0.95 hardware or isoc rings on
244 * AMD 0.96 host, carry over the chain bit of the previous TRB
245 * (which may mean the chain bit is cleared).
247 if (!(ring->type == TYPE_ISOC &&
248 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
249 !xhci_link_trb_quirk(xhci)) {
250 next->link.control &= cpu_to_le32(~TRB_CHAIN);
251 next->link.control |= cpu_to_le32(chain);
253 /* Give this link TRB to the hardware */
255 next->link.control ^= cpu_to_le32(TRB_CYCLE);
257 /* Toggle the cycle bit after the last ring segment. */
258 if (link_trb_toggles_cycle(next))
259 ring->cycle_state ^= 1;
261 ring->enq_seg = ring->enq_seg->next;
262 ring->enqueue = ring->enq_seg->trbs;
263 next = ring->enqueue;
265 if (link_trb_count++ > ring->num_segs) {
266 xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__);
271 trace_xhci_inc_enq(ring);
275 * Return number of free normal TRBs from enqueue to dequeue pointer on ring.
276 * Not counting an assumed link TRB at end of each TRBS_PER_SEGMENT sized segment.
277 * Only for transfer and command rings where driver is the producer, not for
280 static unsigned int xhci_num_trbs_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
282 struct xhci_segment *enq_seg = ring->enq_seg;
283 union xhci_trb *enq = ring->enqueue;
284 union xhci_trb *last_on_seg;
285 unsigned int free = 0;
288 /* Ring might be empty even if enq != deq if enq is left on a link trb */
289 if (trb_is_link(enq)) {
290 enq_seg = enq_seg->next;
294 /* Empty ring, common case, don't walk the segments */
295 if (enq == ring->dequeue)
296 return ring->num_segs * (TRBS_PER_SEGMENT - 1);
299 if (ring->deq_seg == enq_seg && ring->dequeue >= enq)
300 return free + (ring->dequeue - enq);
301 last_on_seg = &enq_seg->trbs[TRBS_PER_SEGMENT - 1];
302 free += last_on_seg - enq;
303 enq_seg = enq_seg->next;
305 } while (i++ <= ring->num_segs);
311 * Check to see if there's room to enqueue num_trbs on the ring and make sure
312 * enqueue pointer will not advance into dequeue segment. See rules above.
313 * return number of new segments needed to ensure this.
316 static unsigned int xhci_ring_expansion_needed(struct xhci_hcd *xhci, struct xhci_ring *ring,
317 unsigned int num_trbs)
319 struct xhci_segment *seg;
324 enq_used = ring->enqueue - ring->enq_seg->trbs;
326 /* how many trbs will be queued past the enqueue segment? */
327 trbs_past_seg = enq_used + num_trbs - (TRBS_PER_SEGMENT - 1);
330 * Consider expanding the ring already if num_trbs fills the current
331 * segment (i.e. trbs_past_seg == 0), not only when num_trbs goes into
332 * the next segment. Avoids confusing full ring with special empty ring
335 if (trbs_past_seg < 0)
338 /* Empty ring special case, enqueue stuck on link trb while dequeue advanced */
339 if (trb_is_link(ring->enqueue) && ring->enq_seg->next->trbs == ring->dequeue)
342 new_segs = 1 + (trbs_past_seg / (TRBS_PER_SEGMENT - 1));
345 while (new_segs > 0) {
347 if (seg == ring->deq_seg) {
348 xhci_dbg(xhci, "Ring expansion by %d segments needed\n",
350 xhci_dbg(xhci, "Adding %d trbs moves enq %d trbs into deq seg\n",
351 num_trbs, trbs_past_seg % TRBS_PER_SEGMENT);
360 /* Ring the host controller doorbell after placing a command on the ring */
361 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
363 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
366 xhci_dbg(xhci, "// Ding dong!\n");
368 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
370 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
371 /* Flush PCI posted writes */
372 readl(&xhci->dba->doorbell[0]);
375 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci)
377 return mod_delayed_work(system_wq, &xhci->cmd_timer,
378 msecs_to_jiffies(xhci->current_cmd->timeout_ms));
381 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
383 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
388 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
389 * If there are other commands waiting then restart the ring and kick the timer.
390 * This must be called with command ring stopped and xhci->lock held.
392 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
393 struct xhci_command *cur_cmd)
395 struct xhci_command *i_cmd;
397 /* Turn all aborted commands in list to no-ops, then restart */
398 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
400 if (i_cmd->status != COMP_COMMAND_ABORTED)
403 i_cmd->status = COMP_COMMAND_RING_STOPPED;
405 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
408 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
411 * caller waiting for completion is called when command
412 * completion event is received for these no-op commands
416 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
418 /* ring command ring doorbell to restart the command ring */
419 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
420 !(xhci->xhc_state & XHCI_STATE_DYING)) {
421 xhci->current_cmd = cur_cmd;
422 xhci_mod_cmd_timer(xhci);
423 xhci_ring_cmd_db(xhci);
427 /* Must be called with xhci->lock held, releases and aquires lock back */
428 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
430 struct xhci_segment *new_seg = xhci->cmd_ring->deq_seg;
431 union xhci_trb *new_deq = xhci->cmd_ring->dequeue;
435 xhci_dbg(xhci, "Abort command ring\n");
437 reinit_completion(&xhci->cmd_ring_stop_completion);
440 * The control bits like command stop, abort are located in lower
441 * dword of the command ring control register.
442 * Some controllers require all 64 bits to be written to abort the ring.
443 * Make sure the upper dword is valid, pointing to the next command,
444 * avoiding corrupting the command ring pointer in case the command ring
445 * is stopped by the time the upper dword is written.
447 next_trb(xhci, NULL, &new_seg, &new_deq);
448 if (trb_is_link(new_deq))
449 next_trb(xhci, NULL, &new_seg, &new_deq);
451 crcr = xhci_trb_virt_to_dma(new_seg, new_deq);
452 xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
454 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
455 * completion of the Command Abort operation. If CRR is not negated in 5
456 * seconds then driver handles it as if host died (-ENODEV).
457 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
458 * and try to recover a -ETIMEDOUT with a host controller reset.
460 ret = xhci_handshake_check_state(xhci, &xhci->op_regs->cmd_ring,
461 CMD_RING_RUNNING, 0, 5 * 1000 * 1000,
462 XHCI_STATE_REMOVING);
464 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
470 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
471 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
472 * but the completion event in never sent. Wait 2 secs (arbitrary
473 * number) to handle those cases after negation of CMD_RING_RUNNING.
475 spin_unlock_irqrestore(&xhci->lock, flags);
476 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
477 msecs_to_jiffies(2000));
478 spin_lock_irqsave(&xhci->lock, flags);
480 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
481 xhci_cleanup_command_queue(xhci);
483 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
488 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
489 unsigned int slot_id,
490 unsigned int ep_index,
491 unsigned int stream_id)
493 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
494 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
495 unsigned int ep_state = ep->ep_state;
497 /* Don't ring the doorbell for this endpoint if there are pending
498 * cancellations because we don't want to interrupt processing.
499 * We don't want to restart any stream rings if there's a set dequeue
500 * pointer command pending because the device can choose to start any
501 * stream once the endpoint is on the HW schedule.
503 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
504 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
507 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
509 writel(DB_VALUE(ep_index, stream_id), db_addr);
510 /* flush the write */
514 /* Ring the doorbell for any rings with pending URBs */
515 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
516 unsigned int slot_id,
517 unsigned int ep_index)
519 unsigned int stream_id;
520 struct xhci_virt_ep *ep;
522 ep = &xhci->devs[slot_id]->eps[ep_index];
524 /* A ring has pending URBs if its TD list is not empty */
525 if (!(ep->ep_state & EP_HAS_STREAMS)) {
526 if (ep->ring && !(list_empty(&ep->ring->td_list)))
527 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
531 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
533 struct xhci_stream_info *stream_info = ep->stream_info;
534 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
535 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
540 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
541 unsigned int slot_id,
542 unsigned int ep_index)
544 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
547 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
548 unsigned int slot_id,
549 unsigned int ep_index)
551 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
552 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
555 if (ep_index >= EP_CTX_PER_DEV) {
556 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
559 if (!xhci->devs[slot_id]) {
560 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
564 return &xhci->devs[slot_id]->eps[ep_index];
567 static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
568 struct xhci_virt_ep *ep,
569 unsigned int stream_id)
571 /* common case, no streams */
572 if (!(ep->ep_state & EP_HAS_STREAMS))
575 if (!ep->stream_info)
578 if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
579 xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
580 stream_id, ep->vdev->slot_id, ep->ep_index);
584 return ep->stream_info->stream_rings[stream_id];
587 /* Get the right ring for the given slot_id, ep_index and stream_id.
588 * If the endpoint supports streams, boundary check the URB's stream ID.
589 * If the endpoint doesn't support streams, return the singular endpoint ring.
591 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
592 unsigned int slot_id, unsigned int ep_index,
593 unsigned int stream_id)
595 struct xhci_virt_ep *ep;
597 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
601 return xhci_virt_ep_to_ring(xhci, ep, stream_id);
606 * Get the hw dequeue pointer xHC stopped on, either directly from the
607 * endpoint context, or if streams are in use from the stream context.
608 * The returned hw_dequeue contains the lowest four bits with cycle state
609 * and possbile stream context type.
611 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
612 unsigned int ep_index, unsigned int stream_id)
614 struct xhci_ep_ctx *ep_ctx;
615 struct xhci_stream_ctx *st_ctx;
616 struct xhci_virt_ep *ep;
618 ep = &vdev->eps[ep_index];
620 if (ep->ep_state & EP_HAS_STREAMS) {
621 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
622 return le64_to_cpu(st_ctx->stream_ring);
624 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
625 return le64_to_cpu(ep_ctx->deq);
628 static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci,
629 unsigned int slot_id, unsigned int ep_index,
630 unsigned int stream_id, struct xhci_td *td)
632 struct xhci_virt_device *dev = xhci->devs[slot_id];
633 struct xhci_virt_ep *ep = &dev->eps[ep_index];
634 struct xhci_ring *ep_ring;
635 struct xhci_command *cmd;
636 struct xhci_segment *new_seg;
637 union xhci_trb *new_deq;
641 bool cycle_found = false;
642 bool td_last_trb_found = false;
646 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
647 ep_index, stream_id);
649 xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n",
654 * A cancelled TD can complete with a stall if HW cached the trb.
655 * In this case driver can't find td, but if the ring is empty we
656 * can move the dequeue pointer to the current enqueue position.
657 * We shouldn't hit this anymore as cached cancelled TRBs are given back
658 * after clearing the cache, but be on the safe side and keep it anyway
661 if (list_empty(&ep_ring->td_list)) {
662 new_seg = ep_ring->enq_seg;
663 new_deq = ep_ring->enqueue;
664 new_cycle = ep_ring->cycle_state;
665 xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue");
668 xhci_warn(xhci, "Can't find new dequeue state, missing td\n");
673 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
674 new_seg = ep_ring->deq_seg;
675 new_deq = ep_ring->dequeue;
676 new_cycle = hw_dequeue & 0x1;
679 * We want to find the pointer, segment and cycle state of the new trb
680 * (the one after current TD's last_trb). We know the cycle state at
681 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
685 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
686 == (dma_addr_t)(hw_dequeue & ~0xf)) {
688 if (td_last_trb_found)
691 if (new_deq == td->last_trb)
692 td_last_trb_found = true;
694 if (cycle_found && trb_is_link(new_deq) &&
695 link_trb_toggles_cycle(new_deq))
698 next_trb(xhci, ep_ring, &new_seg, &new_deq);
700 /* Search wrapped around, bail out */
701 if (new_deq == ep->ring->dequeue) {
702 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
706 } while (!cycle_found || !td_last_trb_found);
710 /* Don't update the ring cycle state for the producer (us). */
711 addr = xhci_trb_virt_to_dma(new_seg, new_deq);
713 xhci_warn(xhci, "Can't find dma of new dequeue ptr\n");
714 xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq);
718 if ((ep->ep_state & SET_DEQ_PENDING)) {
719 xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
724 /* This function gets called from contexts where it cannot sleep */
725 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
727 xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
732 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
733 ret = queue_command(xhci, cmd,
734 lower_32_bits(addr) | trb_sct | new_cycle,
736 STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) |
737 EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
739 xhci_free_command(xhci, cmd);
742 ep->queued_deq_seg = new_seg;
743 ep->queued_deq_ptr = new_deq;
745 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
746 "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle);
748 /* Stop the TD queueing code from ringing the doorbell until
749 * this command completes. The HC won't set the dequeue pointer
750 * if the ring is running, and ringing the doorbell starts the
753 ep->ep_state |= SET_DEQ_PENDING;
754 xhci_ring_cmd_db(xhci);
758 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
759 * (The last TRB actually points to the ring enqueue pointer, which is not part
760 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
762 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
763 struct xhci_td *td, bool flip_cycle)
765 struct xhci_segment *seg = td->start_seg;
766 union xhci_trb *trb = td->first_trb;
769 trb_to_noop(trb, TRB_TR_NOOP);
771 /* flip cycle if asked to */
772 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
773 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
775 if (trb == td->last_trb)
778 next_trb(xhci, ep_ring, &seg, &trb);
783 * Must be called with xhci->lock held in interrupt context,
784 * releases and re-acquires xhci->lock
786 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
787 struct xhci_td *cur_td, int status)
789 struct urb *urb = cur_td->urb;
790 struct urb_priv *urb_priv = urb->hcpriv;
791 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
793 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
794 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
795 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
796 if (xhci->quirks & XHCI_AMD_PLL_FIX)
797 usb_amd_quirk_pll_enable();
800 xhci_urb_free_priv(urb_priv);
801 usb_hcd_unlink_urb_from_ep(hcd, urb);
802 trace_xhci_urb_giveback(urb);
803 usb_hcd_giveback_urb(hcd, urb, status);
806 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
807 struct xhci_ring *ring, struct xhci_td *td)
809 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
810 struct xhci_segment *seg = td->bounce_seg;
811 struct urb *urb = td->urb;
814 if (!ring || !seg || !urb)
817 if (usb_urb_dir_out(urb)) {
818 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
823 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
825 /* for in tranfers we need to copy the data from bounce to sg */
827 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
828 seg->bounce_len, seg->bounce_offs);
829 if (len != seg->bounce_len)
830 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
831 len, seg->bounce_len);
833 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
837 seg->bounce_offs = 0;
840 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
841 struct xhci_ring *ep_ring, int status)
843 struct urb *urb = NULL;
845 /* Clean up the endpoint's TD list */
848 /* if a bounce buffer was used to align this td then unmap it */
849 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
851 /* Do one last check of the actual transfer length.
852 * If the host controller said we transferred more data than the buffer
853 * length, urb->actual_length will be a very big number (since it's
854 * unsigned). Play it safe and say we didn't transfer anything.
856 if (urb->actual_length > urb->transfer_buffer_length) {
857 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
858 urb->transfer_buffer_length, urb->actual_length);
859 urb->actual_length = 0;
862 /* TD might be removed from td_list if we are giving back a cancelled URB */
863 if (!list_empty(&td->td_list))
864 list_del_init(&td->td_list);
865 /* Giving back a cancelled URB, or if a slated TD completed anyway */
866 if (!list_empty(&td->cancelled_td_list))
867 list_del_init(&td->cancelled_td_list);
870 /* Giveback the urb when all the tds are completed */
871 if (last_td_in_urb(td)) {
872 if ((urb->actual_length != urb->transfer_buffer_length &&
873 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
874 (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
875 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
876 urb, urb->actual_length,
877 urb->transfer_buffer_length, status);
879 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
880 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
882 xhci_giveback_urb_in_irq(xhci, td, status);
889 /* Complete the cancelled URBs we unlinked from td_list. */
890 static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep)
892 struct xhci_ring *ring;
893 struct xhci_td *td, *tmp_td;
895 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
898 ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
900 if (td->cancel_status == TD_CLEARED) {
901 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
903 xhci_td_cleanup(ep->xhci, td, ring, td->status);
905 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
906 __func__, td->urb, td->cancel_status);
908 if (ep->xhci->xhc_state & XHCI_STATE_DYING)
913 static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
914 unsigned int ep_index, enum xhci_ep_reset_type reset_type)
916 struct xhci_command *command;
919 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
925 xhci_dbg(xhci, "%s-reset ep %u, slot %u\n",
926 (reset_type == EP_HARD_RESET) ? "Hard" : "Soft",
929 ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
932 xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
933 slot_id, ep_index, ret);
937 static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci,
938 struct xhci_virt_ep *ep,
940 enum xhci_ep_reset_type reset_type)
942 unsigned int slot_id = ep->vdev->slot_id;
946 * Avoid resetting endpoint if link is inactive. Can cause host hang.
947 * Device will be reset soon to recover the link so don't do anything
949 if (ep->vdev->flags & VDEV_PORT_ERROR)
952 /* add td to cancelled list and let reset ep handler take care of it */
953 if (reset_type == EP_HARD_RESET) {
954 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
955 if (td && list_empty(&td->cancelled_td_list)) {
956 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
957 td->cancel_status = TD_HALTED;
961 if (ep->ep_state & EP_HALTED) {
962 xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n",
967 err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
971 ep->ep_state |= EP_HALTED;
973 xhci_ring_cmd_db(xhci);
979 * Fix up the ep ring first, so HW stops executing cancelled TDs.
980 * We have the xHCI lock, so nothing can modify this list until we drop it.
981 * We're also in the event handler, so we can't get re-interrupted if another
982 * Stop Endpoint command completes.
984 * only call this when ring is not in a running state
987 static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep)
989 struct xhci_hcd *xhci;
990 struct xhci_td *td = NULL;
991 struct xhci_td *tmp_td = NULL;
992 struct xhci_td *cached_td = NULL;
993 struct xhci_ring *ring;
995 unsigned int slot_id = ep->vdev->slot_id;
1000 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1001 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1002 "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p",
1003 (unsigned long long)xhci_trb_virt_to_dma(
1004 td->start_seg, td->first_trb),
1005 td->urb->stream_id, td->urb);
1006 list_del_init(&td->td_list);
1007 ring = xhci_urb_to_transfer_ring(xhci, td->urb);
1009 xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n",
1010 td->urb, td->urb->stream_id);
1014 * If a ring stopped on the TD we need to cancel then we have to
1015 * move the xHC endpoint ring dequeue pointer past this TD.
1016 * Rings halted due to STALL may show hw_deq is past the stalled
1017 * TD, but still require a set TR Deq command to flush xHC cache.
1019 hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,
1020 td->urb->stream_id);
1023 if (td->cancel_status == TD_HALTED ||
1024 trb_in_td(xhci, td->start_seg, td->first_trb, td->last_trb, hw_deq, false)) {
1025 switch (td->cancel_status) {
1026 case TD_CLEARED: /* TD is already no-op */
1027 case TD_CLEARING_CACHE: /* set TR deq command already queued */
1029 case TD_DIRTY: /* TD is cached, clear it */
1031 td->cancel_status = TD_CLEARING_CACHE;
1033 /* FIXME stream case, several stopped rings */
1035 "Move dq past stream %u URB %p instead of stream %u URB %p\n",
1036 td->urb->stream_id, td->urb,
1037 cached_td->urb->stream_id, cached_td->urb);
1042 td_to_noop(xhci, ring, td, false);
1043 td->cancel_status = TD_CLEARED;
1047 /* If there's no need to move the dequeue pointer then we're done */
1051 err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index,
1052 cached_td->urb->stream_id,
1055 /* Failed to move past cached td, just set cached TDs to no-op */
1056 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1057 if (td->cancel_status != TD_CLEARING_CACHE)
1059 xhci_dbg(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n",
1061 td_to_noop(xhci, ring, td, false);
1062 td->cancel_status = TD_CLEARED;
1069 * Returns the TD the endpoint ring halted on.
1070 * Only call for non-running rings without streams.
1072 static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep)
1077 if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */
1078 hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0);
1080 td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list);
1081 if (trb_in_td(ep->xhci, td->start_seg, td->first_trb,
1082 td->last_trb, hw_deq, false))
1089 * When we get a command completion for a Stop Endpoint Command, we need to
1090 * unlink any cancelled TDs from the ring. There are two ways to do that:
1092 * 1. If the HW was in the middle of processing the TD that needs to be
1093 * cancelled, then we must move the ring's dequeue pointer past the last TRB
1094 * in the TD with a Set Dequeue Pointer Command.
1095 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1096 * bit cleared) so that the HW will skip over them.
1098 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
1099 union xhci_trb *trb, u32 comp_code)
1101 unsigned int ep_index;
1102 struct xhci_virt_ep *ep;
1103 struct xhci_ep_ctx *ep_ctx;
1104 struct xhci_td *td = NULL;
1105 enum xhci_ep_reset_type reset_type;
1106 struct xhci_command *command;
1109 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
1110 if (!xhci->devs[slot_id])
1111 xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n",
1116 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1117 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1121 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1123 trace_xhci_handle_cmd_stop_ep(ep_ctx);
1125 if (comp_code == COMP_CONTEXT_STATE_ERROR) {
1127 * If stop endpoint command raced with a halting endpoint we need to
1128 * reset the host side endpoint first.
1129 * If the TD we halted on isn't cancelled the TD should be given back
1130 * with a proper error code, and the ring dequeue moved past the TD.
1131 * If streams case we can't find hw_deq, or the TD we halted on so do a
1134 * Proper error code is unknown here, it would be -EPIPE if device side
1135 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1136 * We use -EPROTO, if device is stalled it should return a stall error on
1137 * next transfer, which then will return -EPIPE, and device side stall is
1138 * noted and cleared by class driver.
1140 switch (GET_EP_CTX_STATE(ep_ctx)) {
1141 case EP_STATE_HALTED:
1142 xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n");
1143 if (ep->ep_state & EP_HAS_STREAMS) {
1144 reset_type = EP_SOFT_RESET;
1146 reset_type = EP_HARD_RESET;
1147 td = find_halted_td(ep);
1149 td->status = -EPROTO;
1151 /* reset ep, reset handler cleans up cancelled tds */
1152 err = xhci_handle_halted_endpoint(xhci, ep, td, reset_type);
1155 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1157 case EP_STATE_RUNNING:
1158 /* Race, HW handled stop ep cmd before ep was running */
1159 xhci_dbg(xhci, "Stop ep completion ctx error, ep is running\n");
1161 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1163 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1166 xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0);
1167 xhci_ring_cmd_db(xhci);
1175 /* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1176 xhci_invalidate_cancelled_tds(ep);
1177 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1179 /* Otherwise ring the doorbell(s) to restart queued transfers */
1180 xhci_giveback_invalidated_tds(ep);
1181 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1184 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
1186 struct xhci_td *cur_td;
1187 struct xhci_td *tmp;
1189 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
1190 list_del_init(&cur_td->td_list);
1192 if (!list_empty(&cur_td->cancelled_td_list))
1193 list_del_init(&cur_td->cancelled_td_list);
1195 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
1197 inc_td_cnt(cur_td->urb);
1198 if (last_td_in_urb(cur_td))
1199 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1203 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
1204 int slot_id, int ep_index)
1206 struct xhci_td *cur_td;
1207 struct xhci_td *tmp;
1208 struct xhci_virt_ep *ep;
1209 struct xhci_ring *ring;
1211 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1215 if ((ep->ep_state & EP_HAS_STREAMS) ||
1216 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
1219 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
1221 ring = ep->stream_info->stream_rings[stream_id];
1225 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1226 "Killing URBs for slot ID %u, ep index %u, stream %u",
1227 slot_id, ep_index, stream_id);
1228 xhci_kill_ring_urbs(xhci, ring);
1234 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1235 "Killing URBs for slot ID %u, ep index %u",
1237 xhci_kill_ring_urbs(xhci, ring);
1240 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
1241 cancelled_td_list) {
1242 list_del_init(&cur_td->cancelled_td_list);
1243 inc_td_cnt(cur_td->urb);
1245 if (last_td_in_urb(cur_td))
1246 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1251 * host controller died, register read returns 0xffffffff
1252 * Complete pending commands, mark them ABORTED.
1253 * URBs need to be given back as usb core might be waiting with device locks
1254 * held for the URBs to finish during device disconnect, blocking host remove.
1256 * Call with xhci->lock held.
1257 * lock is relased and re-acquired while giving back urb.
1259 void xhci_hc_died(struct xhci_hcd *xhci)
1263 if (xhci->xhc_state & XHCI_STATE_DYING)
1266 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1267 xhci->xhc_state |= XHCI_STATE_DYING;
1269 xhci_cleanup_command_queue(xhci);
1271 /* return any pending urbs, remove may be waiting for them */
1272 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
1275 for (j = 0; j < 31; j++)
1276 xhci_kill_endpoint_urbs(xhci, i, j);
1279 /* inform usb core hc died if PCI remove isn't already handling it */
1280 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
1281 usb_hc_died(xhci_to_hcd(xhci));
1284 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1285 struct xhci_virt_device *dev,
1286 struct xhci_ring *ep_ring,
1287 unsigned int ep_index)
1289 union xhci_trb *dequeue_temp;
1291 dequeue_temp = ep_ring->dequeue;
1293 /* If we get two back-to-back stalls, and the first stalled transfer
1294 * ends just before a link TRB, the dequeue pointer will be left on
1295 * the link TRB by the code in the while loop. So we have to update
1296 * the dequeue pointer one segment further, or we'll jump off
1297 * the segment into la-la-land.
1299 if (trb_is_link(ep_ring->dequeue)) {
1300 ep_ring->deq_seg = ep_ring->deq_seg->next;
1301 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1304 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1305 /* We have more usable TRBs */
1307 if (trb_is_link(ep_ring->dequeue)) {
1308 if (ep_ring->dequeue ==
1309 dev->eps[ep_index].queued_deq_ptr)
1311 ep_ring->deq_seg = ep_ring->deq_seg->next;
1312 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1314 if (ep_ring->dequeue == dequeue_temp) {
1315 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1322 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1323 * we need to clear the set deq pending flag in the endpoint ring state, so that
1324 * the TD queueing code can ring the doorbell again. We also need to ring the
1325 * endpoint doorbell to restart the ring, but only if there aren't more
1326 * cancellations pending.
1328 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1329 union xhci_trb *trb, u32 cmd_comp_code)
1331 unsigned int ep_index;
1332 unsigned int stream_id;
1333 struct xhci_ring *ep_ring;
1334 struct xhci_virt_ep *ep;
1335 struct xhci_ep_ctx *ep_ctx;
1336 struct xhci_slot_ctx *slot_ctx;
1337 struct xhci_td *td, *tmp_td;
1339 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1340 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1341 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1345 ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
1347 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1349 /* XXX: Harmless??? */
1353 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1354 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
1355 trace_xhci_handle_cmd_set_deq(slot_ctx);
1356 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1358 if (cmd_comp_code != COMP_SUCCESS) {
1359 unsigned int ep_state;
1360 unsigned int slot_state;
1362 switch (cmd_comp_code) {
1363 case COMP_TRB_ERROR:
1364 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1366 case COMP_CONTEXT_STATE_ERROR:
1367 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1368 ep_state = GET_EP_CTX_STATE(ep_ctx);
1369 slot_state = le32_to_cpu(slot_ctx->dev_state);
1370 slot_state = GET_SLOT_STATE(slot_state);
1371 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1372 "Slot state = %u, EP state = %u",
1373 slot_state, ep_state);
1375 case COMP_SLOT_NOT_ENABLED_ERROR:
1376 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1380 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1384 /* OK what do we do now? The endpoint state is hosed, and we
1385 * should never get to this point if the synchronization between
1386 * queueing, and endpoint state are correct. This might happen
1387 * if the device gets disconnected after we've finished
1388 * cancelling URBs, which might not be an error...
1392 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1393 if (ep->ep_state & EP_HAS_STREAMS) {
1394 struct xhci_stream_ctx *ctx =
1395 &ep->stream_info->stream_ctx_array[stream_id];
1396 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1398 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1400 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1401 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1402 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1403 ep->queued_deq_ptr) == deq) {
1404 /* Update the ring's dequeue segment and dequeue pointer
1405 * to reflect the new position.
1407 update_ring_for_set_deq_completion(xhci, ep->vdev,
1410 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1411 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1412 ep->queued_deq_seg, ep->queued_deq_ptr);
1415 /* HW cached TDs cleared from cache, give them back */
1416 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
1417 cancelled_td_list) {
1418 ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
1419 if (td->cancel_status == TD_CLEARING_CACHE) {
1420 td->cancel_status = TD_CLEARED;
1421 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
1423 xhci_td_cleanup(ep->xhci, td, ep_ring, td->status);
1425 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
1426 __func__, td->urb, td->cancel_status);
1430 ep->ep_state &= ~SET_DEQ_PENDING;
1431 ep->queued_deq_seg = NULL;
1432 ep->queued_deq_ptr = NULL;
1433 /* Restart any rings with pending URBs */
1434 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1437 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1438 union xhci_trb *trb, u32 cmd_comp_code)
1440 struct xhci_virt_ep *ep;
1441 struct xhci_ep_ctx *ep_ctx;
1442 unsigned int ep_index;
1444 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1445 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1449 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1450 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1452 /* This command will only fail if the endpoint wasn't halted,
1453 * but we don't care.
1455 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1456 "Ignoring reset ep completion code of %u", cmd_comp_code);
1458 /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1459 xhci_invalidate_cancelled_tds(ep);
1461 /* Clear our internal halted state */
1462 ep->ep_state &= ~EP_HALTED;
1464 xhci_giveback_invalidated_tds(ep);
1466 /* if this was a soft reset, then restart */
1467 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1468 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1471 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1472 struct xhci_command *command, u32 cmd_comp_code)
1474 if (cmd_comp_code == COMP_SUCCESS)
1475 command->slot_id = slot_id;
1477 command->slot_id = 0;
1480 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1482 struct xhci_virt_device *virt_dev;
1483 struct xhci_slot_ctx *slot_ctx;
1485 virt_dev = xhci->devs[slot_id];
1489 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1490 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1492 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1493 /* Delete default control endpoint resources */
1494 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1497 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1500 struct xhci_virt_device *virt_dev;
1501 struct xhci_input_control_ctx *ctrl_ctx;
1502 struct xhci_ep_ctx *ep_ctx;
1503 unsigned int ep_index;
1507 * Configure endpoint commands can come from the USB core configuration
1508 * or alt setting changes, or when streams were being configured.
1511 virt_dev = xhci->devs[slot_id];
1514 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1516 xhci_warn(xhci, "Could not get input context, bad type.\n");
1520 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1522 /* Input ctx add_flags are the endpoint index plus one */
1523 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1525 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1526 trace_xhci_handle_cmd_config_ep(ep_ctx);
1531 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1533 struct xhci_virt_device *vdev;
1534 struct xhci_slot_ctx *slot_ctx;
1536 vdev = xhci->devs[slot_id];
1539 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1540 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1543 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
1545 struct xhci_virt_device *vdev;
1546 struct xhci_slot_ctx *slot_ctx;
1548 vdev = xhci->devs[slot_id];
1550 xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
1554 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1555 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1557 xhci_dbg(xhci, "Completed reset device command.\n");
1560 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1561 struct xhci_event_cmd *event)
1563 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1564 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1567 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1568 "NEC firmware version %2x.%02x",
1569 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1570 NEC_FW_MINOR(le32_to_cpu(event->status)));
1573 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1575 list_del(&cmd->cmd_list);
1577 if (cmd->completion) {
1578 cmd->status = status;
1579 complete(cmd->completion);
1585 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1587 struct xhci_command *cur_cmd, *tmp_cmd;
1588 xhci->current_cmd = NULL;
1589 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1590 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1593 void xhci_handle_command_timeout(struct work_struct *work)
1595 struct xhci_hcd *xhci;
1596 unsigned long flags;
1597 char str[XHCI_MSG_MAX];
1602 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1604 spin_lock_irqsave(&xhci->lock, flags);
1607 * If timeout work is pending, or current_cmd is NULL, it means we
1608 * raced with command completion. Command is handled so just return.
1610 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1611 spin_unlock_irqrestore(&xhci->lock, flags);
1615 cmd_field3 = le32_to_cpu(xhci->current_cmd->command_trb->generic.field[3]);
1616 usbsts = readl(&xhci->op_regs->status);
1617 xhci_dbg(xhci, "Command timeout, USBSTS:%s\n", xhci_decode_usbsts(str, usbsts));
1619 /* Bail out and tear down xhci if a stop endpoint command failed */
1620 if (TRB_FIELD_TO_TYPE(cmd_field3) == TRB_STOP_RING) {
1621 struct xhci_virt_ep *ep;
1623 xhci_warn(xhci, "xHCI host not responding to stop endpoint command\n");
1625 ep = xhci_get_virt_ep(xhci, TRB_TO_SLOT_ID(cmd_field3),
1626 TRB_TO_EP_INDEX(cmd_field3));
1628 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1632 goto time_out_completed;
1635 /* mark this command to be cancelled */
1636 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1638 /* Make sure command ring is running before aborting it */
1639 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1640 if (hw_ring_state == ~(u64)0) {
1642 goto time_out_completed;
1645 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1646 (hw_ring_state & CMD_RING_RUNNING)) {
1647 /* Prevent new doorbell, and start command abort */
1648 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1649 xhci_dbg(xhci, "Command timeout\n");
1650 xhci_abort_cmd_ring(xhci, flags);
1651 goto time_out_completed;
1654 /* host removed. Bail out */
1655 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1656 xhci_dbg(xhci, "host removed, ring start fail?\n");
1657 xhci_cleanup_command_queue(xhci);
1659 goto time_out_completed;
1662 /* command timeout on stopped ring, ring can't be aborted */
1663 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1664 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1667 spin_unlock_irqrestore(&xhci->lock, flags);
1671 static void handle_cmd_completion(struct xhci_hcd *xhci,
1672 struct xhci_event_cmd *event)
1674 unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1676 dma_addr_t cmd_dequeue_dma;
1678 union xhci_trb *cmd_trb;
1679 struct xhci_command *cmd;
1682 if (slot_id >= MAX_HC_SLOTS) {
1683 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
1687 cmd_dma = le64_to_cpu(event->cmd_trb);
1688 cmd_trb = xhci->cmd_ring->dequeue;
1690 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1692 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1695 * Check whether the completion event is for our internal kept
1698 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1700 "ERROR mismatched command completion event\n");
1704 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1706 cancel_delayed_work(&xhci->cmd_timer);
1708 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1710 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1711 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1712 complete_all(&xhci->cmd_ring_stop_completion);
1716 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1718 "Command completion event does not match command\n");
1723 * Host aborted the command ring, check if the current command was
1724 * supposed to be aborted, otherwise continue normally.
1725 * The command ring is stopped now, but the xHC will issue a Command
1726 * Ring Stopped event which will cause us to restart it.
1728 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1729 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1730 if (cmd->status == COMP_COMMAND_ABORTED) {
1731 if (xhci->current_cmd == cmd)
1732 xhci->current_cmd = NULL;
1737 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1739 case TRB_ENABLE_SLOT:
1740 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1742 case TRB_DISABLE_SLOT:
1743 xhci_handle_cmd_disable_slot(xhci, slot_id);
1746 if (!cmd->completion)
1747 xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code);
1749 case TRB_EVAL_CONTEXT:
1752 xhci_handle_cmd_addr_dev(xhci, slot_id);
1755 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1756 le32_to_cpu(cmd_trb->generic.field[3])));
1757 if (!cmd->completion)
1758 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb,
1762 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1763 le32_to_cpu(cmd_trb->generic.field[3])));
1764 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1767 /* Is this an aborted command turned to NO-OP? */
1768 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1769 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1772 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1773 le32_to_cpu(cmd_trb->generic.field[3])));
1774 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1777 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1778 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1780 slot_id = TRB_TO_SLOT_ID(
1781 le32_to_cpu(cmd_trb->generic.field[3]));
1782 xhci_handle_cmd_reset_dev(xhci, slot_id);
1784 case TRB_NEC_GET_FW:
1785 xhci_handle_cmd_nec_get_fw(xhci, event);
1788 /* Skip over unknown commands on the event ring */
1789 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1793 /* restart timer if this wasn't the last command */
1794 if (!list_is_singular(&xhci->cmd_list)) {
1795 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1796 struct xhci_command, cmd_list);
1797 xhci_mod_cmd_timer(xhci);
1798 } else if (xhci->current_cmd == cmd) {
1799 xhci->current_cmd = NULL;
1803 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1805 inc_deq(xhci, xhci->cmd_ring);
1808 static void handle_vendor_event(struct xhci_hcd *xhci,
1809 union xhci_trb *event, u32 trb_type)
1811 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1812 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1813 handle_cmd_completion(xhci, &event->event_cmd);
1816 static void handle_device_notification(struct xhci_hcd *xhci,
1817 union xhci_trb *event)
1820 struct usb_device *udev;
1822 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1823 if (!xhci->devs[slot_id]) {
1824 xhci_warn(xhci, "Device Notification event for "
1825 "unused slot %u\n", slot_id);
1829 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1831 udev = xhci->devs[slot_id]->udev;
1832 if (udev && udev->parent)
1833 usb_wakeup_notification(udev->parent, udev->portnum);
1837 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1839 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1840 * If a connection to a USB 1 device is followed by another connection
1841 * to a USB 2 device.
1843 * Reset the PHY after the USB device is disconnected if device speed
1844 * is less than HCD_USB3.
1845 * Retry the reset sequence max of 4 times checking the PLL lock status.
1848 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1850 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1852 u32 retry_count = 4;
1855 /* Assert PHY reset */
1856 writel(0x6F, hcd->regs + 0x1048);
1858 /* De-assert the PHY reset */
1859 writel(0x7F, hcd->regs + 0x1048);
1861 pll_lock_check = readl(hcd->regs + 0x1070);
1862 } while (!(pll_lock_check & 0x1) && --retry_count);
1865 static void handle_port_status(struct xhci_hcd *xhci,
1866 struct xhci_interrupter *ir,
1867 union xhci_trb *event)
1869 struct usb_hcd *hcd;
1871 u32 portsc, cmd_reg;
1874 unsigned int hcd_portnum;
1875 struct xhci_bus_state *bus_state;
1876 bool bogus_port_status = false;
1877 struct xhci_port *port;
1879 /* Port status change events always have a successful completion code */
1880 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1882 "WARN: xHC returned failed port status event\n");
1884 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1885 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1887 if ((port_id <= 0) || (port_id > max_ports)) {
1888 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1893 port = &xhci->hw_ports[port_id - 1];
1894 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1895 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1897 bogus_port_status = true;
1901 /* We might get interrupts after shared_hcd is removed */
1902 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1903 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1904 bogus_port_status = true;
1908 hcd = port->rhub->hcd;
1909 bus_state = &port->rhub->bus_state;
1910 hcd_portnum = port->hcd_portnum;
1911 portsc = readl(port->addr);
1913 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1914 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1916 trace_xhci_handle_port_status(port, portsc);
1918 if (hcd->state == HC_STATE_SUSPENDED) {
1919 xhci_dbg(xhci, "resume root hub\n");
1920 usb_hcd_resume_root_hub(hcd);
1923 if (hcd->speed >= HCD_USB3 &&
1924 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1925 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1926 if (slot_id && xhci->devs[slot_id])
1927 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1930 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1931 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1933 cmd_reg = readl(&xhci->op_regs->command);
1934 if (!(cmd_reg & CMD_RUN)) {
1935 xhci_warn(xhci, "xHC is not running.\n");
1939 if (DEV_SUPERSPEED_ANY(portsc)) {
1940 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1941 /* Set a flag to say the port signaled remote wakeup,
1942 * so we can tell the difference between the end of
1943 * device and host initiated resume.
1945 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1946 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1947 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1948 xhci_set_link_state(xhci, port, XDEV_U0);
1949 /* Need to wait until the next link state change
1950 * indicates the device is actually in U0.
1952 bogus_port_status = true;
1954 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1955 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1956 port->resume_timestamp = jiffies +
1957 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1958 set_bit(hcd_portnum, &bus_state->resuming_ports);
1959 /* Do the rest in GetPortStatus after resume time delay.
1960 * Avoid polling roothub status before that so that a
1961 * usb device auto-resume latency around ~40ms.
1963 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1964 mod_timer(&hcd->rh_timer,
1965 port->resume_timestamp);
1966 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1967 bogus_port_status = true;
1971 if ((portsc & PORT_PLC) &&
1972 DEV_SUPERSPEED_ANY(portsc) &&
1973 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1974 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1975 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1976 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1977 complete(&port->u3exit_done);
1978 /* We've just brought the device into U0/1/2 through either the
1979 * Resume state after a device remote wakeup, or through the
1980 * U3Exit state after a host-initiated resume. If it's a device
1981 * initiated remote wake, don't pass up the link state change,
1982 * so the roothub behavior is consistent with external
1983 * USB 3.0 hub behavior.
1985 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1986 if (slot_id && xhci->devs[slot_id])
1987 xhci_ring_device(xhci, slot_id);
1988 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1989 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1990 usb_wakeup_notification(hcd->self.root_hub,
1992 bogus_port_status = true;
1998 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1999 * RExit to a disconnect state). If so, let the driver know it's
2000 * out of the RExit state.
2002 if (hcd->speed < HCD_USB3 && port->rexit_active) {
2003 complete(&port->rexit_done);
2004 port->rexit_active = false;
2005 bogus_port_status = true;
2009 if (hcd->speed < HCD_USB3) {
2010 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2011 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
2012 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
2013 xhci_cavium_reset_phy_quirk(xhci);
2018 /* Don't make the USB core poll the roothub if we got a bad port status
2019 * change event. Besides, at that point we can't tell which roothub
2020 * (USB 2.0 or USB 3.0) to kick.
2022 if (bogus_port_status)
2026 * xHCI port-status-change events occur when the "or" of all the
2027 * status-change bits in the portsc register changes from 0 to 1.
2028 * New status changes won't cause an event if any other change
2029 * bits are still set. When an event occurs, switch over to
2030 * polling to avoid losing status changes.
2032 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
2033 __func__, hcd->self.busnum);
2034 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2035 spin_unlock(&xhci->lock);
2036 /* Pass this up to the core */
2037 usb_hcd_poll_rh_status(hcd);
2038 spin_lock(&xhci->lock);
2042 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
2043 * at end_trb, which may be in another segment. If the suspect DMA address is a
2044 * TRB in this TD, this function returns that TRB's segment. Otherwise it
2047 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2048 struct xhci_segment *start_seg,
2049 union xhci_trb *start_trb,
2050 union xhci_trb *end_trb,
2051 dma_addr_t suspect_dma,
2054 dma_addr_t start_dma;
2055 dma_addr_t end_seg_dma;
2056 dma_addr_t end_trb_dma;
2057 struct xhci_segment *cur_seg;
2059 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
2060 cur_seg = start_seg;
2065 /* We may get an event for a Link TRB in the middle of a TD */
2066 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
2067 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
2068 /* If the end TRB isn't in this segment, this is set to 0 */
2069 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
2073 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
2074 (unsigned long long)suspect_dma,
2075 (unsigned long long)start_dma,
2076 (unsigned long long)end_trb_dma,
2077 (unsigned long long)cur_seg->dma,
2078 (unsigned long long)end_seg_dma);
2080 if (end_trb_dma > 0) {
2081 /* The end TRB is in this segment, so suspect should be here */
2082 if (start_dma <= end_trb_dma) {
2083 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
2086 /* Case for one segment with
2087 * a TD wrapped around to the top
2089 if ((suspect_dma >= start_dma &&
2090 suspect_dma <= end_seg_dma) ||
2091 (suspect_dma >= cur_seg->dma &&
2092 suspect_dma <= end_trb_dma))
2097 /* Might still be somewhere in this segment */
2098 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
2101 cur_seg = cur_seg->next;
2102 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
2103 } while (cur_seg != start_seg);
2108 static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
2109 struct xhci_virt_ep *ep)
2112 * As part of low/full-speed endpoint-halt processing
2113 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2115 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
2116 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
2117 !(ep->ep_state & EP_CLEARING_TT)) {
2118 ep->ep_state |= EP_CLEARING_TT;
2119 td->urb->ep->hcpriv = td->urb->dev;
2120 if (usb_hub_clear_tt_buffer(td->urb))
2121 ep->ep_state &= ~EP_CLEARING_TT;
2125 /* Check if an error has halted the endpoint ring. The class driver will
2126 * cleanup the halt for a non-default control endpoint if we indicate a stall.
2127 * However, a babble and other errors also halt the endpoint ring, and the class
2128 * driver won't clear the halt in that case, so we need to issue a Set Transfer
2129 * Ring Dequeue Pointer command manually.
2131 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
2132 struct xhci_ep_ctx *ep_ctx,
2133 unsigned int trb_comp_code)
2135 /* TRB completion codes that may require a manual halt cleanup */
2136 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
2137 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
2138 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
2139 /* The 0.95 spec says a babbling control endpoint
2140 * is not halted. The 0.96 spec says it is. Some HW
2141 * claims to be 0.95 compliant, but it halts the control
2142 * endpoint anyway. Check if a babble halted the
2145 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
2151 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
2153 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
2154 /* Vendor defined "informational" completion code,
2155 * treat as not-an-error.
2157 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
2159 xhci_dbg(xhci, "Treating code as success.\n");
2165 static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2166 struct xhci_ring *ep_ring, struct xhci_td *td,
2169 struct xhci_ep_ctx *ep_ctx;
2171 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2173 switch (trb_comp_code) {
2174 case COMP_STOPPED_LENGTH_INVALID:
2175 case COMP_STOPPED_SHORT_PACKET:
2178 * The "Stop Endpoint" completion will take care of any
2179 * stopped TDs. A stopped TD may be restarted, so don't update
2180 * the ring dequeue pointer or take this TD off any lists yet.
2183 case COMP_USB_TRANSACTION_ERROR:
2184 case COMP_BABBLE_DETECTED_ERROR:
2185 case COMP_SPLIT_TRANSACTION_ERROR:
2187 * If endpoint context state is not halted we might be
2188 * racing with a reset endpoint command issued by a unsuccessful
2189 * stop endpoint completion (context error). In that case the
2190 * td should be on the cancelled list, and EP_HALTED flag set.
2192 * Or then it's not halted due to the 0.95 spec stating that a
2193 * babbling control endpoint should not halt. The 0.96 spec
2194 * again says it should. Some HW claims to be 0.95 compliant,
2195 * but it halts the control endpoint anyway.
2197 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) {
2199 * If EP_HALTED is set and TD is on the cancelled list
2200 * the TD and dequeue pointer will be handled by reset
2201 * ep command completion
2203 if ((ep->ep_state & EP_HALTED) &&
2204 !list_empty(&td->cancelled_td_list)) {
2205 xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n",
2206 (unsigned long long)xhci_trb_virt_to_dma(
2207 td->start_seg, td->first_trb));
2210 /* endpoint not halted, don't reset it */
2213 /* Almost same procedure as for STALL_ERROR below */
2214 xhci_clear_hub_tt_buffer(xhci, td, ep);
2215 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2217 case COMP_STALL_ERROR:
2219 * xhci internal endpoint state will go to a "halt" state for
2220 * any stall, including default control pipe protocol stall.
2221 * To clear the host side halt we need to issue a reset endpoint
2222 * command, followed by a set dequeue command to move past the
2224 * Class drivers clear the device side halt from a functional
2225 * stall later. Hub TT buffer should only be cleared for FS/LS
2226 * devices behind HS hubs for functional stalls.
2228 if (ep->ep_index != 0)
2229 xhci_clear_hub_tt_buffer(xhci, td, ep);
2231 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2233 return 0; /* xhci_handle_halted_endpoint marked td cancelled */
2238 /* Update ring dequeue pointer */
2239 ep_ring->dequeue = td->last_trb;
2240 ep_ring->deq_seg = td->last_trb_seg;
2241 inc_deq(xhci, ep_ring);
2243 return xhci_td_cleanup(xhci, td, ep_ring, td->status);
2246 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2247 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2248 union xhci_trb *stop_trb)
2251 union xhci_trb *trb = ring->dequeue;
2252 struct xhci_segment *seg = ring->deq_seg;
2254 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2255 if (!trb_is_noop(trb) && !trb_is_link(trb))
2256 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2262 * Process control tds, update urb status and actual_length.
2264 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2265 struct xhci_ring *ep_ring, struct xhci_td *td,
2266 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2268 struct xhci_ep_ctx *ep_ctx;
2270 u32 remaining, requested;
2273 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2274 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2275 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2276 requested = td->urb->transfer_buffer_length;
2277 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2279 switch (trb_comp_code) {
2281 if (trb_type != TRB_STATUS) {
2282 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2283 (trb_type == TRB_DATA) ? "data" : "setup");
2284 td->status = -ESHUTDOWN;
2289 case COMP_SHORT_PACKET:
2292 case COMP_STOPPED_SHORT_PACKET:
2293 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2294 td->urb->actual_length = remaining;
2296 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2301 td->urb->actual_length = 0;
2305 td->urb->actual_length = requested - remaining;
2308 td->urb->actual_length = requested;
2311 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2315 case COMP_STOPPED_LENGTH_INVALID:
2318 if (!xhci_requires_manual_halt_cleanup(xhci,
2319 ep_ctx, trb_comp_code))
2321 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2322 trb_comp_code, ep->ep_index);
2324 case COMP_STALL_ERROR:
2325 /* Did we transfer part of the data (middle) phase? */
2326 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2327 td->urb->actual_length = requested - remaining;
2328 else if (!td->urb_length_set)
2329 td->urb->actual_length = 0;
2333 /* stopped at setup stage, no data transferred */
2334 if (trb_type == TRB_SETUP)
2338 * if on data stage then update the actual_length of the URB and flag it
2339 * as set, so it won't be overwritten in the event for the last TRB.
2341 if (trb_type == TRB_DATA ||
2342 trb_type == TRB_NORMAL) {
2343 td->urb_length_set = true;
2344 td->urb->actual_length = requested - remaining;
2345 xhci_dbg(xhci, "Waiting for status stage event\n");
2349 /* at status stage */
2350 if (!td->urb_length_set)
2351 td->urb->actual_length = requested;
2354 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2358 * Process isochronous tds, update urb packet status and actual_length.
2360 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2361 struct xhci_ring *ep_ring, struct xhci_td *td,
2362 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2364 struct urb_priv *urb_priv;
2366 struct usb_iso_packet_descriptor *frame;
2368 bool sum_trbs_for_length = false;
2369 u32 remaining, requested, ep_trb_len;
2370 int short_framestatus;
2372 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2373 urb_priv = td->urb->hcpriv;
2374 idx = urb_priv->num_tds_done;
2375 frame = &td->urb->iso_frame_desc[idx];
2376 requested = frame->length;
2377 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2378 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2379 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2382 /* handle completion code */
2383 switch (trb_comp_code) {
2385 /* Don't overwrite status if TD had an error, see xHCI 4.9.1 */
2386 if (td->error_mid_td)
2389 frame->status = short_framestatus;
2390 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2391 sum_trbs_for_length = true;
2396 case COMP_SHORT_PACKET:
2397 frame->status = short_framestatus;
2398 sum_trbs_for_length = true;
2400 case COMP_BANDWIDTH_OVERRUN_ERROR:
2401 frame->status = -ECOMM;
2403 case COMP_BABBLE_DETECTED_ERROR:
2404 sum_trbs_for_length = true;
2406 case COMP_ISOCH_BUFFER_OVERRUN:
2407 frame->status = -EOVERFLOW;
2408 if (ep_trb != td->last_trb)
2409 td->error_mid_td = true;
2411 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2412 case COMP_STALL_ERROR:
2413 frame->status = -EPROTO;
2415 case COMP_USB_TRANSACTION_ERROR:
2416 frame->status = -EPROTO;
2417 sum_trbs_for_length = true;
2418 if (ep_trb != td->last_trb)
2419 td->error_mid_td = true;
2422 sum_trbs_for_length = true;
2424 case COMP_STOPPED_SHORT_PACKET:
2425 /* field normally containing residue now contains tranferred */
2426 frame->status = short_framestatus;
2427 requested = remaining;
2429 case COMP_STOPPED_LENGTH_INVALID:
2434 sum_trbs_for_length = true;
2439 if (td->urb_length_set)
2442 if (sum_trbs_for_length)
2443 frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) +
2444 ep_trb_len - remaining;
2446 frame->actual_length = requested;
2448 td->urb->actual_length += frame->actual_length;
2451 /* Don't give back TD yet if we encountered an error mid TD */
2452 if (td->error_mid_td && ep_trb != td->last_trb) {
2453 xhci_dbg(xhci, "Error mid isoc TD, wait for final completion event\n");
2454 td->urb_length_set = true;
2458 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2461 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2462 struct xhci_virt_ep *ep, int status)
2464 struct urb_priv *urb_priv;
2465 struct usb_iso_packet_descriptor *frame;
2468 urb_priv = td->urb->hcpriv;
2469 idx = urb_priv->num_tds_done;
2470 frame = &td->urb->iso_frame_desc[idx];
2472 /* The transfer is partly done. */
2473 frame->status = -EXDEV;
2475 /* calc actual length */
2476 frame->actual_length = 0;
2478 /* Update ring dequeue pointer */
2479 ep->ring->dequeue = td->last_trb;
2480 ep->ring->deq_seg = td->last_trb_seg;
2481 inc_deq(xhci, ep->ring);
2483 return xhci_td_cleanup(xhci, td, ep->ring, status);
2487 * Process bulk and interrupt tds, update urb status and actual_length.
2489 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2490 struct xhci_ring *ep_ring, struct xhci_td *td,
2491 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2493 struct xhci_slot_ctx *slot_ctx;
2495 u32 remaining, requested, ep_trb_len;
2497 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
2498 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2499 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2500 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2501 requested = td->urb->transfer_buffer_length;
2503 switch (trb_comp_code) {
2506 /* handle success with untransferred data as short packet */
2507 if (ep_trb != td->last_trb || remaining) {
2508 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2509 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2510 td->urb->ep->desc.bEndpointAddress,
2511 requested, remaining);
2515 case COMP_SHORT_PACKET:
2516 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2517 td->urb->ep->desc.bEndpointAddress,
2518 requested, remaining);
2521 case COMP_STOPPED_SHORT_PACKET:
2522 td->urb->actual_length = remaining;
2524 case COMP_STOPPED_LENGTH_INVALID:
2525 /* stopped on ep trb with invalid length, exclude it */
2529 case COMP_USB_TRANSACTION_ERROR:
2530 if (xhci->quirks & XHCI_NO_SOFT_RETRY ||
2531 (ep->err_count++ > MAX_SOFT_RETRY) ||
2532 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2537 xhci_handle_halted_endpoint(xhci, ep, td, EP_SOFT_RESET);
2544 if (ep_trb == td->last_trb)
2545 td->urb->actual_length = requested - remaining;
2547 td->urb->actual_length =
2548 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2549 ep_trb_len - remaining;
2551 if (remaining > requested) {
2552 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2554 td->urb->actual_length = 0;
2557 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2561 * If this function returns an error condition, it means it got a Transfer
2562 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2563 * At this point, the host controller is probably hosed and should be reset.
2565 static int handle_tx_event(struct xhci_hcd *xhci,
2566 struct xhci_interrupter *ir,
2567 struct xhci_transfer_event *event)
2569 struct xhci_virt_ep *ep;
2570 struct xhci_ring *ep_ring;
2571 unsigned int slot_id;
2573 struct xhci_td *td = NULL;
2574 dma_addr_t ep_trb_dma;
2575 struct xhci_segment *ep_seg;
2576 union xhci_trb *ep_trb;
2577 int status = -EINPROGRESS;
2578 struct xhci_ep_ctx *ep_ctx;
2581 bool handling_skipped_tds = false;
2583 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2584 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2585 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2586 ep_trb_dma = le64_to_cpu(event->buffer);
2588 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2590 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2594 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2595 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
2597 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2599 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2604 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2606 switch (trb_comp_code) {
2607 case COMP_STALL_ERROR:
2608 case COMP_USB_TRANSACTION_ERROR:
2609 case COMP_INVALID_STREAM_TYPE_ERROR:
2610 case COMP_INVALID_STREAM_ID_ERROR:
2611 xhci_dbg(xhci, "Stream transaction error ep %u no id\n",
2613 if (ep->err_count++ > MAX_SOFT_RETRY)
2614 xhci_handle_halted_endpoint(xhci, ep, NULL,
2617 xhci_handle_halted_endpoint(xhci, ep, NULL,
2620 case COMP_RING_UNDERRUN:
2621 case COMP_RING_OVERRUN:
2622 case COMP_STOPPED_LENGTH_INVALID:
2625 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2631 /* Count current td numbers if ep->skip is set */
2633 td_num += list_count_nodes(&ep_ring->td_list);
2635 /* Look for common error cases */
2636 switch (trb_comp_code) {
2637 /* Skip codes that require special handling depending on
2641 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2643 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2644 ep_ring->last_td_was_short)
2645 trb_comp_code = COMP_SHORT_PACKET;
2647 xhci_warn_ratelimited(xhci,
2648 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2651 case COMP_SHORT_PACKET:
2653 /* Completion codes for endpoint stopped state */
2655 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2658 case COMP_STOPPED_LENGTH_INVALID:
2660 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2663 case COMP_STOPPED_SHORT_PACKET:
2665 "Stopped with short packet transfer detected for slot %u ep %u\n",
2668 /* Completion codes for endpoint halted state */
2669 case COMP_STALL_ERROR:
2670 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2674 case COMP_SPLIT_TRANSACTION_ERROR:
2675 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2679 case COMP_USB_TRANSACTION_ERROR:
2680 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2684 case COMP_BABBLE_DETECTED_ERROR:
2685 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2687 status = -EOVERFLOW;
2689 /* Completion codes for endpoint error state */
2690 case COMP_TRB_ERROR:
2692 "WARN: TRB error for slot %u ep %u on endpoint\n",
2696 /* completion codes not indicating endpoint state change */
2697 case COMP_DATA_BUFFER_ERROR:
2699 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2703 case COMP_BANDWIDTH_OVERRUN_ERROR:
2705 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2708 case COMP_ISOCH_BUFFER_OVERRUN:
2710 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2713 case COMP_RING_UNDERRUN:
2715 * When the Isoch ring is empty, the xHC will generate
2716 * a Ring Overrun Event for IN Isoch endpoint or Ring
2717 * Underrun Event for OUT Isoch endpoint.
2719 xhci_dbg(xhci, "underrun event on endpoint\n");
2720 if (!list_empty(&ep_ring->td_list))
2721 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2722 "still with TDs queued?\n",
2723 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2726 case COMP_RING_OVERRUN:
2727 xhci_dbg(xhci, "overrun event on endpoint\n");
2728 if (!list_empty(&ep_ring->td_list))
2729 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2730 "still with TDs queued?\n",
2731 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2734 case COMP_MISSED_SERVICE_ERROR:
2736 * When encounter missed service error, one or more isoc tds
2737 * may be missed by xHC.
2738 * Set skip flag of the ep_ring; Complete the missed tds as
2739 * short transfer when process the ep_ring next time.
2743 "Miss service interval error for slot %u ep %u, set skip flag\n",
2746 case COMP_NO_PING_RESPONSE_ERROR:
2749 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2753 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2754 /* needs disable slot command to recover */
2756 "WARN: detect an incompatible device for slot %u ep %u",
2761 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2766 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2767 trb_comp_code, slot_id, ep_index);
2772 /* This TRB should be in the TD at the head of this ring's
2775 if (list_empty(&ep_ring->td_list)) {
2777 * Don't print wanings if it's due to a stopped endpoint
2778 * generating an extra completion event if the device
2779 * was suspended. Or, a event for the last TRB of a
2780 * short TD we already got a short event for.
2781 * The short TD is already removed from the TD list.
2784 if (!(trb_comp_code == COMP_STOPPED ||
2785 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2786 ep_ring->last_td_was_short)) {
2787 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2788 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2793 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2796 if (trb_comp_code == COMP_STALL_ERROR ||
2797 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2799 xhci_handle_halted_endpoint(xhci, ep, NULL,
2805 /* We've skipped all the TDs on the ep ring when ep->skip set */
2806 if (ep->skip && td_num == 0) {
2808 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2813 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2818 /* Is this a TRB in the currently executing TD? */
2819 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2820 td->last_trb, ep_trb_dma, false);
2823 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2824 * is not in the current TD pointed by ep_ring->dequeue because
2825 * that the hardware dequeue pointer still at the previous TRB
2826 * of the current TD. The previous TRB maybe a Link TD or the
2827 * last TRB of the previous TD. The command completion handle
2828 * will take care the rest.
2830 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2831 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2837 if (ep->skip && usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2838 skip_isoc_td(xhci, td, ep, status);
2843 * Some hosts give a spurious success event after a short
2844 * transfer. Ignore it.
2846 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2847 ep_ring->last_td_was_short) {
2848 ep_ring->last_td_was_short = false;
2853 * xhci 4.10.2 states isoc endpoints should continue
2854 * processing the next TD if there was an error mid TD.
2855 * So host like NEC don't generate an event for the last
2856 * isoc TRB even if the IOC flag is set.
2857 * xhci 4.9.1 states that if there are errors in mult-TRB
2858 * TDs xHC should generate an error for that TRB, and if xHC
2859 * proceeds to the next TD it should genete an event for
2860 * any TRB with IOC flag on the way. Other host follow this.
2861 * So this event might be for the next TD.
2863 if (td->error_mid_td &&
2864 !list_is_last(&td->td_list, &ep_ring->td_list)) {
2865 struct xhci_td *td_next = list_next_entry(td, td_list);
2867 ep_seg = trb_in_td(xhci, td_next->start_seg, td_next->first_trb,
2868 td_next->last_trb, ep_trb_dma, false);
2870 /* give back previous TD, start handling new */
2871 xhci_dbg(xhci, "Missing TD completion event after mid TD error\n");
2872 ep_ring->dequeue = td->last_trb;
2873 ep_ring->deq_seg = td->last_trb_seg;
2874 inc_deq(xhci, ep_ring);
2875 xhci_td_cleanup(xhci, td, ep_ring, td->status);
2881 /* HC is busted, give up! */
2883 "ERROR Transfer event TRB DMA ptr not "
2884 "part of current TD ep_index %d "
2885 "comp_code %u\n", ep_index,
2887 trb_in_td(xhci, ep_ring->deq_seg,
2888 ep_ring->dequeue, td->last_trb,
2893 if (trb_comp_code == COMP_SHORT_PACKET)
2894 ep_ring->last_td_was_short = true;
2896 ep_ring->last_td_was_short = false;
2900 "Found td. Clear skip flag for slot %u ep %u.\n",
2905 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2908 trace_xhci_handle_transfer(ep_ring,
2909 (struct xhci_generic_trb *) ep_trb);
2912 * No-op TRB could trigger interrupts in a case where
2913 * a URB was killed and a STALL_ERROR happens right
2914 * after the endpoint ring stopped. Reset the halted
2915 * endpoint. Otherwise, the endpoint remains stalled
2919 if (trb_is_noop(ep_trb)) {
2920 if (trb_comp_code == COMP_STALL_ERROR ||
2921 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2923 xhci_handle_halted_endpoint(xhci, ep, td,
2928 td->status = status;
2930 /* update the urb's actual_length and give back to the core */
2931 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2932 process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event);
2933 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2934 process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event);
2936 process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event);
2938 handling_skipped_tds = ep->skip &&
2939 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2940 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2943 * If ep->skip is set, it means there are missed tds on the
2944 * endpoint ring need to take care of.
2945 * Process them as short transfer until reach the td pointed by
2948 } while (handling_skipped_tds);
2953 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2954 (unsigned long long) xhci_trb_virt_to_dma(
2955 ir->event_ring->deq_seg,
2956 ir->event_ring->dequeue),
2957 lower_32_bits(le64_to_cpu(event->buffer)),
2958 upper_32_bits(le64_to_cpu(event->buffer)),
2959 le32_to_cpu(event->transfer_len),
2960 le32_to_cpu(event->flags));
2965 * This function handles all OS-owned events on the event ring. It may drop
2966 * xhci->lock between event processing (e.g. to pass up port status changes).
2967 * Returns >0 for "possibly more events to process" (caller should call again),
2968 * otherwise 0 if done. In future, <0 returns should indicate error code.
2970 static int xhci_handle_event(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
2972 union xhci_trb *event;
2975 /* Event ring hasn't been allocated yet. */
2976 if (!ir || !ir->event_ring || !ir->event_ring->dequeue) {
2977 xhci_err(xhci, "ERROR interrupter not ready\n");
2981 event = ir->event_ring->dequeue;
2982 /* Does the HC or OS own the TRB? */
2983 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2984 ir->event_ring->cycle_state)
2987 trace_xhci_handle_event(ir->event_ring, &event->generic);
2990 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2991 * speculative reads of the event's flags/data below.
2994 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
2995 /* FIXME: Handle more event types. */
2998 case TRB_COMPLETION:
2999 handle_cmd_completion(xhci, &event->event_cmd);
3001 case TRB_PORT_STATUS:
3002 handle_port_status(xhci, ir, event);
3005 handle_tx_event(xhci, ir, &event->trans_event);
3008 handle_device_notification(xhci, event);
3011 if (trb_type >= TRB_VENDOR_DEFINED_LOW)
3012 handle_vendor_event(xhci, event, trb_type);
3014 xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
3016 /* Any of the above functions may drop and re-acquire the lock, so check
3017 * to make sure a watchdog timer didn't mark the host as non-responsive.
3019 if (xhci->xhc_state & XHCI_STATE_DYING) {
3020 xhci_dbg(xhci, "xHCI host dying, returning from "
3021 "event handler.\n");
3025 /* Are there more items on the event ring? Caller will call us again to
3032 * Update Event Ring Dequeue Pointer:
3033 * - When all events have finished
3034 * - To avoid "Event Ring Full Error" condition
3036 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
3037 struct xhci_interrupter *ir,
3043 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
3044 deq = xhci_trb_virt_to_dma(ir->event_ring->deq_seg,
3045 ir->event_ring->dequeue);
3047 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
3049 * Per 4.9.4, Software writes to the ERDP register shall always advance
3050 * the Event Ring Dequeue Pointer value.
3052 if ((temp_64 & ERST_PTR_MASK) == (deq & ERST_PTR_MASK) && !clear_ehb)
3055 /* Update HC event ring dequeue pointer */
3056 temp_64 = ir->event_ring->deq_seg->num & ERST_DESI_MASK;
3057 temp_64 |= deq & ERST_PTR_MASK;
3059 /* Clear the event handler busy flag (RW1C) */
3061 temp_64 |= ERST_EHB;
3062 xhci_write_64(xhci, temp_64, &ir->ir_set->erst_dequeue);
3065 /* Clear the interrupt pending bit for a specific interrupter. */
3066 static void xhci_clear_interrupt_pending(struct xhci_hcd *xhci,
3067 struct xhci_interrupter *ir)
3069 if (!ir->ip_autoclear) {
3072 irq_pending = readl(&ir->ir_set->irq_pending);
3073 irq_pending |= IMAN_IP;
3074 writel(irq_pending, &ir->ir_set->irq_pending);
3079 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3080 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
3081 * indicators of an event TRB error, but we check the status *first* to be safe.
3083 irqreturn_t xhci_irq(struct usb_hcd *hcd)
3085 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3086 struct xhci_interrupter *ir;
3087 irqreturn_t ret = IRQ_NONE;
3092 spin_lock(&xhci->lock);
3093 /* Check if the xHC generated the interrupt, or the irq is shared */
3094 status = readl(&xhci->op_regs->status);
3095 if (status == ~(u32)0) {
3101 if (!(status & STS_EINT))
3104 if (status & STS_HCE) {
3105 xhci_warn(xhci, "WARNING: Host Controller Error\n");
3109 if (status & STS_FATAL) {
3110 xhci_warn(xhci, "WARNING: Host System Error\n");
3117 * Clear the op reg interrupt status first,
3118 * so we can receive interrupts from other MSI-X interrupters.
3119 * Write 1 to clear the interrupt status.
3122 writel(status, &xhci->op_regs->status);
3124 /* This is the handler of the primary interrupter */
3125 ir = xhci->interrupters[0];
3127 xhci_clear_interrupt_pending(xhci, ir);
3129 if (xhci->xhc_state & XHCI_STATE_DYING ||
3130 xhci->xhc_state & XHCI_STATE_HALTED) {
3131 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
3132 "Shouldn't IRQs be disabled?\n");
3133 /* Clear the event handler busy flag (RW1C);
3134 * the event ring should be empty.
3136 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
3137 xhci_write_64(xhci, temp_64 | ERST_EHB,
3138 &ir->ir_set->erst_dequeue);
3143 /* FIXME this should be a delayed service routine
3144 * that clears the EHB.
3146 while (xhci_handle_event(xhci, ir) > 0) {
3148 * If half a segment of events have been handled in one go then
3149 * update ERDP, and force isoc trbs to interrupt more often
3151 if (event_loop++ > TRBS_PER_SEGMENT / 2) {
3152 xhci_update_erst_dequeue(xhci, ir, false);
3154 if (ir->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN)
3155 ir->isoc_bei_interval = ir->isoc_bei_interval / 2;
3160 /* Update SW event ring dequeue pointer */
3161 inc_deq(xhci, ir->event_ring);
3164 xhci_update_erst_dequeue(xhci, ir, true);
3168 spin_unlock(&xhci->lock);
3173 irqreturn_t xhci_msi_irq(int irq, void *hcd)
3175 return xhci_irq(hcd);
3177 EXPORT_SYMBOL_GPL(xhci_msi_irq);
3179 /**** Endpoint Ring Operations ****/
3182 * Generic function for queueing a TRB on a ring.
3183 * The caller must have checked to make sure there's room on the ring.
3185 * @more_trbs_coming: Will you enqueue more TRBs before calling
3186 * prepare_transfer()?
3188 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3189 bool more_trbs_coming,
3190 u32 field1, u32 field2, u32 field3, u32 field4)
3192 struct xhci_generic_trb *trb;
3194 trb = &ring->enqueue->generic;
3195 trb->field[0] = cpu_to_le32(field1);
3196 trb->field[1] = cpu_to_le32(field2);
3197 trb->field[2] = cpu_to_le32(field3);
3198 /* make sure TRB is fully written before giving it to the controller */
3200 trb->field[3] = cpu_to_le32(field4);
3202 trace_xhci_queue_trb(ring, trb);
3204 inc_enq(xhci, ring, more_trbs_coming);
3208 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3209 * expand ring if it start to be full.
3211 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3212 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
3214 unsigned int link_trb_count = 0;
3215 unsigned int new_segs = 0;
3217 /* Make sure the endpoint has been added to xHC schedule */
3219 case EP_STATE_DISABLED:
3221 * USB core changed config/interfaces without notifying us,
3222 * or hardware is reporting the wrong state.
3224 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3226 case EP_STATE_ERROR:
3227 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3228 /* FIXME event handling code for error needs to clear it */
3229 /* XXX not sure if this should be -ENOENT or not */
3231 case EP_STATE_HALTED:
3232 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3234 case EP_STATE_STOPPED:
3235 case EP_STATE_RUNNING:
3238 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3240 * FIXME issue Configure Endpoint command to try to get the HC
3241 * back into a known state.
3246 if (ep_ring != xhci->cmd_ring) {
3247 new_segs = xhci_ring_expansion_needed(xhci, ep_ring, num_trbs);
3248 } else if (xhci_num_trbs_free(xhci, ep_ring) <= num_trbs) {
3249 xhci_err(xhci, "Do not support expand command ring\n");
3254 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3255 "ERROR no room on ep ring, try ring expansion");
3256 if (xhci_ring_expansion(xhci, ep_ring, new_segs, mem_flags)) {
3257 xhci_err(xhci, "Ring expansion failed\n");
3262 while (trb_is_link(ep_ring->enqueue)) {
3263 /* If we're not dealing with 0.95 hardware or isoc rings
3264 * on AMD 0.96 host, clear the chain bit.
3266 if (!xhci_link_trb_quirk(xhci) &&
3267 !(ep_ring->type == TYPE_ISOC &&
3268 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3269 ep_ring->enqueue->link.control &=
3270 cpu_to_le32(~TRB_CHAIN);
3272 ep_ring->enqueue->link.control |=
3273 cpu_to_le32(TRB_CHAIN);
3276 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3278 /* Toggle the cycle bit after the last ring segment. */
3279 if (link_trb_toggles_cycle(ep_ring->enqueue))
3280 ep_ring->cycle_state ^= 1;
3282 ep_ring->enq_seg = ep_ring->enq_seg->next;
3283 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3285 /* prevent infinite loop if all first trbs are link trbs */
3286 if (link_trb_count++ > ep_ring->num_segs) {
3287 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
3292 if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
3293 xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
3300 static int prepare_transfer(struct xhci_hcd *xhci,
3301 struct xhci_virt_device *xdev,
3302 unsigned int ep_index,
3303 unsigned int stream_id,
3304 unsigned int num_trbs,
3306 unsigned int td_index,
3310 struct urb_priv *urb_priv;
3312 struct xhci_ring *ep_ring;
3313 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3315 ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
3318 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3323 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3324 num_trbs, mem_flags);
3328 urb_priv = urb->hcpriv;
3329 td = &urb_priv->td[td_index];
3331 INIT_LIST_HEAD(&td->td_list);
3332 INIT_LIST_HEAD(&td->cancelled_td_list);
3334 if (td_index == 0) {
3335 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3341 /* Add this TD to the tail of the endpoint ring's TD list */
3342 list_add_tail(&td->td_list, &ep_ring->td_list);
3343 td->start_seg = ep_ring->enq_seg;
3344 td->first_trb = ep_ring->enqueue;
3349 unsigned int count_trbs(u64 addr, u64 len)
3351 unsigned int num_trbs;
3353 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3361 static inline unsigned int count_trbs_needed(struct urb *urb)
3363 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3366 static unsigned int count_sg_trbs_needed(struct urb *urb)
3368 struct scatterlist *sg;
3369 unsigned int i, len, full_len, num_trbs = 0;
3371 full_len = urb->transfer_buffer_length;
3373 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3374 len = sg_dma_len(sg);
3375 num_trbs += count_trbs(sg_dma_address(sg), len);
3376 len = min_t(unsigned int, len, full_len);
3385 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3389 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3390 len = urb->iso_frame_desc[i].length;
3392 return count_trbs(addr, len);
3395 static void check_trb_math(struct urb *urb, int running_total)
3397 if (unlikely(running_total != urb->transfer_buffer_length))
3398 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3399 "queued %#x (%d), asked for %#x (%d)\n",
3401 urb->ep->desc.bEndpointAddress,
3402 running_total, running_total,
3403 urb->transfer_buffer_length,
3404 urb->transfer_buffer_length);
3407 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3408 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3409 struct xhci_generic_trb *start_trb)
3412 * Pass all the TRBs to the hardware at once and make sure this write
3417 start_trb->field[3] |= cpu_to_le32(start_cycle);
3419 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3420 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3423 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3424 struct xhci_ep_ctx *ep_ctx)
3429 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3430 ep_interval = urb->interval;
3432 /* Convert to microframes */
3433 if (urb->dev->speed == USB_SPEED_LOW ||
3434 urb->dev->speed == USB_SPEED_FULL)
3437 /* FIXME change this to a warning and a suggestion to use the new API
3438 * to set the polling interval (once the API is added).
3440 if (xhci_interval != ep_interval) {
3441 dev_dbg_ratelimited(&urb->dev->dev,
3442 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3443 ep_interval, ep_interval == 1 ? "" : "s",
3444 xhci_interval, xhci_interval == 1 ? "" : "s");
3445 urb->interval = xhci_interval;
3446 /* Convert back to frames for LS/FS devices */
3447 if (urb->dev->speed == USB_SPEED_LOW ||
3448 urb->dev->speed == USB_SPEED_FULL)
3454 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3455 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3456 * (comprised of sg list entries) can take several service intervals to
3459 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3460 struct urb *urb, int slot_id, unsigned int ep_index)
3462 struct xhci_ep_ctx *ep_ctx;
3464 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3465 check_interval(xhci, urb, ep_ctx);
3467 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3471 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3472 * packets remaining in the TD (*not* including this TRB).
3474 * Total TD packet count = total_packet_count =
3475 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3477 * Packets transferred up to and including this TRB = packets_transferred =
3478 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3480 * TD size = total_packet_count - packets_transferred
3482 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3483 * including this TRB, right shifted by 10
3485 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3486 * This is taken care of in the TRB_TD_SIZE() macro
3488 * The last TRB in a TD must have the TD size set to zero.
3490 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3491 int trb_buff_len, unsigned int td_total_len,
3492 struct urb *urb, bool more_trbs_coming)
3494 u32 maxp, total_packet_count;
3496 /* MTK xHCI 0.96 contains some features from 1.0 */
3497 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3498 return ((td_total_len - transferred) >> 10);
3500 /* One TRB with a zero-length data packet. */
3501 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3502 trb_buff_len == td_total_len)
3505 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3506 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3509 maxp = usb_endpoint_maxp(&urb->ep->desc);
3510 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3512 /* Queueing functions don't count the current TRB into transferred */
3513 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3517 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3518 u32 *trb_buff_len, struct xhci_segment *seg)
3520 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
3521 unsigned int unalign;
3522 unsigned int max_pkt;
3526 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3527 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3529 /* we got lucky, last normal TRB data on segment is packet aligned */
3533 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3534 unalign, *trb_buff_len);
3536 /* is the last nornal TRB alignable by splitting it */
3537 if (*trb_buff_len > unalign) {
3538 *trb_buff_len -= unalign;
3539 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3544 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3545 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3546 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3548 new_buff_len = max_pkt - (enqd_len % max_pkt);
3550 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3551 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3553 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3554 if (usb_urb_dir_out(urb)) {
3556 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3557 seg->bounce_buf, new_buff_len, enqd_len);
3558 if (len != new_buff_len)
3559 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3562 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3565 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3566 max_pkt, DMA_TO_DEVICE);
3568 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3569 max_pkt, DMA_FROM_DEVICE);
3572 if (dma_mapping_error(dev, seg->bounce_dma)) {
3573 /* try without aligning. Some host controllers survive */
3574 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3577 *trb_buff_len = new_buff_len;
3578 seg->bounce_len = new_buff_len;
3579 seg->bounce_offs = enqd_len;
3581 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3586 /* This is very similar to what ehci-q.c qtd_fill() does */
3587 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3588 struct urb *urb, int slot_id, unsigned int ep_index)
3590 struct xhci_ring *ring;
3591 struct urb_priv *urb_priv;
3593 struct xhci_generic_trb *start_trb;
3594 struct scatterlist *sg = NULL;
3595 bool more_trbs_coming = true;
3596 bool need_zero_pkt = false;
3597 bool first_trb = true;
3598 unsigned int num_trbs;
3599 unsigned int start_cycle, num_sgs = 0;
3600 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3602 u32 field, length_field, remainder;
3603 u64 addr, send_addr;
3605 ring = xhci_urb_to_transfer_ring(xhci, urb);
3609 full_len = urb->transfer_buffer_length;
3610 /* If we have scatter/gather list, we use it. */
3611 if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3612 num_sgs = urb->num_mapped_sgs;
3614 addr = (u64) sg_dma_address(sg);
3615 block_len = sg_dma_len(sg);
3616 num_trbs = count_sg_trbs_needed(urb);
3618 num_trbs = count_trbs_needed(urb);
3619 addr = (u64) urb->transfer_dma;
3620 block_len = full_len;
3622 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3623 ep_index, urb->stream_id,
3624 num_trbs, urb, 0, mem_flags);
3625 if (unlikely(ret < 0))
3628 urb_priv = urb->hcpriv;
3630 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3631 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3632 need_zero_pkt = true;
3634 td = &urb_priv->td[0];
3637 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3638 * until we've finished creating all the other TRBs. The ring's cycle
3639 * state may change as we enqueue the other TRBs, so save it too.
3641 start_trb = &ring->enqueue->generic;
3642 start_cycle = ring->cycle_state;
3645 /* Queue the TRBs, even if they are zero-length */
3646 for (enqd_len = 0; first_trb || enqd_len < full_len;
3647 enqd_len += trb_buff_len) {
3648 field = TRB_TYPE(TRB_NORMAL);
3650 /* TRB buffer should not cross 64KB boundaries */
3651 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3652 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3654 if (enqd_len + trb_buff_len > full_len)
3655 trb_buff_len = full_len - enqd_len;
3657 /* Don't change the cycle bit of the first TRB until later */
3660 if (start_cycle == 0)
3663 field |= ring->cycle_state;
3665 /* Chain all the TRBs together; clear the chain bit in the last
3666 * TRB to indicate it's the last TRB in the chain.
3668 if (enqd_len + trb_buff_len < full_len) {
3670 if (trb_is_link(ring->enqueue + 1)) {
3671 if (xhci_align_td(xhci, urb, enqd_len,
3674 send_addr = ring->enq_seg->bounce_dma;
3675 /* assuming TD won't span 2 segs */
3676 td->bounce_seg = ring->enq_seg;
3680 if (enqd_len + trb_buff_len >= full_len) {
3681 field &= ~TRB_CHAIN;
3683 more_trbs_coming = false;
3684 td->last_trb = ring->enqueue;
3685 td->last_trb_seg = ring->enq_seg;
3686 if (xhci_urb_suitable_for_idt(urb)) {
3687 memcpy(&send_addr, urb->transfer_buffer,
3689 le64_to_cpus(&send_addr);
3694 /* Only set interrupt on short packet for IN endpoints */
3695 if (usb_urb_dir_in(urb))
3698 /* Set the TRB length, TD size, and interrupter fields. */
3699 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3700 full_len, urb, more_trbs_coming);
3702 length_field = TRB_LEN(trb_buff_len) |
3703 TRB_TD_SIZE(remainder) |
3706 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3707 lower_32_bits(send_addr),
3708 upper_32_bits(send_addr),
3712 addr += trb_buff_len;
3713 sent_len = trb_buff_len;
3715 while (sg && sent_len >= block_len) {
3718 sent_len -= block_len;
3720 if (num_sgs != 0 && sg) {
3721 block_len = sg_dma_len(sg);
3722 addr = (u64) sg_dma_address(sg);
3726 block_len -= sent_len;
3730 if (need_zero_pkt) {
3731 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3732 ep_index, urb->stream_id,
3733 1, urb, 1, mem_flags);
3734 urb_priv->td[1].last_trb = ring->enqueue;
3735 urb_priv->td[1].last_trb_seg = ring->enq_seg;
3736 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3737 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3738 urb_priv->td[1].num_trbs++;
3741 check_trb_math(urb, enqd_len);
3742 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3743 start_cycle, start_trb);
3747 /* Caller must have locked xhci->lock */
3748 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3749 struct urb *urb, int slot_id, unsigned int ep_index)
3751 struct xhci_ring *ep_ring;
3754 struct usb_ctrlrequest *setup;
3755 struct xhci_generic_trb *start_trb;
3758 struct urb_priv *urb_priv;
3761 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3766 * Need to copy setup packet into setup TRB, so we can't use the setup
3769 if (!urb->setup_packet)
3772 /* 1 TRB for setup, 1 for status */
3775 * Don't need to check if we need additional event data and normal TRBs,
3776 * since data in control transfers will never get bigger than 16MB
3777 * XXX: can we get a buffer that crosses 64KB boundaries?
3779 if (urb->transfer_buffer_length > 0)
3781 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3782 ep_index, urb->stream_id,
3783 num_trbs, urb, 0, mem_flags);
3787 urb_priv = urb->hcpriv;
3788 td = &urb_priv->td[0];
3789 td->num_trbs = num_trbs;
3792 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3793 * until we've finished creating all the other TRBs. The ring's cycle
3794 * state may change as we enqueue the other TRBs, so save it too.
3796 start_trb = &ep_ring->enqueue->generic;
3797 start_cycle = ep_ring->cycle_state;
3799 /* Queue setup TRB - see section 6.4.1.2.1 */
3800 /* FIXME better way to translate setup_packet into two u32 fields? */
3801 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3803 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3804 if (start_cycle == 0)
3807 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3808 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3809 if (urb->transfer_buffer_length > 0) {
3810 if (setup->bRequestType & USB_DIR_IN)
3811 field |= TRB_TX_TYPE(TRB_DATA_IN);
3813 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3817 queue_trb(xhci, ep_ring, true,
3818 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3819 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3820 TRB_LEN(8) | TRB_INTR_TARGET(0),
3821 /* Immediate data in pointer */
3824 /* If there's data, queue data TRBs */
3825 /* Only set interrupt on short packet for IN endpoints */
3826 if (usb_urb_dir_in(urb))
3827 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3829 field = TRB_TYPE(TRB_DATA);
3831 if (urb->transfer_buffer_length > 0) {
3832 u32 length_field, remainder;
3835 if (xhci_urb_suitable_for_idt(urb)) {
3836 memcpy(&addr, urb->transfer_buffer,
3837 urb->transfer_buffer_length);
3838 le64_to_cpus(&addr);
3841 addr = (u64) urb->transfer_dma;
3844 remainder = xhci_td_remainder(xhci, 0,
3845 urb->transfer_buffer_length,
3846 urb->transfer_buffer_length,
3848 length_field = TRB_LEN(urb->transfer_buffer_length) |
3849 TRB_TD_SIZE(remainder) |
3851 if (setup->bRequestType & USB_DIR_IN)
3852 field |= TRB_DIR_IN;
3853 queue_trb(xhci, ep_ring, true,
3854 lower_32_bits(addr),
3855 upper_32_bits(addr),
3857 field | ep_ring->cycle_state);
3860 /* Save the DMA address of the last TRB in the TD */
3861 td->last_trb = ep_ring->enqueue;
3862 td->last_trb_seg = ep_ring->enq_seg;
3864 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3865 /* If the device sent data, the status stage is an OUT transfer */
3866 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3870 queue_trb(xhci, ep_ring, false,
3874 /* Event on completion */
3875 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3877 giveback_first_trb(xhci, slot_id, ep_index, 0,
3878 start_cycle, start_trb);
3883 * The transfer burst count field of the isochronous TRB defines the number of
3884 * bursts that are required to move all packets in this TD. Only SuperSpeed
3885 * devices can burst up to bMaxBurst number of packets per service interval.
3886 * This field is zero based, meaning a value of zero in the field means one
3887 * burst. Basically, for everything but SuperSpeed devices, this field will be
3888 * zero. Only xHCI 1.0 host controllers support this field.
3890 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3891 struct urb *urb, unsigned int total_packet_count)
3893 unsigned int max_burst;
3895 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3898 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3899 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3903 * Returns the number of packets in the last "burst" of packets. This field is
3904 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3905 * the last burst packet count is equal to the total number of packets in the
3906 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3907 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3908 * contain 1 to (bMaxBurst + 1) packets.
3910 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3911 struct urb *urb, unsigned int total_packet_count)
3913 unsigned int max_burst;
3914 unsigned int residue;
3916 if (xhci->hci_version < 0x100)
3919 if (urb->dev->speed >= USB_SPEED_SUPER) {
3920 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3921 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3922 residue = total_packet_count % (max_burst + 1);
3923 /* If residue is zero, the last burst contains (max_burst + 1)
3924 * number of packets, but the TLBPC field is zero-based.
3930 if (total_packet_count == 0)
3932 return total_packet_count - 1;
3936 * Calculates Frame ID field of the isochronous TRB identifies the
3937 * target frame that the Interval associated with this Isochronous
3938 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3940 * Returns actual frame id on success, negative value on error.
3942 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3943 struct urb *urb, int index)
3945 int start_frame, ist, ret = 0;
3946 int start_frame_id, end_frame_id, current_frame_id;
3948 if (urb->dev->speed == USB_SPEED_LOW ||
3949 urb->dev->speed == USB_SPEED_FULL)
3950 start_frame = urb->start_frame + index * urb->interval;
3952 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3954 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3956 * If bit [3] of IST is cleared to '0', software can add a TRB no
3957 * later than IST[2:0] Microframes before that TRB is scheduled to
3959 * If bit [3] of IST is set to '1', software can add a TRB no later
3960 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3962 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3963 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3966 /* Software shall not schedule an Isoch TD with a Frame ID value that
3967 * is less than the Start Frame ID or greater than the End Frame ID,
3970 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3971 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3973 * Both the End Frame ID and Start Frame ID values are calculated
3974 * in microframes. When software determines the valid Frame ID value;
3975 * The End Frame ID value should be rounded down to the nearest Frame
3976 * boundary, and the Start Frame ID value should be rounded up to the
3977 * nearest Frame boundary.
3979 current_frame_id = readl(&xhci->run_regs->microframe_index);
3980 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3981 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3983 start_frame &= 0x7ff;
3984 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3985 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3987 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3988 __func__, index, readl(&xhci->run_regs->microframe_index),
3989 start_frame_id, end_frame_id, start_frame);
3991 if (start_frame_id < end_frame_id) {
3992 if (start_frame > end_frame_id ||
3993 start_frame < start_frame_id)
3995 } else if (start_frame_id > end_frame_id) {
3996 if ((start_frame > end_frame_id &&
3997 start_frame < start_frame_id))
4004 if (ret == -EINVAL || start_frame == start_frame_id) {
4005 start_frame = start_frame_id + 1;
4006 if (urb->dev->speed == USB_SPEED_LOW ||
4007 urb->dev->speed == USB_SPEED_FULL)
4008 urb->start_frame = start_frame;
4010 urb->start_frame = start_frame << 3;
4016 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
4017 start_frame, current_frame_id, index,
4018 start_frame_id, end_frame_id);
4019 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
4026 /* Check if we should generate event interrupt for a TD in an isoc URB */
4027 static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i,
4028 struct xhci_interrupter *ir)
4030 if (xhci->hci_version < 0x100)
4032 /* always generate an event interrupt for the last TD */
4033 if (i == num_tds - 1)
4036 * If AVOID_BEI is set the host handles full event rings poorly,
4037 * generate an event at least every 8th TD to clear the event ring
4039 if (i && ir->isoc_bei_interval && xhci->quirks & XHCI_AVOID_BEI)
4040 return !!(i % ir->isoc_bei_interval);
4045 /* This is for isoc transfer */
4046 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
4047 struct urb *urb, int slot_id, unsigned int ep_index)
4049 struct xhci_interrupter *ir;
4050 struct xhci_ring *ep_ring;
4051 struct urb_priv *urb_priv;
4053 int num_tds, trbs_per_td;
4054 struct xhci_generic_trb *start_trb;
4057 u32 field, length_field;
4058 int running_total, trb_buff_len, td_len, td_remain_len, ret;
4059 u64 start_addr, addr;
4061 bool more_trbs_coming;
4062 struct xhci_virt_ep *xep;
4065 xep = &xhci->devs[slot_id]->eps[ep_index];
4066 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
4067 ir = xhci->interrupters[0];
4069 num_tds = urb->number_of_packets;
4071 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
4074 start_addr = (u64) urb->transfer_dma;
4075 start_trb = &ep_ring->enqueue->generic;
4076 start_cycle = ep_ring->cycle_state;
4078 urb_priv = urb->hcpriv;
4079 /* Queue the TRBs for each TD, even if they are zero-length */
4080 for (i = 0; i < num_tds; i++) {
4081 unsigned int total_pkt_count, max_pkt;
4082 unsigned int burst_count, last_burst_pkt_count;
4087 addr = start_addr + urb->iso_frame_desc[i].offset;
4088 td_len = urb->iso_frame_desc[i].length;
4089 td_remain_len = td_len;
4090 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
4091 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
4093 /* A zero-length transfer still involves at least one packet. */
4094 if (total_pkt_count == 0)
4096 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
4097 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
4098 urb, total_pkt_count);
4100 trbs_per_td = count_isoc_trbs_needed(urb, i);
4102 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
4103 urb->stream_id, trbs_per_td, urb, i, mem_flags);
4109 td = &urb_priv->td[i];
4110 td->num_trbs = trbs_per_td;
4111 /* use SIA as default, if frame id is used overwrite it */
4112 sia_frame_id = TRB_SIA;
4113 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
4114 HCC_CFC(xhci->hcc_params)) {
4115 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
4117 sia_frame_id = TRB_FRAME_ID(frame_id);
4120 * Set isoc specific data for the first TRB in a TD.
4121 * Prevent HW from getting the TRBs by keeping the cycle state
4122 * inverted in the first TDs isoc TRB.
4124 field = TRB_TYPE(TRB_ISOC) |
4125 TRB_TLBPC(last_burst_pkt_count) |
4127 (i ? ep_ring->cycle_state : !start_cycle);
4129 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4130 if (!xep->use_extended_tbc)
4131 field |= TRB_TBC(burst_count);
4133 /* fill the rest of the TRB fields, and remaining normal TRBs */
4134 for (j = 0; j < trbs_per_td; j++) {
4137 /* only first TRB is isoc, overwrite otherwise */
4139 field = TRB_TYPE(TRB_NORMAL) |
4140 ep_ring->cycle_state;
4142 /* Only set interrupt on short packet for IN EPs */
4143 if (usb_urb_dir_in(urb))
4146 /* Set the chain bit for all except the last TRB */
4147 if (j < trbs_per_td - 1) {
4148 more_trbs_coming = true;
4151 more_trbs_coming = false;
4152 td->last_trb = ep_ring->enqueue;
4153 td->last_trb_seg = ep_ring->enq_seg;
4155 if (trb_block_event_intr(xhci, num_tds, i, ir))
4158 /* Calculate TRB length */
4159 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
4160 if (trb_buff_len > td_remain_len)
4161 trb_buff_len = td_remain_len;
4163 /* Set the TRB length, TD size, & interrupter fields. */
4164 remainder = xhci_td_remainder(xhci, running_total,
4165 trb_buff_len, td_len,
4166 urb, more_trbs_coming);
4168 length_field = TRB_LEN(trb_buff_len) |
4171 /* xhci 1.1 with ETE uses TD Size field for TBC */
4172 if (first_trb && xep->use_extended_tbc)
4173 length_field |= TRB_TD_SIZE_TBC(burst_count);
4175 length_field |= TRB_TD_SIZE(remainder);
4178 queue_trb(xhci, ep_ring, more_trbs_coming,
4179 lower_32_bits(addr),
4180 upper_32_bits(addr),
4183 running_total += trb_buff_len;
4185 addr += trb_buff_len;
4186 td_remain_len -= trb_buff_len;
4189 /* Check TD length */
4190 if (running_total != td_len) {
4191 xhci_err(xhci, "ISOC TD length unmatch\n");
4197 /* store the next frame id */
4198 if (HCC_CFC(xhci->hcc_params))
4199 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
4201 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
4202 if (xhci->quirks & XHCI_AMD_PLL_FIX)
4203 usb_amd_quirk_pll_disable();
4205 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
4207 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
4208 start_cycle, start_trb);
4211 /* Clean up a partially enqueued isoc transfer. */
4213 for (i--; i >= 0; i--)
4214 list_del_init(&urb_priv->td[i].td_list);
4216 /* Use the first TD as a temporary variable to turn the TDs we've queued
4217 * into No-ops with a software-owned cycle bit. That way the hardware
4218 * won't accidentally start executing bogus TDs when we partially
4219 * overwrite them. td->first_trb and td->start_seg are already set.
4221 urb_priv->td[0].last_trb = ep_ring->enqueue;
4222 /* Every TRB except the first & last will have its cycle bit flipped. */
4223 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
4225 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4226 ep_ring->enqueue = urb_priv->td[0].first_trb;
4227 ep_ring->enq_seg = urb_priv->td[0].start_seg;
4228 ep_ring->cycle_state = start_cycle;
4229 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4234 * Check transfer ring to guarantee there is enough room for the urb.
4235 * Update ISO URB start_frame and interval.
4236 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4237 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4238 * Contiguous Frame ID is not supported by HC.
4240 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4241 struct urb *urb, int slot_id, unsigned int ep_index)
4243 struct xhci_virt_device *xdev;
4244 struct xhci_ring *ep_ring;
4245 struct xhci_ep_ctx *ep_ctx;
4247 int num_tds, num_trbs, i;
4249 struct xhci_virt_ep *xep;
4252 xdev = xhci->devs[slot_id];
4253 xep = &xhci->devs[slot_id]->eps[ep_index];
4254 ep_ring = xdev->eps[ep_index].ring;
4255 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4258 num_tds = urb->number_of_packets;
4259 for (i = 0; i < num_tds; i++)
4260 num_trbs += count_isoc_trbs_needed(urb, i);
4262 /* Check the ring to guarantee there is enough room for the whole urb.
4263 * Do not insert any td of the urb to the ring if the check failed.
4265 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4266 num_trbs, mem_flags);
4271 * Check interval value. This should be done before we start to
4272 * calculate the start frame value.
4274 check_interval(xhci, urb, ep_ctx);
4276 /* Calculate the start frame and put it in urb->start_frame. */
4277 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4278 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
4279 urb->start_frame = xep->next_frame_id;
4280 goto skip_start_over;
4284 start_frame = readl(&xhci->run_regs->microframe_index);
4285 start_frame &= 0x3fff;
4287 * Round up to the next frame and consider the time before trb really
4288 * gets scheduled by hardare.
4290 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4291 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4293 start_frame += ist + XHCI_CFC_DELAY;
4294 start_frame = roundup(start_frame, 8);
4297 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4298 * is greate than 8 microframes.
4300 if (urb->dev->speed == USB_SPEED_LOW ||
4301 urb->dev->speed == USB_SPEED_FULL) {
4302 start_frame = roundup(start_frame, urb->interval << 3);
4303 urb->start_frame = start_frame >> 3;
4305 start_frame = roundup(start_frame, urb->interval);
4306 urb->start_frame = start_frame;
4311 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4314 /**** Command Ring Operations ****/
4316 /* Generic function for queueing a command TRB on the command ring.
4317 * Check to make sure there's room on the command ring for one command TRB.
4318 * Also check that there's room reserved for commands that must not fail.
4319 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4320 * then only check for the number of reserved spots.
4321 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4322 * because the command event handler may want to resubmit a failed command.
4324 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4325 u32 field1, u32 field2,
4326 u32 field3, u32 field4, bool command_must_succeed)
4328 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4331 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4332 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4333 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4337 if (!command_must_succeed)
4340 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4341 reserved_trbs, GFP_ATOMIC);
4343 xhci_err(xhci, "ERR: No room for command on command ring\n");
4344 if (command_must_succeed)
4345 xhci_err(xhci, "ERR: Reserved TRB counting for "
4346 "unfailable commands failed.\n");
4350 cmd->command_trb = xhci->cmd_ring->enqueue;
4352 /* if there are no other commands queued we start the timeout timer */
4353 if (list_empty(&xhci->cmd_list)) {
4354 xhci->current_cmd = cmd;
4355 xhci_mod_cmd_timer(xhci);
4358 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4360 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4361 field4 | xhci->cmd_ring->cycle_state);
4365 /* Queue a slot enable or disable request on the command ring */
4366 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4367 u32 trb_type, u32 slot_id)
4369 return queue_command(xhci, cmd, 0, 0, 0,
4370 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4373 /* Queue an address device command TRB */
4374 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4375 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4377 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4378 upper_32_bits(in_ctx_ptr), 0,
4379 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4380 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4383 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4384 u32 field1, u32 field2, u32 field3, u32 field4)
4386 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4389 /* Queue a reset device command TRB */
4390 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4393 return queue_command(xhci, cmd, 0, 0, 0,
4394 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4398 /* Queue a configure endpoint command TRB */
4399 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4400 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4401 u32 slot_id, bool command_must_succeed)
4403 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4404 upper_32_bits(in_ctx_ptr), 0,
4405 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4406 command_must_succeed);
4409 /* Queue an evaluate context command TRB */
4410 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4411 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4413 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4414 upper_32_bits(in_ctx_ptr), 0,
4415 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4416 command_must_succeed);
4420 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4421 * activity on an endpoint that is about to be suspended.
4423 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4424 int slot_id, unsigned int ep_index, int suspend)
4426 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4427 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4428 u32 type = TRB_TYPE(TRB_STOP_RING);
4429 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4431 return queue_command(xhci, cmd, 0, 0, 0,
4432 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4435 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4436 int slot_id, unsigned int ep_index,
4437 enum xhci_ep_reset_type reset_type)
4439 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4440 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4441 u32 type = TRB_TYPE(TRB_RESET_EP);
4443 if (reset_type == EP_SOFT_RESET)
4446 return queue_command(xhci, cmd, 0, 0, 0,
4447 trb_slot_id | trb_ep_index | type, false);