drivers/usb/host/xhci-rcar.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver for R-Car SoCs
   4  *
   5  * Copyright (C) 2014 Renesas Electronics Corporation
   6  */
   7
   8 #include <linux/firmware.h>
   9 #include <linux/iopoll.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/of.h>
  13 #include <linux/usb/phy.h>
  14
  15 #include "xhci.h"
  16 #include "xhci-plat.h"
  17 #include "xhci-rzv2m.h"
  18
  19 #define XHCI_RCAR_FIRMWARE_NAME_V1      "/*(DEBLOBBED)*/"
  20 #define XHCI_RCAR_FIRMWARE_NAME_V3      "/*(DEBLOBBED)*/"
  21
  22 /*
  23 * - The V3 firmware is for all R-Car Gen3
  24 * - The V2 firmware is possible to use on R-Car Gen2. However, the V2 causes
  25 *   performance degradation. So, this driver continues to use the V1 if R-Car
  26 *   Gen2.
  27 * - The V1 firmware is impossible to use on R-Car Gen3.
  28 */
  29 /*(DEBLOBBED)*/
  30
  31 /*** Register Offset ***/
  32 #define RCAR_USB3_AXH_STA       0x104   /* AXI Host Control Status */
  33 #define RCAR_USB3_INT_ENA       0x224   /* Interrupt Enable */
  34 #define RCAR_USB3_DL_CTRL       0x250   /* FW Download Control & Status */
  35 #define RCAR_USB3_FW_DATA0      0x258   /* FW Data0 */
  36
  37 #define RCAR_USB3_LCLK          0xa44   /* LCLK Select */
  38 #define RCAR_USB3_CONF1         0xa48   /* USB3.0 Configuration1 */
  39 #define RCAR_USB3_CONF2         0xa5c   /* USB3.0 Configuration2 */
  40 #define RCAR_USB3_CONF3         0xaa8   /* USB3.0 Configuration3 */
  41 #define RCAR_USB3_RX_POL        0xab0   /* USB3.0 RX Polarity */
  42 #define RCAR_USB3_TX_POL        0xab8   /* USB3.0 TX Polarity */
  43
  44 /*** Register Settings ***/
  45 /* AXI Host Control Status */
  46 #define RCAR_USB3_AXH_STA_B3_PLL_ACTIVE         0x00010000
  47 #define RCAR_USB3_AXH_STA_B2_PLL_ACTIVE         0x00000001
  48 #define RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK (RCAR_USB3_AXH_STA_B3_PLL_ACTIVE | \
  49                                            RCAR_USB3_AXH_STA_B2_PLL_ACTIVE)
  50
  51 /* Interrupt Enable */
  52 #define RCAR_USB3_INT_XHC_ENA   0x00000001
  53 #define RCAR_USB3_INT_PME_ENA   0x00000002
  54 #define RCAR_USB3_INT_HSE_ENA   0x00000004
  55 #define RCAR_USB3_INT_ENA_VAL   (RCAR_USB3_INT_XHC_ENA | \
  56                                 RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA)
  57
  58 /* FW Download Control & Status */
  59 #define RCAR_USB3_DL_CTRL_ENABLE        0x00000001
  60 #define RCAR_USB3_DL_CTRL_FW_SUCCESS    0x00000010
  61 #define RCAR_USB3_DL_CTRL_FW_SET_DATA0  0x00000100
  62
  63 /* LCLK Select */
  64 #define RCAR_USB3_LCLK_ENA_VAL  0x01030001
  65
  66 /* USB3.0 Configuration */
  67 #define RCAR_USB3_CONF1_VAL     0x00030204
  68 #define RCAR_USB3_CONF2_VAL     0x00030300
  69 #define RCAR_USB3_CONF3_VAL     0x13802007
  70
  71 /* USB3.0 Polarity */
  72 #define RCAR_USB3_RX_POL_VAL    BIT(21)
  73 #define RCAR_USB3_TX_POL_VAL    BIT(4)
  74
  75 static void xhci_rcar_start_gen2(struct usb_hcd *hcd)
  76 {
  77         /* LCLK Select */
  78         writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK);
  79         /* USB3.0 Configuration */
  80         writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1);
  81         writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2);
  82         writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3);
  83         /* USB3.0 Polarity */
  84         writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL);
  85         writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL);
  86 }
  87
  88 static int xhci_rcar_is_gen2(struct device *dev)
  89 {
  90         struct device_node *node = dev->of_node;
  91
  92         return of_device_is_compatible(node, "renesas,xhci-r8a7790") ||
  93                 of_device_is_compatible(node, "renesas,xhci-r8a7791") ||
  94                 of_device_is_compatible(node, "renesas,xhci-r8a7793") ||
  95                 of_device_is_compatible(node, "renesas,rcar-gen2-xhci");
  96 }
  97
  98 static void xhci_rcar_start(struct usb_hcd *hcd)
  99 {
 100         u32 temp;
 101
 102         if (hcd->regs != NULL) {
 103                 /* Interrupt Enable */
 104                 temp = readl(hcd->regs + RCAR_USB3_INT_ENA);
 105                 temp |= RCAR_USB3_INT_ENA_VAL;
 106                 writel(temp, hcd->regs + RCAR_USB3_INT_ENA);
 107                 if (xhci_rcar_is_gen2(hcd->self.controller))
 108                         xhci_rcar_start_gen2(hcd);
 109         }
 110 }
 111
 112 static int xhci_rcar_download_firmware(struct usb_hcd *hcd)
 113 {
 114         struct device *dev = hcd->self.controller;
 115         void __iomem *regs = hcd->regs;
 116         struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
 117         const struct firmware *fw;
 118         int retval, index, j;
 119         u32 data, val, temp;
 120
 121         /*
 122          * According to the datasheet, "Upon the completion of FW Download,
 123          * there is no need to write or reload FW".
 124          */
 125         if (readl(regs + RCAR_USB3_DL_CTRL) & RCAR_USB3_DL_CTRL_FW_SUCCESS)
 126                 return 0;
 127
 128         /* request R-Car USB3.0 firmware */
 129         retval = reject_firmware(&fw, priv->firmware_name, dev);
 130         if (retval)
 131                 return retval;
 132
 133         /* download R-Car USB3.0 firmware */
 134         temp = readl(regs + RCAR_USB3_DL_CTRL);
 135         temp |= RCAR_USB3_DL_CTRL_ENABLE;
 136         writel(temp, regs + RCAR_USB3_DL_CTRL);
 137
 138         for (index = 0; index < fw->size; index += 4) {
 139                 /* to avoid reading beyond the end of the buffer */
 140                 for (data = 0, j = 3; j >= 0; j--) {
 141                         if ((j + index) < fw->size)
 142                                 data |= fw->data[index + j] << (8 * j);
 143                 }
 144                 writel(data, regs + RCAR_USB3_FW_DATA0);
 145                 temp = readl(regs + RCAR_USB3_DL_CTRL);
 146                 temp |= RCAR_USB3_DL_CTRL_FW_SET_DATA0;
 147                 writel(temp, regs + RCAR_USB3_DL_CTRL);
 148
 149                 retval = readl_poll_timeout_atomic(regs + RCAR_USB3_DL_CTRL,
 150                                 val, !(val & RCAR_USB3_DL_CTRL_FW_SET_DATA0),
 151                                 1, 10000);
 152                 if (retval < 0)
 153                         break;
 154         }
 155
 156         temp = readl(regs + RCAR_USB3_DL_CTRL);
 157         temp &= ~RCAR_USB3_DL_CTRL_ENABLE;
 158         writel(temp, regs + RCAR_USB3_DL_CTRL);
 159
 160         retval = readl_poll_timeout_atomic((regs + RCAR_USB3_DL_CTRL),
 161                         val, val & RCAR_USB3_DL_CTRL_FW_SUCCESS, 1, 10000);
 162
 163         release_firmware(fw);
 164
 165         return retval;
 166 }
 167
 168 static bool xhci_rcar_wait_for_pll_active(struct usb_hcd *hcd)
 169 {
 170         int retval;
 171         u32 val, mask = RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK;
 172
 173         retval = readl_poll_timeout_atomic(hcd->regs + RCAR_USB3_AXH_STA,
 174                         val, (val & mask) == mask, 1, 1000);
 175         return !retval;
 176 }
 177
 178 /* This function needs to initialize a "phy" of usb before */
 179 static int xhci_rcar_init_quirk(struct usb_hcd *hcd)
 180 {
 181         /* If hcd->regs is NULL, we don't just call the following function */
 182         if (!hcd->regs)
 183                 return 0;
 184
 185         if (!xhci_rcar_wait_for_pll_active(hcd))
 186                 return -ETIMEDOUT;
 187
 188         return xhci_rcar_download_firmware(hcd);
 189 }
 190
 191 static int xhci_rcar_resume_quirk(struct usb_hcd *hcd)
 192 {
 193         int ret;
 194
 195         ret = xhci_rcar_download_firmware(hcd);
 196         if (!ret)
 197                 xhci_rcar_start(hcd);
 198
 199         return ret;
 200 }
 201
 202 /*
 203  * On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set
 204  * to 1. However, these SoCs don't support 64-bit address memory
 205  * pointers. So, this driver clears the AC64 bit of xhci->hcc_params
 206  * to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in
 207  * xhci_gen_setup() by using the XHCI_NO_64BIT_SUPPORT quirk.
 208  *
 209  * And, since the firmware/internal CPU control the USBSTS.STS_HALT
 210  * and the process speed is down when the roothub port enters U3,
 211  * long delay for the handshake of STS_HALT is neeed in xhci_suspend()
 212  * by using the XHCI_SLOW_SUSPEND quirk.
 213  */
 214 #define SET_XHCI_PLAT_PRIV_FOR_RCAR(firmware)                           \
 215         .firmware_name = firmware,                                      \
 216         .quirks = XHCI_NO_64BIT_SUPPORT | XHCI_TRUST_TX_LENGTH |        \
 217                   XHCI_SLOW_SUSPEND,                                    \
 218         .init_quirk = xhci_rcar_init_quirk,                             \
 219         .plat_start = xhci_rcar_start,                                  \
 220         .resume_quirk = xhci_rcar_resume_quirk,
 221
 222 static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen2 = {
 223         SET_XHCI_PLAT_PRIV_FOR_RCAR(XHCI_RCAR_FIRMWARE_NAME_V1)
 224 };
 225
 226 static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen3 = {
 227         SET_XHCI_PLAT_PRIV_FOR_RCAR(XHCI_RCAR_FIRMWARE_NAME_V3)
 228 };
 229
 230 static const struct xhci_plat_priv xhci_plat_renesas_rzv2m = {
 231         .quirks = XHCI_NO_64BIT_SUPPORT | XHCI_TRUST_TX_LENGTH |
 232                   XHCI_SLOW_SUSPEND,
 233         .init_quirk = xhci_rzv2m_init_quirk,
 234         .plat_start = xhci_rzv2m_start,
 235 };
 236
 237 static const struct of_device_id usb_xhci_of_match[] = {
 238         {
 239                 .compatible = "renesas,xhci-r8a7790",
 240                 .data = &xhci_plat_renesas_rcar_gen2,
 241         }, {
 242                 .compatible = "renesas,xhci-r8a7791",
 243                 .data = &xhci_plat_renesas_rcar_gen2,
 244         }, {
 245                 .compatible = "renesas,xhci-r8a7793",
 246                 .data = &xhci_plat_renesas_rcar_gen2,
 247         }, {
 248                 .compatible = "renesas,xhci-r8a7795",
 249                 .data = &xhci_plat_renesas_rcar_gen3,
 250         }, {
 251                 .compatible = "renesas,xhci-r8a7796",
 252                 .data = &xhci_plat_renesas_rcar_gen3,
 253         }, {
 254                 .compatible = "renesas,rcar-gen2-xhci",
 255                 .data = &xhci_plat_renesas_rcar_gen2,
 256         }, {
 257                 .compatible = "renesas,rcar-gen3-xhci",
 258                 .data = &xhci_plat_renesas_rcar_gen3,
 259         }, {
 260                 .compatible = "renesas,rzv2m-xhci",
 261                 .data = &xhci_plat_renesas_rzv2m,
 262         },
 263         { },
 264 };
 265 MODULE_DEVICE_TABLE(of, usb_xhci_of_match);
 266
 267 static int xhci_renesas_probe(struct platform_device *pdev)
 268 {
 269         const struct xhci_plat_priv *priv_match;
 270
 271         priv_match = of_device_get_match_data(&pdev->dev);
 272
 273         return xhci_plat_probe(pdev, NULL, priv_match);
 274 }
 275
 276 static struct platform_driver usb_xhci_renesas_driver = {
 277         .probe = xhci_renesas_probe,
 278         .remove_new = xhci_plat_remove,
 279         .shutdown = usb_hcd_platform_shutdown,
 280         .driver = {
 281                 .name = "xhci-renesas-hcd",
 282                 .pm = &xhci_plat_pm_ops,
 283                 .of_match_table = usb_xhci_of_match,
 284         },
 285 };
 286 module_platform_driver(usb_xhci_renesas_driver);
 287
 288 MODULE_DESCRIPTION("xHCI Platform Host Controller Driver for Renesas R-Car and RZ");
 289 MODULE_LICENSE("GPL");