2 * xHCI host controller driver for R-Car SoCs
4 * Copyright (C) 2014 Renesas Electronics Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
11 #include <linux/firmware.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
15 #include <linux/usb/phy.h>
16 #include <linux/sys_soc.h>
19 #include "xhci-plat.h"
20 #include "xhci-rcar.h"
23 * - The V3 firmware is for r8a7796 (with good performance) and r8a7795 es2.0
25 * - The V2 firmware can be used on both r8a7795 (es1.x) and r8a7796.
26 * - The V2 firmware is possible to use on R-Car Gen2. However, the V2 causes
27 * performance degradation. So, this driver continues to use the V1 if R-Car
29 * - The V1 firmware is impossible to use on R-Car Gen3.
33 /*** Register Offset ***/
34 #define RCAR_USB3_INT_ENA 0x224 /* Interrupt Enable */
35 #define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */
36 #define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */
38 #define RCAR_USB3_LCLK 0xa44 /* LCLK Select */
39 #define RCAR_USB3_CONF1 0xa48 /* USB3.0 Configuration1 */
40 #define RCAR_USB3_CONF2 0xa5c /* USB3.0 Configuration2 */
41 #define RCAR_USB3_CONF3 0xaa8 /* USB3.0 Configuration3 */
42 #define RCAR_USB3_RX_POL 0xab0 /* USB3.0 RX Polarity */
43 #define RCAR_USB3_TX_POL 0xab8 /* USB3.0 TX Polarity */
45 /*** Register Settings ***/
46 /* Interrupt Enable */
47 #define RCAR_USB3_INT_XHC_ENA 0x00000001
48 #define RCAR_USB3_INT_PME_ENA 0x00000002
49 #define RCAR_USB3_INT_HSE_ENA 0x00000004
50 #define RCAR_USB3_INT_ENA_VAL (RCAR_USB3_INT_XHC_ENA | \
51 RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA)
53 /* FW Download Control & Status */
54 #define RCAR_USB3_DL_CTRL_ENABLE 0x00000001
55 #define RCAR_USB3_DL_CTRL_FW_SUCCESS 0x00000010
56 #define RCAR_USB3_DL_CTRL_FW_SET_DATA0 0x00000100
59 #define RCAR_USB3_LCLK_ENA_VAL 0x01030001
61 /* USB3.0 Configuration */
62 #define RCAR_USB3_CONF1_VAL 0x00030204
63 #define RCAR_USB3_CONF2_VAL 0x00030300
64 #define RCAR_USB3_CONF3_VAL 0x13802007
67 #define RCAR_USB3_RX_POL_VAL BIT(21)
68 #define RCAR_USB3_TX_POL_VAL BIT(4)
70 /* For soc_device_attribute */
71 #define RCAR_XHCI_FIRMWARE_V2 BIT(0) /* FIRMWARE V2 */
72 #define RCAR_XHCI_FIRMWARE_V3 BIT(1) /* FIRMWARE V3 */
74 static const struct soc_device_attribute rcar_quirks_match[] = {
76 .soc_id = "r8a7795", .revision = "ES1.*",
77 .data = (void *)RCAR_XHCI_FIRMWARE_V2,
81 .data = (void *)RCAR_XHCI_FIRMWARE_V3,
85 .data = (void *)RCAR_XHCI_FIRMWARE_V3,
89 .data = (void *)RCAR_XHCI_FIRMWARE_V3,
94 static void xhci_rcar_start_gen2(struct usb_hcd *hcd)
97 writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK);
98 /* USB3.0 Configuration */
99 writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1);
100 writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2);
101 writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3);
102 /* USB3.0 Polarity */
103 writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL);
104 writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL);
107 static int xhci_rcar_is_gen2(struct device *dev)
109 struct device_node *node = dev->of_node;
111 return of_device_is_compatible(node, "renesas,xhci-r8a7790") ||
112 of_device_is_compatible(node, "renesas,xhci-r8a7791") ||
113 of_device_is_compatible(node, "renesas,xhci-r8a7793") ||
114 of_device_is_compatible(node, "renesas,rcar-gen2-xhci");
117 static int xhci_rcar_is_gen3(struct device *dev)
119 struct device_node *node = dev->of_node;
121 return of_device_is_compatible(node, "renesas,xhci-r8a7795") ||
122 of_device_is_compatible(node, "renesas,xhci-r8a7796") ||
123 of_device_is_compatible(node, "renesas,rcar-gen3-xhci");
126 void xhci_rcar_start(struct usb_hcd *hcd)
130 if (hcd->regs != NULL) {
131 /* Interrupt Enable */
132 temp = readl(hcd->regs + RCAR_USB3_INT_ENA);
133 temp |= RCAR_USB3_INT_ENA_VAL;
134 writel(temp, hcd->regs + RCAR_USB3_INT_ENA);
135 if (xhci_rcar_is_gen2(hcd->self.controller))
136 xhci_rcar_start_gen2(hcd);
140 static int xhci_rcar_download_firmware(struct usb_hcd *hcd)
142 struct device *dev = hcd->self.controller;
143 void __iomem *regs = hcd->regs;
144 struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
145 const struct firmware *fw;
146 int retval, index, j, time;
150 const struct soc_device_attribute *attr;
151 const char *firmware_name;
154 * According to the datasheet, "Upon the completion of FW Download,
155 * there is no need to write or reload FW".
157 if (readl(regs + RCAR_USB3_DL_CTRL) & RCAR_USB3_DL_CTRL_FW_SUCCESS)
160 attr = soc_device_match(rcar_quirks_match);
162 quirks = (uintptr_t)attr->data;
164 if (quirks & RCAR_XHCI_FIRMWARE_V2)
165 firmware_name = XHCI_RCAR_FIRMWARE_NAME_V2;
166 else if (quirks & RCAR_XHCI_FIRMWARE_V3)
167 firmware_name = XHCI_RCAR_FIRMWARE_NAME_V3;
169 firmware_name = priv->firmware_name;
171 /* request R-Car USB3.0 firmware */
172 retval = reject_firmware(&fw, firmware_name, dev);
176 /* download R-Car USB3.0 firmware */
177 temp = readl(regs + RCAR_USB3_DL_CTRL);
178 temp |= RCAR_USB3_DL_CTRL_ENABLE;
179 writel(temp, regs + RCAR_USB3_DL_CTRL);
181 for (index = 0; index < fw->size; index += 4) {
182 /* to avoid reading beyond the end of the buffer */
183 for (data = 0, j = 3; j >= 0; j--) {
184 if ((j + index) < fw->size)
185 data |= fw->data[index + j] << (8 * j);
187 writel(data, regs + RCAR_USB3_FW_DATA0);
188 temp = readl(regs + RCAR_USB3_DL_CTRL);
189 temp |= RCAR_USB3_DL_CTRL_FW_SET_DATA0;
190 writel(temp, regs + RCAR_USB3_DL_CTRL);
192 for (time = 0; time < timeout; time++) {
193 val = readl(regs + RCAR_USB3_DL_CTRL);
194 if ((val & RCAR_USB3_DL_CTRL_FW_SET_DATA0) == 0)
198 if (time == timeout) {
204 temp = readl(regs + RCAR_USB3_DL_CTRL);
205 temp &= ~RCAR_USB3_DL_CTRL_ENABLE;
206 writel(temp, regs + RCAR_USB3_DL_CTRL);
208 for (time = 0; time < timeout; time++) {
209 val = readl(regs + RCAR_USB3_DL_CTRL);
210 if (val & RCAR_USB3_DL_CTRL_FW_SUCCESS) {
219 release_firmware(fw);
224 /* This function needs to initialize a "phy" of usb before */
225 int xhci_rcar_init_quirk(struct usb_hcd *hcd)
227 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
229 /* If hcd->regs is NULL, we don't just call the following function */
234 * On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set
235 * to 1. However, these SoCs don't support 64-bit address memory
236 * pointers. So, this driver clears the AC64 bit of xhci->hcc_params
237 * to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in
240 * And, since the firmware/internal CPU control the USBSTS.STS_HALT
241 * and the process speed is down when the roothub port enters U3,
242 * long delay for the handshake of STS_HALT is neeed in xhci_suspend().
244 if (xhci_rcar_is_gen2(hcd->self.controller) ||
245 xhci_rcar_is_gen3(hcd->self.controller)) {
246 xhci->quirks |= XHCI_NO_64BIT_SUPPORT | XHCI_SLOW_SUSPEND;
249 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
250 return xhci_rcar_download_firmware(hcd);
253 int xhci_rcar_resume_quirk(struct usb_hcd *hcd)
257 ret = xhci_rcar_download_firmware(hcd);
259 xhci_rcar_start(hcd);