1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver PCI Bus Glue.
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
17 #include "xhci-trace.h"
19 #define SSIC_PORT_NUM 2
20 #define SSIC_PORT_CFG2 0x880c
21 #define SSIC_PORT_CFG2_OFFSET 0x30
22 #define PROG_DONE (1 << 30)
23 #define SSIC_PORT_UNUSED (1 << 31)
24 #define SPARSE_DISABLE_BIT 17
25 #define SPARSE_CNTL_ENABLE 0xC12C
27 /* Device for a quirk */
28 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
29 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
30 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
31 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
33 #define PCI_VENDOR_ID_ETRON 0x1b6f
34 #define PCI_DEVICE_ID_EJ168 0x7023
36 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
37 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
38 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
39 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
40 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
41 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
42 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
43 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
44 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
45 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
46 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
48 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
49 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
50 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
51 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
52 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
53 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
54 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
55 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
56 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
58 static const char hcd_name[] = "xhci_hcd";
60 static struct hc_driver __read_mostly xhci_pci_hc_driver;
62 static int xhci_pci_setup(struct usb_hcd *hcd);
64 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
65 .reset = xhci_pci_setup,
68 /* called after powerup, by probe or system-pm "wakeup" */
69 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
72 * TODO: Implement finding debug ports later.
73 * TODO: see if there are any quirks that need to be added to handle
74 * new extended capabilities.
77 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
78 if (!pci_set_mwi(pdev))
79 xhci_dbg(xhci, "MWI active\n");
81 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
85 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
87 struct pci_dev *pdev = to_pci_dev(dev);
89 /* Look for vendor-specific quirks */
90 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
91 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
92 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
93 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
94 pdev->revision == 0x0) {
95 xhci->quirks |= XHCI_RESET_EP_QUIRK;
96 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
97 "QUIRK: Fresco Logic xHC needs configure"
98 " endpoint cmd after reset endpoint");
100 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
101 pdev->revision == 0x4) {
102 xhci->quirks |= XHCI_SLOW_SUSPEND;
103 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
104 "QUIRK: Fresco Logic xHC revision %u"
105 "must be suspended extra slowly",
108 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
109 xhci->quirks |= XHCI_BROKEN_STREAMS;
110 /* Fresco Logic confirms: all revisions of this chip do not
111 * support MSI, even though some of them claim to in their PCI
114 xhci->quirks |= XHCI_BROKEN_MSI;
115 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
116 "QUIRK: Fresco Logic revision %u "
117 "has broken MSI implementation",
119 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
122 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
123 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
124 xhci->quirks |= XHCI_BROKEN_STREAMS;
126 if (pdev->vendor == PCI_VENDOR_ID_NEC)
127 xhci->quirks |= XHCI_NEC_HOST;
129 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
130 xhci->quirks |= XHCI_AMD_0x96_HOST;
133 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
134 xhci->quirks |= XHCI_AMD_PLL_FIX;
136 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
137 (pdev->device == 0x145c ||
138 pdev->device == 0x15e0 ||
139 pdev->device == 0x15e1 ||
140 pdev->device == 0x43bb))
141 xhci->quirks |= XHCI_SUSPEND_DELAY;
143 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
144 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
145 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
147 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
148 xhci->quirks |= XHCI_DISABLE_SPARSE;
149 xhci->quirks |= XHCI_RESET_ON_RESUME;
152 if (pdev->vendor == PCI_VENDOR_ID_AMD)
153 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
155 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
156 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
157 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
158 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
159 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
160 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
162 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
163 xhci->quirks |= XHCI_LPM_SUPPORT;
164 xhci->quirks |= XHCI_INTEL_HOST;
165 xhci->quirks |= XHCI_AVOID_BEI;
167 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
168 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
169 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
170 xhci->limit_active_eps = 64;
171 xhci->quirks |= XHCI_SW_BW_CHECKING;
173 * PPT desktop boards DH77EB and DH77DF will power back on after
174 * a few seconds of being shutdown. The fix for this is to
175 * switch the ports from xHCI to EHCI on shutdown. We can't use
176 * DMI information to find those particular boards (since each
177 * vendor will change the board name), so we have to key off all
180 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
182 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
183 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
184 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
185 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
186 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
188 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
189 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
190 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
191 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
192 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
193 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
194 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
195 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
196 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
197 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
199 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
200 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
201 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
202 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
203 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
204 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
205 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
206 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
207 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
208 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
209 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
210 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
211 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
212 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
213 xhci->quirks |= XHCI_MISSING_CAS;
215 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
216 pdev->device == PCI_DEVICE_ID_EJ168) {
217 xhci->quirks |= XHCI_RESET_ON_RESUME;
218 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
219 xhci->quirks |= XHCI_BROKEN_STREAMS;
221 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
222 pdev->device == 0x0014) {
223 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
224 xhci->quirks |= XHCI_ZERO_64B_REGS;
226 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
227 pdev->device == 0x0015) {
228 xhci->quirks |= XHCI_RESET_ON_RESUME;
229 xhci->quirks |= XHCI_ZERO_64B_REGS;
231 if (pdev->vendor == PCI_VENDOR_ID_VIA)
232 xhci->quirks |= XHCI_RESET_ON_RESUME;
234 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
235 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
236 pdev->device == 0x3432)
237 xhci->quirks |= XHCI_BROKEN_STREAMS;
239 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
240 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
241 xhci->quirks |= XHCI_BROKEN_STREAMS;
242 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
243 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
244 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
245 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
247 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
248 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
249 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
250 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
251 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
253 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
254 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
255 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
257 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
258 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
260 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
261 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
262 pdev->device == 0x9026)
263 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
265 if (xhci->quirks & XHCI_RESET_ON_RESUME)
266 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
267 "QUIRK: Resetting on resume");
271 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
273 static const guid_t intel_dsm_guid =
274 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
275 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
276 union acpi_object *obj;
278 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
283 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
284 #endif /* CONFIG_ACPI */
286 /* called during probe() after chip reset completes */
287 static int xhci_pci_setup(struct usb_hcd *hcd)
289 struct xhci_hcd *xhci;
290 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
293 xhci = hcd_to_xhci(hcd);
295 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
297 /* imod_interval is the interrupt moderation value in nanoseconds. */
298 xhci->imod_interval = 40000;
300 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
304 if (!usb_hcd_is_primary_hcd(hcd))
307 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
308 xhci_pme_acpi_rtd3_enable(pdev);
310 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
312 /* Find any debug ports */
313 return xhci_pci_reinit(xhci, pdev);
317 * We need to register our own PCI probe function (instead of the USB core's
318 * function) in order to create a second roothub under xHCI.
320 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
323 struct xhci_hcd *xhci;
324 struct hc_driver *driver;
327 driver = (struct hc_driver *)id->driver_data;
329 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
330 pm_runtime_get_noresume(&dev->dev);
332 /* Register the USB 2.0 roothub.
333 * FIXME: USB core must know to register the USB 2.0 roothub first.
334 * This is sort of silly, because we could just set the HCD driver flags
335 * to say USB 2.0, but I'm not sure what the implications would be in
336 * the other parts of the HCD code.
338 retval = usb_hcd_pci_probe(dev, id);
343 /* USB 2.0 roothub is stored in the PCI device now. */
344 hcd = dev_get_drvdata(&dev->dev);
345 xhci = hcd_to_xhci(hcd);
346 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
348 if (!xhci->shared_hcd) {
350 goto dealloc_usb2_hcd;
353 retval = xhci_ext_cap_init(xhci);
357 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
361 /* Roothub already marked as USB 3.0 speed */
363 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
364 HCC_MAX_PSA(xhci->hcc_params) >= 4)
365 xhci->shared_hcd->can_do_streams = 1;
367 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
368 pm_runtime_put_noidle(&dev->dev);
373 usb_put_hcd(xhci->shared_hcd);
375 usb_hcd_pci_remove(dev);
377 pm_runtime_put_noidle(&dev->dev);
381 static void xhci_pci_remove(struct pci_dev *dev)
383 struct xhci_hcd *xhci;
385 xhci = hcd_to_xhci(pci_get_drvdata(dev));
386 xhci->xhc_state |= XHCI_STATE_REMOVING;
387 if (xhci->shared_hcd) {
388 usb_remove_hcd(xhci->shared_hcd);
389 usb_put_hcd(xhci->shared_hcd);
390 xhci->shared_hcd = NULL;
393 /* Workaround for spurious wakeups at shutdown with HSW */
394 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
395 pci_set_power_state(dev, PCI_D3hot);
397 usb_hcd_pci_remove(dev);
402 * In some Intel xHCI controllers, in order to get D3 working,
403 * through a vendor specific SSIC CONFIG register at offset 0x883c,
404 * SSIC PORT need to be marked as "unused" before putting xHCI
405 * into D3. After D3 exit, the SSIC port need to be marked as "used".
406 * Without this change, xHCI might not enter D3 state.
408 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
410 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
415 for (i = 0; i < SSIC_PORT_NUM; i++) {
416 reg = (void __iomem *) xhci->cap_regs +
418 i * SSIC_PORT_CFG2_OFFSET;
420 /* Notify SSIC that SSIC profile programming is not done. */
421 val = readl(reg) & ~PROG_DONE;
424 /* Mark SSIC port as unused(suspend) or used(resume) */
427 val |= SSIC_PORT_UNUSED;
429 val &= ~SSIC_PORT_UNUSED;
432 /* Notify SSIC that SSIC profile programming is done */
433 val = readl(reg) | PROG_DONE;
440 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
441 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
443 static void xhci_pme_quirk(struct usb_hcd *hcd)
445 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
449 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
451 writel(val | BIT(28), reg);
455 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
459 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
460 reg &= ~BIT(SPARSE_DISABLE_BIT);
461 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
464 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
466 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
467 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
471 * Systems with the TI redriver that loses port status change events
472 * need to have the registers polled during D3, so avoid D3cold.
474 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
475 pci_d3cold_disable(pdev);
477 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
480 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
481 xhci_ssic_port_unused_quirk(hcd, true);
483 if (xhci->quirks & XHCI_DISABLE_SPARSE)
484 xhci_sparse_control_quirk(hcd);
486 ret = xhci_suspend(xhci, do_wakeup);
487 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
488 xhci_ssic_port_unused_quirk(hcd, false);
493 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
495 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
496 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
499 /* The BIOS on systems with the Intel Panther Point chipset may or may
500 * not support xHCI natively. That means that during system resume, it
501 * may switch the ports back to EHCI so that users can use their
502 * keyboard to select a kernel from GRUB after resume from hibernate.
504 * The BIOS is supposed to remember whether the OS had xHCI ports
505 * enabled before resume, and switch the ports back to xHCI when the
506 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
509 * Unconditionally switch the ports back to xHCI after a system resume.
510 * It should not matter whether the EHCI or xHCI controller is
511 * resumed first. It's enough to do the switchover in xHCI because
512 * USB core won't notice anything as the hub driver doesn't start
513 * running again until after all the devices (including both EHCI and
514 * xHCI host controllers) have been resumed.
517 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
518 usb_enable_intel_xhci_ports(pdev);
520 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
521 xhci_ssic_port_unused_quirk(hcd, false);
523 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
526 retval = xhci_resume(xhci, hibernated);
530 static void xhci_pci_shutdown(struct usb_hcd *hcd)
532 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
533 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
537 /* Yet another workaround for spurious wakeups at shutdown with HSW */
538 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
539 pci_set_power_state(pdev, PCI_D3hot);
541 #endif /* CONFIG_PM */
543 /*-------------------------------------------------------------------------*/
545 /* PCI driver selection metadata; PCI hotplugging uses this */
546 static const struct pci_device_id pci_ids[] = { {
547 /* handle any USB 3.0 xHCI controller */
548 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
549 .driver_data = (unsigned long) &xhci_pci_hc_driver,
551 { /* end: all zeroes */ }
553 MODULE_DEVICE_TABLE(pci, pci_ids);
555 /* pci driver glue; this is a "new style" PCI driver module */
556 static struct pci_driver xhci_pci_driver = {
557 .name = (char *) hcd_name,
560 .probe = xhci_pci_probe,
561 .remove = xhci_pci_remove,
562 /* suspend and resume implemented later */
564 .shutdown = usb_hcd_pci_shutdown,
567 .pm = &usb_hcd_pci_pm_ops
572 static int __init xhci_pci_init(void)
574 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
576 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
577 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
578 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
580 return pci_register_driver(&xhci_pci_driver);
582 module_init(xhci_pci_init);
584 static void __exit xhci_pci_exit(void)
586 pci_unregister_driver(&xhci_pci_driver);
588 module_exit(xhci_pci_exit);
590 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
591 MODULE_LICENSE("GPL");