drivers/usb/host/xhci-pci.c

   1 /*
   2  * xHCI host controller driver PCI Bus Glue.
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/acpi.h>
  27
  28 #include "xhci.h"
  29 #include "xhci-trace.h"
  30
  31 #define SSIC_PORT_NUM           2
  32 #define SSIC_PORT_CFG2          0x880c
  33 #define SSIC_PORT_CFG2_OFFSET   0x30
  34 #define PROG_DONE               (1 << 30)
  35 #define SSIC_PORT_UNUSED        (1 << 31)
  36
  37 /* Device for a quirk */
  38 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100       0x1100
  42 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  43
  44 #define PCI_VENDOR_ID_ETRON             0x1b6f
  45 #define PCI_DEVICE_ID_EJ168             0x7023
  46
  47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  48 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  49 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  50 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  52 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  53 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  54 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  55 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  56 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  57 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  58
  59 static const char hcd_name[] = "xhci_hcd";
  60
  61 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  62
  63 static int xhci_pci_setup(struct usb_hcd *hcd);
  64
  65 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  66         .extra_priv_size = sizeof(struct xhci_hcd),
  67         .reset = xhci_pci_setup,
  68 };
  69
  70 /* called after powerup, by probe or system-pm "wakeup" */
  71 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  72 {
  73         /*
  74          * TODO: Implement finding debug ports later.
  75          * TODO: see if there are any quirks that need to be added to handle
  76          * new extended capabilities.
  77          */
  78
  79         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  80         if (!pci_set_mwi(pdev))
  81                 xhci_dbg(xhci, "MWI active\n");
  82
  83         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  84         return 0;
  85 }
  86
  87 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  88 {
  89         struct pci_dev          *pdev = to_pci_dev(dev);
  90
  91         /* Look for vendor-specific quirks */
  92         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  93                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  94                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 ||
  95                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  96                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  97                                 pdev->revision == 0x0) {
  98                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  99                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 100                                 "QUIRK: Fresco Logic xHC needs configure"
 101                                 " endpoint cmd after reset endpoint");
 102                 }
 103                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 104                                 pdev->revision == 0x4) {
 105                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 106                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 107                                 "QUIRK: Fresco Logic xHC revision %u"
 108                                 "must be suspended extra slowly",
 109                                 pdev->revision);
 110                 }
 111                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 112                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 113                 /* Fresco Logic confirms: all revisions of this chip do not
 114                  * support MSI, even though some of them claim to in their PCI
 115                  * capabilities.
 116                  */
 117                 xhci->quirks |= XHCI_BROKEN_MSI;
 118                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 119                                 "QUIRK: Fresco Logic revision %u "
 120                                 "has broken MSI implementation",
 121                                 pdev->revision);
 122                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 123         }
 124
 125         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 126                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 127                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 128
 129         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 130                 xhci->quirks |= XHCI_NEC_HOST;
 131
 132         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 133                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 134
 135         /* AMD PLL quirk */
 136         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 137                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 138
 139         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 140                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 141
 142         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 143                 xhci->quirks |= XHCI_LPM_SUPPORT;
 144                 xhci->quirks |= XHCI_INTEL_HOST;
 145                 xhci->quirks |= XHCI_AVOID_BEI;
 146         }
 147         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 148                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 149                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 150                 xhci->limit_active_eps = 64;
 151                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 152                 /*
 153                  * PPT desktop boards DH77EB and DH77DF will power back on after
 154                  * a few seconds of being shutdown.  The fix for this is to
 155                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 156                  * DMI information to find those particular boards (since each
 157                  * vendor will change the board name), so we have to key off all
 158                  * PPT chipsets.
 159                  */
 160                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 161         }
 162         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 163                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 164                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 165                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 166                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 167         }
 168         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 169                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 170                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 171                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 172                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 173                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 174                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 175                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 176                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 177                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 178         }
 179         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 180             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 181              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 182              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 183              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 184              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 185                 xhci->quirks |= XHCI_MISSING_CAS;
 186
 187         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 188                         pdev->device == PCI_DEVICE_ID_EJ168) {
 189                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 190                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 191                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 192         }
 193         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 194                         pdev->device == 0x0014)
 195                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 196         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 197                         pdev->device == 0x0015)
 198                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 199         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 200                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 201
 202         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 203         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 204                         pdev->device == 0x3432)
 205                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 206
 207         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 208                         pdev->device == 0x1042)
 209                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 210         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 211                         pdev->device == 0x1142)
 212                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 213
 214         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 215                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 216                                 "QUIRK: Resetting on resume");
 217 }
 218
 219 #ifdef CONFIG_ACPI
 220 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 221 {
 222         static const u8 intel_dsm_uuid[] = {
 223                 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
 224                 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
 225         };
 226         union acpi_object *obj;
 227
 228         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
 229                                 NULL);
 230         ACPI_FREE(obj);
 231 }
 232 #else
 233 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 234 #endif /* CONFIG_ACPI */
 235
 236 /* called during probe() after chip reset completes */
 237 static int xhci_pci_setup(struct usb_hcd *hcd)
 238 {
 239         struct xhci_hcd         *xhci;
 240         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 241         int                     retval;
 242
 243         xhci = hcd_to_xhci(hcd);
 244         if (!xhci->sbrn)
 245                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 246
 247         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 248         if (retval)
 249                 return retval;
 250
 251         if (!usb_hcd_is_primary_hcd(hcd))
 252                 return 0;
 253
 254         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 255
 256         /* Find any debug ports */
 257         retval = xhci_pci_reinit(xhci, pdev);
 258         if (!retval)
 259                 return retval;
 260
 261         return retval;
 262 }
 263
 264 /*
 265  * We need to register our own PCI probe function (instead of the USB core's
 266  * function) in order to create a second roothub under xHCI.
 267  */
 268 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 269 {
 270         int retval;
 271         struct xhci_hcd *xhci;
 272         struct hc_driver *driver;
 273         struct usb_hcd *hcd;
 274
 275         driver = (struct hc_driver *)id->driver_data;
 276
 277         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 278         pm_runtime_get_noresume(&dev->dev);
 279
 280         /* Register the USB 2.0 roothub.
 281          * FIXME: USB core must know to register the USB 2.0 roothub first.
 282          * This is sort of silly, because we could just set the HCD driver flags
 283          * to say USB 2.0, but I'm not sure what the implications would be in
 284          * the other parts of the HCD code.
 285          */
 286         retval = usb_hcd_pci_probe(dev, id);
 287
 288         if (retval)
 289                 goto put_runtime_pm;
 290
 291         /* USB 2.0 roothub is stored in the PCI device now. */
 292         hcd = dev_get_drvdata(&dev->dev);
 293         xhci = hcd_to_xhci(hcd);
 294         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 295                                 pci_name(dev), hcd);
 296         if (!xhci->shared_hcd) {
 297                 retval = -ENOMEM;
 298                 goto dealloc_usb2_hcd;
 299         }
 300
 301         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 302                         IRQF_SHARED);
 303         if (retval)
 304                 goto put_usb3_hcd;
 305         /* Roothub already marked as USB 3.0 speed */
 306
 307         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 308                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 309                 xhci->shared_hcd->can_do_streams = 1;
 310
 311         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 312                 xhci_pme_acpi_rtd3_enable(dev);
 313
 314         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 315         pm_runtime_put_noidle(&dev->dev);
 316
 317         return 0;
 318
 319 put_usb3_hcd:
 320         usb_put_hcd(xhci->shared_hcd);
 321 dealloc_usb2_hcd:
 322         usb_hcd_pci_remove(dev);
 323 put_runtime_pm:
 324         pm_runtime_put_noidle(&dev->dev);
 325         return retval;
 326 }
 327
 328 static void xhci_pci_remove(struct pci_dev *dev)
 329 {
 330         struct xhci_hcd *xhci;
 331
 332         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 333         xhci->xhc_state |= XHCI_STATE_REMOVING;
 334         if (xhci->shared_hcd) {
 335                 usb_remove_hcd(xhci->shared_hcd);
 336                 usb_put_hcd(xhci->shared_hcd);
 337         }
 338
 339         /* Workaround for spurious wakeups at shutdown with HSW */
 340         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 341                 pci_set_power_state(dev, PCI_D3hot);
 342
 343         usb_hcd_pci_remove(dev);
 344 }
 345
 346 #ifdef CONFIG_PM
 347 /*
 348  * In some Intel xHCI controllers, in order to get D3 working,
 349  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 350  * SSIC PORT need to be marked as "unused" before putting xHCI
 351  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 352  * Without this change, xHCI might not enter D3 state.
 353  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 354  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 355  */
 356 static void xhci_pme_quirk(struct usb_hcd *hcd, bool suspend)
 357 {
 358         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 359         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 360         u32 val;
 361         void __iomem *reg;
 362         int i;
 363
 364         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 365                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
 366
 367                 for (i = 0; i < SSIC_PORT_NUM; i++) {
 368                         reg = (void __iomem *) xhci->cap_regs +
 369                                         SSIC_PORT_CFG2 +
 370                                         i * SSIC_PORT_CFG2_OFFSET;
 371
 372                         /*
 373                          * Notify SSIC that SSIC profile programming
 374                          * is not done.
 375                          */
 376                         val = readl(reg) & ~PROG_DONE;
 377                         writel(val, reg);
 378
 379                         /* Mark SSIC port as unused(suspend) or used(resume) */
 380                         val = readl(reg);
 381                         if (suspend)
 382                                 val |= SSIC_PORT_UNUSED;
 383                         else
 384                                 val &= ~SSIC_PORT_UNUSED;
 385                         writel(val, reg);
 386
 387                         /* Notify SSIC that SSIC profile programming is done */
 388                         val = readl(reg) | PROG_DONE;
 389                         writel(val, reg);
 390                         readl(reg);
 391                 }
 392         }
 393
 394         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 395         val = readl(reg);
 396         writel(val | BIT(28), reg);
 397         readl(reg);
 398 }
 399
 400 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 401 {
 402         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 403         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 404
 405         /*
 406          * Systems with the TI redriver that loses port status change events
 407          * need to have the registers polled during D3, so avoid D3cold.
 408          */
 409         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 410                 pdev->no_d3cold = true;
 411
 412         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 413                 xhci_pme_quirk(hcd, true);
 414
 415         return xhci_suspend(xhci, do_wakeup);
 416 }
 417
 418 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 419 {
 420         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 421         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 422         int                     retval = 0;
 423
 424         /* The BIOS on systems with the Intel Panther Point chipset may or may
 425          * not support xHCI natively.  That means that during system resume, it
 426          * may switch the ports back to EHCI so that users can use their
 427          * keyboard to select a kernel from GRUB after resume from hibernate.
 428          *
 429          * The BIOS is supposed to remember whether the OS had xHCI ports
 430          * enabled before resume, and switch the ports back to xHCI when the
 431          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 432          * writers.
 433          *
 434          * Unconditionally switch the ports back to xHCI after a system resume.
 435          * It should not matter whether the EHCI or xHCI controller is
 436          * resumed first. It's enough to do the switchover in xHCI because
 437          * USB core won't notice anything as the hub driver doesn't start
 438          * running again until after all the devices (including both EHCI and
 439          * xHCI host controllers) have been resumed.
 440          */
 441
 442         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 443                 usb_enable_intel_xhci_ports(pdev);
 444
 445         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 446                 xhci_pme_quirk(hcd, false);
 447
 448         retval = xhci_resume(xhci, hibernated);
 449         return retval;
 450 }
 451
 452 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 453 {
 454         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 455         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 456
 457         xhci_shutdown(hcd);
 458
 459         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 460         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 461                 pci_set_power_state(pdev, PCI_D3hot);
 462 }
 463 #endif /* CONFIG_PM */
 464
 465 /*-------------------------------------------------------------------------*/
 466
 467 /* PCI driver selection metadata; PCI hotplugging uses this */
 468 static const struct pci_device_id pci_ids[] = { {
 469         /* handle any USB 3.0 xHCI controller */
 470         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 471         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 472         },
 473         { /* end: all zeroes */ }
 474 };
 475 MODULE_DEVICE_TABLE(pci, pci_ids);
 476
 477 /* pci driver glue; this is a "new style" PCI driver module */
 478 static struct pci_driver xhci_pci_driver = {
 479         .name =         (char *) hcd_name,
 480         .id_table =     pci_ids,
 481
 482         .probe =        xhci_pci_probe,
 483         .remove =       xhci_pci_remove,
 484         /* suspend and resume implemented later */
 485
 486         .shutdown =     usb_hcd_pci_shutdown,
 487 #ifdef CONFIG_PM
 488         .driver = {
 489                 .pm = &usb_hcd_pci_pm_ops
 490         },
 491 #endif
 492 };
 493
 494 static int __init xhci_pci_init(void)
 495 {
 496         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 497 #ifdef CONFIG_PM
 498         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 499         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 500         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 501 #endif
 502         return pci_register_driver(&xhci_pci_driver);
 503 }
 504 module_init(xhci_pci_init);
 505
 506 static void __exit xhci_pci_exit(void)
 507 {
 508         pci_unregister_driver(&xhci_pci_driver);
 509 }
 510 module_exit(xhci_pci_exit);
 511
 512 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 513 MODULE_LICENSE("GPL");