drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15 #include <linux/reset.h>
  16
  17 #include "xhci.h"
  18 #include "xhci-trace.h"
  19 #include "xhci-pci.h"
  20
  21 #define SSIC_PORT_NUM           2
  22 #define SSIC_PORT_CFG2          0x880c
  23 #define SSIC_PORT_CFG2_OFFSET   0x30
  24 #define PROG_DONE               (1 << 30)
  25 #define SSIC_PORT_UNUSED        (1 << 31)
  26 #define SPARSE_DISABLE_BIT      17
  27 #define SPARSE_CNTL_ENABLE      0xC12C
  28
  29 /* Device for a quirk */
  30 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100       0x1100
  34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  35
  36 #define PCI_VENDOR_ID_ETRON             0x1b6f
  37 #define PCI_DEVICE_ID_EJ168             0x7023
  38
  39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  47 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI        0x15b5
  50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI        0x15b6
  51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI        0x15c1
  52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI      0x15db
  53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI      0x15d4
  54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI         0x15e9
  55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI         0x15ec
  56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI         0x15f0
  57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI               0x8a13
  58 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI             0x9a13
  60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI            0x1138
  61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI             0x461e
  62 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI           0x464e
  63 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed
  64 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI            0xa71e
  65 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_XHCI            0x7ec0
  66
  67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  70 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  71 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1            0x161a
  72 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2            0x161b
  73 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3            0x161d
  74 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4            0x161e
  75 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5            0x15d6
  76 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6            0x15d7
  77 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7            0x161c
  78 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8            0x161f
  79
  80 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  81 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  82 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI                 0x1242
  83 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  84 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI                 0x3242
  85
  86 static const char hcd_name[] = "xhci_hcd";
  87
  88 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  89
  90 static int xhci_pci_setup(struct usb_hcd *hcd);
  91
  92 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  93         .reset = xhci_pci_setup,
  94 };
  95
  96 /* called after powerup, by probe or system-pm "wakeup" */
  97 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  98 {
  99         /*
 100          * TODO: Implement finding debug ports later.
 101          * TODO: see if there are any quirks that need to be added to handle
 102          * new extended capabilities.
 103          */
 104
 105         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
 106         if (!pci_set_mwi(pdev))
 107                 xhci_dbg(xhci, "MWI active\n");
 108
 109         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
 110         return 0;
 111 }
 112
 113 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 114 {
 115         struct pci_dev                  *pdev = to_pci_dev(dev);
 116         struct xhci_driver_data         *driver_data;
 117         const struct pci_device_id      *id;
 118
 119         id = pci_match_id(pdev->driver->id_table, pdev);
 120
 121         if (id && id->driver_data) {
 122                 driver_data = (struct xhci_driver_data *)id->driver_data;
 123                 xhci->quirks |= driver_data->quirks;
 124         }
 125
 126         /* Look for vendor-specific quirks */
 127         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 128                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 129                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 130                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 131                                 pdev->revision == 0x0) {
 132                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 133                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 134                                 "QUIRK: Fresco Logic xHC needs configure"
 135                                 " endpoint cmd after reset endpoint");
 136                 }
 137                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 138                                 pdev->revision == 0x4) {
 139                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 140                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 141                                 "QUIRK: Fresco Logic xHC revision %u"
 142                                 "must be suspended extra slowly",
 143                                 pdev->revision);
 144                 }
 145                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 146                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 147                 /* Fresco Logic confirms: all revisions of this chip do not
 148                  * support MSI, even though some of them claim to in their PCI
 149                  * capabilities.
 150                  */
 151                 xhci->quirks |= XHCI_BROKEN_MSI;
 152                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 153                                 "QUIRK: Fresco Logic revision %u "
 154                                 "has broken MSI implementation",
 155                                 pdev->revision);
 156                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 157         }
 158
 159         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 160                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 161                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 162
 163         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 164                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
 165                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 166
 167         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 168                 xhci->quirks |= XHCI_NEC_HOST;
 169
 170         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 171                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 172
 173         /* AMD PLL quirk */
 174         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
 175                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 176
 177         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 178                 (pdev->device == 0x145c ||
 179                  pdev->device == 0x15e0 ||
 180                  pdev->device == 0x15e1 ||
 181                  pdev->device == 0x43bb))
 182                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 183
 184         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 185             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 186                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 187
 188         if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
 189                 xhci->quirks |= XHCI_DISABLE_SPARSE;
 190                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 191         }
 192
 193         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 194                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 195
 196         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 197                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 198                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 199                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 200                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 201                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 202
 203         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 204                 xhci->quirks |= XHCI_LPM_SUPPORT;
 205                 xhci->quirks |= XHCI_INTEL_HOST;
 206                 xhci->quirks |= XHCI_AVOID_BEI;
 207         }
 208         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 209                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 210                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 211                 xhci->limit_active_eps = 64;
 212                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 213                 /*
 214                  * PPT desktop boards DH77EB and DH77DF will power back on after
 215                  * a few seconds of being shutdown.  The fix for this is to
 216                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 217                  * DMI information to find those particular boards (since each
 218                  * vendor will change the board name), so we have to key off all
 219                  * PPT chipsets.
 220                  */
 221                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 222         }
 223         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 224                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 225                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 226                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 227                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 228         }
 229         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 230                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 231                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 232                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 233                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 234                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 235                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 236                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 237                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 238                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 239         }
 240         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 241             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 242                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 243         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 244             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 245              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 246              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 247                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 248         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 249             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 250              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 251              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 252              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 253              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 254                 xhci->quirks |= XHCI_MISSING_CAS;
 255
 256         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 257             pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI)
 258                 xhci->quirks |= XHCI_RESET_TO_DEFAULT;
 259
 260         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 261             (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
 262              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
 263              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
 264              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
 265              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
 266              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
 267              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
 268              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
 269              pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
 270              pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
 271              pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
 272              pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI ||
 273              pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI ||
 274              pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
 275              pdev->device == PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI ||
 276              pdev->device == PCI_DEVICE_ID_INTEL_METEOR_LAKE_XHCI))
 277                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 278
 279         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 280                         pdev->device == PCI_DEVICE_ID_EJ168) {
 281                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 282                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 283                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 284         }
 285         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 286             pdev->device == 0x0014) {
 287                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 288                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 289         }
 290         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 291             pdev->device == 0x0015) {
 292                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 293                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 294         }
 295         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 296                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 297
 298         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 299         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 300                         pdev->device == 0x3432)
 301                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 302
 303         if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
 304                 xhci->quirks |= XHCI_LPM_SUPPORT;
 305                 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
 306         }
 307
 308         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 309                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
 310                 /*
 311                  * try to tame the ASMedia 1042 controller which reports 0.96
 312                  * but appears to behave more like 1.0
 313                  */
 314                 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 315                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 316         }
 317         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 318                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
 319                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 320                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 321         }
 322         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 323             (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
 324              pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
 325              pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
 326                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 327
 328         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 329                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 330                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 331
 332         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 333                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 334
 335         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 336              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 337              pdev->device == 0x9026)
 338                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 339
 340         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 341             (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
 342              pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
 343                 xhci->quirks |= XHCI_NO_SOFT_RETRY;
 344
 345         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 346             (pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 ||
 347             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 ||
 348             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 ||
 349             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 ||
 350             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 ||
 351             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 ||
 352             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 ||
 353             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8))
 354                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 355
 356         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 357                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 358                                 "QUIRK: Resetting on resume");
 359 }
 360
 361 #ifdef CONFIG_ACPI
 362 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 363 {
 364         static const guid_t intel_dsm_guid =
 365                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 366                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 367         union acpi_object *obj;
 368
 369         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 370                                 NULL);
 371         ACPI_FREE(obj);
 372 }
 373 #else
 374 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 375 #endif /* CONFIG_ACPI */
 376
 377 /* called during probe() after chip reset completes */
 378 static int xhci_pci_setup(struct usb_hcd *hcd)
 379 {
 380         struct xhci_hcd         *xhci;
 381         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 382         int                     retval;
 383
 384         xhci = hcd_to_xhci(hcd);
 385         if (!xhci->sbrn)
 386                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 387
 388         /* imod_interval is the interrupt moderation value in nanoseconds. */
 389         xhci->imod_interval = 40000;
 390
 391         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 392         if (retval)
 393                 return retval;
 394
 395         if (!usb_hcd_is_primary_hcd(hcd))
 396                 return 0;
 397
 398         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 399                 xhci_pme_acpi_rtd3_enable(pdev);
 400
 401         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 402
 403         /* Find any debug ports */
 404         return xhci_pci_reinit(xhci, pdev);
 405 }
 406
 407 /*
 408  * We need to register our own PCI probe function (instead of the USB core's
 409  * function) in order to create a second roothub under xHCI.
 410  */
 411 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 412 {
 413         int retval;
 414         struct xhci_hcd *xhci;
 415         struct usb_hcd *hcd;
 416         struct xhci_driver_data *driver_data;
 417         struct reset_control *reset;
 418
 419         driver_data = (struct xhci_driver_data *)id->driver_data;
 420         if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
 421                 retval = renesas_xhci_check_request_fw(dev, id);
 422                 if (retval)
 423                         return retval;
 424         }
 425
 426         reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
 427         if (IS_ERR(reset))
 428                 return PTR_ERR(reset);
 429         reset_control_reset(reset);
 430
 431         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 432         pm_runtime_get_noresume(&dev->dev);
 433
 434         /* Register the USB 2.0 roothub.
 435          * FIXME: USB core must know to register the USB 2.0 roothub first.
 436          * This is sort of silly, because we could just set the HCD driver flags
 437          * to say USB 2.0, but I'm not sure what the implications would be in
 438          * the other parts of the HCD code.
 439          */
 440         retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
 441
 442         if (retval)
 443                 goto put_runtime_pm;
 444
 445         /* USB 2.0 roothub is stored in the PCI device now. */
 446         hcd = dev_get_drvdata(&dev->dev);
 447         xhci = hcd_to_xhci(hcd);
 448         xhci->reset = reset;
 449         xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
 450                                                  pci_name(dev), hcd);
 451         if (!xhci->shared_hcd) {
 452                 retval = -ENOMEM;
 453                 goto dealloc_usb2_hcd;
 454         }
 455
 456         retval = xhci_ext_cap_init(xhci);
 457         if (retval)
 458                 goto put_usb3_hcd;
 459
 460         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 461                         IRQF_SHARED);
 462         if (retval)
 463                 goto put_usb3_hcd;
 464         /* Roothub already marked as USB 3.0 speed */
 465
 466         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 467                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 468                 xhci->shared_hcd->can_do_streams = 1;
 469
 470         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 471         pm_runtime_put_noidle(&dev->dev);
 472
 473         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 474                 pm_runtime_allow(&dev->dev);
 475
 476         return 0;
 477
 478 put_usb3_hcd:
 479         usb_put_hcd(xhci->shared_hcd);
 480 dealloc_usb2_hcd:
 481         usb_hcd_pci_remove(dev);
 482 put_runtime_pm:
 483         pm_runtime_put_noidle(&dev->dev);
 484         return retval;
 485 }
 486
 487 static void xhci_pci_remove(struct pci_dev *dev)
 488 {
 489         struct xhci_hcd *xhci;
 490
 491         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 492         if (xhci->quirks & XHCI_RENESAS_FW_QUIRK)
 493                 renesas_xhci_pci_exit(dev);
 494
 495         xhci->xhc_state |= XHCI_STATE_REMOVING;
 496
 497         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 498                 pm_runtime_forbid(&dev->dev);
 499
 500         if (xhci->shared_hcd) {
 501                 usb_remove_hcd(xhci->shared_hcd);
 502                 usb_put_hcd(xhci->shared_hcd);
 503                 xhci->shared_hcd = NULL;
 504         }
 505
 506         /* Workaround for spurious wakeups at shutdown with HSW */
 507         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 508                 pci_set_power_state(dev, PCI_D3hot);
 509
 510         usb_hcd_pci_remove(dev);
 511 }
 512
 513 #ifdef CONFIG_PM
 514 /*
 515  * In some Intel xHCI controllers, in order to get D3 working,
 516  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 517  * SSIC PORT need to be marked as "unused" before putting xHCI
 518  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 519  * Without this change, xHCI might not enter D3 state.
 520  */
 521 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 522 {
 523         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 524         u32 val;
 525         void __iomem *reg;
 526         int i;
 527
 528         for (i = 0; i < SSIC_PORT_NUM; i++) {
 529                 reg = (void __iomem *) xhci->cap_regs +
 530                                 SSIC_PORT_CFG2 +
 531                                 i * SSIC_PORT_CFG2_OFFSET;
 532
 533                 /* Notify SSIC that SSIC profile programming is not done. */
 534                 val = readl(reg) & ~PROG_DONE;
 535                 writel(val, reg);
 536
 537                 /* Mark SSIC port as unused(suspend) or used(resume) */
 538                 val = readl(reg);
 539                 if (suspend)
 540                         val |= SSIC_PORT_UNUSED;
 541                 else
 542                         val &= ~SSIC_PORT_UNUSED;
 543                 writel(val, reg);
 544
 545                 /* Notify SSIC that SSIC profile programming is done */
 546                 val = readl(reg) | PROG_DONE;
 547                 writel(val, reg);
 548                 readl(reg);
 549         }
 550 }
 551
 552 /*
 553  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 554  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 555  */
 556 static void xhci_pme_quirk(struct usb_hcd *hcd)
 557 {
 558         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 559         void __iomem *reg;
 560         u32 val;
 561
 562         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 563         val = readl(reg);
 564         writel(val | BIT(28), reg);
 565         readl(reg);
 566 }
 567
 568 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
 569 {
 570         u32 reg;
 571
 572         reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
 573         reg &= ~BIT(SPARSE_DISABLE_BIT);
 574         writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
 575 }
 576
 577 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 578 {
 579         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 580         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 581         int                     ret;
 582
 583         /*
 584          * Systems with the TI redriver that loses port status change events
 585          * need to have the registers polled during D3, so avoid D3cold.
 586          */
 587         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 588                 pci_d3cold_disable(pdev);
 589
 590         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 591                 xhci_pme_quirk(hcd);
 592
 593         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 594                 xhci_ssic_port_unused_quirk(hcd, true);
 595
 596         if (xhci->quirks & XHCI_DISABLE_SPARSE)
 597                 xhci_sparse_control_quirk(hcd);
 598
 599         ret = xhci_suspend(xhci, do_wakeup);
 600         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 601                 xhci_ssic_port_unused_quirk(hcd, false);
 602
 603         return ret;
 604 }
 605
 606 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 607 {
 608         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 609         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 610         int                     retval = 0;
 611
 612         reset_control_reset(xhci->reset);
 613
 614         /* The BIOS on systems with the Intel Panther Point chipset may or may
 615          * not support xHCI natively.  That means that during system resume, it
 616          * may switch the ports back to EHCI so that users can use their
 617          * keyboard to select a kernel from GRUB after resume from hibernate.
 618          *
 619          * The BIOS is supposed to remember whether the OS had xHCI ports
 620          * enabled before resume, and switch the ports back to xHCI when the
 621          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 622          * writers.
 623          *
 624          * Unconditionally switch the ports back to xHCI after a system resume.
 625          * It should not matter whether the EHCI or xHCI controller is
 626          * resumed first. It's enough to do the switchover in xHCI because
 627          * USB core won't notice anything as the hub driver doesn't start
 628          * running again until after all the devices (including both EHCI and
 629          * xHCI host controllers) have been resumed.
 630          */
 631
 632         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 633                 usb_enable_intel_xhci_ports(pdev);
 634
 635         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 636                 xhci_ssic_port_unused_quirk(hcd, false);
 637
 638         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 639                 xhci_pme_quirk(hcd);
 640
 641         retval = xhci_resume(xhci, hibernated);
 642         return retval;
 643 }
 644
 645 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 646 {
 647         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 648         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 649
 650         xhci_shutdown(hcd);
 651
 652         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 653         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 654                 pci_set_power_state(pdev, PCI_D3hot);
 655 }
 656 #endif /* CONFIG_PM */
 657
 658 /*-------------------------------------------------------------------------*/
 659
 660 static const struct xhci_driver_data reneses_data = {
 661         .quirks  = XHCI_RENESAS_FW_QUIRK,
 662         /*(DEBLOBBED)*/"/*(DEBLOBBED)*/",
 663 };
 664
 665 /* PCI driver selection metadata; PCI hotplugging uses this */
 666 static const struct pci_device_id pci_ids[] = {
 667         { PCI_DEVICE(0x1912, 0x0014),
 668                 .driver_data =  (unsigned long)&reneses_data,
 669         },
 670         { PCI_DEVICE(0x1912, 0x0015),
 671                 .driver_data =  (unsigned long)&reneses_data,
 672         },
 673         /* handle any USB 3.0 xHCI controller */
 674         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 675         },
 676         { /* end: all zeroes */ }
 677 };
 678 MODULE_DEVICE_TABLE(pci, pci_ids);
 679
 680 /*
 681  * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
 682  * load firmware, so don't encumber the xhci-pci driver with it.
 683  */
 684 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
 685 /*(DEBLOBBED)*/
 686 #endif
 687
 688 /* pci driver glue; this is a "new style" PCI driver module */
 689 static struct pci_driver xhci_pci_driver = {
 690         .name =         hcd_name,
 691         .id_table =     pci_ids,
 692
 693         .probe =        xhci_pci_probe,
 694         .remove =       xhci_pci_remove,
 695         /* suspend and resume implemented later */
 696
 697         .shutdown =     usb_hcd_pci_shutdown,
 698 #ifdef CONFIG_PM
 699         .driver = {
 700                 .pm = &usb_hcd_pci_pm_ops
 701         },
 702 #endif
 703 };
 704
 705 static int __init xhci_pci_init(void)
 706 {
 707         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 708 #ifdef CONFIG_PM
 709         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 710         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 711         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 712 #endif
 713         return pci_register_driver(&xhci_pci_driver);
 714 }
 715 module_init(xhci_pci_init);
 716
 717 static void __exit xhci_pci_exit(void)
 718 {
 719         pci_unregister_driver(&xhci_pci_driver);
 720 }
 721 module_exit(xhci_pci_exit);
 722
 723 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 724 MODULE_LICENSE("GPL");