drivers/usb/host/xhci-pci.c

   1 /*
   2  * xHCI host controller driver PCI Bus Glue.
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/acpi.h>
  27
  28 #include "xhci.h"
  29 #include "xhci-trace.h"
  30
  31 #define SSIC_PORT_NUM           2
  32 #define SSIC_PORT_CFG2          0x880c
  33 #define SSIC_PORT_CFG2_OFFSET   0x30
  34 #define PROG_DONE               (1 << 30)
  35 #define SSIC_PORT_UNUSED        (1 << 31)
  36
  37 /* Device for a quirk */
  38 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100       0x1100
  42 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  43
  44 #define PCI_VENDOR_ID_ETRON             0x1b6f
  45 #define PCI_DEVICE_ID_EJ168             0x7023
  46
  47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  48 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  49 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  50 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  52 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  53 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  54 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  55 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  56 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  57 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  58
  59 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  60 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  61 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  62 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  63 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  64 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  65 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI                 0x1242
  66 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  67 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI                 0x3242
  68
  69 static const char hcd_name[] = "xhci_hcd";
  70
  71 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  72
  73 static int xhci_pci_setup(struct usb_hcd *hcd);
  74
  75 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  76         .reset = xhci_pci_setup,
  77 };
  78
  79 /* called after powerup, by probe or system-pm "wakeup" */
  80 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  81 {
  82         /*
  83          * TODO: Implement finding debug ports later.
  84          * TODO: see if there are any quirks that need to be added to handle
  85          * new extended capabilities.
  86          */
  87
  88         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  89         if (!pci_set_mwi(pdev))
  90                 xhci_dbg(xhci, "MWI active\n");
  91
  92         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  93         return 0;
  94 }
  95
  96 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  97 {
  98         struct pci_dev          *pdev = to_pci_dev(dev);
  99
 100         /* Look for vendor-specific quirks */
 101         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 102                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 103                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 104                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 105                                 pdev->revision == 0x0) {
 106                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 107                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 108                                 "QUIRK: Fresco Logic xHC needs configure"
 109                                 " endpoint cmd after reset endpoint");
 110                 }
 111                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 112                                 pdev->revision == 0x4) {
 113                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 114                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 115                                 "QUIRK: Fresco Logic xHC revision %u"
 116                                 "must be suspended extra slowly",
 117                                 pdev->revision);
 118                 }
 119                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 120                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 121                 /* Fresco Logic confirms: all revisions of this chip do not
 122                  * support MSI, even though some of them claim to in their PCI
 123                  * capabilities.
 124                  */
 125                 xhci->quirks |= XHCI_BROKEN_MSI;
 126                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 127                                 "QUIRK: Fresco Logic revision %u "
 128                                 "has broken MSI implementation",
 129                                 pdev->revision);
 130                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 131         }
 132
 133         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 134                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 135                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 136
 137         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 138                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
 139                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 140
 141         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 142                 xhci->quirks |= XHCI_NEC_HOST;
 143
 144         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 145                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 146
 147         /* AMD PLL quirk */
 148         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 149                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 150
 151         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 152                 (pdev->device == 0x145c ||
 153                  pdev->device == 0x15e0 ||
 154                  pdev->device == 0x15e1 ||
 155                  pdev->device == 0x43bb))
 156                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 157
 158         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 159             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 160                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 161
 162         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 163                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 164
 165         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 166                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 167                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 168                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 169                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 170                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 171
 172         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 173                 xhci->quirks |= XHCI_LPM_SUPPORT;
 174                 xhci->quirks |= XHCI_INTEL_HOST;
 175                 xhci->quirks |= XHCI_AVOID_BEI;
 176         }
 177         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 178                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 179                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 180                 xhci->limit_active_eps = 64;
 181                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 182                 /*
 183                  * PPT desktop boards DH77EB and DH77DF will power back on after
 184                  * a few seconds of being shutdown.  The fix for this is to
 185                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 186                  * DMI information to find those particular boards (since each
 187                  * vendor will change the board name), so we have to key off all
 188                  * PPT chipsets.
 189                  */
 190                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 191         }
 192         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 193                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 194                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 195                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 196                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 197         }
 198         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 199                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 200                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 201                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 202                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 203                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 204                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 205                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 206                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 207                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 208         }
 209         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 210                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
 211                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 212         }
 213         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 214             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 215              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 216              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 217              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 218              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 219                 xhci->quirks |= XHCI_MISSING_CAS;
 220
 221         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 222                         pdev->device == PCI_DEVICE_ID_EJ168) {
 223                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 224                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 225                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 226         }
 227         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 228                         pdev->device == 0x0014)
 229                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 230         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 231                         pdev->device == 0x0015)
 232                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 233         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 234                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 235
 236         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 237         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 238                         pdev->device == 0x3432)
 239                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 240
 241         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 242                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
 243                 /*
 244                  * try to tame the ASMedia 1042 controller which reports 0.96
 245                  * but appears to behave more like 1.0
 246                  */
 247                 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 248                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 249         }
 250         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 251                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
 252                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 253                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 254         }
 255         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 256             (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
 257              pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
 258              pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
 259                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 260
 261         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 262                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 263                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 264
 265         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 266                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 267
 268         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 269              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 270              pdev->device == 0x9026)
 271                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 272
 273         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 274                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 275                                 "QUIRK: Resetting on resume");
 276 }
 277
 278 #ifdef CONFIG_ACPI
 279 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 280 {
 281         static const guid_t intel_dsm_guid =
 282                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 283                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 284         union acpi_object *obj;
 285
 286         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 287                                 NULL);
 288         ACPI_FREE(obj);
 289 }
 290 #else
 291 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 292 #endif /* CONFIG_ACPI */
 293
 294 /* called during probe() after chip reset completes */
 295 static int xhci_pci_setup(struct usb_hcd *hcd)
 296 {
 297         struct xhci_hcd         *xhci;
 298         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 299         int                     retval;
 300
 301         xhci = hcd_to_xhci(hcd);
 302         if (!xhci->sbrn)
 303                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 304
 305         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 306         if (retval)
 307                 return retval;
 308
 309         if (!usb_hcd_is_primary_hcd(hcd))
 310                 return 0;
 311
 312         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 313                 xhci_pme_acpi_rtd3_enable(pdev);
 314
 315         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 316
 317         /* Find any debug ports */
 318         return xhci_pci_reinit(xhci, pdev);
 319 }
 320
 321 /*
 322  * We need to register our own PCI probe function (instead of the USB core's
 323  * function) in order to create a second roothub under xHCI.
 324  */
 325 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 326 {
 327         int retval;
 328         struct xhci_hcd *xhci;
 329         struct hc_driver *driver;
 330         struct usb_hcd *hcd;
 331
 332         driver = (struct hc_driver *)id->driver_data;
 333
 334         /* For some HW implementation, a XHCI reset is just not enough... */
 335         if (usb_xhci_needs_pci_reset(dev)) {
 336                 dev_info(&dev->dev, "Resetting\n");
 337                 if (pci_reset_function_locked(dev))
 338                         dev_warn(&dev->dev, "Reset failed");
 339         }
 340
 341         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 342         pm_runtime_get_noresume(&dev->dev);
 343
 344         /* Register the USB 2.0 roothub.
 345          * FIXME: USB core must know to register the USB 2.0 roothub first.
 346          * This is sort of silly, because we could just set the HCD driver flags
 347          * to say USB 2.0, but I'm not sure what the implications would be in
 348          * the other parts of the HCD code.
 349          */
 350         retval = usb_hcd_pci_probe(dev, id);
 351
 352         if (retval)
 353                 goto put_runtime_pm;
 354
 355         /* USB 2.0 roothub is stored in the PCI device now. */
 356         hcd = dev_get_drvdata(&dev->dev);
 357         xhci = hcd_to_xhci(hcd);
 358         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 359                                 pci_name(dev), hcd);
 360         if (!xhci->shared_hcd) {
 361                 retval = -ENOMEM;
 362                 goto dealloc_usb2_hcd;
 363         }
 364
 365         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 366                         IRQF_SHARED);
 367         if (retval)
 368                 goto put_usb3_hcd;
 369         /* Roothub already marked as USB 3.0 speed */
 370
 371         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 372                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 373                 xhci->shared_hcd->can_do_streams = 1;
 374
 375         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 376         pm_runtime_put_noidle(&dev->dev);
 377
 378         dma_set_max_seg_size(&dev->dev, UINT_MAX);
 379
 380         return 0;
 381
 382 put_usb3_hcd:
 383         usb_put_hcd(xhci->shared_hcd);
 384 dealloc_usb2_hcd:
 385         usb_hcd_pci_remove(dev);
 386 put_runtime_pm:
 387         pm_runtime_put_noidle(&dev->dev);
 388         return retval;
 389 }
 390
 391 static void xhci_pci_remove(struct pci_dev *dev)
 392 {
 393         struct xhci_hcd *xhci;
 394
 395         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 396         xhci->xhc_state |= XHCI_STATE_REMOVING;
 397         if (xhci->shared_hcd) {
 398                 usb_remove_hcd(xhci->shared_hcd);
 399                 usb_put_hcd(xhci->shared_hcd);
 400                 xhci->shared_hcd = NULL;
 401         }
 402
 403         /* Workaround for spurious wakeups at shutdown with HSW */
 404         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 405                 pci_set_power_state(dev, PCI_D3hot);
 406
 407         usb_hcd_pci_remove(dev);
 408 }
 409
 410 #ifdef CONFIG_PM
 411 /*
 412  * In some Intel xHCI controllers, in order to get D3 working,
 413  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 414  * SSIC PORT need to be marked as "unused" before putting xHCI
 415  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 416  * Without this change, xHCI might not enter D3 state.
 417  */
 418 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 419 {
 420         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 421         u32 val;
 422         void __iomem *reg;
 423         int i;
 424
 425         for (i = 0; i < SSIC_PORT_NUM; i++) {
 426                 reg = (void __iomem *) xhci->cap_regs +
 427                                 SSIC_PORT_CFG2 +
 428                                 i * SSIC_PORT_CFG2_OFFSET;
 429
 430                 /* Notify SSIC that SSIC profile programming is not done. */
 431                 val = readl(reg) & ~PROG_DONE;
 432                 writel(val, reg);
 433
 434                 /* Mark SSIC port as unused(suspend) or used(resume) */
 435                 val = readl(reg);
 436                 if (suspend)
 437                         val |= SSIC_PORT_UNUSED;
 438                 else
 439                         val &= ~SSIC_PORT_UNUSED;
 440                 writel(val, reg);
 441
 442                 /* Notify SSIC that SSIC profile programming is done */
 443                 val = readl(reg) | PROG_DONE;
 444                 writel(val, reg);
 445                 readl(reg);
 446         }
 447 }
 448
 449 /*
 450  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 451  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 452  */
 453 static void xhci_pme_quirk(struct usb_hcd *hcd)
 454 {
 455         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 456         void __iomem *reg;
 457         u32 val;
 458
 459         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 460         val = readl(reg);
 461         writel(val | BIT(28), reg);
 462         readl(reg);
 463 }
 464
 465 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 466 {
 467         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 468         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 469         int                     ret;
 470
 471         /*
 472          * Systems with the TI redriver that loses port status change events
 473          * need to have the registers polled during D3, so avoid D3cold.
 474          */
 475         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 476                 pci_d3cold_disable(pdev);
 477
 478         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 479                 xhci_pme_quirk(hcd);
 480
 481         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 482                 xhci_ssic_port_unused_quirk(hcd, true);
 483
 484         ret = xhci_suspend(xhci, do_wakeup);
 485         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 486                 xhci_ssic_port_unused_quirk(hcd, false);
 487
 488         return ret;
 489 }
 490
 491 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 492 {
 493         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 494         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 495         int                     retval = 0;
 496
 497         /* The BIOS on systems with the Intel Panther Point chipset may or may
 498          * not support xHCI natively.  That means that during system resume, it
 499          * may switch the ports back to EHCI so that users can use their
 500          * keyboard to select a kernel from GRUB after resume from hibernate.
 501          *
 502          * The BIOS is supposed to remember whether the OS had xHCI ports
 503          * enabled before resume, and switch the ports back to xHCI when the
 504          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 505          * writers.
 506          *
 507          * Unconditionally switch the ports back to xHCI after a system resume.
 508          * It should not matter whether the EHCI or xHCI controller is
 509          * resumed first. It's enough to do the switchover in xHCI because
 510          * USB core won't notice anything as the hub driver doesn't start
 511          * running again until after all the devices (including both EHCI and
 512          * xHCI host controllers) have been resumed.
 513          */
 514
 515         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 516                 usb_enable_intel_xhci_ports(pdev);
 517
 518         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 519                 xhci_ssic_port_unused_quirk(hcd, false);
 520
 521         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 522                 xhci_pme_quirk(hcd);
 523
 524         retval = xhci_resume(xhci, hibernated);
 525         return retval;
 526 }
 527
 528 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 529 {
 530         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 531         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 532
 533         xhci_shutdown(hcd);
 534
 535         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 536         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 537                 pci_set_power_state(pdev, PCI_D3hot);
 538 }
 539 #endif /* CONFIG_PM */
 540
 541 /*-------------------------------------------------------------------------*/
 542
 543 /* PCI driver selection metadata; PCI hotplugging uses this */
 544 static const struct pci_device_id pci_ids[] = { {
 545         /* handle any USB 3.0 xHCI controller */
 546         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 547         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 548         },
 549         { /* end: all zeroes */ }
 550 };
 551 MODULE_DEVICE_TABLE(pci, pci_ids);
 552
 553 /* pci driver glue; this is a "new style" PCI driver module */
 554 static struct pci_driver xhci_pci_driver = {
 555         .name =         (char *) hcd_name,
 556         .id_table =     pci_ids,
 557
 558         .probe =        xhci_pci_probe,
 559         .remove =       xhci_pci_remove,
 560         /* suspend and resume implemented later */
 561
 562         .shutdown =     usb_hcd_pci_shutdown,
 563 #ifdef CONFIG_PM
 564         .driver = {
 565                 .pm = &usb_hcd_pci_pm_ops
 566         },
 567 #endif
 568 };
 569
 570 static int __init xhci_pci_init(void)
 571 {
 572         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 573 #ifdef CONFIG_PM
 574         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 575         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 576         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 577 #endif
 578         return pci_register_driver(&xhci_pci_driver);
 579 }
 580 module_init(xhci_pci_init);
 581
 582 static void __exit xhci_pci_exit(void)
 583 {
 584         pci_unregister_driver(&xhci_pci_driver);
 585 }
 586 module_exit(xhci_pci_exit);
 587
 588 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 589 MODULE_LICENSE("GPL");