drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15 #include <linux/reset.h>
  16
  17 #include "xhci.h"
  18 #include "xhci-trace.h"
  19 #include "xhci-pci.h"
  20
  21 #define SSIC_PORT_NUM           2
  22 #define SSIC_PORT_CFG2          0x880c
  23 #define SSIC_PORT_CFG2_OFFSET   0x30
  24 #define PROG_DONE               (1 << 30)
  25 #define SSIC_PORT_UNUSED        (1 << 31)
  26 #define SPARSE_DISABLE_BIT      17
  27 #define SPARSE_CNTL_ENABLE      0xC12C
  28
  29 /* Device for a quirk */
  30 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100       0x1100
  34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  35
  36 #define PCI_VENDOR_ID_ETRON             0x1b6f
  37 #define PCI_DEVICE_ID_EJ168             0x7023
  38
  39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  47 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI        0x15b5
  50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI        0x15b6
  51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI        0x15c1
  52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI      0x15db
  53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI      0x15d4
  54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI         0x15e9
  55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI         0x15ec
  56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI         0x15f0
  57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI               0x8a13
  58 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI             0x9a13
  60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI            0x1138
  61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI         0x51ed
  62 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI       0x54ed
  63
  64 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  65 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  68
  69 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  70 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  71 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI                 0x1242
  72 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  73 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI                 0x3242
  74
  75 static const char hcd_name[] = "xhci_hcd";
  76
  77 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  78
  79 static int xhci_pci_setup(struct usb_hcd *hcd);
  80 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
  81                                       struct usb_tt *tt, gfp_t mem_flags);
  82
  83 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  84         .reset = xhci_pci_setup,
  85         .update_hub_device = xhci_pci_update_hub_device,
  86 };
  87
  88 /* called after powerup, by probe or system-pm "wakeup" */
  89 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  90 {
  91         /*
  92          * TODO: Implement finding debug ports later.
  93          * TODO: see if there are any quirks that need to be added to handle
  94          * new extended capabilities.
  95          */
  96
  97         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  98         if (!pci_set_mwi(pdev))
  99                 xhci_dbg(xhci, "MWI active\n");
 100
 101         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
 102         return 0;
 103 }
 104
 105 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 106 {
 107         struct pci_dev                  *pdev = to_pci_dev(dev);
 108         struct xhci_driver_data         *driver_data;
 109         const struct pci_device_id      *id;
 110
 111         id = pci_match_id(pdev->driver->id_table, pdev);
 112
 113         if (id && id->driver_data) {
 114                 driver_data = (struct xhci_driver_data *)id->driver_data;
 115                 xhci->quirks |= driver_data->quirks;
 116         }
 117
 118         /* Look for vendor-specific quirks */
 119         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 120                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 121                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 122                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 123                                 pdev->revision == 0x0) {
 124                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 125                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 126                                 "QUIRK: Fresco Logic xHC needs configure"
 127                                 " endpoint cmd after reset endpoint");
 128                 }
 129                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 130                                 pdev->revision == 0x4) {
 131                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 132                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 133                                 "QUIRK: Fresco Logic xHC revision %u"
 134                                 "must be suspended extra slowly",
 135                                 pdev->revision);
 136                 }
 137                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 138                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 139                 /* Fresco Logic confirms: all revisions of this chip do not
 140                  * support MSI, even though some of them claim to in their PCI
 141                  * capabilities.
 142                  */
 143                 xhci->quirks |= XHCI_BROKEN_MSI;
 144                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 145                                 "QUIRK: Fresco Logic revision %u "
 146                                 "has broken MSI implementation",
 147                                 pdev->revision);
 148                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 149         }
 150
 151         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 152                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 153                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 154
 155         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 156                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
 157                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 158
 159         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 160                 xhci->quirks |= XHCI_NEC_HOST;
 161
 162         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 163                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 164
 165         /* AMD PLL quirk */
 166         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
 167                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 168
 169         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 170                 (pdev->device == 0x145c ||
 171                  pdev->device == 0x15e0 ||
 172                  pdev->device == 0x15e1 ||
 173                  pdev->device == 0x43bb))
 174                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 175
 176         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 177             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 178                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 179
 180         if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
 181                 xhci->quirks |= XHCI_DISABLE_SPARSE;
 182                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 183         }
 184
 185         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 186                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 187
 188         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 189                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 190                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 191                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 192                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 193                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 194
 195         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 196                 xhci->quirks |= XHCI_LPM_SUPPORT;
 197                 xhci->quirks |= XHCI_INTEL_HOST;
 198                 xhci->quirks |= XHCI_AVOID_BEI;
 199         }
 200         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 201                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 202                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 203                 xhci->limit_active_eps = 64;
 204                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 205                 /*
 206                  * PPT desktop boards DH77EB and DH77DF will power back on after
 207                  * a few seconds of being shutdown.  The fix for this is to
 208                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 209                  * DMI information to find those particular boards (since each
 210                  * vendor will change the board name), so we have to key off all
 211                  * PPT chipsets.
 212                  */
 213                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 214         }
 215         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 216                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 217                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 218                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 219                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 220         }
 221         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 222                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 223                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 224                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 225                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 226                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 227                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 228                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 229                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 230                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 231         }
 232         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 233             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 234                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 235         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 236             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 237              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 238              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 239                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 240         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 241             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 242              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 243              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 244              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 245              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 246                 xhci->quirks |= XHCI_MISSING_CAS;
 247
 248         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 249             (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
 250              pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI))
 251                 xhci->quirks |= XHCI_RESET_TO_DEFAULT;
 252
 253         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 254             (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
 255              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
 256              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
 257              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
 258              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
 259              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
 260              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
 261              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
 262              pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
 263              pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
 264              pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
 265                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 266
 267         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 268                         pdev->device == PCI_DEVICE_ID_EJ168) {
 269                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 270                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 271                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 272         }
 273         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 274             pdev->device == 0x0014) {
 275                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 276                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 277         }
 278         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 279             pdev->device == 0x0015) {
 280                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 281                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 282         }
 283         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 284                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 285
 286         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 287         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 288                         pdev->device == 0x3432)
 289                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 290
 291         if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
 292                 xhci->quirks |= XHCI_LPM_SUPPORT;
 293                 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
 294         }
 295
 296         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 297                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
 298                 /*
 299                  * try to tame the ASMedia 1042 controller which reports 0.96
 300                  * but appears to behave more like 1.0
 301                  */
 302                 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 303                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 304         }
 305         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 306                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
 307                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 308                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 309         }
 310         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 311             (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
 312              pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
 313              pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
 314                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 315
 316         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 317                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 318                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 319
 320         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 321                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 322
 323         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 324              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 325              pdev->device == 0x9026)
 326                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 327
 328         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 329             (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
 330              pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
 331                 xhci->quirks |= XHCI_NO_SOFT_RETRY;
 332
 333         if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) {
 334                 xhci->quirks |= XHCI_ZHAOXIN_HOST;
 335
 336                 if (pdev->device == 0x9202) {
 337                         xhci->quirks |= XHCI_RESET_ON_RESUME;
 338                         xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
 339                 }
 340
 341                 if (pdev->device == 0x9203)
 342                         xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
 343         }
 344
 345         /* xHC spec requires PCI devices to support D3hot and D3cold */
 346         if (xhci->hci_version >= 0x120)
 347                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 348
 349         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 350                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 351                                 "QUIRK: Resetting on resume");
 352 }
 353
 354 #ifdef CONFIG_ACPI
 355 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 356 {
 357         static const guid_t intel_dsm_guid =
 358                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 359                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 360         union acpi_object *obj;
 361
 362         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 363                                 NULL);
 364         ACPI_FREE(obj);
 365 }
 366
 367 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev)
 368 {
 369         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 370         struct xhci_hub *rhub = &xhci->usb3_rhub;
 371         int ret;
 372         int i;
 373
 374         /* This is not the usb3 roothub we are looking for */
 375         if (hcd != rhub->hcd)
 376                 return;
 377
 378         if (hdev->maxchild > rhub->num_ports) {
 379                 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n");
 380                 return;
 381         }
 382
 383         for (i = 0; i < hdev->maxchild; i++) {
 384                 ret = usb_acpi_port_lpm_incapable(hdev, i);
 385
 386                 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret);
 387
 388                 if (ret >= 0) {
 389                         rhub->ports[i]->lpm_incapable = ret;
 390                         continue;
 391                 }
 392         }
 393 }
 394
 395 #else
 396 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 397 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { }
 398 #endif /* CONFIG_ACPI */
 399
 400 /* called during probe() after chip reset completes */
 401 static int xhci_pci_setup(struct usb_hcd *hcd)
 402 {
 403         struct xhci_hcd         *xhci;
 404         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 405         int                     retval;
 406
 407         xhci = hcd_to_xhci(hcd);
 408         if (!xhci->sbrn)
 409                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 410
 411         /* imod_interval is the interrupt moderation value in nanoseconds. */
 412         xhci->imod_interval = 40000;
 413
 414         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 415         if (retval)
 416                 return retval;
 417
 418         if (!usb_hcd_is_primary_hcd(hcd))
 419                 return 0;
 420
 421         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 422                 xhci_pme_acpi_rtd3_enable(pdev);
 423
 424         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 425
 426         /* Find any debug ports */
 427         return xhci_pci_reinit(xhci, pdev);
 428 }
 429
 430 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
 431                                       struct usb_tt *tt, gfp_t mem_flags)
 432 {
 433         /* Check if acpi claims some USB3 roothub ports are lpm incapable */
 434         if (!hdev->parent)
 435                 xhci_find_lpm_incapable_ports(hcd, hdev);
 436
 437         return xhci_update_hub_device(hcd, hdev, tt, mem_flags);
 438 }
 439
 440 /*
 441  * We need to register our own PCI probe function (instead of the USB core's
 442  * function) in order to create a second roothub under xHCI.
 443  */
 444 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 445 {
 446         int retval;
 447         struct xhci_hcd *xhci;
 448         struct usb_hcd *hcd;
 449         struct xhci_driver_data *driver_data;
 450         struct reset_control *reset;
 451
 452         driver_data = (struct xhci_driver_data *)id->driver_data;
 453         if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
 454                 retval = renesas_xhci_check_request_fw(dev, id);
 455                 if (retval)
 456                         return retval;
 457         }
 458
 459         reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
 460         if (IS_ERR(reset))
 461                 return PTR_ERR(reset);
 462         reset_control_reset(reset);
 463
 464         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 465         pm_runtime_get_noresume(&dev->dev);
 466
 467         /* Register the USB 2.0 roothub.
 468          * FIXME: USB core must know to register the USB 2.0 roothub first.
 469          * This is sort of silly, because we could just set the HCD driver flags
 470          * to say USB 2.0, but I'm not sure what the implications would be in
 471          * the other parts of the HCD code.
 472          */
 473         retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
 474
 475         if (retval)
 476                 goto put_runtime_pm;
 477
 478         /* USB 2.0 roothub is stored in the PCI device now. */
 479         hcd = dev_get_drvdata(&dev->dev);
 480         xhci = hcd_to_xhci(hcd);
 481         xhci->reset = reset;
 482         xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
 483                                                  pci_name(dev), hcd);
 484         if (!xhci->shared_hcd) {
 485                 retval = -ENOMEM;
 486                 goto dealloc_usb2_hcd;
 487         }
 488
 489         retval = xhci_ext_cap_init(xhci);
 490         if (retval)
 491                 goto put_usb3_hcd;
 492
 493         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 494                         IRQF_SHARED);
 495         if (retval)
 496                 goto put_usb3_hcd;
 497         /* Roothub already marked as USB 3.0 speed */
 498
 499         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 500                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 501                 xhci->shared_hcd->can_do_streams = 1;
 502
 503         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 504         pm_runtime_put_noidle(&dev->dev);
 505
 506         if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0)
 507                 pm_runtime_forbid(&dev->dev);
 508         else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 509                 pm_runtime_allow(&dev->dev);
 510
 511         dma_set_max_seg_size(&dev->dev, UINT_MAX);
 512
 513         return 0;
 514
 515 put_usb3_hcd:
 516         usb_put_hcd(xhci->shared_hcd);
 517 dealloc_usb2_hcd:
 518         usb_hcd_pci_remove(dev);
 519 put_runtime_pm:
 520         pm_runtime_put_noidle(&dev->dev);
 521         return retval;
 522 }
 523
 524 static void xhci_pci_remove(struct pci_dev *dev)
 525 {
 526         struct xhci_hcd *xhci;
 527
 528         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 529         if (xhci->quirks & XHCI_RENESAS_FW_QUIRK)
 530                 renesas_xhci_pci_exit(dev);
 531
 532         xhci->xhc_state |= XHCI_STATE_REMOVING;
 533
 534         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 535                 pm_runtime_forbid(&dev->dev);
 536
 537         if (xhci->shared_hcd) {
 538                 usb_remove_hcd(xhci->shared_hcd);
 539                 usb_put_hcd(xhci->shared_hcd);
 540                 xhci->shared_hcd = NULL;
 541         }
 542
 543         /* Workaround for spurious wakeups at shutdown with HSW */
 544         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 545                 pci_set_power_state(dev, PCI_D3hot);
 546
 547         usb_hcd_pci_remove(dev);
 548 }
 549
 550 #ifdef CONFIG_PM
 551 /*
 552  * In some Intel xHCI controllers, in order to get D3 working,
 553  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 554  * SSIC PORT need to be marked as "unused" before putting xHCI
 555  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 556  * Without this change, xHCI might not enter D3 state.
 557  */
 558 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 559 {
 560         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 561         u32 val;
 562         void __iomem *reg;
 563         int i;
 564
 565         for (i = 0; i < SSIC_PORT_NUM; i++) {
 566                 reg = (void __iomem *) xhci->cap_regs +
 567                                 SSIC_PORT_CFG2 +
 568                                 i * SSIC_PORT_CFG2_OFFSET;
 569
 570                 /* Notify SSIC that SSIC profile programming is not done. */
 571                 val = readl(reg) & ~PROG_DONE;
 572                 writel(val, reg);
 573
 574                 /* Mark SSIC port as unused(suspend) or used(resume) */
 575                 val = readl(reg);
 576                 if (suspend)
 577                         val |= SSIC_PORT_UNUSED;
 578                 else
 579                         val &= ~SSIC_PORT_UNUSED;
 580                 writel(val, reg);
 581
 582                 /* Notify SSIC that SSIC profile programming is done */
 583                 val = readl(reg) | PROG_DONE;
 584                 writel(val, reg);
 585                 readl(reg);
 586         }
 587 }
 588
 589 /*
 590  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 591  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 592  */
 593 static void xhci_pme_quirk(struct usb_hcd *hcd)
 594 {
 595         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 596         void __iomem *reg;
 597         u32 val;
 598
 599         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 600         val = readl(reg);
 601         writel(val | BIT(28), reg);
 602         readl(reg);
 603 }
 604
 605 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
 606 {
 607         u32 reg;
 608
 609         reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
 610         reg &= ~BIT(SPARSE_DISABLE_BIT);
 611         writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
 612 }
 613
 614 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 615 {
 616         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 617         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 618         int                     ret;
 619
 620         /*
 621          * Systems with the TI redriver that loses port status change events
 622          * need to have the registers polled during D3, so avoid D3cold.
 623          */
 624         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 625                 pci_d3cold_disable(pdev);
 626
 627         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 628                 xhci_pme_quirk(hcd);
 629
 630         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 631                 xhci_ssic_port_unused_quirk(hcd, true);
 632
 633         if (xhci->quirks & XHCI_DISABLE_SPARSE)
 634                 xhci_sparse_control_quirk(hcd);
 635
 636         ret = xhci_suspend(xhci, do_wakeup);
 637         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 638                 xhci_ssic_port_unused_quirk(hcd, false);
 639
 640         return ret;
 641 }
 642
 643 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 644 {
 645         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 646         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 647         int                     retval = 0;
 648
 649         reset_control_reset(xhci->reset);
 650
 651         /* The BIOS on systems with the Intel Panther Point chipset may or may
 652          * not support xHCI natively.  That means that during system resume, it
 653          * may switch the ports back to EHCI so that users can use their
 654          * keyboard to select a kernel from GRUB after resume from hibernate.
 655          *
 656          * The BIOS is supposed to remember whether the OS had xHCI ports
 657          * enabled before resume, and switch the ports back to xHCI when the
 658          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 659          * writers.
 660          *
 661          * Unconditionally switch the ports back to xHCI after a system resume.
 662          * It should not matter whether the EHCI or xHCI controller is
 663          * resumed first. It's enough to do the switchover in xHCI because
 664          * USB core won't notice anything as the hub driver doesn't start
 665          * running again until after all the devices (including both EHCI and
 666          * xHCI host controllers) have been resumed.
 667          */
 668
 669         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 670                 usb_enable_intel_xhci_ports(pdev);
 671
 672         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 673                 xhci_ssic_port_unused_quirk(hcd, false);
 674
 675         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 676                 xhci_pme_quirk(hcd);
 677
 678         retval = xhci_resume(xhci, hibernated);
 679         return retval;
 680 }
 681
 682 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 683 {
 684         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 685         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 686
 687         xhci_shutdown(hcd);
 688
 689         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 690         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 691                 pci_set_power_state(pdev, PCI_D3hot);
 692 }
 693 #endif /* CONFIG_PM */
 694
 695 /*-------------------------------------------------------------------------*/
 696
 697 static const struct xhci_driver_data reneses_data = {
 698         .quirks  = XHCI_RENESAS_FW_QUIRK,
 699         /*(DEBLOBBED)*/"/*(DEBLOBBED)*/",
 700 };
 701
 702 /* PCI driver selection metadata; PCI hotplugging uses this */
 703 static const struct pci_device_id pci_ids[] = {
 704         { PCI_DEVICE(0x1912, 0x0014),
 705                 .driver_data =  (unsigned long)&reneses_data,
 706         },
 707         { PCI_DEVICE(0x1912, 0x0015),
 708                 .driver_data =  (unsigned long)&reneses_data,
 709         },
 710         /* handle any USB 3.0 xHCI controller */
 711         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 712         },
 713         { /* end: all zeroes */ }
 714 };
 715 MODULE_DEVICE_TABLE(pci, pci_ids);
 716
 717 /*
 718  * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
 719  * load firmware, so don't encumber the xhci-pci driver with it.
 720  */
 721 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
 722 /*(DEBLOBBED)*/
 723 #endif
 724
 725 /* pci driver glue; this is a "new style" PCI driver module */
 726 static struct pci_driver xhci_pci_driver = {
 727         .name =         hcd_name,
 728         .id_table =     pci_ids,
 729
 730         .probe =        xhci_pci_probe,
 731         .remove =       xhci_pci_remove,
 732         /* suspend and resume implemented later */
 733
 734         .shutdown =     usb_hcd_pci_shutdown,
 735 #ifdef CONFIG_PM
 736         .driver = {
 737                 .pm = &usb_hcd_pci_pm_ops
 738         },
 739 #endif
 740 };
 741
 742 static int __init xhci_pci_init(void)
 743 {
 744         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 745 #ifdef CONFIG_PM
 746         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 747         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 748         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 749 #endif
 750         return pci_register_driver(&xhci_pci_driver);
 751 }
 752 module_init(xhci_pci_init);
 753
 754 static void __exit xhci_pci_exit(void)
 755 {
 756         pci_unregister_driver(&xhci_pci_driver);
 757 }
 758 module_exit(xhci_pci_exit);
 759
 760 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 761 MODULE_LICENSE("GPL");