drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15 #include <linux/reset.h>
  16
  17 #include "xhci.h"
  18 #include "xhci-trace.h"
  19 #include "xhci-pci.h"
  20
  21 #define SSIC_PORT_NUM           2
  22 #define SSIC_PORT_CFG2          0x880c
  23 #define SSIC_PORT_CFG2_OFFSET   0x30
  24 #define PROG_DONE               (1 << 30)
  25 #define SSIC_PORT_UNUSED        (1 << 31)
  26 #define SPARSE_DISABLE_BIT      17
  27 #define SPARSE_CNTL_ENABLE      0xC12C
  28
  29 /* Device for a quirk */
  30 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100       0x1100
  34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  35
  36 #define PCI_VENDOR_ID_ETRON             0x1b6f
  37 #define PCI_DEVICE_ID_EJ168             0x7023
  38
  39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  47 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI        0x15b5
  50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI        0x15b6
  51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI        0x15c1
  52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI      0x15db
  53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI      0x15d4
  54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI         0x15e9
  55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI         0x15ec
  56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI         0x15f0
  57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI               0x8a13
  58 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI             0x9a13
  60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI            0x1138
  61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI             0x461e
  62
  63 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI                   0x1639
  64 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  65 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  68 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1            0x161a
  69 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2            0x161b
  70 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3            0x161d
  71 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4            0x161e
  72 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5            0x15d6
  73 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6            0x15d7
  74 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7            0x161c
  75 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8            0x161f
  76
  77 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  78 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  79 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI                 0x1242
  80 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  81 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI                 0x3242
  82
  83 static const char hcd_name[] = "xhci_hcd";
  84
  85 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  86
  87 static int xhci_pci_setup(struct usb_hcd *hcd);
  88
  89 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  90         .reset = xhci_pci_setup,
  91 };
  92
  93 /* called after powerup, by probe or system-pm "wakeup" */
  94 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  95 {
  96         /*
  97          * TODO: Implement finding debug ports later.
  98          * TODO: see if there are any quirks that need to be added to handle
  99          * new extended capabilities.
 100          */
 101
 102         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
 103         if (!pci_set_mwi(pdev))
 104                 xhci_dbg(xhci, "MWI active\n");
 105
 106         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
 107         return 0;
 108 }
 109
 110 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 111 {
 112         struct pci_dev                  *pdev = to_pci_dev(dev);
 113         struct xhci_driver_data         *driver_data;
 114         const struct pci_device_id      *id;
 115
 116         id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev);
 117
 118         if (id && id->driver_data) {
 119                 driver_data = (struct xhci_driver_data *)id->driver_data;
 120                 xhci->quirks |= driver_data->quirks;
 121         }
 122
 123         /* Look for vendor-specific quirks */
 124         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 125                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 126                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 127                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 128                                 pdev->revision == 0x0) {
 129                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 130                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 131                                 "QUIRK: Fresco Logic xHC needs configure"
 132                                 " endpoint cmd after reset endpoint");
 133                 }
 134                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 135                                 pdev->revision == 0x4) {
 136                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 137                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 138                                 "QUIRK: Fresco Logic xHC revision %u"
 139                                 "must be suspended extra slowly",
 140                                 pdev->revision);
 141                 }
 142                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 143                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 144                 /* Fresco Logic confirms: all revisions of this chip do not
 145                  * support MSI, even though some of them claim to in their PCI
 146                  * capabilities.
 147                  */
 148                 xhci->quirks |= XHCI_BROKEN_MSI;
 149                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 150                                 "QUIRK: Fresco Logic revision %u "
 151                                 "has broken MSI implementation",
 152                                 pdev->revision);
 153                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 154         }
 155
 156         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 157                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 158                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 159
 160         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 161                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
 162                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 163
 164         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 165                 xhci->quirks |= XHCI_NEC_HOST;
 166
 167         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 168                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 169
 170         /* AMD PLL quirk */
 171         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
 172                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 173
 174         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 175                 (pdev->device == 0x145c ||
 176                  pdev->device == 0x15e0 ||
 177                  pdev->device == 0x15e1 ||
 178                  pdev->device == 0x43bb))
 179                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 180
 181         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 182             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 183                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 184
 185         if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
 186                 xhci->quirks |= XHCI_DISABLE_SPARSE;
 187                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 188         }
 189
 190         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 191                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 192
 193         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 194                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 195                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 196                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 197                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 198                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 199
 200         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 201                 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
 202                 xhci->quirks |= XHCI_BROKEN_D3COLD;
 203
 204         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 205                 xhci->quirks |= XHCI_LPM_SUPPORT;
 206                 xhci->quirks |= XHCI_INTEL_HOST;
 207                 xhci->quirks |= XHCI_AVOID_BEI;
 208         }
 209         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 210                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 211                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 212                 xhci->limit_active_eps = 64;
 213                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 214                 /*
 215                  * PPT desktop boards DH77EB and DH77DF will power back on after
 216                  * a few seconds of being shutdown.  The fix for this is to
 217                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 218                  * DMI information to find those particular boards (since each
 219                  * vendor will change the board name), so we have to key off all
 220                  * PPT chipsets.
 221                  */
 222                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 223         }
 224         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 225                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 226                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 227                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 228                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 229         }
 230         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 231                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 232                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 233                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 234                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 235                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 236                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 237                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 238                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 239                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 240         }
 241         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 242             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 243                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 244         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 245             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 246              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 247              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 248                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 249         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 250             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 251              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 252              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 253              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 254              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 255                 xhci->quirks |= XHCI_MISSING_CAS;
 256
 257         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 258             (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
 259              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
 260              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
 261              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
 262              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
 263              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
 264              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
 265              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
 266              pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
 267              pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
 268              pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
 269              pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI))
 270                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 271
 272         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 273                         pdev->device == PCI_DEVICE_ID_EJ168) {
 274                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 275                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 276                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 277         }
 278         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 279             pdev->device == 0x0014) {
 280                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 281                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 282         }
 283         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 284             pdev->device == 0x0015) {
 285                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 286                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 287         }
 288         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 289                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 290
 291         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 292         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 293                         pdev->device == 0x3432)
 294                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 295
 296         if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
 297                 xhci->quirks |= XHCI_LPM_SUPPORT;
 298                 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
 299         }
 300
 301         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 302                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
 303                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 304         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 305                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
 306                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 307                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 308         }
 309         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 310             (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
 311              pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
 312              pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
 313                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 314
 315         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 316                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 317                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 318
 319         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 320                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 321
 322         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 323              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 324              pdev->device == 0x9026)
 325                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 326
 327         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 328             (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
 329              pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
 330                 xhci->quirks |= XHCI_NO_SOFT_RETRY;
 331
 332         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 333             (pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 ||
 334             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 ||
 335             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 ||
 336             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 ||
 337             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 ||
 338             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 ||
 339             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 ||
 340             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8))
 341                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 342
 343         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 344                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 345                                 "QUIRK: Resetting on resume");
 346 }
 347
 348 #ifdef CONFIG_ACPI
 349 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 350 {
 351         static const guid_t intel_dsm_guid =
 352                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 353                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 354         union acpi_object *obj;
 355
 356         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 357                                 NULL);
 358         ACPI_FREE(obj);
 359 }
 360 #else
 361 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 362 #endif /* CONFIG_ACPI */
 363
 364 /* called during probe() after chip reset completes */
 365 static int xhci_pci_setup(struct usb_hcd *hcd)
 366 {
 367         struct xhci_hcd         *xhci;
 368         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 369         int                     retval;
 370
 371         xhci = hcd_to_xhci(hcd);
 372         if (!xhci->sbrn)
 373                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 374
 375         /* imod_interval is the interrupt moderation value in nanoseconds. */
 376         xhci->imod_interval = 40000;
 377
 378         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 379         if (retval)
 380                 return retval;
 381
 382         if (!usb_hcd_is_primary_hcd(hcd))
 383                 return 0;
 384
 385         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 386                 xhci_pme_acpi_rtd3_enable(pdev);
 387
 388         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 389
 390         /* Find any debug ports */
 391         return xhci_pci_reinit(xhci, pdev);
 392 }
 393
 394 /*
 395  * We need to register our own PCI probe function (instead of the USB core's
 396  * function) in order to create a second roothub under xHCI.
 397  */
 398 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 399 {
 400         int retval;
 401         struct xhci_hcd *xhci;
 402         struct usb_hcd *hcd;
 403         struct xhci_driver_data *driver_data;
 404         struct reset_control *reset;
 405
 406         driver_data = (struct xhci_driver_data *)id->driver_data;
 407         if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
 408                 retval = renesas_xhci_check_request_fw(dev, id);
 409                 if (retval)
 410                         return retval;
 411         }
 412
 413         reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
 414         if (IS_ERR(reset))
 415                 return PTR_ERR(reset);
 416         reset_control_reset(reset);
 417
 418         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 419         pm_runtime_get_noresume(&dev->dev);
 420
 421         /* Register the USB 2.0 roothub.
 422          * FIXME: USB core must know to register the USB 2.0 roothub first.
 423          * This is sort of silly, because we could just set the HCD driver flags
 424          * to say USB 2.0, but I'm not sure what the implications would be in
 425          * the other parts of the HCD code.
 426          */
 427         retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
 428
 429         if (retval)
 430                 goto put_runtime_pm;
 431
 432         /* USB 2.0 roothub is stored in the PCI device now. */
 433         hcd = dev_get_drvdata(&dev->dev);
 434         xhci = hcd_to_xhci(hcd);
 435         xhci->reset = reset;
 436         xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
 437                                                  pci_name(dev), hcd);
 438         if (!xhci->shared_hcd) {
 439                 retval = -ENOMEM;
 440                 goto dealloc_usb2_hcd;
 441         }
 442
 443         retval = xhci_ext_cap_init(xhci);
 444         if (retval)
 445                 goto put_usb3_hcd;
 446
 447         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 448                         IRQF_SHARED);
 449         if (retval)
 450                 goto put_usb3_hcd;
 451         /* Roothub already marked as USB 3.0 speed */
 452
 453         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 454                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 455                 xhci->shared_hcd->can_do_streams = 1;
 456
 457         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 458         pm_runtime_put_noidle(&dev->dev);
 459
 460         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 461                 pm_runtime_allow(&dev->dev);
 462
 463         return 0;
 464
 465 put_usb3_hcd:
 466         usb_put_hcd(xhci->shared_hcd);
 467 dealloc_usb2_hcd:
 468         usb_hcd_pci_remove(dev);
 469 put_runtime_pm:
 470         pm_runtime_put_noidle(&dev->dev);
 471         return retval;
 472 }
 473
 474 static void xhci_pci_remove(struct pci_dev *dev)
 475 {
 476         struct xhci_hcd *xhci;
 477
 478         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 479
 480         xhci->xhc_state |= XHCI_STATE_REMOVING;
 481
 482         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 483                 pm_runtime_forbid(&dev->dev);
 484
 485         if (xhci->shared_hcd) {
 486                 usb_remove_hcd(xhci->shared_hcd);
 487                 usb_put_hcd(xhci->shared_hcd);
 488                 xhci->shared_hcd = NULL;
 489         }
 490
 491         /* Workaround for spurious wakeups at shutdown with HSW */
 492         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 493                 pci_set_power_state(dev, PCI_D3hot);
 494
 495         usb_hcd_pci_remove(dev);
 496 }
 497
 498 #ifdef CONFIG_PM
 499 /*
 500  * In some Intel xHCI controllers, in order to get D3 working,
 501  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 502  * SSIC PORT need to be marked as "unused" before putting xHCI
 503  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 504  * Without this change, xHCI might not enter D3 state.
 505  */
 506 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 507 {
 508         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 509         u32 val;
 510         void __iomem *reg;
 511         int i;
 512
 513         for (i = 0; i < SSIC_PORT_NUM; i++) {
 514                 reg = (void __iomem *) xhci->cap_regs +
 515                                 SSIC_PORT_CFG2 +
 516                                 i * SSIC_PORT_CFG2_OFFSET;
 517
 518                 /* Notify SSIC that SSIC profile programming is not done. */
 519                 val = readl(reg) & ~PROG_DONE;
 520                 writel(val, reg);
 521
 522                 /* Mark SSIC port as unused(suspend) or used(resume) */
 523                 val = readl(reg);
 524                 if (suspend)
 525                         val |= SSIC_PORT_UNUSED;
 526                 else
 527                         val &= ~SSIC_PORT_UNUSED;
 528                 writel(val, reg);
 529
 530                 /* Notify SSIC that SSIC profile programming is done */
 531                 val = readl(reg) | PROG_DONE;
 532                 writel(val, reg);
 533                 readl(reg);
 534         }
 535 }
 536
 537 /*
 538  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 539  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 540  */
 541 static void xhci_pme_quirk(struct usb_hcd *hcd)
 542 {
 543         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 544         void __iomem *reg;
 545         u32 val;
 546
 547         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 548         val = readl(reg);
 549         writel(val | BIT(28), reg);
 550         readl(reg);
 551 }
 552
 553 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
 554 {
 555         u32 reg;
 556
 557         reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
 558         reg &= ~BIT(SPARSE_DISABLE_BIT);
 559         writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
 560 }
 561
 562 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 563 {
 564         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 565         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 566         int                     ret;
 567
 568         /*
 569          * Systems with the TI redriver that loses port status change events
 570          * need to have the registers polled during D3, so avoid D3cold.
 571          */
 572         if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD))
 573                 pci_d3cold_disable(pdev);
 574
 575         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 576                 xhci_pme_quirk(hcd);
 577
 578         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 579                 xhci_ssic_port_unused_quirk(hcd, true);
 580
 581         if (xhci->quirks & XHCI_DISABLE_SPARSE)
 582                 xhci_sparse_control_quirk(hcd);
 583
 584         ret = xhci_suspend(xhci, do_wakeup);
 585         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 586                 xhci_ssic_port_unused_quirk(hcd, false);
 587
 588         return ret;
 589 }
 590
 591 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 592 {
 593         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 594         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 595         int                     retval = 0;
 596
 597         reset_control_reset(xhci->reset);
 598
 599         /* The BIOS on systems with the Intel Panther Point chipset may or may
 600          * not support xHCI natively.  That means that during system resume, it
 601          * may switch the ports back to EHCI so that users can use their
 602          * keyboard to select a kernel from GRUB after resume from hibernate.
 603          *
 604          * The BIOS is supposed to remember whether the OS had xHCI ports
 605          * enabled before resume, and switch the ports back to xHCI when the
 606          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 607          * writers.
 608          *
 609          * Unconditionally switch the ports back to xHCI after a system resume.
 610          * It should not matter whether the EHCI or xHCI controller is
 611          * resumed first. It's enough to do the switchover in xHCI because
 612          * USB core won't notice anything as the hub driver doesn't start
 613          * running again until after all the devices (including both EHCI and
 614          * xHCI host controllers) have been resumed.
 615          */
 616
 617         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 618                 usb_enable_intel_xhci_ports(pdev);
 619
 620         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 621                 xhci_ssic_port_unused_quirk(hcd, false);
 622
 623         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 624                 xhci_pme_quirk(hcd);
 625
 626         retval = xhci_resume(xhci, hibernated);
 627         return retval;
 628 }
 629
 630 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 631 {
 632         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 633         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 634
 635         xhci_shutdown(hcd);
 636
 637         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 638         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 639                 pci_set_power_state(pdev, PCI_D3hot);
 640 }
 641 #endif /* CONFIG_PM */
 642
 643 /*-------------------------------------------------------------------------*/
 644
 645 static const struct xhci_driver_data reneses_data = {
 646         .quirks  = XHCI_RENESAS_FW_QUIRK,
 647         /*(DEBLOBBED)*/"/*(DEBLOBBED)*/",
 648 };
 649
 650 /* PCI driver selection metadata; PCI hotplugging uses this */
 651 static const struct pci_device_id pci_ids[] = {
 652         { PCI_DEVICE(0x1912, 0x0014),
 653                 .driver_data =  (unsigned long)&reneses_data,
 654         },
 655         { PCI_DEVICE(0x1912, 0x0015),
 656                 .driver_data =  (unsigned long)&reneses_data,
 657         },
 658         /* handle any USB 3.0 xHCI controller */
 659         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 660         },
 661         { /* end: all zeroes */ }
 662 };
 663 MODULE_DEVICE_TABLE(pci, pci_ids);
 664
 665 /*
 666  * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
 667  * load firmware, so don't encumber the xhci-pci driver with it.
 668  */
 669 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
 670 /*(DEBLOBBED)*/
 671 #endif
 672
 673 /* pci driver glue; this is a "new style" PCI driver module */
 674 static struct pci_driver xhci_pci_driver = {
 675         .name =         hcd_name,
 676         .id_table =     pci_ids,
 677
 678         .probe =        xhci_pci_probe,
 679         .remove =       xhci_pci_remove,
 680         /* suspend and resume implemented later */
 681
 682         .shutdown =     usb_hcd_pci_shutdown,
 683 #ifdef CONFIG_PM
 684         .driver = {
 685                 .pm = &usb_hcd_pci_pm_ops
 686         },
 687 #endif
 688 };
 689
 690 static int __init xhci_pci_init(void)
 691 {
 692         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 693 #ifdef CONFIG_PM
 694         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 695         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 696         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 697 #endif
 698         return pci_register_driver(&xhci_pci_driver);
 699 }
 700 module_init(xhci_pci_init);
 701
 702 static void __exit xhci_pci_exit(void)
 703 {
 704         pci_unregister_driver(&xhci_pci_driver);
 705 }
 706 module_exit(xhci_pci_exit);
 707
 708 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 709 MODULE_LICENSE("GPL");