drivers/usb/host/xhci-pci.c

   1 /*
   2  * xHCI host controller driver PCI Bus Glue.
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/acpi.h>
  27
  28 #include "xhci.h"
  29 #include "xhci-trace.h"
  30
  31 #define SSIC_PORT_NUM           2
  32 #define SSIC_PORT_CFG2          0x880c
  33 #define SSIC_PORT_CFG2_OFFSET   0x30
  34 #define PROG_DONE               (1 << 30)
  35 #define SSIC_PORT_UNUSED        (1 << 31)
  36
  37 /* Device for a quirk */
  38 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100       0x1100
  42 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  43
  44 #define PCI_VENDOR_ID_ETRON             0x1b6f
  45 #define PCI_DEVICE_ID_EJ168             0x7023
  46
  47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  48 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  49 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  50 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  52 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  53 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  54 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  55 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  56 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  57 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  58
  59 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  60 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  61 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  62 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  63 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  64 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  65 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI                 0x1242
  66 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  67 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI                 0x3242
  68
  69 static const char hcd_name[] = "xhci_hcd";
  70
  71 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  72
  73 static int xhci_pci_setup(struct usb_hcd *hcd);
  74
  75 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  76         .reset = xhci_pci_setup,
  77 };
  78
  79 /* called after powerup, by probe or system-pm "wakeup" */
  80 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  81 {
  82         /*
  83          * TODO: Implement finding debug ports later.
  84          * TODO: see if there are any quirks that need to be added to handle
  85          * new extended capabilities.
  86          */
  87
  88         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  89         if (!pci_set_mwi(pdev))
  90                 xhci_dbg(xhci, "MWI active\n");
  91
  92         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  93         return 0;
  94 }
  95
  96 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  97 {
  98         struct pci_dev          *pdev = to_pci_dev(dev);
  99
 100         /* Look for vendor-specific quirks */
 101         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 102                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 103                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 ||
 104                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 105                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 106                                 pdev->revision == 0x0) {
 107                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 108                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 109                                 "QUIRK: Fresco Logic xHC needs configure"
 110                                 " endpoint cmd after reset endpoint");
 111                 }
 112                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 113                                 pdev->revision == 0x4) {
 114                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 115                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 116                                 "QUIRK: Fresco Logic xHC revision %u"
 117                                 "must be suspended extra slowly",
 118                                 pdev->revision);
 119                 }
 120                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 121                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 122                 /* Fresco Logic confirms: all revisions of this chip do not
 123                  * support MSI, even though some of them claim to in their PCI
 124                  * capabilities.
 125                  */
 126                 xhci->quirks |= XHCI_BROKEN_MSI;
 127                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 128                                 "QUIRK: Fresco Logic revision %u "
 129                                 "has broken MSI implementation",
 130                                 pdev->revision);
 131                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 132         }
 133
 134         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 135                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 136                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 137
 138         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 139                 xhci->quirks |= XHCI_NEC_HOST;
 140
 141         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 142                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 143
 144         /* AMD PLL quirk */
 145         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 146                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 147
 148         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 149                 (pdev->device == 0x145c ||
 150                  pdev->device == 0x15e0 ||
 151                  pdev->device == 0x15e1 ||
 152                  pdev->device == 0x43bb))
 153                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 154
 155         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 156             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 157                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 158
 159         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 160                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 161
 162         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 163                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 164                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 165                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 166                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 167                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 168
 169         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 170                 xhci->quirks |= XHCI_LPM_SUPPORT;
 171                 xhci->quirks |= XHCI_INTEL_HOST;
 172                 xhci->quirks |= XHCI_AVOID_BEI;
 173         }
 174         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 175                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 176                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 177                 xhci->limit_active_eps = 64;
 178                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 179                 /*
 180                  * PPT desktop boards DH77EB and DH77DF will power back on after
 181                  * a few seconds of being shutdown.  The fix for this is to
 182                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 183                  * DMI information to find those particular boards (since each
 184                  * vendor will change the board name), so we have to key off all
 185                  * PPT chipsets.
 186                  */
 187                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 188         }
 189         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 190                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 191                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 192                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 193                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 194         }
 195         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 196                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 197                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 198                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 199                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 200                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 201                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 202                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 203                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 204                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 205         }
 206         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 207                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
 208                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 209         }
 210         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 211             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 212              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 213              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 214              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 215              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 216                 xhci->quirks |= XHCI_MISSING_CAS;
 217
 218         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 219                         pdev->device == PCI_DEVICE_ID_EJ168) {
 220                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 221                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 222                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 223         }
 224         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 225                         pdev->device == 0x0014)
 226                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 227         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 228                         pdev->device == 0x0015)
 229                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 230         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 231                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 232
 233         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 234         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 235                         pdev->device == 0x3432)
 236                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 237
 238         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 239                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
 240                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 241         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 242                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
 243                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 244                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 245         }
 246         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 247             (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
 248              pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
 249              pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
 250                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 251
 252         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 253                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 254                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 255
 256         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 257                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 258
 259         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 260              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 261              pdev->device == 0x9026)
 262                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 263
 264         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 265                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 266                                 "QUIRK: Resetting on resume");
 267 }
 268
 269 #ifdef CONFIG_ACPI
 270 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 271 {
 272         static const guid_t intel_dsm_guid =
 273                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 274                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 275         union acpi_object *obj;
 276
 277         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 278                                 NULL);
 279         ACPI_FREE(obj);
 280 }
 281 #else
 282 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 283 #endif /* CONFIG_ACPI */
 284
 285 /* called during probe() after chip reset completes */
 286 static int xhci_pci_setup(struct usb_hcd *hcd)
 287 {
 288         struct xhci_hcd         *xhci;
 289         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 290         int                     retval;
 291
 292         xhci = hcd_to_xhci(hcd);
 293         if (!xhci->sbrn)
 294                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 295
 296         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 297         if (retval)
 298                 return retval;
 299
 300         if (!usb_hcd_is_primary_hcd(hcd))
 301                 return 0;
 302
 303         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 304                 xhci_pme_acpi_rtd3_enable(pdev);
 305
 306         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 307
 308         /* Find any debug ports */
 309         return xhci_pci_reinit(xhci, pdev);
 310 }
 311
 312 /*
 313  * We need to register our own PCI probe function (instead of the USB core's
 314  * function) in order to create a second roothub under xHCI.
 315  */
 316 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 317 {
 318         int retval;
 319         struct xhci_hcd *xhci;
 320         struct hc_driver *driver;
 321         struct usb_hcd *hcd;
 322
 323         driver = (struct hc_driver *)id->driver_data;
 324
 325         /* For some HW implementation, a XHCI reset is just not enough... */
 326         if (usb_xhci_needs_pci_reset(dev)) {
 327                 dev_info(&dev->dev, "Resetting\n");
 328                 if (pci_reset_function_locked(dev))
 329                         dev_warn(&dev->dev, "Reset failed");
 330         }
 331
 332         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 333         pm_runtime_get_noresume(&dev->dev);
 334
 335         /* Register the USB 2.0 roothub.
 336          * FIXME: USB core must know to register the USB 2.0 roothub first.
 337          * This is sort of silly, because we could just set the HCD driver flags
 338          * to say USB 2.0, but I'm not sure what the implications would be in
 339          * the other parts of the HCD code.
 340          */
 341         retval = usb_hcd_pci_probe(dev, id);
 342
 343         if (retval)
 344                 goto put_runtime_pm;
 345
 346         /* USB 2.0 roothub is stored in the PCI device now. */
 347         hcd = dev_get_drvdata(&dev->dev);
 348         xhci = hcd_to_xhci(hcd);
 349         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 350                                 pci_name(dev), hcd);
 351         if (!xhci->shared_hcd) {
 352                 retval = -ENOMEM;
 353                 goto dealloc_usb2_hcd;
 354         }
 355
 356         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 357                         IRQF_SHARED);
 358         if (retval)
 359                 goto put_usb3_hcd;
 360         /* Roothub already marked as USB 3.0 speed */
 361
 362         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 363                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 364                 xhci->shared_hcd->can_do_streams = 1;
 365
 366         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 367         pm_runtime_put_noidle(&dev->dev);
 368
 369         return 0;
 370
 371 put_usb3_hcd:
 372         usb_put_hcd(xhci->shared_hcd);
 373 dealloc_usb2_hcd:
 374         usb_hcd_pci_remove(dev);
 375 put_runtime_pm:
 376         pm_runtime_put_noidle(&dev->dev);
 377         return retval;
 378 }
 379
 380 static void xhci_pci_remove(struct pci_dev *dev)
 381 {
 382         struct xhci_hcd *xhci;
 383
 384         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 385         xhci->xhc_state |= XHCI_STATE_REMOVING;
 386         if (xhci->shared_hcd) {
 387                 usb_remove_hcd(xhci->shared_hcd);
 388                 usb_put_hcd(xhci->shared_hcd);
 389                 xhci->shared_hcd = NULL;
 390         }
 391
 392         /* Workaround for spurious wakeups at shutdown with HSW */
 393         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 394                 pci_set_power_state(dev, PCI_D3hot);
 395
 396         usb_hcd_pci_remove(dev);
 397 }
 398
 399 #ifdef CONFIG_PM
 400 /*
 401  * In some Intel xHCI controllers, in order to get D3 working,
 402  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 403  * SSIC PORT need to be marked as "unused" before putting xHCI
 404  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 405  * Without this change, xHCI might not enter D3 state.
 406  */
 407 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 408 {
 409         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 410         u32 val;
 411         void __iomem *reg;
 412         int i;
 413
 414         for (i = 0; i < SSIC_PORT_NUM; i++) {
 415                 reg = (void __iomem *) xhci->cap_regs +
 416                                 SSIC_PORT_CFG2 +
 417                                 i * SSIC_PORT_CFG2_OFFSET;
 418
 419                 /* Notify SSIC that SSIC profile programming is not done. */
 420                 val = readl(reg) & ~PROG_DONE;
 421                 writel(val, reg);
 422
 423                 /* Mark SSIC port as unused(suspend) or used(resume) */
 424                 val = readl(reg);
 425                 if (suspend)
 426                         val |= SSIC_PORT_UNUSED;
 427                 else
 428                         val &= ~SSIC_PORT_UNUSED;
 429                 writel(val, reg);
 430
 431                 /* Notify SSIC that SSIC profile programming is done */
 432                 val = readl(reg) | PROG_DONE;
 433                 writel(val, reg);
 434                 readl(reg);
 435         }
 436 }
 437
 438 /*
 439  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 440  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 441  */
 442 static void xhci_pme_quirk(struct usb_hcd *hcd)
 443 {
 444         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 445         void __iomem *reg;
 446         u32 val;
 447
 448         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 449         val = readl(reg);
 450         writel(val | BIT(28), reg);
 451         readl(reg);
 452 }
 453
 454 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 455 {
 456         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 457         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 458         int                     ret;
 459
 460         /*
 461          * Systems with the TI redriver that loses port status change events
 462          * need to have the registers polled during D3, so avoid D3cold.
 463          */
 464         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 465                 pci_d3cold_disable(pdev);
 466
 467         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 468                 xhci_pme_quirk(hcd);
 469
 470         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 471                 xhci_ssic_port_unused_quirk(hcd, true);
 472
 473         ret = xhci_suspend(xhci, do_wakeup);
 474         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 475                 xhci_ssic_port_unused_quirk(hcd, false);
 476
 477         return ret;
 478 }
 479
 480 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 481 {
 482         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 483         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 484         int                     retval = 0;
 485
 486         /* The BIOS on systems with the Intel Panther Point chipset may or may
 487          * not support xHCI natively.  That means that during system resume, it
 488          * may switch the ports back to EHCI so that users can use their
 489          * keyboard to select a kernel from GRUB after resume from hibernate.
 490          *
 491          * The BIOS is supposed to remember whether the OS had xHCI ports
 492          * enabled before resume, and switch the ports back to xHCI when the
 493          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 494          * writers.
 495          *
 496          * Unconditionally switch the ports back to xHCI after a system resume.
 497          * It should not matter whether the EHCI or xHCI controller is
 498          * resumed first. It's enough to do the switchover in xHCI because
 499          * USB core won't notice anything as the hub driver doesn't start
 500          * running again until after all the devices (including both EHCI and
 501          * xHCI host controllers) have been resumed.
 502          */
 503
 504         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 505                 usb_enable_intel_xhci_ports(pdev);
 506
 507         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 508                 xhci_ssic_port_unused_quirk(hcd, false);
 509
 510         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 511                 xhci_pme_quirk(hcd);
 512
 513         retval = xhci_resume(xhci, hibernated);
 514         return retval;
 515 }
 516
 517 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 518 {
 519         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 520         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 521
 522         xhci_shutdown(hcd);
 523
 524         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 525         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 526                 pci_set_power_state(pdev, PCI_D3hot);
 527 }
 528 #endif /* CONFIG_PM */
 529
 530 /*-------------------------------------------------------------------------*/
 531
 532 /* PCI driver selection metadata; PCI hotplugging uses this */
 533 static const struct pci_device_id pci_ids[] = { {
 534         /* handle any USB 3.0 xHCI controller */
 535         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 536         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 537         },
 538         { /* end: all zeroes */ }
 539 };
 540 MODULE_DEVICE_TABLE(pci, pci_ids);
 541
 542 /* pci driver glue; this is a "new style" PCI driver module */
 543 static struct pci_driver xhci_pci_driver = {
 544         .name =         (char *) hcd_name,
 545         .id_table =     pci_ids,
 546
 547         .probe =        xhci_pci_probe,
 548         .remove =       xhci_pci_remove,
 549         /* suspend and resume implemented later */
 550
 551         .shutdown =     usb_hcd_pci_shutdown,
 552 #ifdef CONFIG_PM
 553         .driver = {
 554                 .pm = &usb_hcd_pci_pm_ops
 555         },
 556 #endif
 557 };
 558
 559 static int __init xhci_pci_init(void)
 560 {
 561         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 562 #ifdef CONFIG_PM
 563         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 564         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 565         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 566 #endif
 567         return pci_register_driver(&xhci_pci_driver);
 568 }
 569 module_init(xhci_pci_init);
 570
 571 static void __exit xhci_pci_exit(void)
 572 {
 573         pci_unregister_driver(&xhci_pci_driver);
 574 }
 575 module_exit(xhci_pci_exit);
 576
 577 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 578 MODULE_LICENSE("GPL");